JP2003140914A - Electronic control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic control device for rewriting constant data of a main CPU and a sub CPU with one rewriting interface. SOLUTION: A write control program for the main CPU 103 is stored from a rewrite host computer 500 into a RAM 120 of the main CPU 103 via the rewriting interface 102, and is executed by the main CPU 103. The constant data of the sub CPU 109 stored in a nonvolatile memory 104 of the main CPU 103 from the rewrite host computer 500 via the rewriting interface 102 is transferred to the sub CPU 109 via a communication wire 108 to be written into a RAM 110. Thus, one rewriting interface 102 allows rewriting of the constant data of both the main CPU 103 and the sub CPU 109.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic control device having a plurality of CPUs.

[0002]

2. Description of the Related Art An electronic control unit (ECU) including a plurality of CPUs is known. For example, JP-A-5-81
Japanese Unexamined Patent Publication No. 222 discloses a technique in which, in a system having two main CPUs and sub CPUs, the operating states of the CPUs are monitored to detect a CPU failure. Moreover, in order to reduce the calculation load of the CPU,
A system configured by using is also known. In this system, the arithmetic processing is shared by the plurality of CPUs, and the arithmetic processing is coordinated among the plurality of CPUs. In this way, when the electronic control unit is composed of a plurality of CPUs,
A control program and control data are required for each CPU.

[0003]

Generally, an electronic control device having a CPU is equipped with an interface circuit for rewriting the control program and the control data in preparation for version up of the control program or control data executed by the CPU. To be Electronic control unit has multiple C
In the case of the PU, a plurality of interface circuits are required according to the number of CPUs, which leads to an increase in the cost of the device.

An object of the present invention is to provide at low cost an electronic control device capable of rewriting programs and data for a plurality of CPUs.

[0005]

(1) An electronic control device according to a first aspect of the present invention includes a first non-volatile memory circuit for storing at least a first execution program and a first volatile memory circuit. A first arithmetic circuit that executes the first execution program, a second non-volatile memory circuit that stores at least the second execution program, and a second volatile memory circuit. A second arithmetic circuit that executes the execution program, a communication path that communicates between the first arithmetic circuit and the second arithmetic circuit, and communication between the first arithmetic circuit and an external device. An interface circuit and a control circuit for transferring data and / or an execution program used in the second arithmetic circuit via the interface circuit to the second arithmetic circuit via the first arithmetic circuit and storing the data and / or the execution program By the above To achieve the purpose. (2) The invention according to claim 2 is the electronic control device according to claim 1, wherein the control circuit is
(1) A writing program transmitted from an external device via an interface circuit is stored in a first volatile memory circuit, and (2) a writing program stored in the first volatile memory circuit is a first arithmetic circuit. The first arithmetic circuit data and the second arithmetic circuit data transmitted from the external device through the interface circuit are stored in the first non-volatile memory circuit, respectively. ) First
The execution program of is executed by the first arithmetic circuit, the second arithmetic circuit data stored in the first nonvolatile memory circuit is stored in the second volatile memory circuit via the communication path, and (2 )
The first arithmetic circuit data stored in the first non-volatile memory circuit is used in the first arithmetic circuit, (3) the second execution program is executed in the second arithmetic circuit, and (4) It is characterized in that the first arithmetic circuit and the second arithmetic circuit are controlled so that the second arithmetic circuit data stored in the second volatile memory circuit is used in the second arithmetic circuit. (3) The invention according to claim 3 is the electronic control device according to claim 1, wherein the control circuit is
(1) A first writing program stored in the first volatile memory circuit, which is transmitted from an external device through the interface circuit, and (2) A first writing program stored in the first volatile memory circuit. Is executed by the first arithmetic circuit and transmitted from the external device through the interface circuit, the first arithmetic circuit data, the second arithmetic program, the second arithmetic circuit data, and The second write program is stored in the first non-volatile storage circuit, respectively, and (3) the second write program stored in the first non-volatile storage circuit is transferred to the second volatile storage circuit via a communication path. And (4) the second write program stored in the second volatile storage circuit is executed by the second arithmetic circuit to execute the first
The second execution program and the second arithmetic circuit data stored in the nonvolatile storage circuit of the second storage device via the communication path.
In the non-volatile memory circuit, and when the normal mode is started, (1) the first execution program stored in the first non-volatile memory circuit is executed by the first arithmetic circuit, and (2) the first arithmetic circuit. The first arithmetic circuit data stored in the non-volatile memory circuit is used in the first arithmetic circuit, and (3) the second execution program stored in the second non-volatile memory circuit is used as the second arithmetic circuit. (4) The second non-volatile memory circuit stored in the second non-volatile memory circuit.
The first arithmetic circuit and the second arithmetic circuit are controlled so that the arithmetic circuit data of (1) is used in the second arithmetic circuit. (4) The invention according to claim 4 is the electronic control device according to claim 1, wherein the control circuit is
(1) A first writing program stored in the first volatile memory circuit, which is transmitted from an external device through the interface circuit, and (2) A first writing program stored in the first volatile memory circuit. Is stored in the first non-volatile memory circuit, and the first execution program and the first arithmetic circuit data transmitted from the external device through the interface circuit are stored in the first non-volatile memory circuit. The second writing program transmitted from the external device via the interface circuit is stored in the second volatile memory circuit via the communication path, and (4) the second volatile memory circuit is stored in the second volatile memory circuit. A second non-volatile memory circuit that executes the write program by the second arithmetic circuit and transmits the second execution program and the second arithmetic circuit data transmitted from the external device through the interface circuit through the communication path. Each stored, the normal mode startup, (1) a first executable program stored in the first non-volatile storage circuit is performed in the first arithmetic circuit, (2)
The first arithmetic circuit data stored in the first nonvolatile memory circuit is used in the first arithmetic circuit, and (3) the second execution program stored in the second nonvolatile memory circuit is used as the second execution program. (4) The first arithmetic circuit and the second arithmetic circuit so that the second arithmetic circuit data stored in the second non-volatile memory circuit is used in the second arithmetic circuit. It is characterized by controlling.

[0006]

The present invention has the following effects. (1) According to the first aspect of the invention, in the electronic control device including the first arithmetic circuit and the second arithmetic circuit, the data and / or the execution program transmitted from the external device via the interface circuit can be the first. The data is transferred to / stored in the second arithmetic circuit via the arithmetic circuit. As a result, it is possible to rewrite the data and the program with an inexpensive structure as compared with the case where the second arithmetic circuit is also provided with the interface circuit for communicating with the external device. (2) In the invention according to claim 2, the first arithmetic circuit data and the second arithmetic circuit data transmitted from the external device via the interface circuit at the time of starting the write mode are stored in the first arithmetic circuit. In the first non-volatile memory circuit, the second arithmetic circuit data is stored in the second volatile memory circuit of the second arithmetic circuit via the communication path at the time of starting the normal mode. As a result, the arithmetic circuit data can be rewritten with an inexpensive structure. (3) In the invention according to claim 3, the first execution program and data for the first arithmetic circuit transmitted from the external device through the interface circuit at the time of starting the write mode, and the second arithmetic circuit for the second arithmetic circuit. The second execution program and the data are respectively stored in the first nonvolatile memory circuit of the first operation circuit, and the second execution program and the data for the second operation circuit are subjected to the second operation via the communication path. The data is stored in the second non-volatile memory circuit of the circuit.
As a result, the arithmetic circuit execution program and data can be rewritten with an inexpensive configuration. (4) In the invention according to claim 4, the first execution program and data for the first arithmetic circuit transmitted from the external device via the interface circuit at the time of starting the write mode are respectively stored in the first arithmetic circuit of the first arithmetic circuit. The second execution program and the data for the second arithmetic circuit, which are stored in the first non-volatile memory circuit and are transmitted from the external device through the interface circuit, are respectively transmitted through the communication path to the second arithmetic circuit of the second arithmetic circuit. The non-volatile memory circuit is stored. As a result, the operating circuit execution program and data can be rewritten with an inexpensive configuration, and the used capacity of the storage circuit can be increased as compared with the case where the second execution program and data are stored in the first nonvolatile storage circuit. Can be kept low.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a configuration of an electronic control unit according to a first embodiment of the present invention. In FIG. 1, an electronic control unit (ECU) 100 is a first CPU.
It has 103, the 2nd CPU109, and the rewriting interface 102. The electronic control unit 100 controls the drive of the motor 101 based on the signal input from the sensor 105. The CPU 103 is a main CPU, and normally the CPU 103 outputs a drive signal for the motor 101. When the CPU 103 is activated, the CPU
103 performs initialization processing of itself, and when the initialization processing ends, a WD (watch dog) signal 106 is sent to the CPU 109.
To start sending.

The CPU 109 is a sub CPU,
The WD signal 106 transmitted from 103 is monitored. CP
When an abnormality occurs in U103, WD by CPU103
The transmission of signal 106 stops. The CPU 109 transmits the reset output 107 toward the CPU 103 when the elapsed time after the WD signal 106 is no longer received exceeds, for example, 200 msec. This allows the CPU
103 is reset and restarted.

The CPU 103 uses the detection signal x input from the sensor 105 to calculate the drive signal y for the motor 101 by the following equation (1).

[Equation 1] y = Ax + B (1) However, A and B are constants.

The input signal x from the sensor 105 is the CPU
It is also input to 109. The CPU 109 is the CPU 103
The same calculation as the above is performed by the above equation (1), and the calculation result is transmitted to the CPU 103 via the communication line 108. CPU103
Compares the calculation result of the CPU 103 itself (denoted as y1) with the calculation result transmitted from the CPU 109 (denoted as y2), and outputs the drive signal y to the motor 101 only when both match. The CPU 103 does not output the drive signal y to the motor 101 when the calculation results by the CPU 103 itself and the CPU 109 do not match. As a result, the drive control for the motor 101 is stopped.

The CPU 103 has a non-volatile memory 104 and a RAM 120 inside. Non-volatile memory 1
04 is constituted by a flash memory, for example. The non-volatile memory 104 includes an application program executed by the CPU 103, constant data for the CPU 103 including the above A and B used for the calculation by the CPU 103, and the above A and B used for the calculation by the CPU 109. The constant data for the CPU 109 is stored. RAM1
20 is used as a work area by the CPU 103, and also stores a write control program described later.

Writing of programs and data to the non-volatile memory 104 is performed by the rewriting interface 10.
2 is performed by connecting the rewriting host computer 500. For example, a case where the constant data for the CPU 103 and the constant data for the CPU 109 stored in the nonvolatile memory 104 are rewritten will be described as an example. When a rewrite command is input to the rewrite host computer 500 with the write control program, the constant data for the CPU 103, and the constant data for the CPU 109 set in the rewrite host computer 500,
The rewrite host computer 500 sends a rewrite start signal to the CPU 1 via the rewrite interface 102.
Send to 03.

When the CPU 103 receives the rewrite start signal, it switches to the rewrite mode. When the rewriting host computer 500 transmits the writing control program to the CPU 103 via the rewriting interface 102, the CPU 103 receives this program and the RAM 103
It is stored in 120. By the CPU 103 executing the write control program transferred to the RAM 120,
The constant data for the CPU 103 and the constant data for the CPU 109 are rewritten from the host computer 500 to the CPU.
It is transferred to 103 via the rewriting interface 102. The CPU 103 overwrites (updates data) the transferred constant data for the CPU 103 and the transferred constant data for the CPU 109 in the nonvolatile memory 104, respectively.
The CPU 103 and the CPU 109 end the rewrite mode and return to the normal mode.

The CPU 109 has a RAM 110 inside.
And a non-volatile memory 111. Non-volatile memory 1
An application program executed by the CPU 109 is stored in 11. The RAM 110 is the CPU 10
CPU 109 including the above-mentioned A and B which is used as a work area by CPU 9 and is also used for calculation in CPU 109
Stores constant data for use. In the first embodiment, C
The PU 109 constant data is not saved in the CPU 109 when the power is turned off.

The writing of data to the RAM 110 is performed every time the electronic control unit 100 is activated in the normal mode. When the initialization process at startup is completed, the CPU 103 sends the CPU 109 before starting the transmission of the WD signal 106.
Constant data for transmission to the CPU 109 via the communication line 108. The CPU 109 stores the input constant data for the CPU 109 in the RAM 110.

The constant data for the CPU 109 includes the CPU
Data C indicating the time required for the initialization processing of the CPU 103 itself by the 103 is also included. Also, the CPU 109
It also includes data indicating the elapsed time (200 msec in the above example) until the D signal 106 is monitored and the reset output 107 is transmitted.

Both CPUs of the electronic control unit 100 described above
The flow of processing by the program executed in 103 and the CPU 109 in the normal mode will be described with reference to the flowcharts of FIGS. 2 and 3. FIG. 2 is a flowchart showing the processing performed by the CPU 103. In step S2101 of FIG. 2, the CPU 103 executes the initialization process 1
And go to step S2102. Step S210
2, the CPU 103 transmits constant data (A, B, and C) to the CPU 109, respectively, and the step S2
Go to 103. In step S2103, the CPU1
03 performs the initialization process 2, and progresses to step S2104.

In step S2104, the CPU 10
3 inputs the signal x from the sensor 105 and performs step S
Proceed to 2105. In step S2105, the CPU
The 103 calculates the drive signal y1 by the above equation (1), and proceeds to step S2106. In step S2106, the CPU 103 causes the drive signal y2 from the CPU 109.
Is received and the process proceeds to step S2107. Step S21
At 07, the CPU 103 determines whether or not y1 = y2 holds. The CPU 103 makes an affirmative decision in step S2107 if y1 = y2 is true to proceed to step S2108, and makes a negative decision in step S2107 if y1 = y2 is not true to proceed to step S2109.

In step S2108, the CPU 10
3 outputs the drive signal y (= y1) to the motor 101 and returns to step S2104. On the other hand, the CPU 103 stops the output of the drive signal y and returns to step S2104.

FIG. 3 is a flowchart showing the processing performed by the CPU 109. In step S2201 of FIG. 3, the CPU 109 starts counting the time of the initialization waiting timer, and proceeds to step S2202. Step S2202
In step S2, the CPU 109 receives constant data (A, B, and C) from the CPU 103, respectively.
Go to 203. In step S2203, CPU1
At 09, it is determined whether or not the time measured by the initialization waiting timer has passed the time corresponding to the data C. CPU109
Is affirmatively determined in step S2203 when the time measured by the timer has passed the time in the data C, the step S2
In step 204, the determination process is repeated when the time measured by the timer is less than the time measured by the data C.

In step S2204, the CPU 10
9 starts the counting of the timer waiting for the WD signal 106, and proceeds to step S2205. In step S2205, the CPU 109 determines whether or not the WD signal 106 has been received from the CPU 103. When the WD signal 106 is received, the CPU 109 makes an affirmative decision in step S2205 to proceed to step S2206, and when the WD signal 106 is not received makes a negative decision in step S2205 and proceeds to step S2207.

In step S2206, the CPU 10
9 resets the clocking of the timer waiting for the WD signal 106 and proceeds to step S2207. In step S2207, the CPU 109 determines whether or not the time measured by the timer waiting for the WD signal 106 has passed 200 msec.
When the timer counts 200 msec, the CPU 109 makes an affirmative decision in step S2207 and advances to step S2211, where the timer counts 200 msec.
If not, step S2207 is denied and the process proceeds to step S2208. In step S2211, the CPU 109 outputs the reset output 107 to the CPU 10.
3 and returns to step S2201.

In step S2208, the CPU 10
9 inputs the signal x from the sensor 105 to perform step S
Proceed to 2209. In step S2209, the CPU
109 calculates the drive signal y2 by the above equation (1), and proceeds to step S2210. In step S2210, CPU 109 transmits drive signal y2 to CPU 103 and returns to step S2205.

According to the first embodiment described above,
The following effects can be obtained. (1) The write control program for the main CPU 103 is stored in the RAM 120 of the main CPU 103 from the rewrite host computer 500 via the rewrite interface 102, and the main CPU 103 is caused to execute this write control program. By executing the write control program, the non-volatile memory 104 of the main CPU 103
The constant data of the sub CPU 109 stored in the sub CPU 109 is transferred to the sub CPU 109 via the communication line 108 and stored in the RAM.
Written in 110. As a result, it becomes possible to rewrite the constant data for the sub CPU 109 used for the calculation in the sub CPU 109 not having the rewriting interface. (2) Sub CPU10 constant data for the sub CPU109
Since the data is stored in the RAM 110 in 9, the sub C
A non-volatile memory for constant data can be eliminated in the PU 109. Further, since there is only one rewriting interface 102, the constant data of both the main CPU 103 and the sub CPU 109 can be rewritten, so that the device can be constructed at low cost. Further, compared with the case where the constant data for the main CPU 103 and the constant data for the sub CPU 109 are respectively rewritten using a plurality of rewriting interfaces, the labor and time required for rewriting can be reduced. (3) Similar to the constants A and B, the data indicating the waiting time C of the sub CPU 109 is also written in the nonvolatile memory 104 of the main CPU 103, transferred to the RAM 110, and the data of the waiting time C is updated. . As a result, even when the initialization time of the main CPU 103 is changed, the waiting time C of the sub CPU 109 can be easily changed according to the changed initialization time.

In the above description, the nonvolatile memory 104
Constant data and CP for CPU103 stored in
The case where the constant data for U109 is rewritten has been described as an example. Similarly, the application program executed by the CPU 103 can be rewritten. In this case, the rewrite command may be input to the rewrite host computer 500 with the write control program and the application program for the CPU 103 set in the rewrite host computer 500. When the rewrite command is input, the rewrite host computer 500 transmits a rewrite start signal to the CPU 103 via the rewrite interface 102.

Upon receiving the rewrite start signal, the main CPU 103 switches to the rewrite mode, receives the write control program transmitted from the rewrite host computer 500, and stores it in the RAM 120. CPU10
3 executes the write control program transferred into the RAM 120 and rewrites the application program for the CPU 103 and receives it from the host computer 500. The CPU 103 overwrites the received application program in the nonvolatile memory 104 (updates the program data).

(Second Embodiment) In the second embodiment, the application program of the sub CPU is once stored in the non-volatile memory in the main CPU, and the application program for the sub CPU is also rewritten.
FIG. 4 is a diagram showing the configuration of the electronic control device according to the second embodiment of the present invention. In FIG. 4, an electronic control unit (ECU) 300 includes a CPU 303 and a CPU 108.
And a rewrite interface 302. Similar to the first embodiment, the electronic control unit 300 controls the drive of a motor (not shown) based on a signal input from a sensor (not shown). CPU 303 is the main CPU
In general, the CPU 303 outputs a drive signal for the motor.

The CPU 303 has a non-volatile memory 304 and a RAM 320 inside. Non-volatile memory 3
Reference numeral 04 denotes an application program executed by the CPU 303, constant data for the CPU 303 including the above-mentioned A and B used for calculation by the CPU 303, and a CPU
A CPU 308 including a write control program for 308, an application program executed by the CPU 308, and the above-described A and B used for calculation in the CPU 308.
And constant data for each are stored. RAM320
Is used as a work area by the CPU 303,
A write control program for the CPU 303 is stored.

Writing of programs and data to the non-volatile memory 304 is performed by the rewriting interface 30.
2 is performed by connecting the rewriting host computer 600. For example, the application program for the CPU 303 and the CP stored in the non-volatile memory 304
An example will be described in which the constant data for U303, the application program for the CPU 308, and the constant data for the CPU 308 are rewritten. Rewrite to the rewrite host computer 600 with the application program and constant data for the CPU 303, the application program and constant data for the CPU 308, the write control program for the CPU 303, and the write control program for the CPU 308 set in the rewrite host computer 600. When a command is input, the rewrite host computer 600 sends a rewrite start signal to the CPU 30 via the rewrite interface 302.
Send to 3.

Upon receiving the rewriting start signal, the CPU 303 switches to the rewriting mode. The rewrite host computer 600 writes the write control program for the CPU 303 to the CPU 30 via the rewrite interface 302.
3, the CPU 303 receives this program and stores it in the RAM 320. CPU303 is RAM
By executing the CPU 303 write control program transferred into 320, the application program and constant data for the CPU 303, the application program and constant data for the CPU 308, and the CPU
The write control program for 308 is transferred from the rewrite host computer 600 to the rewrite interface 302.
Are respectively transferred to the CPU 303 via. CPU3
Reference numeral 03 denotes the transferred application program and constant data for the CPU 303, the application program and constant data for the CPU 308, and the CPU 308.
The write control program for each is overwritten in the nonvolatile memory 304 (data update).

The CPU 308 internally has a RAM 309.
And a non-volatile memory 310. Non-volatile memory 3
Reference numeral 10 denotes an application program executed by the CPU 308 and the CPU 3 used by the CPU 308 for calculation.
08 constant data is stored. RAM309 is C
CPU used in addition to work area by PU308
A write control program for 308 is stored.

Writing to the non-volatile memory 310 is performed as follows. The CPU 303 is an application program and constant data for the CPU 308 transmitted from the rewriting host computer 600, and C
Write control program for PU308 to non-volatile memory 3
When the data is written in 04, a rewrite start signal is sent to the communication line 307
To the CPU 308 via.

When the CPU 308 receives the rewriting start signal, it switches to the rewriting mode. The CPU 303 stores the CPU 308 write control program stored in the non-volatile memory 304 via the communication line 307.
8, the CPU 308 receives this program and stores it in the RAM 309. CPU308 is RAM
By executing the CPU 308 write control program transferred to the CPU 309, the application program for the CPU 308 and the constant data in the nonvolatile memory 304 are transferred to the CPU 308 via the communication line 307 and stored in the nonvolatile memory 310. Overwritten (data updated). As described above, the CPU 303 and the CPU 308 end the rewrite mode and return to the normal mode.

According to the second embodiment described above,
In the non-volatile memory 304 of the main CPU 303, the rewrite host computer 600 stores the write control program for the sub CPU 308 via the rewrite interface 302, and transfers the write control program to the RAM 309 of the sub CPU 308 via the communication line 307. The transferred write control program is stored in the sub CPU 308.
To run. By executing the write control program for the CPU 308, the main CPU 3 from the rewrite host computer 600 via the rewrite interface 302.
03 sub-CP stored in the non-volatile memory 304
U308 application program, sub CPU3
The constant data for 08 is transferred to the sub CPU 308 via the communication line 307, respectively, and is overwritten (updated) in the nonvolatile memory 310. This allows rewriting of the non-volatile memory 310 in the sub CPU 308 that does not have a rewriting interface.

According to the second embodiment described above,
The sub CP is stored in the non-volatile memory 304 in the CPU 303.
U308 application program and constant data,
Although the write control program for the sub CPU 308 is still stored, these may be erased as needed after the transfer to the sub CPU 308 is completed.

(Third Embodiment) The third embodiment is a case where the non-volatile memory in the main CPU has no room and cannot store application programs for the sub CPU. FIG. 5 is a diagram showing a configuration of an electronic control device according to a third embodiment of the present invention.
In FIG. 5, the electronic control unit (ECU) 400 is a CP
It has a U403, a CPU 408, and a rewrite interface 402. The electronic control device 400 performs drive control for a motor (not shown) based on a signal input from a sensor (not shown), as in the first and second embodiments. The CPU 403 is a main CPU, and normally the CPU 403 outputs a drive signal for the motor.

The CPU 403 has a nonvolatile memory 404 and a RAM 420 inside. Non-volatile memory 4
Reference numeral 04 denotes an application program executed by the CPU 403, and a CPU used for calculation by the CPU 403.
The constant data for 403 are stored respectively. RAM4
20 is used as a work area by the CPU 403 and also stores a write control program for the CPU 403.

Writing of programs and data to the non-volatile memory 404 is performed by the rewriting interface 40.
2 is performed by connecting the rewriting host computer 700. For example, the application program for the CPU 403 and the CP stored in the non-volatile memory 404
The case of rewriting the constant data for U403, the application program for the CPU 408 and the constant data for the CPU 408 will be described as an example. Rewrite to the rewrite host computer 700 with the application program and constant data for the CPU 403, the application program and constant data for the CPU 408, the write control program for the CPU 403, and the write control program for the CPU 408 set in the rewrite host computer 700. When a command is input, the rewrite host computer 700 sends a rewrite start signal to the CPU 40 via the rewrite interface 402.
Send to 3.

When the CPU 403 receives the rewriting start signal, it switches to the rewriting mode. The rewrite host computer 700 writes the write control program for the CPU 403 via the rewrite interface 402 to the CPU 40.
3, the CPU 403 receives this program and stores it in the RAM 420. CPU403 is RAM
By executing the CPU 403 write control program transferred in 420, the application program for CPU 403 and constant data are transferred from the rewriting host computer 700 to the rewriting interface 40.
2 to the CPU 403 respectively. CPU
The 403 overwrites (updates the data) the transferred application program for the CPU 403 and the constant data in the nonvolatile memory 404, respectively.

The CPU 408 has a RAM 409 inside.
And a non-volatile memory 410. Non-volatile memory 4
Reference numeral 10 denotes an application program executed by the CPU 408 and the CPU 4 used by the CPU 408 for calculation.
08 constant data is stored. RAM409 is C
In addition to being used as a work area by the PU 408, a CPU
A write control program for 408 is stored.

Writing to the non-volatile memory 410 is performed as follows. The CPU 403 writes the application program for the CPU 403 and the constant data transmitted from the rewriting host computer 700 in the non-volatile memory 404, and then transmits a rewriting start signal to the CPU 408 via the communication line 407.

When the CPU 408 receives the rewrite start signal, it switches to the rewrite mode. The CPU 403 communicates with the rewriting host computer 700, and the CPU 40
8 write control program is received from the rewrite host computer 700 via the rewrite interface 402, and the received program is transmitted via the communication line 407 to C
Transfer to PU 408. The CPU 408 is the communication line 407.
The program transferred via is stored in the RAM 409. CPU transferred from CPU 408 to RAM 409
By executing the write control program for 408,
The application program and constant data for the CPU 408 in the rewriting host computer 700 are written in the rewriting interface 402 → CPU 403 → communication line 4
It is transferred to the CPU 408 via 07.

The CPU 408 is the transferred CPU 408.
The application program for use with the constant data is overwritten in the non-volatile memory 410 (data update). As described above, the CPU 403 and the CPU 408 end the rewrite mode and return to the normal mode. In the operation described above, the CPU 403 is the rewriting host computer 7
00 and the CPU 408. That is, the CPU 403 temporarily stores a predetermined amount of programs and data input from the rewriting interface 402 in the RAM 420, and a predetermined amount of programs and data stored in the RAM 420 for each communication line 407.
The operation of transmitting data from the CPU to the CPU 408 is repeated.

According to the third embodiment described above,
Rewriting the main CPU 403 Host computer 70
0 as a gateway between the sub CPU 408 and the sub CPU 408 in the RAM 409.
The write control program for 408 is transferred and the sub CPU 408 executes this write control program. Sub C
By executing the writing control program for the PU 408, the sub C stored in the rewriting host computer 700
PU408 application program and sub CPU
The constant data for 408 is transferred to the sub CPU 408 via the rewriting interface 402 → main CPU 403 → communication line 407, and is overwritten (data update) in the non-volatile memory 410 in the sub CPU 408. As a result, the non-volatile memory 40 in the main CPU 403
4, it becomes possible to rewrite the non-volatile memory 410 in the sub CPU 408 that does not have a rewriting interface when the free space is small.

Correspondence between each component in the claims and each component in the embodiment of the invention will be described. An application program corresponds to the execution program. The arithmetic circuit data corresponds to constant data. The first arithmetic circuit is composed of, for example, a main CPU. The second arithmetic circuit is, for example, a sub C
It is composed of PU. The first nonvolatile memory circuit is
For example, it is configured by a non-volatile memory on the main CPU side. The first volatile storage circuit is composed of, for example, a RAM on the main CPU side. The second non-volatile memory circuit is composed of, for example, a non-volatile memory on the sub CPU side. The second volatile storage circuit is composed of, for example, a RAM on the sub CPU side. The communication path is composed of, for example, a communication line. The interface circuit is composed of, for example, a rewrite interface. The external device is composed of, for example, a rewriting host computer. The control circuit
For example, it is composed of a main CPU and a sub CPU. The write mode corresponds to the rewrite mode.
Note that each component is not limited to the above configuration as long as the characteristic function of the present invention is not impaired.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an electronic control device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a flow of processing by a program executed by a main CPU.

FIG. 3 is a flowchart showing a flow of processing by a program executed by a sub CPU.

FIG. 4 is a diagram showing a configuration of an electronic control device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of an electronic control device according to a third embodiment of the present invention.

[Explanation of symbols]

100, 300, 400 ... Electronic control device, 101 ... Motor, 102, 302, 402 ... Rewriting interface, 103, 303, 403 ... Main CPU, 105 ...
Sensor, 104,111,304,310,404,410
... Non-volatile memory, 108, 307, 407 ... Communication line, 1
09,308,408 ... Sub CPU, 110, 120, 30
9,320,409,420 ... RAM

Claims (4)

[Claims] 1. A first arithmetic circuit having at least a first non-volatile memory circuit for storing a first execution program and a first volatile memory circuit, the first arithmetic circuit executing the first execution program, A second arithmetic circuit having at least a second non-volatile memory circuit for storing a second execution program and a second volatile memory circuit for executing the second execution program; and the first arithmetic operation. A communication path for communicating between a circuit and the second arithmetic circuit, an interface circuit for communicating between the first arithmetic circuit and an external device, and the second arithmetic via the interface circuit. An electronic control device comprising: a control circuit that transfers data used in a circuit and / or an execution program to the second arithmetic circuit via the first arithmetic circuit to store the data. 2. The electronic control device according to claim 1, wherein the control circuit, when the write mode is activated, (1) writes the write program transmitted from the external device through the interface circuit to the first volatilization device. Stored in a first memory circuit, and (2) the write program stored in the first volatile memory circuit is executed by the first arithmetic circuit and transmitted from the external device through the interface circuit. The first arithmetic circuit data and the second arithmetic circuit data are respectively stored in the first non-volatile memory circuit, and when the normal mode is activated, (1) the first execution program is executed by the first arithmetic circuit. Storing the second arithmetic circuit data, which is executed by a circuit and stored in the first non-volatile memory circuit, in the second volatile memory circuit via the communication path, (2)
The first arithmetic circuit data stored in the first non-volatile memory circuit is used in the first arithmetic circuit, and (3) the second execution program is executed in the second arithmetic circuit. (4) The first arithmetic circuit and the second arithmetic circuit are arranged so that the second arithmetic circuit data stored in the second volatile memory circuit is used in the second arithmetic circuit. An electronic control device characterized by controlling. 3. The electronic control device according to claim 1, wherein the control circuit, when the write mode is activated, (1) executes the first write program transmitted from the external device via the interface circuit. (1) executing the first write program stored in the first volatile storage circuit on the first arithmetic circuit to execute the interface circuit from the external device. The first execution program, the first arithmetic circuit data, the second execution program, the second arithmetic circuit data, and the second write program transmitted via the first non-volatile (3) storing the second write program stored in the storage circuit, respectively, in the storage circuit, and storing the second write program stored in the first non-volatile storage circuit in the second volatile storage circuit via the communication path; The above The second write program stored in the second volatile storage circuit is executed by the second arithmetic circuit, and the second execution program and the second stored in the first non-volatile storage circuit. The arithmetic circuit data is stored in the second non-volatile memory circuit via the communication path, and when the normal mode is activated, (1) the first execution stored in the first non-volatile memory circuit is performed. Executing a program in the first arithmetic circuit, (2) using the first arithmetic circuit data stored in the first nonvolatile memory circuit in the first arithmetic circuit, (3) the above Executing the second execution program stored in the second non-volatile memory circuit by the second arithmetic circuit, and (4) for the second arithmetic circuit stored in the second non-volatile memory circuit. The first operation so that data is used in the second operation circuit. An electronic control unit controlling a circuit and the second arithmetic circuit. 4. The electronic control device according to claim 1, wherein the control circuit, when the write mode is activated, (1) executes the first write program transmitted from the external device via the interface circuit. (1) executing the first write program stored in the first volatile storage circuit on the first arithmetic circuit to execute the interface circuit from the external device. The first execution program and the data for the first arithmetic circuit, which are transmitted via the interface circuit, are stored in the first non-volatile memory circuit, respectively, and are transmitted from the external device via the interface circuit. Storing a second write program in the second volatile storage circuit via the communication path;
(4) The second execution executed by the second arithmetic circuit to execute the second write program stored in the second volatile storage circuit and transmitted from the external device via the interface circuit. The program and the data for the second arithmetic circuit are respectively stored in the second non-volatile storage circuit via the communication path, and at the time of starting the normal mode, (1) stored in the first non-volatile storage circuit. The first execution program is executed by the first arithmetic circuit, and (2) the first arithmetic circuit data stored in the first nonvolatile memory circuit is used by the first arithmetic circuit. , (3) the second
The second execution program stored in the non-volatile memory circuit is executed by the second arithmetic circuit, and (4) the second arithmetic circuit data stored in the second non-volatile memory circuit is stored. An electronic control device, which controls the first arithmetic circuit and the second arithmetic circuit so as to be used in the second arithmetic circuit.