JP2003140567A - Light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for improving the characteristics of a TFT (thin film transistor) and realizing the optimum structure of the TFT for the driving condition of a pixel section and a drive circuit by using a smaller num ber of photo masks. SOLUTION: A light emitting device is provided with a semiconductor film, a first electrode and a first insulation film which is nipped between the semiconductor film and the first electrode. Moreover, the light emitting device is provided with a second electrode and a second insulation film which is nipped between the semiconductor film and the second electrode. The first and the second electrodes are overlapped with each other through a channel forming area of the semiconductor film. In the case of the TFT in which reduction in off-current is considered to be more important that the increase in on-current, a constant voltage (a common voltage) is always applied to the first electrode. In the case of the TFT in which the increase in the on-current is considered to be more important that the reduction in the off-current, the same voltage is applied to the first and the second electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a light emitting element (OLED: Organic Light Emitting Device) formed on a plastic substrate.
The present invention relates to a light emitting device. The present invention also relates to an OLED module in which an IC including a controller is mounted on the OLED panel. In this specification, the OLED panel and the OLED module are collectively referred to as a light emitting device. The invention further relates to an electronic device using the light emitting device.

[0002]

2. Description of the Related Art In recent years, a technique for forming a TFT (thin film transistor) on a substrate has made great progress, and its application and development to an active matrix type display device has been advanced. In particular,
Since a TFT using a polysilicon film has a higher field effect mobility (also referred to as mobility) than a conventional TFT using an amorphous silicon film, high speed operation is possible.
Therefore, it is possible to control a pixel, which has been conventionally performed by a drive circuit outside the substrate, by a drive circuit formed on the same substrate as the pixel.

Such an active matrix type display device has various advantages such as reduction of manufacturing cost, miniaturization of display device, increase of yield, reduction of throughput, etc. by forming various circuits and elements on the same substrate. Is obtained.

Further, OLE is used as a self-luminous element.
Active matrix light-emitting devices having D (hereinafter, simply referred to as light-emitting devices) have been actively researched. The light emitting device is an organic light emitting device (OELD: Organic EL Display) or an organic light emitting diode (OLED: Orga).
nic Light Emitting Diode) is also called.

Since the OLED emits light by itself, it has a high visibility, does not require a backlight required for a liquid crystal display (LCD), is suitable for thinning, and has no limitation on a viewing angle. Therefore, in recent years, a light emitting device using an OLED is a CR
It is receiving attention as a display device that replaces the T and LCD.

[0006] The OLED has a layer containing an organic light emitting material (hereinafter referred to as an organic light emitting layer) capable of obtaining luminescence generated by applying an electric field (hereinafter referred to as an organic light emitting layer), an anode layer, and a cathode layer. The organic light emitting layer is provided between the anode and the cathode and is composed of a single layer or a plurality of layers. Luminescence in the organic light emitting layer includes light emission when returning from a singlet excited state to a ground state (fluorescence) and light emission when returning from a triplet excited state to a ground state (phosphorescence).

In the present specification, all layers formed between the anode and the cathode of the OLED are defined as organic light emitting layers.
The organic light emitting layer specifically includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, an OLED has a structure in which an anode, a light emitting layer, and a cathode are laminated in this order, and in addition to this structure, an anode / hole injection layer /
It may have a structure in which a light emitting layer / cathode or an anode / hole injection layer / light emitting layer / electron transport layer / cathode are laminated in this order.

[0008]

By the way, as one form of a light emitting device, an active matrix drive system is known in which a TFT is provided for each pixel and an image is displayed by sequentially writing a video signal. The TFT is an essential element for realizing the active matrix driving method.

Most of the TFTs are made of amorphous silicon, but the TFTs made of amorphous silicon have a low electric field effect mobility and have a frequency necessary for processing a video signal. Since it could not be operated, it was used exclusively as a switching element provided for each pixel. A data line side driving circuit that outputs a video signal to the data line and a scanning line side driving circuit that outputs a scanning signal to the scanning line are TAB (Tape Automated Bonding) and C.
It was covered by an external IC (driver IC) mounted by OG (Chip on Glass).

However, since the pixel pitch becomes narrower as the pixel density increases, it is considered that the method of mounting the driver IC has a limit. For example, in the case of UXGA (1200 × 1600 pixels), the RGB color system requires 6000 connection terminals even if simply estimated. An increase in the number of connecting terminals causes an increase in the probability of contact failure. In addition, the area (frame area) in the peripheral portion of the pixel portion is increased, which becomes a factor of impairing the miniaturization and external design of a semiconductor device using this as a display. From this background, the need for a display device integrated with a drive circuit has become clear. By integrally forming the pixel portion and the scanning line side and data line side driving circuits on the same substrate, the number of connection terminals can be drastically reduced and the area of the frame region can be reduced.

As a means for achieving this, a method of forming a TFT with a polycrystalline silicon film has been proposed. However, even if a TFT is formed by using polycrystalline silicon, the electrical characteristics of the TFT will be limited to the MO formed on the single crystal silicon substrate.
It was not comparable to the characteristics of the S-transistor. For example, the field effect mobility is 1/10 or less that of single crystal silicon. In addition, there is a problem that off-state current becomes high due to defects formed at crystal grain boundaries.

Generally, in a light emitting device, at least a TFT functioning as a switching element and a TFT for supplying a current to an OLED are provided in each pixel.
While a low off-current (I _off ) is required for the TFT that functions as a switching element, a TFT for supplying a current to the OLED has a high driving capability (on-current,
(I _on ), and prevention of deterioration due to hot carrier effect and improvement of reliability are required. In addition, the TFT of the data line side driving circuit also has a high driving ability (ON current, I _on ).
Also, it is required to prevent deterioration due to the hot carrier effect and improve reliability.

As a TFT structure for reducing the off current value, a lightly doped drain (LDD) is used.
n) The structure is known. In this structure, an LDD region added with an impurity element at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. Further, as an effective structure for preventing the deterioration of the on-current value due to hot carriers, an LD in which a part of the LDD region overlaps the gate electrode
The D structure (hereinafter, Gate-drain Overlapped LDD is abbreviated as GOLD) is known.

The TFT is manufactured by laminating a semiconductor film, an insulating film, or a conductive film while etching them into a predetermined shape using a photomask. However, if the structure of the TFT is optimized in order to obtain the characteristics required for the pixel portion and each drive circuit, the number of photomasks increases, the manufacturing process becomes complicated, and the number of processes inevitably increases.

Another object of the present invention is to provide a technique for improving the characteristics of the TFT and realizing a TFT having a structure optimal for the driving conditions of the pixel portion and the driving circuit with a small number of photomasks.

[0016]

In order to solve the above problems, a thin film transistor included in a light emitting device of the present invention is
A semiconductor film, a first electrode, and a first insulating film sandwiched between the semiconductor film and the first electrode, and a second electrode
Electrode and a second insulating film sandwiched between the semiconductor film and the second electrode. Then, the first electrode and the second electrode overlap with each other with the channel formation region included in the semiconductor film interposed therebetween.

In the present invention, in the case of a TFT used as a switching element in which reduction of off-current is more important than increase of on-current, a constant voltage (common voltage) is always applied to the first electrode. In addition, this constant voltage is
In the case of an n-channel TFT, it is smaller than the threshold, and in the case of a p-channel TFT, it is larger than the threshold.

By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

Further, in the present invention, the increase of the on-current is more important than the decrease of the off-current. For example, in the case of a TFT included in a buffer of a driving circuit, the same voltage is applied to the first electrode and the second electrode. Apply.

In this specification, the drive circuit is a circuit for generating a signal for displaying an image in the pixel portion, and includes a data line drive circuit and a scanning line drive circuit.

By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same way as when the thickness of the semiconductor film is made thin, so that the subthreshold coefficient (S value) is increased. ) Can be reduced, and the field effect mobility can be further improved. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Further, it is possible to suppress variation in threshold value as compared with the case where there is one electrode. Therefore, by using the TFT having this structure in the drive circuit, the drive voltage can be lowered. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

A circuit diagram of the thin film transistor of the present invention will be described with reference to FIG. Here, only the p-channel TFT is shown as a representative. In the case of the n-channel TFT, the arrow direction is opposite to that in the case of the p-channel TFT. FIG. 30A is a circuit diagram of a general thin film transistor having only one electrode. FIG. 30B is a circuit diagram of a thin film transistor of the invention which has two electrodes with a semiconductor film sandwiched between them and a constant voltage (here, a ground voltage) is applied to one electrode. is there. Figure 3
0 (C) has two electrodes sandwiching a semiconductor film,
Furthermore, the two electrodes are electrically connected to each other,
It is a circuit diagram of a thin film transistor of the present invention. In the following description of the present invention, the circuit diagram shown in FIG. 30 is used.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIG. In FIG. 1A, a first electrode 11 is formed on a substrate 10 having an insulating surface.
The first electrode 11 may be made of a conductive material. Typically, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta),
It can be formed of an alloy or compound composed of one or more selected from titanium (Ti). Alternatively, a stack of several conductive films may be used as the first electrode. The first electrode 11 has a thickness of 150 to 400 nm.

A first insulating film 12 is formed so as to cover the first electrode 11. Note that in this embodiment mode, two layers of insulating films (a first insulating film A 12a and a first insulating film B 12) are used.
A laminate of b) is used as the first insulating film 12. In FIG. 1, a silicon oxynitride film or a silicon nitride film is formed with a thickness of 10 to 50 nm as the first insulating film A 12a. The first insulating film B 12b is a silicon oxynitride film or a silicon oxide film and is formed to a thickness of 0.5 to 1 μm. When a silicon oxynitride film is used, a film formed by a plasma CVD method from a mixed gas of SiH ₄ , NH ₃ , and N ₂ O and containing 20 to 40 atomic% of nitrogen is used. By using a nitrogen-containing insulating film such as a silicon oxynitride film or a silicon nitride film, diffusion of impurities such as alkali metal from the substrate 10 side can be prevented.

The surface of the first insulating film 12 may have irregularities due to the first electrode 11 previously formed. The unevenness is flattened by polishing the surface.
Chemical-mechanical polishing (Chemical-Mecha
nical Polishing: hereinafter referred to as CMP). As the CMP polishing agent (slurry) for the first insulating film 12, for example, fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in a KOH-added aqueous solution. The first insulating film is removed by CMP to the extent of 0.1 to 0.5 μm to planarize the surface.
Note that the surface of the first insulating film does not necessarily need to be polished. The level difference of the unevenness on the surface of the planarized first insulating film is preferably 5 nm or less, and more preferably 1 nm or less. The improved flatness makes it possible to reduce the thickness of the first insulating film used as a gate insulating film to be formed later.
The mobility of can be improved. Further, since the flatness is improved, off current can be reduced when a TFT is manufactured.

A semiconductor film 13 is formed on the first insulating film 12 whose surface is flattened. The semiconductor film 13 has a channel forming region 18 and an impurity region 19 sandwiching the channel forming region 18. Then, the semiconductor film 1
A second insulating film 14 is formed on the semiconductor film 3, and the second electrode 1 is formed on the semiconductor film 13 with the second insulating film 14 interposed therebetween.
5 is formed.

The first electrode 11 and the second electrode 15 overlap each other with the channel forming region 18 interposed therebetween.

In addition, the third insulating film 16 and the wiring 17 are provided as needed.

The first electrode 11 and the second electrode 15 may be electrically connected, or a common voltage may be applied to either one of the electrodes.

In FIG. 1A, AA 'when the first electrode 11 and the second electrode 15 are directly connected.
A cross-sectional view of is shown in FIG.

As shown in FIG. 1B, the first electrode 11
The second electrode 15 and the second electrode 15 are connected to each other outside the semiconductor film 13 through a contact hole 21 formed in the first insulating film 12 and the second insulating film 14.

In FIG. 1A, the first electrode 11 and the second electrode 11
1C is a cross-sectional view taken along the line AA ′ in the case where the electrode 15 is connected by a wiring 24 formed of the same conductive film as the wiring 17. Note that in this specification, connection means electrical connection unless otherwise specified.

As shown in FIG. 1C, the first electrode 11
And the wiring 24 form the first insulating film 12 and the second insulating film 14.
And the contact hole 2 formed in the third insulating film 16
3 are connected. Further, the second electrode 15 and the wiring 24 are connected via the contact hole 22 formed in the third insulating film 16.

The method of electrically connecting the first electrode 11 and the second electrode 15 is not limited to the configuration shown in FIGS. 1B and 1C.

The film thickness to be removed by CMP is determined in consideration of the thickness of the first insulating film 12 and its dielectric constant and the thickness of the second insulating film 14. The film remaining here substantially functions as a gate insulating film. Therefore, when the first insulating film is formed by laminating a plurality of insulating films, the first electrode 11
Only the uppermost insulating film may be polished above, or the lower insulating film may be exposed.

For example, the first insulating film A 12a and the first insulating film A 12a
The insulating film B 12b is formed of a silicon oxynitride film and has a dielectric constant of 7.5, and when the second insulating film 14 is formed of a silicon oxide film, the dielectric constant is 3.9, which is different. In that case, the finished dimensions after CMP are preferably such that the thickness of the first insulating film 12 is 150 nm and the thickness of the second insulating film 14 is 110 nm.

By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

The TFT is a top gate type (planar type) depending on the arrangement of the semiconductor film, the gate insulating film and the gate electrode.
And bottom gate type (inverted stagger type) are known.
In any case, it is necessary to reduce the thickness of the semiconductor film in order to reduce the subthreshold coefficient. When a semiconductor film obtained by crystallizing an amorphous semiconductor film is used as in a TFT, the amorphous semiconductor film becomes thin and its crystallinity deteriorates, and the effect of purely reducing the film thickness is obtained. I can't. However, the thickness of the semiconductor film is substantially reduced by electrically connecting the first electrode and the second electrode and overlapping the two electrodes above and below the semiconductor film as shown in FIG. Similarly to the above, it is possible to deplete quickly with the application of voltage, reduce the field effect mobility and the subthreshold coefficient, and increase the on-current.

When the first electrode 11 and the second electrode 15 are electrically connected, the closer the dielectric constants of the first insulating film 12 and the second insulating film 14 are, the closer the electric field The on-current can be increased by decreasing the effect mobility and the subthreshold coefficient.

Further, in the portion where the first electrode 11 and the channel forming region overlap, the film thickness of the first insulating film 12 when the film thickness is uniform, the second electrode 15 and the channel. In the portion where the formation area overlaps, the second
When the thickness of the insulating film 14 is uniform, the closer it is, the smaller the field effect mobility and the subthreshold coefficient and the larger the on-current.
If the film thickness of the first insulating film in the portion overlapping the first electrode 11 is d1 and the film thickness of the second insulating film in the portion overlapping the second electrode 15 is d2, | d1-d2 | / d1 ≦
0.1, and | d1-d2 | / d2 ≦ 0.
It is desirable to satisfy 1. More preferably, | d1-d
2 | /d1≦0.05, and | d1-d2
It is preferable to satisfy | /d2≦0.05.

Most preferably, the first electrode 11 and the second electrode
Of the thin film transistor when the ground voltage is applied to the first electrode 11 and the thin film transistor when the ground voltage is applied to the second electrode 15 in a state where the ground voltage is not electrically connected to the first electrode 11. That is, the first electrode 11 and the second electrode 15 are electrically connected after the thresholds are set to be approximately the same. By doing so, the field effect mobility and the subthreshold coefficient can be further reduced, and the on-current can be further increased.

With this structure, a channel (dual channel) can be formed above and below the semiconductor film,
The characteristics of the TFT can be improved.

Further, wiring for transmitting various signals or electric power can be formed simultaneously with the first electrode 11. Also,
When combined with the planarization treatment by CMP, it does not affect the semiconductor film or the like formed thereover.
In addition, the wiring density can be increased by the multilayer wiring. Hereinafter, specific examples applied to an active matrix light emitting device will be shown by examples.

In the light emitting element used in this embodiment, the hole injecting layer, the electron injecting layer, the hole transporting layer, the electron transporting layer or the like is composed of an inorganic compound alone or an organic compound mixed with an inorganic compound. It can also be in the form of a material. Further, these layers may be partially mixed with each other.

[0045]

EXAMPLES Examples of the present invention will be shown below. Example 1 A process for manufacturing a semiconductor device of the present invention will be described. Here, a method for manufacturing a TFT in the pixel portion will be described in detail. In this embodiment, the common voltage is applied to the first electrode of the TFT (switching TFT) used as the switching element, and the TFT (driving TFT) that controls the current flowing through the light emitting element is the first electrode. An example in which the second electrode is connected is shown. Note that this embodiment describes only a method for manufacturing a TFT in a pixel portion, but a TFT for a driver circuit can be manufactured at the same time.

2 to 5 used in the present embodiment,
6A to 8C are cross-sectional views illustrating the manufacturing process, and FIGS. 6A to 8C are top views corresponding to the cross-sectional views, and the common reference numerals are used for convenience of description.

In FIG. 2A, the substrate 101 can be made of any material as long as it has an insulating surface and can withstand a processing temperature in a later step. Typically, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

A first wiring 105 and first electrodes 103, 104 and 106 are formed on the insulating surface of the substrate 101. The first wiring and the first electrode are made of Al, W, Mo, T
It is formed of a conductive material composed of one or more selected from i and Ta. Although W is used in this embodiment, a stack of W on TaN may be used as the first wiring and the first electrode.

The first wiring 105 and the first electrodes 103, 1
After forming 04 and 106, the first insulating film 102 is formed. In this embodiment, the first insulating film 102 includes two insulating films (a first insulating film A 102a and a first insulating film B 1).
02b) are laminated. As the first insulating film A 102a, a silicon oxynitride film is used,
It is formed with a thickness of nm. The first insulating film B 102b is formed using a silicon oxide film or a silicon oxynitride film and has a thickness of 0.5 to 1 μm.
It is formed with a thickness of m.

FIG. 6 (A) shows a top view of the pixel portion in FIG. 2 (A). A-A ', BB', C-
A cross-sectional view taken along line C ′ and DD ′ corresponds to FIG. The first electrodes 103 and 104 are connected to the common wiring 2
Is part of 00. Further, the first electrode 106 is a part of the first wiring 105.

The surface of the first insulating film 102 has unevenness due to the first wiring and the first electrode formed previously, and it is desirable to flatten it. CMP is used as a flattening method. As the CMP polishing agent (slurry) for the first insulating film 102, for example, fumed silica particles obtained by thermally decomposing silicon chloride gas in a KOH-added aqueous solution may be used. The first insulating film is removed by CMP to the extent of 0.1 to 0.5 μm to planarize the surface.

Thus, the flattened first insulating film 108 is formed as shown in FIG. 2B, and the semiconductor layer is formed thereon. The semiconductor layer is formed of a semiconductor having a crystal structure. This is obtained by crystallizing the amorphous semiconductor layer formed over the first insulating film 108. After the amorphous semiconductor layer is deposited, it is crystallized by heat treatment or irradiation with laser light. The material of the amorphous semiconductor layer is not limited, but is preferably silicon or silicon germanium (Si _x Ge _1-x ; 0
<X <1, typically x = 0.001 to 0.05) formed of an alloy or the like.

After that, the semiconductor layer is divided into islands by etching, and semiconductor films 109 to 1 are formed as shown in FIG.
11 is formed.

FIG. 6 (B) shows a top view of FIG. 2 (C). AA ', BB', CC ', DD'
A cross-sectional view taken along line corresponds to FIG. First electrode 1
03 and 104 overlap with the semiconductor film 109 with the planarized first insulating film 108 interposed therebetween. The first electrode 106 overlaps with the semiconductor film 110 with the first insulating film 108 interposed therebetween. Note that the semiconductor film 111 is a semiconductor film for forming a capacitor, and the first insulating film 108.
It is overlapped with the first wiring 105 with the interposing therebetween.

Next, a second insulating film 112 that covers the semiconductor films 109 to 111 is formed. The second insulating film 112 is
It is formed of an insulator containing silicon by a plasma CVD method or a sputtering method. Its thickness is 40 to 150 nm.

Then, a contact hole 113 is formed in the first insulating film 108 and the second insulating film 112 to partially expose the first wiring 105 (FIG. 2D).

Next, as shown in FIG. 3A, a conductive film is formed over the second insulating film 112 to form a second gate electrode and a second wiring. In the present invention, the second gate electrode is formed by stacking two or more conductive films. The first conductive film 12 formed on the second insulating film 112
0 is formed of a nitride of a refractory metal such as molybdenum or tungsten, and the second conductive film 121 formed thereover is formed of a refractory metal, a low resistance metal such as aluminum or copper, or polysilicon. Specifically, one or more kinds of nitrides selected from W, Mo, Ta, and Ti are selected as the first conductive film, and W, Mo, and
One or a plurality of alloys selected from Ta, Ti, Al, and Cu, or n-type polycrystalline silicon is used. For example, the first
Of the second conductive film 121 is formed of TaN.
May be formed of W. When the second gate electrode and the second wiring are formed of a three-layer conductive film, the first layer is Mo,
The third layer may be Al and the third layer may be TiN. Further, the first layer may be W, the second layer may be Al, and the third layer may be TiN. By forming the wiring in multiple layers, the thickness of the wiring itself is increased, so that the wiring resistance can be suppressed.

Next, as shown in FIG. 3B, a mask 122 is formed between the first conductive film 120 and the second conductive film 121.
Is used to perform the first etching process. By the first etching treatment, first shape electrodes 123 to 129 having a tapered end portion are formed (first conductive films 123a to 123a).
129a and the second conductive films 123b to 129b).
The second insulating film 112 has electrodes 123 to 12 of the first shape.
In the portion not covered with 9, the surface is thinned by etching about 20 to 50 nm.

The first doping process is performed by an ion implantation method or an ion doping method in which ions are implanted without mass separation. The doping is performed by the first shape electrode 124,
Using 125, 126, and 129 as a mask, the first concentration one conductivity type impurity region 151 is formed in the semiconductor films 109 to 111.
~ 153 formed. The first concentration is 1 × 10 ^{20 to} 1.5 ×
10 ²¹ / cm ³

Next, a second etching process is performed as shown in FIG. 3C without removing the resist mask. In this etching process, the second conductive film is anisotropically etched to form the second shape electrodes 134 to 140 (the first conductive films 134a to 140a and the second conductive film 1).
34b-140b). Second shape electrode 134-
The width of 140 is reduced by this etching process, and the end portion thereof has the first concentration of one conductivity type impurity regions 151 to 153.
It is formed so as to be located inside the (second impurity region). As shown in the next step, the length of the LDD is determined by this receding width. The second shape electrodes 134 to 140 are the second
Function as an electrode.

FIG. 7A shows a top view of FIG. 3C.
A cross-sectional view taken along AA ′, BB ′, CC ′, and DD ′ corresponds to FIG. A second shaped electrode 135,
Reference numeral 136 denotes electrodes 138, 13 functioning as gate wirings.
It is a part of 9. Second shape electrodes 135, 136;
The first electrodes 103 and 104 overlap with each other with the first insulating film 108, the semiconductor film 109, and the second insulating film 112 interposed therebetween. In addition, the second shape electrode 140 and the first electrode 106 include the first insulating film 108 and the semiconductor film 11.
0 and the second insulating film 112 are sandwiched in between and overlap each other.

Further, the second shape electrode 140 is a part of the electrode 137 functioning as the second wiring. And
The second wiring 137 is formed of the second insulating film 112 and the semiconductor film 11.
1, the first wiring 10 with the first insulating film 108 interposed therebetween.
It overlaps with 5. The second wiring 137 is connected to the first wiring 105 via the contact hole 113. The electrode 134 also functions as a source wiring.

Then, in this state, the second conductivity type impurity is subjected to the second doping treatment to add the single conductivity type impurity to the semiconductor films 109 to 111 (FIG. 3C). Second-concentration one-conductivity-type impurity regions (first impurity regions) 155, 156, 158, and 15 formed by this doping process.
9, 161, 162, 164, 165, 168, 16
9, 171, 172, 175, 176 are formed. First impurity regions 156, 158, 162, 164, 16
9, 171, 175 are electrodes 135, 13 of the second shape.
6, the first conductive film 135a which constitutes 137, 140,
It is formed in a self-aligned manner so as to overlap with 136a, 137a, 140a. The impurities added by the ion doping method are the first conductive films 135a, 136a, 137a, 14
Since it is added through 0a, the number of ions reaching the semiconductor film is reduced, and the concentration is inevitably low. Its concentration is 1
× a ^{10 17 ~1 × 10 19 / cm} 3. In addition, the first impurity regions 155, 159, 161, 165, 168, 17
2, 176 are electrodes 135, 136, 13 of the second shape.
7. First conductive films 135a and 136 which form 140
It is formed in a self-aligned manner so as not to overlap a, 137a, 140a.

By this second doping process,
Channel forming regions 157, 163, 170, 174;
More than the first concentration one conductivity type impurity regions 151 to 153,
High impurity concentration second impurity regions 154, 160, 16
6, 167, 173, 177 are formed.

Next, as shown in FIG. 4A, a mask 143 made of resist is formed, and a third doping process is performed. By this third doping process, the third impurity regions 144 to 150 of the conductivity type opposite to the one conductivity type of the third concentration are formed in the semiconductor film 110. The third impurity regions are regions 146, 14 overlapping the second shape electrode 140.
8 and non-overlapping areas 144, 145, 149, 150
The impurity element is added in the concentration range of 1.5 × 10 ^{20 to} 5 × 10 ²¹ / cm ³ .

Through the steps up to this point, a region to which an impurity for the purpose of controlling valence electrons is added is formed in each semiconductor film. The first electrodes 103, 104 and 106 and the second shape electrodes 135, 136 and 140 function as gate electrodes at positions overlapping with the semiconductor film.

After that, a step of activating the impurity element added to each semiconductor film is performed. This activation is performed using a gas heating type instant thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 400 to 700 ° C., typically 450 to 500 ° C. In addition to this, a laser annealing method using the second harmonic (532 nm) of a YAG laser can be applied. The second harmonic of the YAG laser (532 nm) is used for activation by irradiation with laser light.
Is used to irradiate the semiconductor film with this light. Of course, the same applies not only to the laser light but also to the RTA method using a lamp light source,
The semiconductor film is heated by radiation from a lamp light source from both sides or one side of the substrate.

Thereafter, as shown in FIG. 4B, a passivation film 180 made of silicon nitride is formed to a thickness of 50 to 100 nm by a plasma CVD method, and heat treatment is performed at 410 ° C. using a clean oven to perform nitriding. Hydrogen released from the silicon film hydrogenates the semiconductor film.

Next, a third insulating film 181 made of an organic insulating material is formed on the passivation film 180.
The reason for using the organic insulating material is to flatten the surface of the third insulating film 181. In order to obtain a more complete flat surface, it is desirable that this surface be flattened by the CMP method. When using the CMP method together,
Oxide film formed by plasma CVD method, SOG (Spin on Glass) or PS formed by coating method
G or the like can also be used. Note that the passivation film 180 may be regarded as part of the third insulating film 181.

Next, as shown in FIG. 4C, contact holes are formed in the second insulating film 112, the passivation film 180, and the third insulating film 181, and the wirings 182 to 18 are formed.
6 is formed. This wiring is formed by laminating a titanium film and an aluminum film.

FIG. 7B is a top view of FIG. 4C. A cross-sectional view taken along AA ′, BB ′, CC ′, and DD ′ corresponds to FIG.

The wiring 182 includes the source wiring 134 and the second wiring.
Of impurity region 154. The wiring 183 is
It is connected to the second impurity region 166 and the first wiring 137. The wiring 184 is the gate wirings 138 and 139.
It is connected to the. The wiring 185 functions as a power supply line, and the third impurity region 144 and the second impurity region 1
It is connected to 77. The wiring 186 is connected to the third impurity region 150.

In the above steps, assuming that the impurity region of one conductivity type is n-type and the impurity region opposite to the one conductivity type is p-type, an n-channel TFT which is a switching TFT.
202, p-channel TFT 203 which is a driving TFT
Is formed. In this embodiment, the switching T
Although the n-channel TFT is used for the FT and the p-channel TFT is used for the driving TFT, the present invention is not limited to this structure. The switching TFT and the driving TFT may be p-channel TFTs or n-channel TFTs. However, when the anode of the OLED is used as the pixel electrode, the driving TFT is preferably a p-channel TFT,
When the cathode of the OLED is used as a pixel electrode, a driving T
The FT is preferably an n-channel TFT.

Next, as shown in FIG. 5, a transparent conductive film containing indium tin oxide as a main component is formed to a thickness of 60 to 120 nm on the surface of the flattened third insulating film 181. After that, the transparent conductive film is etched to form the wiring 1
A pixel electrode (third electrode) 188 connected to 86 is formed. FIG. 8 shows a top view immediately after forming the pixel electrode 188 of FIG. AA ', BB', CC ', D
A sectional view taken along line -D 'corresponds to FIG.

In the n-channel TFT 202, the first
The impurity regions 156, 158, 162, 164 function as LDDs, and the second impurity regions 154, 166 function as source or drain regions. This n-channel TFT 20
2 has a form in which two TFTs are connected in series with the second impurity region 160 inserted. The length of the LDD in the channel length direction is 0.5 to 2.5 μm, preferably 1.5 μm. The structure of such an LDD is mainly intended to prevent the deterioration of the TFT due to the hot carrier effect. p
In the channel TFT 203, the third impurity region 14
4, 150 function as a source or drain region.

In this embodiment, a constant voltage (common voltage) is always applied to the common wiring 200 to apply the common voltage to the first electrodes 103 and 104. The constant voltage is smaller than the threshold in the case of the n-channel TFT and larger than the threshold in the case of the p-channel TFT. By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one. TFT formed as a switching element in a pixel portion of a semiconductor device
Is important because the reduction of the off current is more important than the increase of the on current.

Further, in this embodiment, the driving TFT 203 is
In, by forming the pair of electrodes 106 and 140 which are electrically connected by inserting the semiconductor film, the thickness of the semiconductor film is substantially halved, and depletion progresses rapidly with the application of the gate voltage. It is possible to increase the field effect mobility and reduce the subthreshold coefficient. As a result, the driving voltage can be lowered by using the TFT having this structure for the driving TFT. Further, the current driving capability is improved, and the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

A capacitor is formed in a portion where the first wiring 105, the first insulating film 108, and the semiconductor film 111 overlap each other. In addition, the second wiring 137
Then, a capacitor is formed in a portion where the second insulating film 112 and the semiconductor film 111 overlap with each other.

Next, as shown in FIG. 5, the third insulating film 1
81, an n-channel type TFT 202 and a p-channel type T
A partition layer 190 covering the FT 203 is formed. Since the organic compound layer and the cathode cannot be subjected to wet treatment (treatment such as etching with a chemical solution or washing with water), the pixel electrode 1
A partition layer 190 made of a photosensitive resin material is provided on the third insulating film at the position of 88. The partition layer 190 is formed using an organic resin material such as polyimide, polyamide, polyimide amide, or acrylic. This partition layer 190
Is formed so as to cover the end portion of the pixel electrode. Further, the end portion of the partition layer 190 is formed so as to have a taper angle of 45 to 60 degrees.

The active matrix drive type light emitting device shown here is constructed by arranging light emitting elements in a matrix. The light emitting element 195 includes an anode, a cathode, and an organic compound layer formed between them. Pixel electrode 18
8 is an anode when formed of a transparent conductive film. The organic compound layer 192 is formed by combining a hole transporting material having a relatively high hole mobility, an electron transporting material having the opposite property, a light emitting material, and the like. They may be formed in layers or may be mixed and formed.

The organic compound material is formed as a thin film layer having a total thickness of about 100 nm. Therefore, it is necessary to improve the flatness of the surface of ITO formed as the anode. If the flatness is poor, at worst the short-circuit with the cathode formed on the organic compound layer will occur. As another means for preventing this, a method of forming an insulating film having a thickness of 1 to 5 nm can be adopted. As the insulating film, polyimide, polyimide amide, polyamide, acrylic, or the like can be used.
The counter electrode (fourth electrode) 193 can be used as a cathode by being formed using a material such as an alkali metal or an alkaline earth metal such as MgAg or LiF.

For the counter electrode 193, a material containing magnesium (Mg), lithium (Li) or calcium (Ca) having a small work function is used. Preferably MgAg
(Material in which Mg and Ag are mixed at Mg: Ag = 10: 1)
The electrode consisting of Besides, MgAgAl electrode,
Examples thereof include LiAl electrodes and LiFAl electrodes. Further, an insulating film 194 made of silicon nitride or a DLC film is formed on the upper layer thereof with a thickness of 2 to 30 nm, preferably 5 to 10 nm. The DLC film can be formed by a plasma CVD method, and even if formed at a temperature of 100 ° C. or lower, the DLC film can be formed with good coverage with covering the end portion of the partition layer 190.
The internal stress of the DLC film can be relaxed by mixing a slight amount of argon, and it can be used as a protective film. The DLC film contains oxygen and C
Since it has a high gas barrier property against O, CO ₂ , H ₂ O, etc., it is suitable as the insulating film 194 used as a barrier film.

In this embodiment, the source wiring and the gate wiring are formed at the same time, and thereafter, the wiring for supplying the drain current of the driving TFT to the pixel electrode and the power supply line are formed at the same time. The thicker the wiring, the larger the step created by the wiring. If the step becomes large, there is a high possibility that the wiring manufactured in a later step will be broken or the characteristics of the element will be deteriorated. Therefore, it is preferable that the wiring formed in the previous step has a smaller wiring thickness. Since the power supply line is a wiring for supplying a current flowing to the light emitting element, it is desirable to increase the film thickness to reduce the resistance. In the light emitting device of this embodiment, since the power supply line is formed after the source wiring and the gate wiring are formed, the thickness of the power supply line can be increased and the resistance can be reduced.

Further, in this embodiment, the source wiring is formed under the third insulating film at the same time as the gate wiring, and the pixel electrode is formed into the third wiring.
Since it is formed on the insulating film, the source wiring and the pixel electrode can be overlapped without directly connecting with each other without providing a new insulating film. Therefore, the light emitting area of the light emitting element can be further expanded.

In this embodiment, the switching TF is used.
At T202, the common voltage is applied to the first electrode, and the driving TFT 203 shows an example in which the first electrode and the second electrode are connected. However, the present invention is not limited to this configuration. The first electrode and the second electrode may be connected in the switching TFT 202, or the common voltage may be applied to the first electrode in the driving TFT 203.

In the light emitting device of this embodiment, the switching TFT has a double gate structure (a structure including an active layer having two channel formation regions connected in series). The configuration is not limited to this. The switching TFT may have a single-gate structure, or may have a multi-gate structure such as a triple-gate structure (a structure including an active layer having two or more channel forming regions connected in series). . Also, drive TF
Regarding T, it may have a multi-gate structure such as a double-gate structure or a triple-gate structure (a structure including an active layer having two or more channel formation regions connected in series) instead of a single-gate structure. good.

When the airtightness is improved by a process such as packaging, a connector (flexible printed circuit: FPC) for connecting a terminal routed from an element or a circuit formed on the substrate and an external signal terminal is attached. Completed as a product.

(Embodiment 2) In this embodiment, a pixel structure of the light emitting device of the present invention different from that of Embodiment 1 will be described.

FIG. 9 shows a top view of a pixel of the light emitting device of this embodiment. FIG. 10 shows a cross-sectional view taken along the lines AA ′, BB ′, and CC ′ of FIG. Note that, in order to make the structure of the pixel easy to understand in FIG. 9, a partition layer, an organic light emitting layer, a cathode, which are manufactured in a step after the pixel electrode is formed,
The protective film is omitted.

A switching TFT 301 is an n-channel TFT in this embodiment. A driving TFT 302 is a p-channel TFT in this embodiment.
Is used. The switching TFT and the driving T
The FT may be an n-channel TFT or a p-channel TFT.

The switching TFT 301 includes first electrodes 306 and 307, a first insulating film 350 which is in contact with the first electrodes 306 and 307, and a semiconductor film 303 which is in contact with the first insulating film 350. The second insulating film 351 is in contact with the semiconductor film 303 and the second electrodes 308 and 309 are in contact with the second insulating film 351.

One of the source region and the drain region 304 and 305 of the semiconductor film 303 is connected to the source wiring 311 through the wiring 310, and the other is connected to the wiring 3.
It is connected to the second wiring 313 via 12. Second
Wiring 313 of the first wiring 3 through the contact hole
It is connected to 14.

The first electrodes 306 and 307 are overlapped with the second electrodes 308 and 309 with the first insulating film 350, the semiconductor film 303, and the second insulating film 351 interposed therebetween.

The driving TFT 302 has a first electrode 321.
And a first insulating film 350 in contact with the first electrode 321.
And a semiconductor film 322 in contact with the first insulating film 350.
And a second insulating film 351 in contact with the semiconductor film 322.
And a second electrode 320 in contact with the second insulating film 351.
And have.

The first electrode 321 is a part of the first wiring 314, and the second electrode 320 is a part of the second wiring 313.

One of the source region and the drain region 323, 324 included in the semiconductor film 322 is connected to the power supply line 326 via the wiring 325, and the other is connected to the wiring 327.
Is connected to the pixel electrode 328 via.

The first electrode 321 is made up of the first insulating film 35.
0, the semiconductor film 322, and the second insulating film 351 are sandwiched therebetween, and overlap with the second electrode 320.

A storage capacitor is formed in a portion where the power supply line 326 and the first wiring 314 overlap with each other with the first insulating film 350 and the second insulating film 351 interposed therebetween.

Reference numeral 330 is a common wire, to which a constant voltage (ground voltage in this embodiment) is applied.
The wiring 332 partially includes the second electrodes 308 and 309, and the gate wiring 331 is formed through the contact holes formed in the first insulating film 350 and the second insulating film 351.
Connected with.

In this embodiment, even in the TFT in the same pixel,
The switching TFT 301 applies a common voltage to the first electrode. By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

Further, the driving TFT 302, which allows a larger current than the switching TFT, electrically connects the first electrode and the second electrode. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly as if the semiconductor film was substantially thinned.
The subthreshold coefficient can be reduced, and the field effect mobility can be further improved. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Further, it is possible to suppress variation in threshold value as compared with the case where there is one electrode. Therefore, TF of this structure
By using T in the drive circuit, the drive voltage can be lowered. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

The present invention is not limited to this structure.
The first electrode and the second electrode may be connected in the switching TFT, or the first electrode may be connected in the driving TFT.
A common voltage may be applied to the electrodes.

In the light emitting device of this embodiment, the switching TFT has a double gate structure (a structure including an active layer having two channel formation regions connected in series). The configuration is not limited to this. The switching TFT may have a single-gate structure, or may have a multi-gate structure such as a triple-gate structure (a structure including an active layer having two or more channel forming regions connected in series). . Also, drive TF
Regarding T, it may have a multi-gate structure such as a double-gate structure or a triple-gate structure (a structure including an active layer having two or more channel formation regions connected in series) instead of a single-gate structure. good.

In this embodiment, the source wiring and the power supply line are formed at the same time, and then the wiring for supplying the drain current of the driving TFT to the pixel electrode and the gate wiring are formed at the same time. Since the source wiring and the power supply line are formed below the third insulating film 370 and the pixel electrode is formed on the third insulating film, the source wiring and the power supply line can be connected to each other without providing a new insulating film. The pixel electrodes can be stacked without being directly connected. Therefore, the light emitting area of the light emitting element can be further expanded.

(Embodiment 3) In this embodiment, a pixel structure of the light emitting device of the present invention, which is different from those of Embodiments 1 and 2, will be described.

FIG. 11 shows a top view of a pixel of the light emitting device of this embodiment. AA ', BB', CC ', D of FIG.
A sectional view taken along line -D 'is shown in FIG. Note that in FIG. 11, the partition wall layer, the organic light emitting layer, the cathode, and the protective film, which are manufactured in a step after the pixel electrode is formed, are omitted for easy understanding of the structure of the pixel.

A switching TFT 401 is an n-channel TFT in this embodiment. A driving TFT 402 is a p-channel TFT in this embodiment.
Is used. The switching TFT and the driving T
The FT may be an n-channel TFT or a p-channel TFT.

The switching TFT 401 includes first electrodes 406 and 407, a first insulating film 450 in contact with the first electrodes 406 and 407, and a semiconductor film 403 in contact with the first insulating film 450. The second insulating film 451 is in contact with the semiconductor film 403, and the second electrodes 408 and 409 are in contact with the second insulating film 451.

One of the source region and the drain region 404, 405 included in the semiconductor film 403 is connected to the source wiring 411 through the wiring 410, and the other is connected to the wiring 4.
It is connected to the second wiring 413 via 12. Second
Wiring 413 of the first wiring 4 through the contact hole
It is connected to 14.

The first electrodes 406 and 407 overlap the second electrodes 408 and 409 with the first insulating film 450, the semiconductor film 403, and the second insulating film 451 interposed therebetween.

The driving TFT 402 has a first electrode 421.
And a first insulating film 450 in contact with the first electrode 421.
And a semiconductor film 422 in contact with the first insulating film 450.
And a second insulating film 451 which is in contact with the semiconductor film 422.
And a second electrode 420 in contact with the second insulating film 451.
And have.

The first electrode 421 is a part of the first wiring 414, and the second electrode 420 is a part of the second wiring 413.

One of the source region and the drain region 423 and 424 of the semiconductor film 422 is connected to the power supply line 426, and the other is connected to the pixel electrode 4 through the wiring 427.
28 is connected.

The first electrode 421 is the first insulating film 45.
0, the semiconductor film 422, and the second insulating film 451 are sandwiched between them and overlap with the second electrode 420.

A storage capacitor is formed in a portion where the power supply line 426 and the second wiring 413 overlap with each other with the third insulating film 470 interposed therebetween. In addition, the second wiring 41
A storage capacitor is formed in a portion where 3 and the first wiring 414 overlap with each other with the first insulating film 450 and the second insulating film 451 sandwiched therebetween.

Reference numeral 430 is a common wire, to which a constant voltage (ground voltage in this embodiment) is applied.
The wiring 432 partially includes second electrodes 408 and 409, and the gate wiring 431 is formed through a contact hole formed in the first insulating film 450 and the second insulating film 451.
Connected with.

Further, the adjacent gate wirings 431 are connected by the wiring 460 without making contact with the power supply line 426.

In this embodiment, even in the TFT in the same pixel,
The switching TFT 401 applies a common voltage to the first electrode. By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

Further, the driving TFT 402 which allows a larger current to flow than the switching TFT electrically connects the first electrode and the second electrode. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly as if the semiconductor film was substantially thinned.
The subthreshold coefficient can be reduced, and the field effect mobility can be further improved. Further, it is possible to suppress variation in threshold value as compared with the case where there is one electrode. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Therefore, TF of this structure
By using T in the drive circuit, the drive voltage can be lowered. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

The present invention is not limited to this structure.
The first electrode and the second electrode may be connected in the switching TFT, or the first electrode may be connected in the driving TFT.
A common voltage may be applied to the electrodes.

In the light emitting device of this embodiment, the switching TFT has a double gate structure (a structure including an active layer having two channel formation regions connected in series), but this embodiment The configuration is not limited to this. The switching TFT may have a single-gate structure, or may have a multi-gate structure such as a triple-gate structure (a structure including an active layer having two or more channel forming regions connected in series). . Also, drive TF
Regarding T, it may have a multi-gate structure such as a double-gate structure or a triple-gate structure (a structure including an active layer having two or more channel formation regions connected in series) instead of a single-gate structure. good.

In this embodiment, the gate wiring and the power supply line are formed at the same time, and thereafter, the wiring for supplying the drain current of the driving TFT to the pixel electrode and the source wiring are formed at the same time. Since the source wiring is formed under the third insulating film 470 and the pixel electrode is formed on the third insulating film, the source wiring and the pixel electrode are directly connected without providing a new insulating film. Can be stacked without any. Therefore, the light emitting area of the light emitting element can be further expanded.

(Embodiment 4) In this embodiment, a pixel structure of the light emitting device of the present invention, which is different from those of Embodiments 1, 2 and 3, will be described.

FIG. 13 shows a top view of a pixel of the light emitting device of this embodiment. 14A and 14B are cross-sectional views taken along lines AA ′, BB ′, and CC ′ in FIG. 13. Note that in FIG. 13, the partition wall layer, the organic light emitting layer, the cathode, and the protective film, which are manufactured in a process after the pixel electrode is formed, are omitted for easy understanding of the structure of the pixel.

A switching TFT 501 is an n-channel TFT in this embodiment. A driving TFT 502 is a p-channel TFT in this embodiment.
Is used. The switching TFT and the driving T
The FT may be an n-channel TFT or a p-channel TFT.

The switching TFT 501 includes first electrodes 506 and 507, a first insulating film 550 that is in contact with the first electrodes 506 and 507, and a semiconductor film 503 that is in contact with the first insulating film 550. , A second insulating film 551 in contact with the semiconductor film 503, and second electrodes 508 and 509 in contact with the second insulating film 551.

One of the source region and the drain region 504, 505 included in the semiconductor film 503 is connected to the source wiring 511 through the wiring 510, and the other is connected to the wiring 5.
It is connected to the second wiring 513 via 12. Second
Wiring 513 of the first wiring 5 through the contact hole
It is connected to 14.

The first electrodes 506 and 507 overlap the second electrodes 508 and 509 with the first insulating film 550, the semiconductor film 503, and the second insulating film 551 interposed therebetween.

The driving TFT 502 has a first electrode 521.
And a first insulating film 550 in contact with the first electrode 521.
And a semiconductor film 522 in contact with the first insulating film 550.
And a second insulating film 551 in contact with the semiconductor film 522.
And a second electrode 520 in contact with the second insulating film 551.
And have.

The first electrode 521 is a part of the first wiring 514, and the second electrode 520 is a part of the second wiring 513.

One of the source region and the drain region 523, 524 of the semiconductor film 522 is connected to the wiring 562 via the wiring 525, and the other is connected to the pixel electrode 528 via the wiring 527. The wiring 562 is connected to the power supply line 526.

The first electrode 521 is the first insulating film 55.
0, the semiconductor film 522, and the second insulating film 551 are sandwiched therebetween, and overlap with the second electrode 520.

A storage capacitor is formed in a portion where the power supply line 526 and the second wiring 513 overlap with each other with the first insulating film 550 and the second insulating film 551 sandwiched therebetween.

Reference numeral 530 is a common wire to which a constant voltage (ground voltage in this embodiment) is applied.
The wiring 532 partially includes the second electrodes 508 and 509, and the gate wiring 531 is provided through the contact holes formed in the first insulating film 550 and the second insulating film 551.
Connected with.

In this embodiment, even in the TFT in the same pixel,
The switching TFT 501 applies a common voltage to the first electrode. By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

Further, the driving TFT 502, which allows a larger current than the switching TFT, electrically connects the first electrode and the second electrode. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly as if the semiconductor film was substantially thinned.
The subthreshold coefficient can be reduced, and the field effect mobility can be further improved. Further, it is possible to suppress variation in threshold value as compared with the case where there is one electrode. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Therefore, TF of this structure
By using T in the drive circuit, the drive voltage can be lowered. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

The present invention is not limited to this structure.
The first electrode and the second electrode may be connected in the switching TFT, or the first electrode may be connected in the driving TFT.
A common voltage may be applied to the electrodes.

In this embodiment, the power supply line and the common wiring are formed at the same time, the source wiring is formed after that, and further, the wiring and the gate for supplying the drain current of the driving TFT to the pixel electrode. The wiring and the wiring are formed at the same time. Since the source wiring and the power supply line are formed below the third insulating film 570 and the pixel electrode is formed on the third insulating film 570, the source wiring and the power supply line can be formed without providing a new insulating film. And the pixel electrode can be overlapped without being directly connected. Therefore, the light emitting area of the light emitting element can be further expanded.

(Embodiment 5) In this embodiment, a pixel structure of a light emitting device of the present invention different from those of Embodiments 1, 2, 3 and 4 will be described.

FIG. 15 shows a top view of a pixel of the light emitting device of this embodiment. AA ', BB', CC ', D of FIG.
A sectional view taken along line -D 'is shown in FIG. Note that, in FIG. 15, the partition wall layer, the organic light emitting layer, the cathode, and the protective film, which are manufactured in a step after the pixel electrode is formed, are omitted for easy understanding of the structure of the pixel.

A switching TFT 701 is an n-channel TFT in this embodiment. A driving TFT 702 is a p-channel TFT in this embodiment.
Is used. The switching TFT and the driving T
The FT may be an n-channel TFT or a p-channel TFT.

The switching TFT 701 includes first electrodes 706 and 707, a first insulating film 750 that is in contact with the first electrodes 706 and 707, and a semiconductor film 703 that is in contact with the first insulating film 750. A second insulating film 751 which is in contact with the semiconductor film 703 and second electrodes 708 and 709 which are in contact with the second insulating film 751.

One of the source region and the drain region 704, 705 included in the semiconductor film 703 is connected to the source wiring 711 through a wiring 710, and the other is connected to the wiring 7.
It is connected to the second wiring 713 through 12.

The first electrodes 706 and 707 overlap the second electrodes 708 and 709 with the first insulating film 750, the semiconductor film 703, and the second insulating film 751 interposed therebetween.

The driving TFT 702 has a first electrode 721.
And a first insulating film 750 in contact with the first electrode 721.
And a semiconductor film 722 in contact with the first insulating film 750.
And a second insulating film 751 in contact with the semiconductor film 722.
And a second electrode 720 in contact with the second insulating film 751.
And have.

The first electrode 721 is a part of the wiring 714 connected to the common wiring 730, and the second electrode 7
Reference numeral 20 is a part of the second wiring 713.

One of the source region and the drain region 723 and 724 of the semiconductor film 722 is connected to the power supply line 726, and the other is connected to the pixel electrode 7 through the wiring 727.
28 is connected.

The first electrode 721 is the first insulating film 75.
0, the semiconductor film 722, and the second insulating film 751 are sandwiched therebetween, and overlap with the second electrode 720.

The power supply line 726 is connected to the impurity region 761 of the semiconductor film 760 for forming a capacitor. A storage capacitor is formed in a portion where the power supply line 726 and the second wiring 713 overlap with each other with the third insulating film 770 interposed therebetween. In addition, the second wiring 71
A storage capacitor is formed in a portion where 3 and the semiconductor film 760 overlap with each other with the second insulating film 751 interposed therebetween. Further, a storage capacitor is formed in a portion where the semiconductor film 760 and the first wiring 714 overlap with each other with the first insulating film 750 interposed therebetween.

A constant voltage (ground voltage in this embodiment) is applied to the common wiring 730. Wiring 732
Connects adjacent gate wirings 731 without contacting the source wiring 711. The gate wiring 731 partially includes second electrodes 708 and 709.

In this embodiment, the switching TFT 70 is used.
1 and the driving TFT 702 apply a common voltage to the first electrode. By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

The present invention is not limited to this structure, and the first electrode and the second electrode may be connected.

In the light emitting device of this embodiment, the switching TFT has a double gate structure (a structure including an active layer having two channel formation regions connected in series), but this embodiment is The configuration is not limited to this. The switching TFT may have a single-gate structure, or may have a multi-gate structure such as a triple-gate structure (a structure including an active layer having two or more channel forming regions connected in series). . Also, drive TF
Regarding T, it may have a multi-gate structure such as a double-gate structure or a triple-gate structure (a structure including an active layer having two or more channel formation regions connected in series) instead of a single-gate structure. good.

In this embodiment, the source wiring and the gate wiring are formed at the same time, and thereafter, the wiring for supplying the drain current of the driving TFT to the pixel electrode and the power supply line are formed at the same time. The thicker the wiring, the larger the step created by the wiring. If the step becomes large, there is a high possibility that the wiring manufactured in a later step will be broken or the characteristics of the element will be deteriorated. Therefore, it is preferable that the wiring formed in the previous step has a smaller wiring thickness. Since the power supply line is a wiring for supplying a current flowing to the light emitting element, it is desirable to increase the film thickness to reduce the resistance. In the light emitting device of this embodiment, since the power supply line is formed after the source wiring and the gate wiring are formed, the thickness of the power supply line can be increased and the resistance can be reduced.

Further, in this embodiment, since the source wiring is formed under the third insulating film 770 at the same time as the gate wiring and the pixel electrode is formed on the third insulating film 770, a new insulating film is formed. The source wiring and the pixel electrode can be overlapped without directly connecting, even without providing. Therefore, the light emitting area of the light emitting element can be further expanded.

Example 6 In this example, an example of manufacturing a semiconductor film by a method different from that of Example 1 will be described.

In FIG. 17A, 1100 is a substrate having an insulating surface. In FIG. 17A, the substrate 1
As the glass substrate 100, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this step may be used.

First, as shown in FIG. 17A, the substrate 1
First electrodes 1102a and 1102b are formed on 100. The first electrodes 1102a and 1102b may be formed of a conductive material. Typically,
It can be formed of an alloy or compound of one or more selected from aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), and titanium (Ti). Alternatively, a stack of several conductive films may be used as the first electrode.

Then, the first electrodes 1102a and 1102
a first insulating film 1101 is formed on the insulating surface so as to cover b.
Has been done. The first insulating film 1101 is silicon oxide
Film, silicon nitride film or silicon oxynitride film (SiO
_xN_y) And the like. A typical example is the first insulating film 11.
01 has a two-layer structure, and SiH_Four, NH₃, And N
₂First silicon oxynitride film formed by using O as a reaction gas
50-100nm film, SiH_Four, And N₂O is the reaction gas
The second silicon oxynitride film formed as
A structure in which layers are formed to have a thickness of 50 nm is adopted. Well
In addition, a film thickness of 10 nm or less is formed as one layer of the first insulating film 1101.
Lower silicon nitride film (SiN film) or second oxynitride
Silicon film (SiN_xO_yUsing a membrane (X >> Y))
preferable. During gettering, nickel has a high oxygen concentration.
Contact with the semiconductor film because it tends to move to
It is extremely useful to use a silicon nitride film as the first insulating film.
It is effective. In addition, the first silicon oxynitride film and the second nitrogen oxide
Three-layer structure in which a silicon oxide film and a silicon nitride film are sequentially laminated
You may use a structure.

Next, a first semiconductor layer 1103 having an amorphous structure is formed on the first insulating film. For the first semiconductor layer 1103, a semiconductor material containing silicon as its main component is used. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied and is formed with a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method. In order to obtain a semiconductor layer having a high-quality crystal structure by the subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the film of the first semiconductor layer 1103 having an amorphous structure is 5 × 10 ¹⁸ / cm ³ (Secondary ion mass spectrometry (SIM
The atomic concentration measured in S) should be reduced below. These impurities become a factor that hinders later crystallization, and also becomes a factor that increases the density of trap centers and recombination centers even after crystallization. Therefore, it is desirable to use not only a high-purity material gas but also an ultrahigh vacuum-compatible CVD apparatus equipped with a mirror surface treatment (electrolytic polishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.

Next, as a technique for crystallizing the first semiconductor layer 1103 having an amorphous structure, here, Japanese Unexamined Patent Publication (Kokai) No. Hei 8 (1996) -86
Crystallization is carried out using the technique described in Japanese Patent No. 78329.
The technique described in the publication is a crystal structure that expands from an added region as a starting point by selectively adding a metal element that promotes crystallization to an amorphous silicon film (also called an amorphous silicon film) and performing heat treatment. To form a semiconductor layer having First, on the surface of the first semiconductor layer 1103 having an amorphous structure, 1 to 1 by weight of a metal element (here, nickel) having a catalytic action that promotes crystallization is calculated.
A nickel acetate salt solution containing 00 ppm is applied by a spinner to form a nickel-containing layer 1104 (FIG. 17B).
As a method other than the method of forming the nickel-containing layer 1104 by coating, a method of forming an extremely thin film by a sputtering method, a vapor deposition method, or a plasma treatment may be used. In addition, although the example of coating the entire surface is shown here, a nickel-containing layer may be selectively formed by forming a mask.

Next, heat treatment is performed to perform crystallization.
In this case, in crystallization, silicide is formed in a portion of the semiconductor layer in contact with a metal element that promotes crystallization of a semiconductor, and crystallization proceeds with the silicide as a nucleus. Thus, FIG. 17C
A first semiconductor layer 1105 having the crystal structure shown in is formed. Note that the concentration of oxygen contained in the first semiconductor layer 1105 after crystallization is preferably 5 × 10 ¹⁸ / cm ³ or less. Here, the heat treatment for dehydrogenation (4
After 50 ° C. for 1 hour, heat treatment for crystallization (550
C. to 650.degree. C. for 4 to 24 hours). Further, when crystallization is performed by irradiation with intense light, any one of infrared light, visible light, or ultraviolet light or a combination thereof can be used, but typically, a halogen lamp, a metal halide, or the like. Light emitted from a lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp is used. The lamp light source is 1
It is lit for 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, and the semiconductor layer is momentarily 600 to 100.
It may be heated to about 0 ° C. If necessary,
Before irradiation with strong light, heat treatment may be performed to release hydrogen contained in the first semiconductor layer 1105 having an amorphous structure. Further, crystallization may be performed by simultaneously performing heat treatment and irradiation with strong light. Considering the productivity, it is desirable to perform crystallization by irradiating strong light.

First semiconductor layer 1 thus obtained
A metallic element (here, nickel) remains in 105. Even if it is not uniformly distributed in the film, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ as an average concentration. Of course, even in such a state, it is possible to form various semiconductor elements including the TFT,
The element is removed by the method described below.

Next, in order to increase the crystallization rate (ratio of crystal components in the total volume of the film) and repair defects left in crystal grains, the first semiconductor layer 1105 having a crystal structure is formed.
The laser light (first laser light) is irradiated to the above in the air or an oxygen atmosphere. When the laser light (first laser light) is irradiated, unevenness is formed on the surface and a thin oxide film 1106 is formed. (FIG. 17D) As the laser light (first laser light), excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of YAG laser are used. Further, light emitted from an ultraviolet lamp may be used instead of the excimer laser light.

Further, an oxide film (called chemical oxide) is formed from an ozone-containing aqueous solution (typically ozone water) to form a barrier layer 1 composed of an oxide film having a total thickness of 1 to 10 nm.
107, and a second semiconductor layer 1108 containing a rare gas element is formed on the barrier layer 1107 (FIG. 17).
(E)). Note that here, the oxide film 1106 formed when the first semiconductor layer 1105 having a crystal structure is irradiated with laser light is also regarded as part of the barrier layer. The barrier layer 1107 functions as an etching stopper when only the second semiconductor layer 1108 is selectively removed in a later step. Further, instead of the ozone-containing aqueous solution, the chemical oxide can be similarly formed by treating with an aqueous solution in which sulfuric acid, hydrochloric acid, nitric acid and the like are mixed with hydrogen peroxide solution. As another method for forming the barrier layer 1107, ozone may be generated by irradiation of ultraviolet rays in an oxygen atmosphere to oxidize the surface of the semiconductor layer having the crystal structure to form the barrier layer 1107. As another method for forming the barrier layer 1107, an oxide film having a thickness of about 1 to 10 nm may be deposited as a barrier layer by a plasma CVD method, a sputtering method, an evaporation method, or the like. As another method of forming the barrier layer 1107, a clean oven may be used and heated to about 200 to 350 ° C. to form a thin oxide film. Note that the barrier layer 1107 is not particularly limited as long as it is formed by any one of the above methods or a combination of those methods; It is necessary to have a film quality or film thickness that can be transferred to the second semiconductor layer.

[0166] Here, the second semiconductor layer 1108 containing a rare gas element is formed by a sputtering method to form a gettering site. (FIG. 17E) Note that it is desirable to appropriately adjust the sputtering conditions so that a rare gas element is not added to the first semiconductor layer. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Of these, argon (Ar), which is an inexpensive gas, is preferable. Here, the second semiconductor layer is formed using a target made of silicon in an atmosphere containing a rare gas element. There are two meanings of containing the rare gas element ion, which is an inert gas, in the film. One is to form dangling bonds to give strain to the semiconductor layer, and the other is to give strain to the lattice of the semiconductor layer. In order to give strain between the lattices of the semiconductor layer, it is remarkably obtained when an element having an atomic radius larger than that of silicon such as argon (Ar), krypton (Kr), and xenon (Xe) is used. Further, by containing a rare gas element in the film, not only lattice strain but also dangling bonds are formed, which contributes to the gettering action.

When the second semiconductor layer is formed using a target containing phosphorus, which is an impurity element of one conductivity type, in addition to gettering by a rare gas element, gettering is performed by utilizing the Coulomb force of phosphorus. It can be carried out.

During gettering, nickel tends to move to a region having a high oxygen concentration. Therefore, the oxygen concentration contained in the second semiconductor layer 1108 is higher than that contained in the first semiconductor layer. High concentration, eg 5 × 10 ¹⁸
/ Cm ³ or more is desirable.

Next, heat treatment is performed to perform gettering for reducing or removing the concentration of the metal element (nickel) in the first semiconductor layer. As the heat treatment for performing gettering, treatment for irradiating strong light or heat treatment may be performed. By this gettering,
The metal element moves in the direction of the arrow in FIG. 17F (that is, the direction from the substrate side to the surface of the second semiconductor layer), and the metal contained in the first semiconductor layer 1105 covered with the barrier layer 1107. The element is removed or the concentration of the metal element is reduced. The distance that the metal element moves during gettering may be at least the thickness of the first semiconductor layer, and gettering can be completed in a relatively short time. Here, nickel is used as the first semiconductor layer 1105.
Are all moved to the second semiconductor layer 1108 so that they are not segregated into the second semiconductor layer 1108, and almost no nickel contained in the first semiconductor layer 1105 exists, that is, the nickel concentration in the film is 1 × 10 ^18.
/ Cm ³ or less, preferably 1 × 10 ¹⁷ / cm ³ or less, gettering is sufficiently performed.

Depending on the condition of the heat treatment for gettering, the crystallinity of the first semiconductor layer is increased at the same time as gettering, and defects left in the crystal grains are repaired, that is, crystallinity is improved. be able to.

In this specification, gettering means that the metal element in the gettered region (here, the first semiconductor layer) is released by thermal energy and moves to the gettering site by diffusion. . Therefore,
Gettering depends on the processing temperature, and the higher the temperature, the shorter the gettering.

When a process of irradiating strong light is used as the gettering heat treatment, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and it is turned on 1 to 10 times. It is preferably repeated 2 to 6 times. The light emission intensity of the lamp light source is arbitrary, but is instantaneously 60
The semiconductor layer is heated to 0 to 1000 ° C., preferably 700 to 750 ° C.

When heat treatment is performed, heat treatment may be performed in a nitrogen atmosphere at 450 to 800 ° C. for 1 to 24 hours, for example at 550 ° C. for 14 hours. In addition to the heat treatment, strong light may be irradiated.

Then, the barrier layer 1107 is etched by etching.
As the topper, only the second semiconductor layer indicated by 1106
After selectively removing the barrier layer 110 formed of an oxide film
Remove 7. Selectively etch only the second semiconductor layer
ClF ₃Do not use plasma
Dry etching or hydrazine or tetraethyl
Lumonium hydroxide (Chemical formula (CH₃)
_FourWet with an alkaline solution such as an aqueous solution containing (NOH)
Etching can be performed. Also, the second semiconductor
After removing the layer, the surface of the barrier layer is nickel with TXRF.
When the concentration is measured, nickel is detected at a high concentration
Therefore, it is desirable to remove the barrier layer, which contains hydrofluoric acid.
It should be removed with an etchant.

Next, the first semiconductor layer having a crystal structure is irradiated with laser light (second laser light) in a nitrogen atmosphere or vacuum. When the laser light (second laser light) is applied, the height difference of the unevenness formed by the irradiation of the first laser light (PV value: Peak to Valley, the difference between the maximum value and the minimum value of the height) Is reduced, that is, flattened. (FIG. 17 (G)) Here, the PV value of the unevenness is AF
It may be observed by M (atomic force microscope). Specifically, the uneven P formed by the irradiation of the first laser beam
-The surface with a V value of about 10 to 30 nm is the second
By irradiating the laser light of, the PV value of the unevenness on the surface can be set to 5 nm or less, and depending on the condition, it can be 1.5.
can be less than or equal to nm. As the laser light (second laser light), excimer laser light having a wavelength of 400 nm or less, and the second and third harmonics of a YAG laser are used. Further, light emitted from an ultraviolet lamp may be used instead of the excimer laser light.

The energy density of the second laser light is made higher than that of the first laser light, preferably 30 to 60 mJ / cm ² . However, the second
If the energy density of the laser light is higher than that of the first laser light by 90 mJ / cm ² or more, the surface roughness will increase, and the crystallinity will be further lowered or microcrystallized. Is becoming worse.

Although the irradiation of the second laser light is higher than the energy density of the first laser light, the crystallinity hardly changes before and after the irradiation. In addition, the crystal state such as grain size hardly changes. That is, it is considered that only flattening is performed by the irradiation of the second laser light.

The merit that the semiconductor layer having a crystal structure is flattened by the irradiation of the second laser light is very large. For example, the improved flatness makes it possible to reduce the thickness of the second insulating film used as a gate insulating film to be formed later and improve the mobility of the TFT. In addition, since the flatness is improved, TF
When T is manufactured, off current can be reduced.

Further, when the gettering site is added to the first semiconductor layer by irradiating it with the second laser beam, the rare gas element in the semiconductor layer having a crystalline structure is removed. The effect of removing or reducing is also obtained.

Next, the planarized first semiconductor layer 11
09 is used to form a semiconductor film having a desired shape by using a known patterning technique.

This embodiment can be implemented by freely combining with Embodiments 1 to 5.

(Embodiment 7) This embodiment shows an example of forming a semiconductor film by a thermal crystallization method using a catalytic element.

When a catalytic element is used, it is disclosed in JP-A-7-130.
It is desirable to use the techniques disclosed in Japanese Patent No. 652 and Japanese Patent Laid-Open No. 8-78329.

Here, an example in which the technique disclosed in Japanese Patent Laid-Open No. 7-130652 is applied to the present invention is shown in FIG.
8 shows. First, the first electrode 1252 is formed over the substrate 1251. Then, so as to cover the first electrode 1252,
A first insulating film 1253 was formed on the substrate 1251, and an amorphous silicon film 1254 was formed thereon. Further, a nickel acetate salt solution containing 10 ppm by weight of nickel was applied to form a nickel-containing layer 1255. (Figure 18 (A))

Next, after a dehydrogenation step at 500 ° C. for 1 hour, at 500 to 650 ° C. for 4 to 12 hours, for example, 550.
The crystalline silicon film 1256 is subjected to heat treatment at 8 ° C. for 8 hours.
Was formed. The crystalline silicon film 125 thus obtained
6 had a very good crystalline quality. (Fig. 18 (B))

The technique disclosed in JP-A-8-78329 enables selective crystallization of an amorphous semiconductor film by selectively adding a catalytic element. FIG. 1 shows the case where the same technology is applied to the present invention.
This will be explained in Section 9.

First, the first electrode 1302 is formed on the glass substrate 1301. Then, a first insulating film 1303 was provided over the substrate 1301 so as to cover the first electrode 1302, and an amorphous silicon film 1304 was formed thereover. Then, a silicon oxide film 1305 was continuously formed over the amorphous silicon film 1304. At this time, the thickness of the silicon oxide film 1305 was set to 150 nm.

Next, the silicon oxide film 1305 is patterned to selectively form contact holes 1306,
Then, a nickel acetate salt solution containing 10 ppm by weight of nickel was applied. As a result, the nickel-containing layer 1307 is formed, and the nickel-containing layer 1307 is formed only on the bottom of the contact hole 1306.
04 was contacted (FIG. 19 (A)).

Next, at 500 to 650 ° C. for 4 to 24 hours,
For example, heat treatment was performed at 570 ° C. for 14 hours to form a crystalline silicon film 1308. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and then the crystallization proceeds in the lateral direction. The crystalline silicon film 1308 thus formed is composed of rod-shaped or needle-shaped crystals aggregated, and the respective crystals grow macroscopically with a certain directionality, so that the crystallinity is uniform. This has the advantage (FIG. 19 (B)).

In addition to nickel (Ni), the catalyst elements usable in the above two techniques are germanium (Ge), iron (Fe), palladium (Pd), tin (S).
n), lead (Pb), cobalt (Co), platinum (Pt),
Elements such as copper (Cu) and gold (Au) may be used.

A crystalline semiconductor film (including a crystalline silicon film, a crystalline silicon germanium film, etc.) is formed by using the above technique and is patterned to obtain a crystalline T film.
A semiconductor layer of FT can be formed. A TFT manufactured from a crystalline semiconductor film using the technique of this embodiment is
Excellent characteristics were obtained, but high reliability was required for that reason. However, by adopting the TFT structure of the present invention, a TFT that makes the most of the technique of this embodiment
It has become possible to fabricate.

Next, an example of performing a step of removing the catalytic element from the crystalline semiconductor film after forming the crystalline semiconductor film by using the above-mentioned catalytic element with the amorphous semiconductor film as an initial film A description will be given using 20. In this example, as the method, the technique described in JP-A-10-135468 or JP-A-10-135469 was used.

The technique described in the publication is a technique for removing the catalytic element used for crystallization of the amorphous semiconductor film after crystallization by using the gettering action of phosphorus. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 1.
It can be reduced to 0 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ .

Here, a non-alkali glass substrate represented by Corning's 1737 substrate was used. FIG. 20 (A)
Then, the first electrode 1402 is formed over the substrate 1401. Then, the substrate 14 is formed so as to cover the first electrode 1402.
01, a first insulating film 1403 was provided, and a crystalline silicon film 1404 was formed thereon.

Then, a silicon oxide film 1405 for a mask is formed to a thickness of 150 nm on the surface of the crystalline silicon film 1404, a contact hole is provided by patterning, and a region where the crystalline silicon film is partially exposed is provided. There is. Then, a step of adding phosphorus was performed to provide a region 1406 in which phosphorus was added to the crystalline silicon film.

In this state, 550 to 80 in a nitrogen atmosphere.
When heat treatment is performed at 0 ° C. for 5 to 24 hours, for example at 600 ° C. for 12 hours, the region 1406 in which phosphorus is added to the crystalline silicon film acts as a gettering site, and the catalyst left in the crystalline silicon film 1404. The element could be segregated in the gettering region 1406 to which phosphorus was added (FIG. 20B).

Then, the silicon oxide film 140 for the mask is used.
5 and the phosphorus-added region 1406 are removed by etching, so that the concentration of the catalytic element used in the crystallization process is reduced to 1 × 10 ¹⁷ atms / cm ³ or less. I was able to get This crystalline silicon film could be used as it is as a semiconductor layer of the TFT of the present invention.

This embodiment can be implemented in combination with the first to fifth embodiments.

(Embodiment 8) In this embodiment, the structure of the semiconductor device of the present invention will be described.

FIG. 21 shows a block diagram of a light emitting device of the present invention. In FIG. 21, a driving circuit of a light emitting device which displays an image using a digital video signal will be described as an example. The light emitting device shown in FIG. 21 includes a data line driver circuit 800, a scan line driver circuit 801, and a pixel portion 802.

The pixel portion 802 has a plurality of source wirings,
A plurality of gate wirings and a plurality of power supply lines are formed,
A region surrounded by the source wiring, the gate wiring, and the power supply line corresponds to a pixel. Note that in FIG. 21, one of a plurality of pixels
One source wiring 807, one gate wiring 809,
Only a pixel having one power supply line 808 is shown as a representative. Each pixel is a switching T that serves as a switching element.
FT 803, driving TFT 804, storage capacitor 805
And a light emitting element 806.

The gate electrode of the switching TFT 803 is connected to the gate wiring 809. One of a source region and a drain region of the switching TFT 803 is a source wiring 807 and the other is a driving TFT 80.
4 gate electrodes.

One of the source region and the drain region of the driving TFT 804 is connected to the power supply line 808 and the other is connected to the light emitting element 806. Then, the driving TFT 804
A storage capacitor 805 is formed by the gate electrode and the power supply line 808. Note that the storage capacitor 805 does not necessarily have to be formed.

The data line driving circuit 800 has a shift register 810, a first latch 811, and a second latch 812. The shift register 810 is supplied with a clock signal (S-CLK) and a start pulse signal (S-SP) for the data line driver circuit. The first latch 811 has a latch signal (Latch) that determines the latch timing.
signals) and a video signal (Video signal)
als) is given.

A clock signal (S
-CLK) and the start pulse signal (S-SP) are input, a sampling signal that determines the sampling timing of the video signal is generated and input to the first latch 811.

The sampling signal from the shift register 810 is buffered and amplified by a buffer or the like,
It may be input to the first latch 811. Since many circuits or circuit elements are connected to the wiring to which the sampling signal is input, load capacitance (parasitic capacitance)
Is big. This buffer is effective in order to prevent "dullness" of the rising or falling of the timing signal caused by the large load capacitance.

The first latch 811 has a plurality of stages of latches. The first latch 811 samples the input video signal in synchronization with the input sampling signal, and sequentially stores the sampled video signal in the latch of each stage.

The time until the video signals are completely written in the latches of all the stages of the first latch 811 is called a line period. In practice, the line period may include a period in which a horizontal blanking period is added to the line period.

When one line period ends, the second latch 8
A latch signal is input to 12. At this moment, the video signal written and held in the first latch 811 is
The signals are sent to the latch 812 all at once, written in and held in the latches of all stages of the second latch 812.

The video signal is sequentially written in the first latch 811 which has finished sending the video signal to the second latch 812, based on the sampling signal from the shift register 810.

During this second one-line period, the video signal written and held in the second latch 812 is input to the source / source wiring.

On the other hand, the scan line driver circuit has a shift register 821 and a buffer 822. The shift register 821 has a clock signal (G-C) for the scanning line driver circuit.
LK) and the start pulse signal (G-SP) are given.

A clock signal (G
-CLK) and the start pulse signal (G-SP) are input, a selection signal that determines the timing of selecting the gate wiring is generated and input to the buffer 822. The selection signal input to the buffer 822 is buffer-amplified and input to the gate wiring 809.

When the gate wiring 809 is selected, the switching TFT 803 having the gate electrode connected to the selected gate wiring 809 is turned on. Then, the video signal input to the source wiring is input to the gate electrode of the driving TFT 804 via the switching TFT 803 which is turned on.

The switching of the driving TFT 804 is controlled based on the information of 1 or 0 included in the video signal input to the gate electrode. Driving TFT 80
When 4 is on, the potential of the power supply line is applied to the pixel electrode of the light emitting element 806, and the light emitting element 806 emits light. When the driving TFT 804 is off, the potential of the power supply line is the light emitting element 8
The light-emitting element 806 does not emit light because it is not applied to the pixel electrode of 06.

In the circuit included in the data line driver circuit 800 and the scan line driver circuit 801, in the light emitting device shown in FIG. 21, the first electrode and the second electrode of the TFT are electrically connected. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same manner as when the semiconductor film is made thinner, so that the subthreshold coefficient can be made smaller. Further, the field effect mobility can be further improved. Further, it is possible to suppress variation in threshold value as compared with the case where there is one electrode. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Therefore, the drive voltage can be reduced. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced.
Therefore, the integration density can be improved.

Also, in the pixel portion 802, the switching TFT 80 used as a switching element.
A common voltage is applied to one of the first electrode and the second electrode of No. 3. As a result, it is possible to suppress variations in the threshold and to suppress the off-current as compared with the case where there is one electrode.

A driving TFT 804 for supplying a current to the light emitting element 806 electrically connects the first electrode and the second electrode. As a result, the on-current can be increased as compared with the case where the number of electrodes is one. In addition,
The driving TFT is not limited to this configuration, and a common voltage may be applied to either one of the first electrode and the second electrode without electrically connecting the first electrode and the second electrode. May be. Further, a thin film transistor having a general structure having only one electrode may be included.

This embodiment can be implemented in combination with Embodiments 1 to 7.

(Embodiment 9) In this embodiment, an external view of a light emitting device using the present invention will be described.

FIG. 22A is a top view of the light emitting device.
22B is a cross-sectional view taken along the line AA ′ of FIG. 22A, and FIG. 22C is a cross-sectional view taken along the line BB ′ of FIG.

Pixel portion 400 provided on substrate 4001
2, the data line driving circuit 4003, and the first and second scanning line driving circuits 4004a and 4004b are provided so as to surround the sealing material 4009. In addition, the pixel portion 4002
, The data line driving circuit 4003, and the sealing material 400 on the first and second scanning line driving circuits 4004a and 4004b.
8 are provided. Therefore, the pixel portion 4002, the data line driver circuit 4003, the first and second scan line driver circuits 4004a and 4004b, the substrate 4001 and the sealant 4009.
And a sealing material 4008, which is sealed with a filling material 4210.

Further, the pixel portion 4 provided on the substrate 4001
002, the data line driving circuit 4003, the first and second
The scan line driver circuits 4004a and 4004b each include a plurality of TFTs. In FIG. 22B, the base film 401 is typically used.
The CMOS 4201 included in the data line driver circuit 4003 and the driving TFT (TFT that controls the current to the light emitting element) 420 included in the pixel portion 4002, which are formed on the pixel 0.
2 is illustrated.

In this embodiment, a p-channel TFT or an n-channel TFT having an electrically connected first electrode and a second electrode of the present invention is used for the CMOS 4201, and the driving TFT 4202 is used. Is a p-channel TFT having an electrically connected first electrode and second electrode. Further, the pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the driving TFT 4202.

CMOS 4201 and driving TFT 420
A third insulating film 4301 is formed on the second electrode 2, and a pixel electrode (anode) 4203 electrically connected to the drain of the driving TFT 4202 is formed thereon. Pixel electrode 4203
For this, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide,
Tin oxide or indium oxide can be used.
Moreover, you may use what added gallium to the said transparent conductive film.

A fourth insulating film 4302 is formed on the pixel electrode 4203, and an opening is formed on the pixel electrode 4203 in the fourth insulating film 4302. In this opening, the organic light emitting layer 4 is formed on the pixel electrode 4203.
204 is formed. As the organic light emitting layer 4204, a known organic light emitting material or an inorganic organic light emitting material can be used. The organic light emitting material includes a low molecular weight (monomer) material and a high molecular weight (polymer) material, and either of them may be used.

As a method for forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used. Further, the structure of the organic light emitting layer may be a laminated structure or a single layer structure by freely combining the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer or the electron injection layer.

A cathode 4205 made of a conductive film having a light-shielding property (typically, a conductive film containing aluminum, copper or silver as a main component or a laminated film of these and another conductive film) is formed on the organic light emitting layer 4204. Is formed. Also, the cathode 4
It is desirable to exclude water and oxygen existing at the interface between 205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise the organic light emitting layer 4204 in a nitrogen or rare gas atmosphere and to form the cathode 4205 without exposing it to oxygen or moisture. In the present embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film forming apparatus. And the cathode 4205
Is given a predetermined voltage.

As described above, the pixel electrode (anode) 42
03, an organic light emitting layer 4204 and a cathode 4205 are formed to form a light emitting element 4303. And the light emitting element 4303
A protective film 4209 is formed over the insulating film 4302 so as to cover the insulating film 4302. The protective film 4209 is effective in preventing oxygen, moisture, and the like from entering the light-emitting element 4303.

Reference numeral 4005a is a lead wiring connected to the power supply line, and is electrically connected to the source region of the driving TFT 4202. The lead wiring 4005a passes between the sealing material 4009 and the substrate 4001, and the FPC 4006 has the FPC 4006 with the anisotropic conductive film 4300 interposed therebetween.
It is electrically connected to the wiring 4301.

As the sealing material 4008, a glass material, a metal material (typically a stainless material), a ceramic material, and a plastic material (including a plastic film) can be used. As a plastic material, FRP
(Fiberglass-Reinforced Pl
astics) plate, PVF (polyvinyl fluoride)
A film, mylar film, polyester film or acrylic resin film can be used. Alternatively, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can be used.

However, when the light emitting direction of the light emitting element is toward the cover material side, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

As the filler 4210, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone can be used. Resin, PVB (polyvinyl butyral) or E
VA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.

In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, the substrate 400 of the sealing material 4008 is used.
A concave portion 4007 is provided on the surface on the first side, and a hygroscopic substance or a substance 4207 capable of adsorbing oxygen is arranged. The hygroscopic substance or the substance 4207 capable of adsorbing oxygen is held by the recessed cover material 4208 in the recess 4007 so that the hygroscopic substance or the substance 4207 capable of adsorbing oxygen does not scatter. Note that the recess cover material 4208 has a fine mesh shape and has a structure in which air and moisture can pass through and a hygroscopic substance or a substance that can adsorb oxygen 4207 cannot pass through. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the light-emitting element 4303 can be suppressed.

As shown in FIG. 22C, the pixel electrode 42
At the same time that 03 is formed, a conductive film 4203a is formed so as to be in contact with the lead wiring 4005a.

The anisotropic conductive film 4300 has a conductive filler 4300a. Substrate 4001 and F
By thermocompression bonding with PC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.

This embodiment can be implemented by freely combining with Embodiments 1 to 8.

Example 10 The light emitting device of the present invention can be used in various electronic devices.

Electronic equipment using the present invention include video cameras, digital cameras, goggle type displays (head mount displays), navigation systems,
Sound reproduction devices (car audio, audio components, etc.), notebook personal computers, game machines,
A portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like), an image reproducing device provided with a recording medium (specifically, a DVD: Digital Versatile Dis).
c) and the like, and a device equipped with a display capable of displaying the image by reproducing the recording medium) and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 23A shows a display device, which is a housing 20.
01, support base 2002, display unit 2003, speaker unit 2004, video input terminal 2005 and the like. The present invention can be used in the display portion 2003 and other circuits.
The display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 23B shows a digital still camera including a main body 2101, a display portion 2102, an image receiving portion 2103,
An operation key 2104, an external connection port 2105, a shutter 2106 and the like are included. The present invention can be used in the display portion 2102 and other circuits.

FIG. 23C shows a laptop personal computer, which has a main body 2201, a housing 2202, and a display section 2.
203, keyboard 2204, external connection port 220
5, including a pointing mouse 2206 and the like. The present invention can be used in the display portion 2203 and other circuits.

FIG. 23D shows a mobile computer, which has a main body 2301, a display portion 2302, and a switch 230.
3, an operation key 2304, an infrared port 2305 and the like. The present invention can be used in the display portion 2302 and other circuits.

[0244] FIG. 23E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, a recording medium ( DVD, etc.) reading unit 240
5, an operation key 2406, a speaker portion 2407, and the like. The display portion A2403 mainly displays image information and the display portion B2404 mainly displays textual information, but the display portion A2403 can be used for the display portions A, B2403 and 2404 of the present invention and other circuits. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 23F shows a goggle type display (head mounted display), which is a main body 250.
1, a display portion 2502 and an arm portion 2503 are included. The present invention can be used in the display portion 2502 and other circuits.

FIG. 23G shows a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, and an image receiving portion 260.
6, a battery 2607, a voice input unit 2608, operation keys 2609, and the like. The present invention can be used in the display portion 2602 and other circuits.

[0247] Here, FIG. 23H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a voice input portion 2704, a voice output portion 2705, operation keys 2706,
An external connection port 2707, an antenna 2708, and the like are included.
The present invention can be used in the display portion 2703 and other circuits.

If the emission brightness of the organic light emitting material becomes higher in the future, it is possible to magnify and project light including image information emitted from the light emitting device with a lens or the like and use it for a front type or rear type projector. Become.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Further, this embodiment can be implemented by freely combining with Embodiments 1 to 9.

(Embodiment 11) In this embodiment, the T of the present invention is used.
In the FT, the characteristics of the TFT when the first electrode and the second electrode are electrically connected will be described.

FIG. 24A shows a sectional view of a TFT according to the present invention in which the first electrode and the second electrode are electrically connected.
For comparison, a cross-sectional view of a TFT having only one electrode is shown in FIG. In addition, FIG.
FIG. 25 shows the relationship between the gate voltage and the drain current obtained by simulation in the TFT shown in FIG.

The TFT shown in FIG. 24A has a first electrode 2801, a first insulating film 2802 in contact with the first electrode 2801, a semiconductor film 2808 in contact with the first insulating film 2802, and a semiconductor The second insulating film 2 in contact with the film 2808
806 and a second electrode 2807 which is in contact with the second insulating film. The semiconductor film 2808 is provided in the channel formation region 2
803, a first impurity region 2804 in contact with the channel formation region 2803, and a second impurity region 2805 in contact with the first impurity region 2804.

First electrode 2801 and second electrode 2807
Overlap with each other with the channel formation region 2803 sandwiched therebetween. Then, the first electrode 2801 and the second electrode 28
The same voltage is applied to 07.

First insulating film 2802 and second insulating film 2
806 is formed of silicon oxide. Also the first electrode,
The second electrode is made of Al. Channel length is 7μ
m, the channel width is 4 μm, the thickness of the first insulating film in the portion where the first gate electrode and the channel formation region overlap is 110 μm, and the second in the portion where the second gate electrode and the channel formation region overlap. The thickness of the insulating film is 11
It is 0 μm. The thickness of the channel formation region is 50 nm
And the length of the first impurity region in the channel length direction is 1.5 μm.

Then, 1 is formed in the channel formation region 2803.
An impurity imparting p-type of × 10 ¹⁷ / cm ³ is doped, and the first impurity region has an n of 3 × 10 ¹⁷ / cm ³ .
The impurity imparting type is doped, and the second impurity region is doped with the impurity imparting n-type of 5 × 10 ¹⁹ / cm ³ .

The TFT shown in FIG. 24B has a first insulating film 2902, a second insulating film 2906 in contact with the first insulating film 2902, and a second electrode 2 in contact with the second insulating film.
907. The semiconductor film 2908 includes a channel formation region 2903, a first impurity region 2904 in contact with the channel formation region 2903, and a first impurity region 290.
4 has a second impurity region 2905 which is in contact with 4.

The second electrode 2907 overlaps with the channel formation region 2903.

First insulating film 2902 and second insulating film 2
906 is formed of silicon oxide. The second electrode is made of Al. The channel length is 7 μm, the channel width is 4 μm, and the thickness of the second insulating film in the portion where the second gate electrode and the channel formation region overlap is 110 μm.
m. The thickness of the channel formation region is 50 nm, and the length of the first impurity region in the channel length direction is 1.5 μm.

Then, 1 is formed in the channel formation region 2903.
An impurity imparting p-type of × 10 ¹⁷ / cm ³ is doped, and the first impurity region has an n of 3 × 10 ¹⁷ / cm ³ .
The impurity imparting type is doped, and the second impurity region is doped with the impurity imparting n-type of 5 × 10 ¹⁹ / cm ³ .

In FIG. 25, the horizontal axis represents the gate voltage and the vertical axis represents the drain current. FIG. 24 (A)
The drain current value with respect to the gate voltage of the TFT of is shown by a solid line, and the drain current value with respect to the gate voltage of the TFT of FIG.

From FIG. 25 to FIG. 24A, the TFT
Mobility of 139 cm ² / V · s, S value of 0.118 V / d
ec was obtained. Further, in FIG. 24B, the TFT mobility is 86.3 cm ² / V · s and the S value is 0.160 V / d.
ec was obtained. From this, when the first electrode and the second electrode are provided and the second electrode is electrically connected, the mobility is higher than that when only one electrode is provided, and S
The value becomes smaller.

(Embodiment 12) In this embodiment, an embodiment of a thin film transistor included in the semiconductor device of the present invention will be described with reference to FIG.

FIG. 26 shows a sectional view of the thin film transistor of this embodiment. The thin film transistor shown in FIG.
Electrode 3001, a first insulating film 3002 in contact with the first electrode 3001, a semiconductor film 3008 in contact with the first insulating film 3002, a second insulating film 3006 in contact with the semiconductor film 3008, and a second insulating film Second electrode 300 in contact with the membrane
Have 7. The semiconductor film 3008 includes a channel formation region 3003 and a first formation region which is in contact with the channel formation region 3003.
Impurity region 3004 and a second impurity region 3005 in contact with the first impurity region 3004.

The concentration of one conductivity type impurity added to the first impurity region 3004 is the same as that of the second impurity region 300.
The concentration is lower than the concentration of one conductivity type impurity added to No. 5.

[0265] The first electrode 3001 and the second electrode 3007
Overlap with each other with the channel formation region 3003 interposed therebetween. Then, the first electrode 3001 and the second electrode 30
The same voltage is applied to 07.

In the thin film transistor of this example, the tapered portion of the first electrode 3001 overlaps with the first impurity region 3004. And the first electrode 30
01 is substantially flat in the portion overlapping with the channel formation region 3003. With the above configuration, the first
The electrode and the channel forming region overlap with each other at a substantially constant interval. In this state, the film thickness of the first insulating film in the portion where the first electrode and the channel formation region overlap and the thickness of the second insulating film in the portion where the second electrode and the channel formation region overlap If the film thickness is made substantially the same, the S value can be made smaller.

This embodiment can be implemented in combination with Embodiments 1 to 11.

(Embodiment 13) In this embodiment, a drive circuit of a light emitting device of the present invention will be described. In the present invention, a decoder using a p-channel TFT as shown in FIG. 27 is used instead of a general shift register. Note that FIG.
Is an example of a scanning line driving circuit.

In FIG. 27, reference numeral 900 is a decoder of the scanning line driving circuit, and 901 is a buffer portion of the scanning line driving circuit. The buffer section means a section in which a plurality of buffers (buffer amplifiers) are integrated.

First, the decoder 900 of the scanning line driver circuit will be described. First, reference numeral 902 denotes an input signal line (hereinafter, referred to as a selection line) of the decoder 900, here A1, A1.
Bar (a signal in which the polarity of A1 is inverted), A2, A2 bar (a signal in which the polarity of A2 is inverted), ... An, An bar (A
signal in which the polarity of n is inverted). That is, it can be considered that 2n selection lines are lined up.

The number of select lines depends on how many gate wirings are output from the scanning line driving circuit. For example, in the case of having a pixel portion for VGA display, since there are 480 gate wirings, 9 bits worth (equivalent to n = 9)
Therefore, a total of 18 selection lines are required. The selection line 902 transmits the signals shown in the timing chart of FIG. Figure 2
As shown in FIG. 8, ^assuming that the frequency of A1 is 1, the frequency of A2 is 2 ⁻¹ times, the frequency of A3 is 2 ⁻² times, and the frequency of An is 2 ^{− (n−1)} times.

Reference numeral 903a denotes a first stage NAND circuit (also referred to as a NAND cell), and 903b denotes a second stage NAN.
The D circuit, 903c, is the n-th stage NAND. NAND
The circuit requires as many gate wirings as possible, and n circuits are required here. That is, in the present invention, the decoder 900 is composed of a plurality of NAND circuits.

NAND circuits 903a to 903c are also provided.
Form a NAND circuit by combining the p-channel TFTs 904 to 909. Note that 2n TFTs are actually used in the NAND circuit 903. The gates of the p-channel TFTs 904 to 909 are provided with select lines 902 (A1, A1 bar, A2, A2 bar ... A).
n, An bar).

At this time, in the NAND circuit 903a,
, A1, A2 ... An (these are called positive selection lines)
P-channel TF with gate connected to either
T904 to 906 are connected in parallel with each other, and
Positive power supply line (V _DH) Connected to 910,
It is connected to the output line 911 as a common drain.
In addition, A1 bar, A2 bar ... An bar (these are negative selections)
P) with a gate connected to either
The channel type TFTs 907 to 909 are connected in series with each other.
P-channel TFT 90 located at the circuit end
The source of 9 is the negative power supply line (V_DL) Connected to 912
The p-channel TFT 907 located at one circuit end is
Rain is connected to output line 911.

As described above, in the present invention, the NAND circuit includes n number of one conductivity type TFTs connected in series (here, p channel type TFT) and n number of one conductivity type TFTs connected in parallel (here, n type conductivity type TFT). p-channel TFT).
However, in the n NAND circuits 903a to 903c, the combinations of p-channel TFTs and select lines are all different. That is, only one output line 911 is always selected, and the output line 911 is selected as the selection line 902.
A signal is input so that is sequentially selected from the end.

Next, the buffer 901 is the NAND circuit 90.
3a to 903c corresponding to the plurality of buffers 913
a to 913c. However, buffer 91
All of 3a to 913c may have the same structure.

The buffers 913a to 913c are formed by using p-channel type TFTs 914 to 916 as one conductivity type TFTs. Output line 911 from decoder 900
Is a p-channel TFT 914 (first one conductivity type TFT)
Connected with the gate of. The p-channel TFT 914 uses the ground power supply line (GND) 917 as a source and the gate wiring 9
18 is the drain. In addition, the p-channel TFT 91
5 (second one conductivity type TFT) is always on with the ground power supply line 917 as a gate, the positive power supply line (V _DH ) 919 as a source, and the gate wiring 918 as a drain.

That is, the buffers 913a to 913c are the first
Second one-conductivity-type TFT (p-channel TFT 914) and second one-conductivity-type TFT (p-channel TFT 914) connected in series with the first one-conductivity-type TFT and having the drain of the first one-conductivity-type TFT as a gate. Type TFT 915).

Further, the p-channel TFT 916 (third third conductivity type TFT) uses the reset signal line (Reset) as a gate, the positive power supply line 919 as a source, and the gate wiring 918.
Is the drain. The ground power supply line 917 is a negative power supply line (however, a power supply line that gives a voltage such that a p-channel TFT used as a switching element of a pixel is turned on).
It doesn't matter.

At this time, there is a relationship of W1 <W2 between the channel width of the p-channel TFT 915 (referred to as W1) and the channel width of the p-channel TFT 914 (referred to as W2). The channel width is the length of the channel formation region in the direction perpendicular to the channel length.

The operation of the buffer 913a is as follows. First, when a positive voltage is applied to the output line 911,
The p-channel TFT 914 is turned off (no channel is formed). On the other hand, p-channel TFT
Since 915 is always on (a channel is formed), the positive power supply line 919 is connected to the gate wiring 918.
Is applied.

However, when a negative voltage is applied to the output line 911, the p-channel TFT 914 is turned on. At this time, since the channel width of the p-channel TFT 914 is larger than the channel width of the p-channel TFT 915, the potential of the gate wiring 918 is the p-channel TFT 9
14 is pulled to the output, and as a result, the ground power line 917
Is applied to the gate wiring 918.

Therefore, the gate wiring 918 is connected to the output line 91.
When a negative voltage is applied to 1, a negative voltage (a voltage that turns on a p-channel TFT used as a pixel switching element) is output, and when a positive voltage is applied to the output line 911, it is always positive. A voltage (a voltage at which a p-channel TFT used as a pixel switching element is turned off) is output.

Note that the p-channel TFT 916 is used as a reset switch for forcibly raising the gate wiring 918 to which a negative voltage is applied to a positive voltage. That is, when the selection period of the gate wiring 918 ends. A reset signal is input and a positive voltage is applied to the gate wiring 918. However, the p-channel TFT 916 can be omitted.

The scanning line drive circuit having the above-described operation sequentially selects the gate wirings.

Next, FIG. 29 shows the structure of the data line drive circuit. The data line driving circuit shown in FIG.
1, a latch 3302 and a buffer 3303. Since the configurations of the decoder 3301 and the buffer 3303 are similar to those of the scan line driver circuit, description thereof is omitted here.

In the case of the data line driving circuit shown in FIG. 29, the latch 3302 is composed of a first stage latch 3304 and a second stage latch 3305. The first-stage latch 3304 and the second-stage latch 3305 each have a plurality of unit units 3307a formed by m p-channel TFTs 3306a to 3306c. The output line 3308 from the decoder 3301 is a unit unit 3307.
m number of p-channel TFTs 3306a to 3306 forming a
It is input to the gate of 306c. In addition, m is an arbitrary integer.

For example, in the case of VGA display, the number of source wirings is 640. When m = 1, 640 NAND circuits are required, and 20 selection lines (corresponding to 10 bits) are required. However, if m = 8, the required N
There are 80 AND circuits, and the required selection lines are 14 (7
It corresponds to bit minutes). That is, assuming that the number of source wirings is M, the required NAND circuits are (M / m).

Then, the p-channel TFTs 3306a-
The sources of 3306c are video signal lines (V1, V2 ...
Vk) 3309. That is, when a negative voltage is applied to the output line 3308, the p-channel type TFTs 330 are simultaneously operated.
6a to 3306c are turned on, and the video signal corresponding to each is captured. In addition, the video signals thus captured are p-channel TFTs 3306a to 330.
Capacitors 3310a-331 connected to each of 6c
It is held at 0c.

The second stage latch 3305 also has a plurality of unit units 3307b.
b is m p-channel type TFTs 3311a to 3311c
Is formed by. p-channel type TFTs 3311a to 331
All the gates of 1c are connected to the latch signal line 3312, and when a negative voltage is applied to the latch signal line 3312, the p-channel TFTs 3311a to 3311c are simultaneously turned on.

As a result, capacitors 3310a-331
The signal held at 0c is the p-channel TFT 33.
Capacitor 33 connected to each of 11a to 3311c
13a to 3313c, the buffer 33
It is output to 03. Then, as described in FIG. 27, the signal is output to the source wiring 3314 via the buffer. The source line is sequentially selected by the data line driving circuit having the above operation.

As described above, by forming the scanning line driving circuit and the data line driving circuit only by the p-channel type TFT, the pixel portion and the driving circuit are all p-channel type TF.
It becomes possible to form T. Therefore, in manufacturing an active matrix light emitting device, the yield and throughput of the TFT process can be significantly improved, and the manufacturing cost can be reduced.

The present invention can be implemented when either the data line driving circuit or the scanning line driving circuit is an external IC chip.

This embodiment can be implemented in combination with the first to twelfth embodiments. (Embodiment 14) In this embodiment, a measured value of the drain current Id with respect to the voltage difference (gate voltage Vgs) between the second electrode and the source region in the TFT having two electrodes according to the present invention will be described. In addition, the actual measurement value was calculated | required in each case when the 1st electrode was set to GND and when the 1st electrode and the 2nd electrode were electrically connected. Further, for comparison, a measured value of the drain current Id with respect to the gate voltage of the TFT without the first electrode was also obtained.

A concrete structure of the TFT used in this embodiment is shown in FIG. FIG. 34A shows a top view of a TFT having two electrodes of the present invention, and FIG. 34B shows a cross-sectional view taken along the line AA ′ of FIG. 34A. In addition, FIG. 34 (C)
A top view of a TFT having only the second electrode for comparison is shown in FIG. 34, and a cross-sectional view taken along line BB ′ of FIG.
4 (D).

In the TFT shown in FIGS. 34A and 34B, a base film 901 using a SiNO film is formed on a glass substrate 900 with a thickness of 50 nm.
W of 00 nm is formed as the first electrode 902. Then, the base film 90 is formed so as to cover the first electrode 902.
First insulating film 903 which functions as a gate insulating film on
Is deposited. Note that the first insulating film 903 is formed of 110
nm SiNO film.

A semiconductor film 904 having a thickness of 54 nm is formed on the first insulating film 903. Next, SiN
A 115-nm-thick second insulating film 905 was formed using an O film. Then, a second electrode 906 including two conductive films 906a and 906b is formed over the second insulating film 905. In this example, TaN of 50 nm and 370 nm
A second electrode 906 was formed by stacking W and W. Further, impurities are added to the semiconductor film 904, and the semiconductor film 90
Reference numeral 4 has a channel formation region 907 and an impurity region 908 sandwiching the channel formation region.

The TFT shown in FIGS. 34C and 34D is different from that shown in FIG. 34 only in that the first electrode 902 is not provided.
This is different from the TFTs shown in (A) and (B).

The voltage difference (gate voltage Vgs) between the second electrode and the source region of the TFT shown in FIGS. 34C and 34D.
The measured value of the drain current Id with respect to is shown in FIG. In the TFT shown in FIGS. 34A and 34B, the first
32 shows measured values of the drain current Id with respect to the voltage difference (gate voltage Vgs) between the second electrode and the source region when the electrode 902 of FIG. Also, FIG.
In the TFTs shown in (A) and (B), the first electrode 90
2 when the second electrode 906 and the second electrode 906 are electrically connected
33 shows measured values of the drain current Id with respect to the voltage difference (gate voltage Vgs) between the electrode and the source region. In each graph, the solid line shows the drain current Id and the broken line shows the mobility.

From the comparison between FIG. 31 and FIGS. 32 and 33,
It can be seen that the threshold value is closer to 0 and the S value is improved when the first electrode is provided, as compared with the case where the first electrode is not provided. Further, from the comparison between FIG. 32 and FIG. 33, the on-current is higher in the case where the first electrode and the second electrode are electrically connected than in the case where the first electrode is grounded. You can see it getting higher.

[0301]

According to the present invention, by applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

Further, by applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same manner as when the thickness of the semiconductor film is made thin, so that the subthreshold coefficient is It is possible to reduce the size and further improve the field effect mobility. Further, it is possible to suppress variation in threshold value as compared with the case where there is one electrode. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Therefore, by using the TFT having this structure in the drive circuit, the drive voltage can be lowered. Also, since the on-current can be increased,
The size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a TFT of the present invention.

2A to 2C are cross-sectional views illustrating a manufacturing process of a light-emitting device.

3A to 3C are cross-sectional views illustrating a manufacturing process of a light-emitting device.

4A to 4C are cross-sectional views illustrating a manufacturing process of a light-emitting device.

5A to 5C are cross-sectional views illustrating a manufacturing process of a light-emitting device.

6A to 6C are top views illustrating manufacturing steps of a light-emitting device.

FIG. 7 is a top view illustrating a manufacturing process of a light-emitting device.

FIG. 8 is a top view of a pixel of a light emitting device.

FIG. 9 is a top view of a pixel of a light emitting device.

FIG. 10 is a cross-sectional view of a pixel of a light emitting device.

FIG. 11 is a top view of a pixel of a light emitting device.

FIG. 12 is a cross-sectional view of a pixel of a light emitting device.

FIG. 13 is a top view of a pixel of a light emitting device.

FIG. 14 is a cross-sectional view of a pixel of a light emitting device.

FIG. 15 is a top view of a pixel of a light emitting device.

FIG. 16 is a cross-sectional view of a pixel of a light emitting device.

FIG. 17 is a diagram showing a step of crystallizing a semiconductor layer.

FIG. 18 is a diagram showing a step of crystallizing a semiconductor layer.

FIG. 19 is a diagram showing a step of crystallizing a semiconductor layer.

FIG. 20 is a diagram showing a step of crystallizing a semiconductor layer.

FIG. 21 is a block diagram illustrating a structure of a light emitting device.

22A and 22B are an external view and a cross-sectional view of a light-emitting device.

FIG. 23 is a diagram of an electronic device including a semiconductor device of the present invention.

FIG. 24 is a diagram showing a structure of a TFT used for simulation.

FIG. 25 is a diagram showing characteristics of TFTs obtained by simulation.

FIG. 26 is a cross-sectional view of a thin film transistor of the invention.

FIG. 27 is a circuit diagram of a scan line driver circuit of a light emitting device of the present invention.

FIG. 28 is a timing chart of a scan line driver circuit of a light emitting device of the present invention.

FIG. 29 is a circuit diagram of a data line driving circuit of a light emitting device of the present invention.

30A and 30B are a circuit diagram of a general thin film transistor and a circuit diagram of a thin film transistor of the invention.

FIG. 31 is an actual measurement value of Id-Vgs characteristics of a general TFT.

FIG. 32 is a measured value of Id-Vgs characteristics of the TFT of the present invention.

FIG. 33 is an actual measurement value of Id-Vgs characteristics of the TFT of the present invention.

34A and 34B are a top view and a cross-sectional view of a TFT whose measured values are obtained.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 612C F term (reference) 3K007 AB05 AB17 AB18 BA06 BB07 DA05 GA04 5C094 AA13 AA15 AA25 BA03 BA27 CA19 CA25 DA09 DA13 DB01 DB04 EA04 EA07 FA01 FA02 FB01 FB20 5F052 AA02 AA24 BB02 BB07 DA02 DA03 DB02 DB03 DB07 EA16 FA06 FA19 HA01 JA01 JA03 JA04 5F110 AA01 AA06 AEEEEEEEE BB02 BB02 BB02 BB02 BB04 CC10 DD01 DD02 DD03 EE02 EE02 DF02 DD11 EE02 FF03 FF04 FF09 FF28 FF30 GG01 GG02 GG13 GG31 GG34 GG43 GG45 GG47 HJ04 HJ06 HJ12 HJ13 HJ23 HL03 HL04 HL11 HM15 NN03 NN04 PP PP23 PP23 PP23Q PP23 PP23Q PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP25 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP17 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP23 PP17 PP23 PP23 PP23 PP23 PP23 PP2 PP3 NN3 NN3 NN3 NN3 NN3 NN3 ONE4

Claims (11)

[Claims] 1. A light emitting device having a first wiring, a second wiring, a third wiring, a fourth wiring, a first thin film transistor, a second thin film transistor, and a light emitting element. The first and second thin film transistors include a first electrode, a first insulating film in contact with the first electrode, and the first thin film.
A semiconductor film in contact with the insulating film, a second insulating film in contact with the semiconductor film, and a second electrode in contact with the second insulating film, respectively, and covering the first wiring. A first insulating film is formed, the second and third wirings are formed on the second insulating film, and a third insulating film is formed to cover the second and third wirings.
An insulating film is formed, the fourth wiring is formed on the third insulating film, and the first wiring and the first electrode of the first thin film transistor are connected to each other. The second wiring is connected to the second electrode of the first thin film transistor, and the semiconductor film of the first thin film transistor has 2
One of the impurity regions is connected to the third wiring and the other is connected to the first and second electrodes of the second thin film transistor, and the two impurity regions are included in the semiconductor film of the second thin film transistor.
One of the impurity regions is connected to the fourth wiring and the other is connected to a pixel electrode of the light emitting element, and the semiconductor film has a channel formation region sandwiched between the two impurity regions. The first electrode and the second electrode are overlapped with each other with the channel forming region interposed therebetween, and the first insulating film and the second insulating film have substantially the same dielectric constant, The film thickness of a portion of the first insulating film overlapping with the first electrode and the film thickness of a portion of the second insulating film overlapping with the second electrode are substantially the same. Light emitting device. 2. The fifth wiring according to claim 1, wherein the second wiring adjacent to each other has a fifth wiring formed on the third insulating film through a contact hole formed in the third insulating film. A light-emitting device characterized in that it is connected together with. 3. A light emitting device having a first wiring, a second wiring, a third wiring, a fourth wiring, a first thin film transistor, a second thin film transistor, and a light emitting element. The first and second thin film transistors include a first electrode, a first insulating film in contact with the first electrode, and the first thin film.
A semiconductor film in contact with the insulating film, a second insulating film in contact with the semiconductor film, and a second electrode in contact with the second insulating film, respectively, and covering the first wiring. A first insulating film is formed, the third and fourth wirings are formed on the second insulating film, and a third insulating film is formed to cover the third and fourth wirings.
An insulating film is formed, the second wiring is formed on the third insulating film, and the first wiring is connected to the first electrode of the first thin film transistor. The second wiring is connected to the second electrode of the first thin film transistor, and the semiconductor film of the first thin film transistor has 2
One of the impurity regions is connected to the third wiring and the other is connected to the first and second electrodes of the second thin film transistor, and the two impurity regions are included in the semiconductor film of the second thin film transistor.
One of the impurity regions is connected to the fourth wiring and the other is connected to a pixel electrode of the light emitting element, and the semiconductor film has a channel formation region sandwiched between the two impurity regions. The first electrode and the second electrode are overlapped with each other with the channel formation region interposed therebetween, and the first insulating film and the second insulating film have substantially the same dielectric constant, The film thickness of a portion of the first insulating film overlapping with the first electrode and the film thickness of a portion of the second insulating film overlapping with the second electrode are substantially the same. Light emitting device. 4. A light emitting device having a first wiring, a second wiring, a third wiring, a fourth wiring, a first thin film transistor, a second thin film transistor, and a light emitting element. The first and second thin film transistors include a first electrode, a first insulating film in contact with the first electrode, and the first thin film.
A semiconductor film in contact with the insulating film, a second insulating film in contact with the semiconductor film, and a second electrode in contact with the second insulating film, respectively, and covering the first wiring. A first insulating film is formed, the third wiring is formed on the second insulating film, and a third insulating film is formed so as to cover the third wiring, The second and fourth wirings are formed on a third insulating film, the first wiring is connected to the first electrode of the first thin film transistor, and the second wiring is formed. The wiring is connected to the second electrode of the first thin film transistor, and the semiconductor film of the first thin film transistor has 2
One of the impurity regions is connected to the third wiring and the other is connected to the first and second electrodes of the second thin film transistor, and the two impurity regions are included in the semiconductor film of the second thin film transistor.
One of the impurity regions is connected to the fourth wiring and the other is connected to a pixel electrode of the light emitting element, and the semiconductor film has a channel formation region sandwiched between the two impurity regions. The first electrode and the second electrode are overlapped with each other with the channel formation region interposed therebetween, and the first insulating film and the second insulating film have substantially the same dielectric constant, The film thickness of a portion of the first insulating film overlapping with the first electrode and the film thickness of a portion of the second insulating film overlapping with the second electrode are substantially the same. Light emitting device. 5. The fifth wiring according to claim 4, wherein the adjacent second wirings are formed on the second insulating film through a contact hole formed in the third insulating film. A light-emitting device characterized in that it is connected together with. 6. A light emitting device having a first wiring, a second wiring, a third wiring, a fourth wiring, a first thin film transistor, a second thin film transistor, and a light emitting element. The first and second thin film transistors include a first electrode, a first insulating film in contact with the first electrode, and the first thin film.
A second insulating film in contact with the semiconductor film, a second insulating film in contact with the semiconductor film, and a second electrode in contact with the second insulating film. The first insulating film is formed so as to cover the third insulating film, the third wiring is formed on the second insulating film, and the third insulating film is formed so as to cover the third wiring. The second wiring is formed on the third insulating film, the first wiring is connected to the first electrode of the first thin film transistor, and the second wiring is formed. The wiring is connected to the second electrode of the first thin film transistor, and the semiconductor film of the first thin film transistor has 2
One of the impurity regions is connected to the third wiring and the other is connected to the first and second electrodes of the second thin film transistor, and the two impurity regions are included in the semiconductor film of the second thin film transistor.
One of the impurity regions is connected to the fourth wiring and the other is connected to a pixel electrode of the light emitting element, and the semiconductor film has a channel formation region sandwiched between the two impurity regions. The first electrode and the second electrode are overlapped with each other with the channel forming region interposed therebetween, and the first insulating film and the second insulating film have substantially the same dielectric constant, The film thickness of a portion of the first insulating film overlapping with the first electrode and the film thickness of a portion of the second insulating film overlapping with the second electrode are substantially the same. Light emitting device. 7. The adjacent fourth wiring according to claim 6, wherein the second wiring is provided through the contact holes formed in the first and second insulating films.
And a fifth wiring formed on the insulating film of FIG. 8. A light emitting device having a first wiring, a second wiring, a third wiring, a fourth wiring, a first thin film transistor, a second thin film transistor, and a light emitting element. The first and second thin film transistors include a first electrode, a first insulating film in contact with the first electrode, and the first thin film.
A semiconductor film in contact with the insulating film, a second insulating film in contact with the semiconductor film, and a second electrode in contact with the second insulating film, respectively, and covering the first wiring. A first insulating film is formed, the second and third wirings are formed on the second insulating film, and a third insulating film is formed to cover the second and third wirings.
An insulating film is formed, the fourth wiring is formed on the third insulating film, the first wiring, the first electrodes of the first and second thin film transistors, Is connected, the second wiring is connected to the second electrode of the first thin film transistor, and the semiconductor film of the first thin film transistor has 2
One of the impurity regions is connected to the third wiring and the other is connected to the second electrode of the second thin film transistor, and the two impurity regions are included in the semiconductor film of the second thin film transistor.
One of the impurity regions is connected to the fourth wiring and the other is connected to a pixel electrode of the light emitting element, and the semiconductor film has a channel formation region sandwiched between the two impurity regions. The first electrode and the second electrode are overlapped with each other with the channel forming region interposed therebetween, and the first insulating film and the second insulating film have substantially the same dielectric constant, The film thickness of a portion of the first insulating film overlapping with the first electrode and the film thickness of a portion of the second insulating film overlapping with the second electrode are substantially the same. Light emitting device. 9. The fifth wiring according to claim 8, wherein the second wiring adjacent to each other has a fifth wiring formed on the third insulating film through a contact hole formed in the third insulating film. A light-emitting device characterized in that it is connected together with. 10. The semiconductor film according to claim 1, wherein the semiconductor film of the first thin film transistor has 2
One of the impurity regions is a sixth wiring formed on the third insulating film, the other is a seventh wiring formed on the third insulating film, and the second and third impurity regions are formed. Is connected through a second contact hole formed in the insulating film, and the sixth wiring is connected to the third contact film formed in the third insulating film.
Is connected to the third wiring through a contact hole of, and the seventh wiring is a fourth wiring formed on the third insulating film.
Is connected to the second electrode of the second thin film transistor through a contact hole of the second thin film transistor, and the second electrode of the second thin film transistor is a fifth contact formed in the second insulating film. It is connected to the first electrode of the second thin film transistor through a hole, the semiconductor film has a channel forming region sandwiched between the two impurity regions, and the first electrode and the The second electrode is overlapped with the channel formation region sandwiched therebetween, and the first insulating film and the second insulating film have substantially the same dielectric constant, and the second electrode of the first insulating film is the same. 1. A light emitting device, wherein a film thickness in a portion overlapping with the first electrode and a film thickness in a portion overlapping with the second electrode of the second insulating film are substantially the same. 11. The light emitting device according to claim 1, wherein the first insulating film is planarized by chemical mechanical polishing.