JP2003134479A - Video and sound multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide 270 Mb/s serial data stipulated in SMPTE-259M by multiplexing an NTSC composite television signal and a composite sound signal. SOLUTION: A video FIFO memory 2 reads a 10-bit video data signal Dv1 sampled at 14.318 MHz in accordance with 27 MHz timing clock signal CL4. A sound FIFO memory 4 reads a 10-bit video data signal Da1 sampled at 1 MHz in accordance with the 27 MHz timing clock signal CL4. A multiplexing part (MPX) 8 multiplexes a video data signal Dv2, a sound data signal Da2 and a frame synchronizing data signal Df in time division and outputs the multiplexed signal as a 10-bit multiplexed data signal Do1. A P/S converting part 10 converts the multiplexed data signal Do1 into a 270 Mb/s serial data signal Do2 in accordance with a 270 MHz timing clock CL7 generated by a multiplying part 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video / audio multiplexer, and more particularly to a video / audio for multiplexing an NTSC composite television signal and a composite audio signal and outputting as a 270 Mb / s serial data signal defined in SMPTE-259M. It relates to a multiplexer.

[0002]

2. Description of the Related Art As a format of a digital video signal in a broadcasting station, a Society of Motion Picture and Television Engineers (SMPTE: Society of Motion)
Picture and Television En
There is a serial data signal defined by G.

A data transmission rate of 270 Mb / s is defined as a format of a component digital television signal (a signal divided into a luminance component and a color difference component) called D1 defined in SMPTE-259M. In addition, as the format of the composite digital television signal called D2, the data transmission rate 1
43 Mb / s is specified.

A large number of signal distributors and transmission devices corresponding to these serial data signals are installed in the broadcasting station.

By the way, when an audio signal is transmitted together with an NTSC composite television signal, for example, when the audio signal is a composite audio signal, the composite audio signal is once returned to an audio baseband signal by a decoder and then multiplexed into a video data signal. The signal is transmitted, the audio baseband signal is separated at the transmission destination, and is returned to the composite audio signal by the encoder.

The composite audio signal is, for example, as shown in FIG. 6, a signal in which a plurality of audio signals are multiplexed into one signal by means such as frequency division, and includes a main channel signal, a sub-channel signal and a sub-channel signal. Broadcast mode control signal A signal in which subcarriers are frequency division multiplexed.

[0007]

As described above, conventionally, when transmitting a composite voice signal, the composite voice signal is once converted into a voice baseband signal by a decoder and then transmitted, and the voice baseband signal is encoded at the transmission destination. To restore the composite audio signal.

However, the composite audio signal is multiplexed with the composite digital television signal to obtain the SMPTE-259 signal.
If it can be mapped to the 270 Mb / s serial data signal defined in M, it can be transmitted using a signal distributor or transmission device for the 270 Mb / s serial data signal, and the facility efficiency in the broadcasting station can be improved.

An object of the present invention is to multiplex an NTSC composite television signal and a composite audio signal to produce an SMPT.
An object of the present invention is to provide a video / audio multiplexer that outputs a 270 Mb / s serial data signal defined in E-259M.

[0010]

A video / audio multiplexer of the present invention is a video / audio multiplexer for multiplexing an NTSC composite television signal and a composite audio signal, wherein the NTSC composite television signal is a color subcarrier. Audio data is sampled at a frequency four times (14.318 MHz), converted into a video data signal, written in a video FIFO memory and read by a first timing clock of frequency 27 MHz, and the composite audio signal is sampled at a frequency 1 MHz. The signal is converted into a signal, written in the audio FIFO memory, read out by the second timing clock having a frequency of 27 MHz, and further, a frame synchronization data signal is generated in accordance with the timing clock having a frequency of 27 MHz, respectively from the video FIFO memory and the audio FIFO memory. Out Amount of data, as well as the ratio of the data amount of the frame sync data signal is 1 in the frame period 315: 22: comprising means for time division multiplexing such that the 257.

Specifically, an NTSC composite television signal and a composite audio signal are multiplexed to obtain 270 Mb /
A video / audio multiplexer for outputting as a s serial data signal, wherein the NTSC composite television signal is converted into a 10-bit parallel video data signal in response to a sampling clock signal which is four times the color subcarrier frequency (14.318 MHz). A video A / D conversion unit for conversion, a video FIFO for writing an output data signal of the video A / D conversion unit and reading the output data signal according to a first timing clock signal of a frequency of 27 MHz, and the composite audio signal for a frequency of 1M.
A voice A / D conversion unit for converting into a 10-bit parallel voice data signal according to a sampling clock signal of Hz, and a second timing clock signal with a frequency of 27 MHz while writing the output data signal of the voice A / D conversion unit. An audio FIFO to be read out by the above, a sampling clock generation unit for generating the sampling clock signal, a frame synchronization data generation unit for generating a 10-bit parallel frame synchronization data signal according to a third timing clock signal having a frequency of 27 MHz, A timing clock generation unit that generates the first timing clock signal, the second timing clock signal, and the third timing clock signal, and the video FIFO.
10-bit parallel video data signals and audio data signals respectively output from the memory and the audio FIFO memory, and a frame synchronization data signal from the frame synchronization data generator are received, and each data signal is time-division multiplexed 10. A multiplexing unit for outputting a bit parallel video / audio multiplexed data signal, and the frequency of 27 MH
The third timing clock signal of z is multiplied by 10, and 27
A multiplication unit that generates a 0 MHz timing clock signal and a P / S conversion unit that serially converts the 10-bit parallel video / audio multiplexed data signal according to the 270 MHz timing clock signal are provided.

Further, the timing clock generator is
The first timing clock so that the ratio of the data amounts of the video data signal, the audio data signal, and the frame synchronization data signal input to the multiplexing unit becomes 315: 22: 257 in one frame period and time division multiplexing is performed. And the second timing clock and the third timing clock
Timing clocks are generated respectively.

Further, the sampling clock generation section includes a color subcarrier extraction circuit for extracting a color subcarrier of the NTSC composite television signal, and a pulse generation circuit for generating a pulse synchronized with the extracted color subcarrier. A first multiplication circuit that multiplies the pulse by 4 to output the 14.318 MHz sampling clock signal that is four times the color subcarrier frequency, and a second multiplication circuit that multiplies the 14.318 MHz sampling clock signal by 66. And the output of this second multiplication circuit is divided by 35 to 27M
A first frequency dividing circuit for outputting a clock signal of 1 Hz and the 1 MHz by dividing the 27 MHz clock signal by 27
And a second frequency dividing circuit for outputting the sampling clock signal.

Furthermore, the audio A / D converter divides the sampling clock signal having the frequency of 1 MHz by 2 to generate a sampling clock signal of 500 kHz, and the composite audio signal is sampled at the frequency of 500 kHz. An A / D conversion circuit for converting a 20-bit parallel audio data signal according to a clock signal;
And a selection circuit for alternately selecting the upper 10 bits and the lower 10 bits of the bit parallel audio data signal according to the 500 kHz sampling clock signal and outputting the selected 10 bit parallel audio data signal. Good.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a video signal Sv and an audio signal Sa are multiplexed and 270 Mb / s specified in SMPTE-259M.
2 shows a video / audio multiplexer that outputs the serial data signal Ds.

Here, the input video signal Sv is an EIA RS- established by the Electronic Industries Association (EIA).
It is a 170A standard NTSC composite television signal.

The input audio signal Sa is a composite audio signal obtained by multiplexing a plurality of audio signals into one signal by means of frequency division or the like. For example, as shown in FIG. 6, a main channel signal and a sub channel signal. And a broadcast mode control signal is a signal in which subcarriers are frequency division multiplexed.

In FIG. 1, a video A / D converter 1 for digitally converting an input video signal Sv into a video data signal Dv1, and a video FIFO memory 2 for writing the video data signal Dv1 and reading it as a video data signal Dv2. , An audio A / D converter 3 for digitally converting the input audio signal Sa into an audio data signal Da1, and an audio data signal Da1.
Audio FIFO memory 4 for writing and reading out as an audio data signal Da2, a sampling clock generation unit 5 for generating sampling clock signals CL1 and CL2 and a timing clock CL3 based on the color subcarrier of the input video signal Sv, and an image. FIFO memory 2,
4, a timing clock generator 6 for generating the read timing clocks CL4 and CL5 and a frame synchronization data generation timing clock CL6, and a frame synchronization data generator 7 for generating a frame synchronization data signal Df according to the timing clock CL6. , The video data signal Dv2, the audio data signal Da2, and the frame synchronization data signal Df are time-division multiplexed to output as a video / audio multiplexed data signal Do1, and the timing clock CL6 is multiplied to obtain a timing clock CL7. The multiplication unit 9 to generate and the timing clock CL
A P / S converter 10 for converting the video / audio multiplexed data signal Do1 into a serial data signal Do2 in accordance with 7; and a scrambler 11 for scrambling the serial data signal Do2 and outputting it as a video / audio multiplexed serial data signal Ds. Is equipped with.

Here, the video A / D conversion unit 1 samples the video signal Sv according to the sampling clock signal CL1 which is four times (14.318 MHz) the color subcarrier frequency, and the 10-bit parallel video data signal Dv1. Convert to.

The video FIFO memory 2 is a dual port memory capable of simultaneously executing writing / reading, and writes the video data signal Dv1 in response to the sampling clock signal CL1 and reads it in response to the timing clock signal CL4 having a frequency of 27 MHz. It is output as a 10-bit parallel video data signal Dv2.

The audio A / D converter 3 receives the audio signal Sa according to the sampling clock signal CL2 having a frequency of 1 MHz.
Is sampled and converted into a 10-bit parallel audio data signal Da1.

The audio FIFO memory 4 is a dual port memory capable of executing writing / reading at the same time. The audio data signal Da1 is written according to the sampling clock signal CL2, and the audio data signal Da1 is read according to the timing clock CL5 having a frequency of 27 MHz. It is output as a bit parallel audio data signal Da2.

The sampling clock generating section 5 is based on the color subcarrier of the input video signal Sv and sampling clock signals CL1 and CL2 and a timing clock CL.
3 are generated respectively.

FIG. 2 is a block diagram showing an example of the sampling clock generator 5.

Input video signal Sv, that is, NTSC
Color subcarrier of composite television signal (3.57
95 MHz) for extracting the color subcarrier, a pulse generating circuit 52 for generating a pulse synchronized with the extracted color subcarrier, and a pulse for 3.5795 MHz multiplied by 4 to obtain a frequency of 4 times the color subcarrier frequency. A first multiplication circuit 53 that outputs a sampling clock signal CL1 of 14.318 MHz, a second multiplication circuit 54 that multiplies the sampling clock signal CL1 by 66, and an output (about 945 MHz) of the second multiplication circuit 54 to 35 A first divider circuit 55 that divides and outputs a 27 MHz timing clock signal CL3, and a second divider circuit that divides the 27 MHz timing clock signal CL3 by 27 to output a 1 MHz sampling clock signal CL2. 56 and.

In this way, based on the color subcarrier of the input NTSC composite television signal, 14.
318 MHz sampling clock signal CL1 and 1
MHz sampling clock signal CL2 and 27 MH
The z timing clock signal CL3 can be generated respectively.

The timing clock generation unit 6 generates the read timing clocks CL4 and CL5 of the FIFO memories 2 and 4 and the frame synchronization data generation timing clock CL6 based on the timing clock signal CL3, and sends them at a predetermined timing. .

The frame synchronization data generator 7 has a frequency of 2
The synchronization data signal Df of the 10-bit parallel transmission frame is generated according to the timing clock CL6 of 7 MHz.

The frame synchronization data is data inserted to identify the beginning of a frame in which video and audio data signals are multiplexed, and is a data pattern that does not appear frequently in the data to be transmitted, such as 3FF (for 10-bit data). h), 000 (h), 000 (h), ...
Generate a data pattern like. In addition, in order to match the number of data, dummy data is added to a portion where the data is insufficient.

The multiplexing section (MPX) 8 is a 10-bit parallel video data signal Dv2 and audio data signal Da read from the video FIFO memory 2 and the audio FIFO memory 4 in accordance with the timing clocks CL4 and CL5.
2 and a 10-bit parallel frame-synchronization data signal Df output from the frame-synchronization data generation unit 6 according to the timing clock CL3, and output as time-division-multiplexed 10-bit parallel video / audio multiplexed data signal Do1. To do.

The multiplier 9 multiplies the timing clock CL6 having a frequency of 27 MHz by 10 to generate the timing clock CL7 having a frequency of 270 MHz.

The P / S converter 10 converts the 10-bit parallel video / audio multiplexed data signal Do1 into a 270 Mb / s video / audio multiplexed serial data signal Do2 according to the 270 MHz timing clock CL7.

The scramble section 11 scrambles the video / audio multiplexed serial data signal Do2 to prevent the same code from continuing in the serial data, and performs a 270 Mb / s video / audio multiplexed serial data signal Ds.
Output as.

The scramble process is performed by, for example, SMPTE.
-292M (Bit-Serial Digital I
interface for High-Difinit
Ion Television Systems) generator polynomial G (X): G (X) = (X ⁹ +
A known scramble circuit by X ⁴ +1) (X + 1) can be used.

Next, the multiplexing operation will be described.

First, the data amount of the video data signal Dv2, the audio data signal Da2, and the frame synchronization data signal Df in one frame period will be considered.

The video FIFO memory 2 receives the video data signal Dv1 at 14.318 MHz as shown in FIG.
The data is written according to the sampling clock signal CL1 of 1 and is read out as the video data signal Dv2 according to the timing clock signal CL4 of 27 MHz as shown in FIG. The vertical axis represents the address.

The voice FIFO memory 4 is shown in FIG.
As shown in (b), the audio data signal Da1 is set to 1 MHz.
The data is written in accordance with the sampling clock signal CL2 of, and is read out as the audio data signal Da2 in response to the timing clock signal CL5 of 27 MHz, as shown in FIG.

Here, since the data amount of the video data signal and the audio data signal written in one frame period is proportional to the sampling frequency, the data amount ratio is 14.318 MHz: 1 MHz ... (1) .

Further, since the data of one frame period written in the FIFO memory is read in response to the timing clock signal of 27 MHz, the time for reading the video data signal from the video FIFO memory 2 is 1 of the writing time.
4.318 MHz / 27 MHz = 35/66. Similarly, the time for reading the audio data signal from the audio FIFO memory 4 is 1 MHz / 27 MHz = 1 of the writing time.
/ 27.

Therefore, the ratio of the total readable data amount in one frame period to the data amount of the video data signal and the audio data signal is set to 27 MHz: 14.318 MHz: 1 MHz = 594: 315: 22 (2) By doing so, the video data signal and the audio data signal can be time-division multiplexed in one frame period.

These numerical values are the minimum values that can be represented by integer ratios. However, 14.318 MHz is exactly a circulating decimal number of 14.31818 ... MHz.

That is, as shown in FIG. 4, the data structure of one frame is such that the data amount 315 of the video data signal, the data amount 22 of the audio data signal, and the remaining data amount 257 become a frame synchronization pattern and dummy data. Map to.

The multiplexing unit (MPX) 8 is shown in FIG.
As shown in (d), the video data signal Dv2 and the audio data signal Da2, which are intermittently read from the video FIFO memories 2 and 4, are received, respectively, and the frame synchronization data signal Df is received during the output stop period of the FIFO memory. As shown in FIG. 3E, the time-division multiplexed 10-bit parallel video / audio multiplexed data signal Do1 is output.

In the above description of the audio A / D converter 3, the audio signal Sa is sampled by the sampling clock signal CL2 having a frequency of 1 MHz and converted into the 10-bit parallel audio data signal Da1.
For example, as shown in FIG.
It can be configured as kHz.

In FIG. 5, a frequency dividing circuit 31 for dividing the sampling clock signal CL2 having a frequency of 1 MHz by 2 to generate a sampling clock signal CL4 having a frequency of 500 kHz.
And an A / D conversion circuit 32 for sampling the input audio signal Sa with a sampling clock signal CL4 of 500 kHz and converting the audio signal Sa into a 20-bit parallel audio data signal Da, upper 10 bits and lower 1 of the audio data signal Da.
It has a selection circuit 33 which alternately selects 0 bit in accordance with the sampling clock signal CL4 of 500 kHz and outputs it as a 10-bit parallel audio data signal Da1.

Thus, the sampling frequency is set to 500
20-bit parallel audio data signal Da as kHz
Converted to a 20-bit parallel audio data signal D
The upper 10 bits and the lower 10 bits of a may be divided, and the upper bits and the lower bits may be alternately switched according to the sampling clock signal CL4 of 500 kHz to form the 10-bit parallel audio data signal Da1.

The sampling frequency is 500 kHz.
However, since it is sufficiently high with respect to the maximum frequency of the input audio signal Sa, the distortion is small in the digitization.

In this way, the video and audio multiplexed 27
On the side that receives the 0 Mb / s serial data signal Ds, the descramble circuit descrambles the received serial data signal Ds, and the S / P (serial /
After converting to a 10-bit parallel video / audio multiplexed data signal by a (parallel) conversion circuit, it is possible to perform frame synchronization and separate into a 10-bit parallel video data signal and audio data signal, and perform D / A conversion on each.

[0051]

As described above, according to the present invention, N
Since the TSC composite television signal and the composite audio signal can be multiplexed and output as a 270 Mb / s serial data signal, a signal distributor or transmission for the 270 Mb / s serial data signal defined in SMPTE-259M. It is possible to directly transmit the composite audio signal by using the device, and improve the equipment efficiency in the broadcasting station.

Further, by setting the data structure of one frame to the data amount 315 of the video data signal, the data amount 22 of the audio data signal, and the data amount 257 of the frame synchronization pattern and the dummy data, the periodicity in the data mapping is ensured. It is also possible to have a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a sampling clock generation unit 5 shown in FIG.

FIG. 3 is a diagram illustrating a multiplexing operation.

FIG. 4 is a diagram showing a data structure of multiplexed one frame.

5 is a block diagram showing another embodiment of the audio A / D conversion unit 3 shown in FIG.

FIG. 6 is a diagram showing an example of a composite audio signal.

[Explanation of symbols]

1 Video A / D converter 2 Video FIFO memory 3 Audio A / D converter 4 voice FIFO memory 5 Sampling clock generator 6 Timing clock generator 7 Frame synchronization data generator 8 Multiplexing part (MPX) 9 multiplier 10 P / S converter 11 Scrambler 51-color subcarrier extraction circuit 52 pulse generator 53, 54 multiplication circuit 55,56 frequency divider

Claims (6)

[Claims] 1. A video / audio multiplexer for multiplexing an NTSC composite television signal and a composite audio signal, wherein the NTSC composite television signal and the composite audio signal are each converted into a data signal of multiple bits in parallel. Video FIFO memory and audio FIFO
The ratio of the video data signal and the audio data signal is set to 315: 22 with the entire one frame period being 594 by writing the data into the O memory and reading the data with a timing shifted in a time shorter than the writing time. A video / audio multiplexing apparatus, wherein a frame synchronization pattern and dummy data are inserted into the frame to generate a time-division multiplexed multiple-bit parallel data signal. 2. A video / audio multiplexer for multiplexing an NTSC composite television signal and a composite audio signal, wherein the NTSC composite television signal is sampled at four times the color subcarrier frequency (14.318 MHz). It is converted into a video data signal, written in the video FIFO memory, read out by the first timing clock with a frequency of 27 MHz, and the composite audio signal with a frequency of 1 MH.
voice FI by sampling with z and converting to voice data signal
Write to the FO memory and read by the second timing clock of frequency 27 MHz, and further frequency 27 MHz
Frame synchronization data signal according to the timing clock of the video FIFO memory and the audio FI.
A video / audio system comprising means for time-division multiplexing so that the amount of data output from the FO memory and the ratio of the amount of data of the frame synchronization data signal are 315: 22: 257 in one frame period. Multiplexer. 3. A video / audio multiplexer that multiplexes an NTSC composite television signal and a composite audio signal to output as a 270 Mb / s serial data signal, wherein the NTSC composite television signal has a color subcarrier frequency of 4 A video A / D conversion unit for converting into a 10-bit parallel video data signal according to a double (14.318 MHz) sampling clock signal, and this video A / D conversion unit.
The output data signal of the D conversion unit is written and the frequency is 27M.
A video FIFO to be read in response to a first timing clock signal of Hz, and an audio A / D converter to convert the composite audio signal into a 10-bit parallel audio data signal in response to a sampling clock signal of frequency 1 MHz. An audio FIFO for writing the output data signal of the audio A / D converter and reading it with a second timing clock signal of frequency 27 MHz, a sampling clock generator for generating the sampling clock signal, and a frequency 27 MH.
a frame synchronization data generation unit that generates a 10-bit parallel frame synchronization data signal in response to a third timing clock signal of z, the first timing clock signal, the second timing clock signal, and the third timing. Timing clock generators for respectively generating clock signals, and 10 output from the video FIFO memory and the audio FIFO memory, respectively.
Multiplexing for receiving a bit-parallel video data signal and an audio data signal, and a frame synchronization data signal from the frame synchronization data generation unit, and outputting a 10-bit parallel video-audio multiplexed data signal in which each data signal is time-division multiplexed. Section and the third of the frequency 27 MHz
Timing clock signal is multiplied by 10 to 270MHz
A multiplication unit for generating the timing clock signal of
The 0-bit parallel video / audio multiplexed data signal is converted into the above 27
An audiovisual multiplexing apparatus, comprising: a P / S conversion unit that performs serial conversion according to a timing clock signal of 0 MHz. 4. The timing clock generation unit has a ratio of the data amounts of the video data signal, the audio data signal and the frame synchronization data signal input to the multiplexing unit to 1
4. The first timing clock, the second timing clock, and the third timing clock are generated so that they are time-division multiplexed at 315: 22: 257 in a frame period. The audiovisual multiplexing device described. 5. The sampling clock generation unit includes a color subcarrier extraction circuit that extracts a color subcarrier of the NTSC composite television signal, and a pulse generation circuit that generates a pulse synchronized with the extracted color subcarrier. The pulse is multiplied by 4 to obtain the 1
A first multiplication circuit which outputs a sampling clock signal of 4.318 MHz, and a second multiplication circuit which multiplies the sampling clock signal of 14.318 MHz by 66.
The output of the second multiplier circuit is divided by 35 to output a 27 MHz clock signal, and the 27 M
4. A video / audio multiplexer according to claim 3, further comprising a second frequency dividing circuit which divides the frequency of the Hz clock signal by 27 and outputs the sampling clock signal of 1 MHz. 6. The audio A / D conversion unit uses the frequency 1
Divide the sampling clock signal of MHz by 2 to 500
A frequency dividing circuit for generating a sampling clock signal of kHz, an A / D conversion circuit for converting the composite audio signal into a 20-bit parallel audio data signal according to the sampling clock signal of 500 kHz, and the 20-bit parallel audio. A selection circuit for alternately selecting the upper 10 bits and the lower 10 bits of the data signal in accordance with the sampling clock signal of 500 kHz and outputting the selected 10-bit parallel audio data signal. The video / audio multiplexer according to claim 3.