JP2003134416A - Display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image signal display unit which displays a two-screen display of a PC signal and a TV signal having different formats with small deterioration in picture quality. SOLUTION: The display unit is equipped with a clock generating means 8 which generates a clock RCLK of frequency synchronized with the PC signal, a clock generating means 6 which generates a clock SCLK of frequency synchronized with the TV signal, an AD converting means 1 which samples the TV signal with the clock SCLK, a picture detection processing means 9 which detects horizontal effective display periods and the numbers of effective display lines of the PC signal and TV signal, an arithmetic means 10 which computes the horizontal reduction rate α and vertical reduction rate β of the TV signal according to the detection result of the processing means 9, an image reducing means 2 which reduces the output signal of the AD converting means 1, and a DA converting means 3 which performs DA conversion of the output of the image reducing means 2 with the clock RCLK, and makes a display while inserting a sub-picture generated by reducing the TV signal at a fixed rate into part of a main picture of the PC signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual-screen display device for image signals and television signals, and more particularly to a display device for suitably displaying child screens of image signals of various formats in image signals of various formats. Regarding

[0002]

2. Description of the Related Art In a conventional two-screen display device, a main screen and a sub-screen are NTSC signals or high-definition TV signals,
The child screen is a video that is reduced in size according to the video format of the main screen and then combined with the main screen. As described above, only combinations of video signals of formats assumed in advance are targeted for input, and signals of various formats are not targeted.

On the other hand, the video signal of a computer has a different horizontal frequency, vertical frequency, number of display pixels, and number of display lines depending on the model, and it is necessary to display two screens in a conventional NTSC or high-definition two-screen display device. I can't. Therefore, the following two-screen display technology is used.

In FIG. 4, a PC signal (parent screen signal) which is a first video signal and a T signal which is a second video signal are displayed on the same screen.
The display device of the prior art which displays V signal (child screen signal) on two screens is shown. The conventional display device includes an AD converter 1, a sync separation circuit 5, a PLL circuit 6, and a line memory 102.
A DA converter 103, a sync separation circuit 7, a PLL circuit 108, a CPU 110, and a video composition circuit 4.

The AD converter 1 is means for converting an analog TV signal into a digital signal series.

The sync separation circuit 5 is a TV which is a child screen signal.
It is a means for separating the horizontal synchronizing signal from the signal.

The PLL circuit 6 is a circuit for generating a clock synchronized with the horizontal sync signal from the sync separation circuit 5.
This clock is used as a sampling clock for AD conversion in the AD converter 1 and as a writing clock to a line memory described later.

The line memory 102 is means for storing the digital signal series from the AD converter 1.

The sync separation circuit 7 is a PC which is a main screen signal.
It is a means for separating the horizontal synchronizing signal from the signal.

The PLL circuit 108 is a circuit for generating a clock synchronized with the horizontal sync signal from the sync separation circuit 7, and is constituted by a wide band PLL in order to deal with various sync signals and to deal with reduction and expansion which will be described later. There is.

The DA converter 103 is means for converting a digital signal sequence read from the line memory 102 into an analog signal using the clock from the PLL circuit 108.

The video synthesizing circuit 4 is means for synthesizing the child screen signal and the parent screen signal from the DA converter 103 into a two-screen display signal.

The CPU 110 is a means for controlling the PLL circuit 108 to vary the clock, and is composed of a microcomputer.

The relationship between the parent screen and the child screen will be described with reference to FIG. In FIG. 5, the effective display area of the parent screen is x _h ×
x _v, and the effective display area of the child screen is y _h × y _v .

The operation of the conventional two-screen display device will be described below with reference to FIGS. 4 and 5. In FIG. 4, the TV signal of the child screen signal is converted into a digital signal sequence in the AD converter 1 using the clock of the PLL circuit 6 synchronized with the horizontal synchronizing signal of the sync separation circuit 5, and written in the line memory 102. Get caught. The digital signal series of the TV signal is read from the line memory 102 in synchronization with the clock of the PLL circuit 108 synchronized with the horizontal synchronization signal of the synchronization separation circuit 7, and D
It is converted into an analog signal in the A converter 103, and is combined into a two-screen display signal in the video combining circuit 4. At this time,
The CPU 110 causes the TV signal read from the line memory 102 to have a desired reduction size (horizontal reduction rate y _h / x _h , vertical reduction rate y _v / x _v ) and a predetermined aspect ratio as shown in FIG. The clock of the PLL circuit 108 is controlled. Therefore, the clock of the PLL circuit 108 is
Horizontal frequency of PC signal, horizontal frequency of TV signal, PLL
Depending on the clock frequency of the circuit 6 and the horizontal reduction rate, it is necessary to raise the frequency of the read clock (shorten the time axis) or lower it (long the time axis).

In this way, a predetermined aspect ratio (for example, 4:
The TV signals of 3) are combined.

In the above-mentioned conventional technique, the PLL circuit 1 is used in order to synthesize a TV signal of a predetermined aspect (for example, 4: 3) with a desired reduced size on the PC signal of the main screen.
The 08 clock needs to have a higher frequency (shorter time axis) or lower (longer time axis) frequency of the read clock. For this reason, the PLL circuit 108 needs to be a wideband PLL with a wide variable range.
The converter 103 also needs to correspond to a wideband clock in accordance with the PLL circuit 108. However, the broadband PL
The L and wide band DA converters are expensive and cannot be inexpensively displayed in two screens.

[0018]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to eliminate the need for a wide band PLL or a wide band DA converter, and to arbitrarily display two screens of video signals of various formats including PC signals. An object of the present invention is to provide a display device that can be displayed at a ratio of 1 and can be inexpensively configured.

[0019]

In order to solve the above-mentioned problems, the present invention provides a part of the first image signal, which is the main screen, with the second image signal at a constant rate y / x (x, y). Is a positive integer) and is inserted and displayed as a child screen in a display device, and a predetermined frequency rcl synchronized with the first image signal is displayed.
first clock generating means for generating a clock RCLK of k [Hz], second clock generating means for generating a clock SCLK of a predetermined frequency sclk [Hz] synchronized with the second image signal, AD conversion means for sampling with the clock SCLK generated by the second clock generation means, at least the horizontal effective display period MDh [s] and the effective display line number MDv [Line] of the first image signal are detected,
And the horizontal effective display period SDh of the second image signal
[s], video detection means for detecting the number of effective display lines SDv [Line], and calculation means for calculating the horizontal reduction rate α and the vertical reduction rate β of the second image signal based on the detection result of the video detection means. And the horizontal reduction rate α calculated by the calculation means
And an image reduction means for reducing the output signal of the AD conversion means at a vertical reduction rate β, and a clock RCLK generated by the first clock generation means for outputting the output of the image enlargement means by DA.
DA conversion means for converting, the first image signal and the D
A configuration is provided that includes a video synthesizing unit that synthesizes the output of the A converting unit.

With the above structure, the display device of the present invention detects the respective video formats of the first image signal and the second image signal by the image detecting means, and the image compressing means detects the second image format. Since the image signal is reduced at a predetermined rate with respect to the first image signal and is inserted and displayed as a sub-screen, the image format of the input signal can be changed without changing the first clock according to the reduction rate as in the conventional case. Regardless, the display image can be displayed such that the child screen with respect to the parent screen has a predetermined size, and thus it is possible to provide an inexpensive image signal display device.

According to the present invention, in the display device, the calculating means calculates a horizontal reduction rate α represented by the following equation (Equation 1) and a vertical reduction rate β represented by the equation (Equation 2).

[0022]

[Equation 3]

In order to solve the above-mentioned problems, the present invention provides a second image signal at a constant rate y / x (x, y is a positive integer) in a part of the first image signal which is the main screen. In a display device which is reduced and inserted and displayed as a child screen, first clock generating means for generating a clock RCLK having a predetermined frequency rclk [Hz] synchronized with the first image signal, and the second image. Second clock generating means for generating a clock SCLK having a predetermined frequency sclk [Hz] synchronized with the signal;
Clock SCL generated by the second clock generating means
AD conversion means for sampling at K, at least the horizontal effective display period MDh [s] of the first image signal, the number MDv [Line] of effective display lines, and the horizontal effective display of the second image signal. Video detection means for detecting the period SDh [s] and the number of effective display lines SDv [Line], and horizontal reduction rate α and vertical reduction rate β and vertical expansion of the second image signal based on the detection result of the video detection means. Calculation means for calculating the rate γ; image reduction means for reducing the output signal of the AD conversion means by the horizontal reduction rate α and the vertical reduction rate β calculated by the calculation means; and vertical enlargement calculated by the calculation means. Rate γ
An image enlarging means for enlarging the output signal of the image reducing means, a DA converting means for DA converting the output of the image enlarging means with the clock generated by the first clock generating means, and the first image signal. A video synthesizing means for synthesizing the outputs of the DA converting means is provided.

With the above-mentioned structure, the display device of the present invention detects the respective video formats of the first image signal and the second image signal by the image detecting means, and uses the image compressing means and the image enlarging means. , The second image signal is reduced with respect to the first image signal at a predetermined rate and is inserted and displayed as a child screen. Therefore, the first clock is input without changing according to the reduction rate as in the related art. Regardless of the video format of the signal, the display video can be displayed such that the child screen with respect to the parent screen has a predetermined size, and an inexpensive image signal display device can be provided.

According to the present invention, in the above display device, the calculating means includes a horizontal reduction rate α represented by the following equation (Equation 1), a vertical reduction rate β represented by the equation (Equation 2 '), and (Equation 3). The vertical magnification rate γ represented by the formula is calculated.

[0026]

[Equation 4]

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The configuration of the display device according to the first embodiment of the present invention will be described with reference to the block diagram of FIG. Here, consider a case where the child screen is displayed at y _i / x _i (x _i > y _i ) times the effective display area of the parent screen.
Here, x _i is the horizontal (or vertical) size of the main screen effective display area, and y _i is the horizontal (or vertical) size of the small screen effective display area.

Referring to FIG. 1, a display device according to a first embodiment of the present invention includes an AD converter 1, a horizontal / vertical reduction circuit 2, a DA converter 3, an image synthesizing circuit 4, and a sync separation circuit. 5, a PLL circuit 6, a sync separation circuit 7, and a PLL
The circuit 8, the video detection processing circuit 9, the CPU 10, the video processing circuit 11, the scan converter 12, and the display unit 1.
3 and 3. In FIG. 1, parts common to FIG. 4 are given the same reference numerals.

Next, the operation of the display device of the present invention will be described. The sub-screen input video signal of the TV signal, which is the second video signal, is sampled by the AD converter 1 into a digital signal series V1 and input to the horizontal / vertical reduction circuit 2. Also,
The sub-screen input video signal is input to the sync separation circuit 5 and the horizontal sync signal SH is separated from the video signal and input to the PLL circuit 6. The PLL circuit 6 generates a reference clock SCLK having a predetermined frequency sclk [Hz] that is synchronized with the horizontal synchronization signal SH according to the type of the input sub-screen video signal. The reference clock SCLK is input to the AD converter 1 as a sampling clock for AD conversion. Further, the sub-screen input video signal is also input to the video detection processing circuit 9.

The horizontal / vertical reduction circuit 2 receives the control signal C2 for specifying the reduction ratio output from the CPU 10 and performs a reduction process on the digital signal series V1 at the reduction ratio designated by the CPU 10 to reduce the display screen size. The digital signal series V2 is generated. This specific operation will be described below.

Referring to FIG. 2, the horizontal / vertical reduction circuit 2 described above is used.
The configuration and operation of will be described. 2A shows the configuration of the horizontal / vertical reduction circuit 2, and FIG. 2B shows the operation outline thereof. In FIG. 2A, the horizontal / vertical reduction circuit 2 is configured to include a pre-filter 21 and an NM conversion unit 22. The pre-filter 21 is means for removing a predetermined high frequency component of the input digital signal sequence V1 in order to avoid the generation of aliasing distortion due to the compression process. As shown in FIG. 2B, the N-M converter 22 horizontally sets n sample points to m (n ≧ m) sample points in the horizontal direction with respect to the video signal of N pixels × L lines. An image reduced to Nm / n pixels x Lm '/ n' lines by performing compression by nm conversion signal processing for converting n'sample points into m '(n'≥m') sample points. It is a conversion means for generating a signal.

The parent screen input video signal, which is a PC signal, is input to the sync separation circuit 7, and the horizontal sync signal M is converted from the video signal.
H is separated and input to the PLL circuit 8. PLL circuit 8
Generates a clock RCLK having a predetermined frequency rclk [Hz] synchronized with the horizontal synchronization signal MH according to the system.
The DA converter 3 converts the digital signal series V2 into the analog signal series V3 with the clock RCLK synchronized with the parent screen input video signal.

The image detection processing circuit 9 detects the horizontal signal period MF of the parent screen input image signal of the PC signal which is the first image signal.
h [Hz], vertical signal period MFv [Hz], horizontal effective display period M
Dh [s] and the number of effective display lines MDv [Line] are detected, and the horizontal signal period SFh [Hz] and vertical signal period SFv of the child screen input video signal of the TV signal which is the second video signal are detected.
[Hz], horizontal effective display period SDh [s], and effective display line number SDv [Line] are also detected. The control signal C1 detected by the image detection processing circuit 9 is input to the CPU 10. CP
In U10, the reduction ratio of the small screen image input signal is calculated from the data detected by the image detection processing circuit 9 so that the small screen has a predetermined size. When the horizontal reduction ratio is α and the vertical reduction ratio is β, each reduction ratio is represented by the following equations (Equation 1) and (Equation 2).

[0034]

[Equation 5]

The result of the reduction ratio calculated by the CPU 10 is used as a control signal C2 for designating the reduction ratio, and the horizontal / vertical compression circuit 2
Entered in.

The video synthesizing circuit 4 synthesizes the parent screen input video signal and the analog signal series V3 of the DA converter 3 to obtain a synthetic video signal V4. The composite video signal V4 is subjected to signal processing such as sharpness improvement, noise removal and conversion into a three primary color signal series in the video processing circuit 11 to obtain a three primary color R, G, B signal series V5. The signal series V5 is the scan converter 1
In step 2, the signal format V6 is obtained by performing a process of converting the signal format into a signal format suitable for the display format of the display unit 13. Display unit 13
Realizes the function of displaying the signal sequence V6 and displaying the child screens of various formats, which are multiplied by y _i / x _i of the parent screen in the parent screen of various formats.

The second embodiment of the present invention will be described with reference to the block diagram of FIG.
The display device according to the embodiment will be described. The second embodiment is a case where an NTSC system (240 lines) screen is displayed in an area for 300 lines, for example, on a main screen with an extremely large number of lines (1024 lines) in the XGA system. The display device according to the first embodiment includes an AD converter 1, a horizontal / vertical reduction circuit 2, a vertical enlargement circuit 14, and
An A converter 3, an image synthesis circuit 4, a sync separation circuit 5,
A PLL circuit 6, a sync separation circuit 7, a PLL circuit 8,
Video detection processing circuit 9, CPU 15, video processing circuit 1
1, a scan converter 12, and a display unit 13. 3, the same parts as those in FIG. 1 are designated by the same reference numerals.

The vertical enlargement circuit 14 receives the control signal C3 for designating the enlargement ratio output from the CPU 15, and outputs the digital signal series SV2 from the horizontal / vertical reduction circuit 2 to the CPU.
The enlargement processing is performed at the enlargement ratio designated by 15, and a digital signal sequence V2 ′ with an enlarged display screen size is generated. The vertical expansion circuit 14 expands the image signal of the L line by mn conversion signal processing for converting n ′ sample points in the vertical direction into m ″ (n ′ ≦ m ″) sample points. , Lm ”/
An image signal enlarged to the n'line is generated. CPU15
Is the equation (1) and the equation (2) in the first embodiment.
Performs expression calculations. In the formula (2), MDv × y _v /
If x _v > SDv, the CPU 15 causes the vertical reduction ratio β = 1.
And Further, when the CPU 15 sets the vertical expansion rate to γ,
The following equation (3) is calculated.

[0039]

[Equation 6]

The horizontal reduction ratio α and the vertical reduction ratio β = 1 calculated by the CPU 15 are input to the horizontal / vertical compression circuit 2 as a control signal C2 designating the reduction ratio. Further, the vertical enlargement ratio γ represented by the equation (3) is a control signal C that specifies the enlargement ratio.
3 is input to the vertical expansion circuit 14. That is, when the y _v / x _v times the number of effective display lines of the parent screen input video signal is less than the number of effective display lines of the child screen input video signal, the child screen input video signal is vertically enlarged.

In the above description, the horizontal reduction rate and the vertical reduction rate are different, but the present invention is not limited to this, and it is clear that the same reduction rate may be used.

As is clear from the above description, according to the present invention, the reduction can be performed by the horizontal / vertical reduction circuit 2, so that the PLL circuit 8 has a plurality of frequency division ratios corresponding to various formats. It is possible to use a PLL that operates, and it is not necessary to use a wide-band PLL having a wide variable range as in the related art. Therefore, the DA converter 3 does not need to have a wide-band, and the cost can be reduced.

[0043]

As described above, according to the constitution of the present invention,
It is possible to provide a low-cost display device capable of displaying two screens of video signals of various formats at an arbitrary ratio.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display device according to a first embodiment of the present invention.

2A and 2B are a block diagram showing a configuration of a horizontal and vertical reduction circuit in the portable display device according to the first embodiment and an operation explanatory diagram for explaining the operation.

FIG. 3 is a block diagram showing a configuration of a display device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a conventional display device that displays a parent screen signal and a child screen signal on two screens.

FIG. 5 is a diagram illustrating a relationship between a parent screen and a child screen.

[Explanation of symbols]

1 AD converter 2 Horizontal / vertical reduction circuit 3 DA converter 4 Video synthesis circuit 5 Sync separation circuit 6 PLL circuit 7 Sync separation circuit 8 PLL circuit 9 Video detection processing circuit 10 CPU 11 Video processing circuit 12 scan converter 13 Display 14 Vertical expansion circuit 15 CPU 21 pre-filter 22 MN converter

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Haruki Takada             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony company Hitachi Eitech Tech F-term (reference) 5C025 AA30 BA02 BA27 BA28 CA02                       CA06 CA10 CA11                 5C082 AA02 BA12 BA34 BA35 BC03                       BC19 CA34 CA62 DA76 MM07

Claims (4)

[Claims] 1. A second image signal is reduced at a constant rate y / x (x, y is a positive integer) into a part of the first image signal which is a parent screen, and is inserted and displayed as a child screen. In the display device, the predetermined frequency rcl synchronized with the first image signal
first clock generating means for generating a clock of k [Hz], and a predetermined frequency scl synchronized with the second image signal
second clock generating means for generating a clock of k [Hz], AD converting means for sampling with the clock generated by the second clock generating means, and at least a horizontal effective display period MDh of the first image signal. [s], the number of effective display lines MDv [Line], and the horizontal effective display period SDh [s] of the second image signal, the number of effective display lines S
Video detecting means for detecting Dv [Line], computing means for computing the horizontal reduction rate α and vertical reduction rate β of the second image signal based on the detection result of the video detecting means, and the computing means Image reduction means for reducing the output signal of the AD conversion means by the horizontal reduction rate and the vertical reduction rate, and a DA conversion means for DA converting the output of the image reduction means with the clock generated by the first clock generation means. A display device, comprising: a video synthesizing unit for synthesizing the first image signal and the output of the DA converting unit. 2. The display according to claim 1, wherein the calculation means calculates a horizontal reduction ratio α and a vertical reduction ratio β represented by the following equations (Equation 1) and (Equation 2). apparatus. [Equation 1] 3. The second image signal is reduced by a constant ratio y / x (x, y is a positive integer) to a part of the first image signal which is the parent screen, and is inserted and displayed as a child screen. In the display device, the predetermined frequency rcl synchronized with the first image signal
first clock generating means for generating a clock of k [Hz], and a predetermined frequency scl synchronized with the second image signal
second clock generating means for generating a clock of k [Hz], AD converting means for sampling with the clock generated by the second clock generating means, and at least a horizontal effective display period MDh of the first image signal. [s], the number of effective display lines MDv [Line], and the horizontal effective display period SDh [s] of the second image signal, the number of effective display lines S
Image detecting means for detecting Dv [Line]; calculating means for calculating a horizontal reduction rate α, a vertical reduction rate β and a vertical enlargement rate γ of the second image signal based on the detection result of the image detection means; An image reduction unit that reduces the output signal of the AD conversion unit by the horizontal reduction ratio and the vertical reduction ratio calculated by the calculation unit, and an output signal of the image reduction unit by the vertical expansion ratio calculated by the calculation unit. Image enlarging means, DA converting means for DA converting the output of the image enlarging means with the clock generated by the first clock generating means, and the first
2. An image signal display device, comprising: an image synthesizing means for synthesizing the image signal of 1. and the output of the DA converting means. 4. The calculation means is a horizontal reduction ratio α shown by the following formula (Formula 1), a vertical reduction ratio β shown by the formula (2 ′), and a vertical enlargement ratio shown by the formula (3). The display device according to claim 3, wherein γ is calculated. [Equation 2]