JP2003133951A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit suitable for cellular phones. SOLUTION: A CPU 6 sends a DATA signal and a CLK signal to a PLLIC 1 to set desired frequencies for a programmable RF counter 2 or a programmable reference counter 9. Next, a STB signal having a predetermined pulse width which is determined by a predetermined value set in a counter 8, is sent from the CPU 6 to the PLLIC 1. At the leading edge of the STB signal, the reset of the counter 8 is cancelled, and the counter 8 starts counting REF signals. After counting the REF signals to the predetermined value, the counter 8 outputs a LE signal at the leading edge of the REF signal, and is reset at the trailing edge of the STB signal. Thus, a signal with a pulse width narrower than that of the STB signal is disregarded as a noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL) circuit.

[0002]

2. Description of the Related Art A PLL circuit detects a phase difference between an input signal and an output signal and controls a feedback loop from a voltage controlled oscillator (VCO) and a VCO output to accurately synchronize with an input signal and a reference frequency. It has a function to generate an output signal of the specified frequency, keeps the output oscillation frequency constant, and by incorporating a counter, it is possible to output a signal at a frequency that is an integral multiple of the input signal. Is widely used for frequency control of mobile phones and the like.

In recent years, small size, light weight, and large screens have always been required for mobile phones, and folding type mobile phones have become the mainstream as a mounting form satisfying these conditions. Due to the configuration of the mobile phone, the foldable type often has an electric circuit formed in each of the upper part and the lower part of the case. Generally, the upper part of the housing and the lower part of the housing are connected to each other at a hinge portion by a bendable flexible board. As mobile phones become smaller, lighter, and more sophisticated, the density of electrical wiring becomes higher, the impedance of each signal line becomes higher, and the frequency of the clock signal also becomes higher, making it impossible to lower the line impedance. . Moreover, since electric wiring is often exposed on the flexible board, even slight noise tends to be easily superimposed on the signal line. Nowadays, where such thinning and high functionality are required, miniaturization of substrate wiring and
Since the components and circuits are becoming smaller and more sophisticated, a more careful design is required in comparison with the conventional mobile phone, against external factors such as malfunction of the circuit due to static electricity.

In a PLL circuit, generally, setting of frequency data or the like to a counter or the like incorporated therein is
It is executed by the input signals DATA, CLK and STB.
The input signal DATA including the frequency data to be set is bit-serially read and buffered in the PLL circuit in synchronization with the input clock signal CLK, and then set to a predetermined counter in the PLL circuit by the input pulse signal STB. . Therefore, in order to correctly set the frequency data in the counter, the input signals DATA, CLK, S
It is necessary to prevent the TB from malfunctioning due to noise such as static electricity.

FIG. 3 shows a configuration example of a conventional PLL circuit.
In addition, the DATA signal, the CLK signal,
The data format of the STB signal on the time axis is shown in FIG. In the PLL circuit PLLIC1 shown in FIG.
The data of the DATA signal transmitted from U6 is input to the control latch 5 by using the CLK signal as a synchronization signal, and then the data corresponding to the data portion of the data format shown in FIG. Holds temporarily.

In the DATA signal, the data address corresponding to the address portion of the data format passes through the control latch 5 to specify the latch destination,
It is input to and held by the latch decoder 7.

The STB signal output from the CPU 6 after the DATA signal and the CLK signal have been output is input to the latch decoder 7 as a load enable (LE) signal to specify the data address held in the latch decoder 7. The gate of either the latch 3 or the latch 10 is opened in accordance with the above, and the data stored in the shift register 4 is sent to the programmable RF counter 2 or the programmable reference counter 9 via the latch 3 or the latch 10, and the frequency is A desired count value is set by the setting data.

Generally, a DATA signal having a different address is C
Programmable R by sending twice from PU6
F counter 2 and programmable reference counter 9
By setting the frequency setting data respectively, the PLL circuit configured by the PLLIC 1 can generate a signal of a desired frequency.

In FIG. 3, C for controlling the PLLIC1
Among the signal lines of the LK signal, DATA signal, and STB signal, the signal line in which the influence of noise is most prominent is the STB signal. This is because, as shown in FIG. 5, when unexpected noise is superimposed on the STB signal, the frequency setting data will be transferred to the PLLIC 1 even if the DATA signal for setting the desired frequency setting data is not sent from the CPU 6. This is because, because the CPU 6 recognizes that it is sent from the CPU 6, it malfunctions so as to set an invalid frequency according to the invalid contents of the shift register 4 and the latch decoder 7.

In such a case, the PLL circuit does not generate a desired frequency, which may cause a call disconnection during a call, for example. In the configuration example of FIG. 3, for the purpose of preventing such a malfunction, the RC filter 16 is inserted to remove the noise component and pass only the STB signal having a desired characteristic. The cutoff frequency of 16 was optimized.

The power-on reset circuit 15 has P
It is a circuit that automatically resets the value of the internal register of each circuit so that the register inside the PLLIC1 does not become unstable and malfunctions immediately after power is applied to the LLIC1.

[0012]

However, in this method, various noises are generated because the noise waveform superimposed on the signal line varies depending on the conditions of the voltage and capacitance for applying static electricity and the applied portion to the mobile phone. There is a problem in that the RC filter must be configured by selecting the cutoff frequency so that the desired STB signal can pass through while being removed at the same time. Further, it must be checked in advance where in the signal line the noise due to electrostatic application is superimposed. Since it is necessary to confirm and then construct the RC filter with an effective circuit layout, there are many circuit restrictions, and there is a problem that a large number of design steps are required to obtain an optimum solution.

An object of the present invention is to provide a PLL circuit having a circuit that ignores noise so that malfunction does not occur even if noise due to external factors, particularly static electricity, is superimposed on the signal line.

[0014]

To achieve the above object, the PLL circuit according to the present invention sets frequency setting data and frequency setting data by a data signal, a clock signal and a strobe pulse sent from a CPU. A PLL circuit for receiving an address, comprising a shift register circuit, a latch decoder circuit, and a counter circuit,
The shift register circuit receives and temporarily stores the frequency setting data transmitted in synchronization with the clock signal, and the latch decoder circuit sets the destination address to which the frequency setting data transmitted in synchronization with the clock signal should be set. When the counter circuit starts counting the reference frequency signal from the leading edge of the strobe pulse and is reset at the trailing edge of the strobe pulse, the counter circuit reaches a predetermined specified count value. Output the load enable signal, and using the load enable signal as a control signal, set the frequency setting data accumulated in the shift register circuit to a specified location in the PLL circuit specified by the destination address accumulated in the latch decoder circuit. To do.

A data signal sent from the CPU,
A PLL circuit that receives a frequency setting data and a destination address to which the frequency setting data should be set by a clock signal and a strobe pulse, and includes a shift register circuit, a latch decoder circuit, and a programmable counter circuit. The frequency setting data sent in synchronization with is received and temporarily stored,
The latch decoder circuit receives and temporarily stores the destination address to which the frequency setting data to be set, which is transmitted in synchronization with the clock signal, and the programmable counter circuit,
Starts counting the reference frequency signal from the leading edge of the strobe pulse, resets at the trailing edge of the strobe pulse, and outputs the load enable signal when the count value reaches the specified count value preset in the programmable counter circuit. Then, using the load enable signal as a control signal, the frequency setting data stored in the shift register circuit is designated by the destination address stored in the latch decoder circuit.
It is set in a designated place in the L circuit.

Further, the frequency setting data includes at least frequency data regarding a comparison frequency division number for the programmable RF counter and frequency data regarding a reference frequency division number for the programmable reference counter.

Further, the frequency setting data includes at least a specified count value of the strobe pulse width for the programmable counter circuit.

When the power is turned on, the specified count value of the strobe pulse width of the programmable counter circuit is automatically initialized to 1.

Corresponding to the setting of the specified count value of the strobe pulse width for the programmable counter circuit,
The pulse width of the strobe pulse sent from the CPU is automatically set to the specified count value times the reference frequency signal period.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a PLL circuit according to a first embodiment of the present invention, FIG. 4 is its timing chart, and FIG. 6 is a DATA signal, CLK.
The data format on the time axis regarding the signal and the STB signal is shown. As shown in FIG. 6, the DA sent by the CPU 6
The TA signal is composed of frequency setting data to be set in various counters in the PLL circuit and destination addresses of various counters to be set.

The PLLIC 1 of FIG. 1 is constructed by adding a counter 8 to the constituent circuit shown in FIG. Further, this eliminates the need for the RC filter used in the configuration of FIG. 3 for generating the STB signal input to the PLLIC 1. The counter 8 is provided between the STB signal input section of the PLLIC 1 and the latch decoder 7.

As shown in FIG. 4, the counter 8 has STB
When the signal is at the low level, it is in the reset state, and counting is started at the rising edge of the STB signal sent by the CPU 6. However, this relationship may be reversed. This makes S
The pulse width of the TB signal is counted by the REF signal which is the reference frequency signal from the oscillator OSC12, and when the preset desired pulse width (the time width corresponding to the count value 3 in the example of FIG. 4) is reached, the load is performed. The enable (LE) signal is output.

This LE signal is input to the latch decoder 7, the gate of either the latch 3 or the latch 10 is opened according to the designation of the destination address held in the latch decoder 7, and the frequency stored in the shift register 4 is opened. The setting data is sent to the programmable RF counter 2 or the programmable reference counter 9 via the latch 3 or the latch 10 to set desired frequency setting data.

Here, the reference frequency signal REF signal is the OSC.
It is a stabilized signal that has passed through a buffer circuit 11 that amplifies and shapes the output signal of 12. Further, as shown in FIG. 4, the STB signal sent by the CPU 6 has a pulse width equal to or larger than the cycle of the REF signal counted by the counter 8. Therefore, as shown in FIG. The narrow pulse of does not satisfy the desired count value based on the REF signal and is invalid as the LE signal and is removed.

(Description of Operation of First Embodiment) The operation of the PLL circuit according to the first embodiment of the present invention will be described below with reference to FIGS. 1, 4 and 7. In the explanation, the set value of the counter 8 is 3.

In FIG. 7, when the power is first turned on (step 100), the power-on reset circuit 15 is activated and each circuit and registers in the PLLIC 1 are reset (step 101). Next, the CPU 6 uses the DATA signal and the CLK signal for the programmable RF counter 2 as the desired comparison frequency divider frequency or for the programmable reference counter 9 as the desired reference frequency divider frequency. PL as frequency setting data
It is sent to LIC1 (step 102).

Subsequently, when an STB signal having a desired pulse width, that is, an STB signal having a pulse width exceeding the time obtained by multiplying the specified value of the counter 8 by the period of the REF signal is sent from the CPU 6 to the PLLIC 1, As shown in FIG. 4, the reset of the counter 8 is released at the same time when the STB signal rises, and the counter 8 starts counting the REF signal (step 103).

After the counter 8 counts the REF signal 3 times, the counter 8 is LE at the same time when the REF signal rises.
A signal is output (step 104), and the counter 8 is reset at the same time when the STB signal falls (step 1).
05). Step 10 for further data setting
Returning to 2, when the DATA signal is input and the STB signal is input, the same operation as described above is performed.

The operation of the PLL circuit after the setting is completed is the same as that of a general PLL circuit.
Although not described in detail, the comparison frequency divider frequency signal ROUT from the programmable RF counter 2 and the reference frequency divider frequency signal REFO from the programmable reference counter 9 are compared in a subsequent phase comparator (not shown). The detected phase difference signal is converted into a voltage by the charge pump circuit, and then the output frequency signal FIN is generated by the voltage controlled oscillator (VCO), and this FIN signal is fed back to the programmable RF counter 2 to set the comparison frequency divider. Loop control is performed by dividing by the frequency division number.

As described above, by generating the LE signal from the STB signal via the counter 8, when noise is superimposed on the STB line as shown in FIG. 5, the PLLIC 1 outputs invalid data as the LE signal. It will not be set, and even if noise is superimposed on the STB line as shown in FIG. 4, it will not be recognized as an LE signal. Although the case where the value of the count 8 is 3 has been described in this description, the count value may be any value.

(Second Embodiment) PLL according to the present invention
The configuration according to the second embodiment of the circuit is shown in FIG. In FIG. 2, a programmable counter 14 is arranged in place of the counter 8 in the first embodiment, and a latch 1 for latching data to the programmable counter 14 is provided.
The difference is that 3 is added. Like the programmable RF counter 2 and the programmable reference counter 9, the programmable counter 14 can arbitrarily set a counter value by frequency setting data by an instruction from the CPU 6.

The operation will be described with reference to the flowchart of FIG. The power of the PLLIC1 is turned on (step 2
00), the circuits and registers are reset by the power-on reset circuit 15 (step 201), and in this case, the counter value of the programmable counter 14 is further set to 1 (step 202). CPU
6 is an address for designating the programmable counter 14, and frequency setting data such that the count value becomes 3
The DATA signal and the CLK signal are used to send to the PLLIC 1 (step 203), and the pulse width of the STB signal from the CPU 6 is controlled to be equal to or more than the three-cycle width of the REF signal which is the reference frequency signal (step 204).

Next, after the desired frequency setting data of the programmable RF counter 2 or the programmable reference counter 9 is sent using the DATA signal and the CLK signal (step 205), it is the setting value of the programmable counter 14 set previously. ST with a pulse width exceeding the time obtained by multiplying 3 by the period of the REF signal
The B signal is sent from the CPU 6.

When the STB signal rises, the reset of the programmable counter 14 is released and the programmable counter 14 starts counting the REF signal (step 206). Programmable counter 14 is REF
After counting three signals, the programmable counter 14 outputs the LE signal at the same time when the REF signal rises (step 207), and the programmable counter 14 is reset at the same time when the STB signal falls (step 208). When the frequency setting data is further set, the process returns to step 205 and the operation is similarly continued. Other operations are the same as those in the first embodiment.

As described above, the pulse width of the STB signal can be variably set so that the programmable counter 14 can detect it as the LE signal according to the pulse width. For example, even if various noises having different pulse widths are superimposed, the PLLIC 1 can be ignored as noise. Therefore, the designer can set the optimum pulse width of the STB signal and the count value of the programmable counter 14 on the assumption of various noises, so that the number of designing steps can be reduced and the PLL which is easily resistant to noise can be provided without an additional circuit. A circuit can be provided.

In this description, the programmable counter 1
Although the value of 4 is set to 3, an appropriate value can be set according to the noise environment. As for the counting method of the counter, FIG. 4 shows the case of counting at the rising edge of the REF signal, but the counting method is not limited to this, and counting may be performed at the falling edge. The STB signal may be low active instead of high active. In addition, in the first embodiment, the counter 8 is set to PLLI.
It can also be provided outside C1.

As another embodiment, in addition to the PLLIC, the I signal using other DATA signal, CLK signal, and STB signal is used.
Also for C, the same effect can be obtained by adopting the method of the present invention.

[0039]

As described above, a circuit in which the pulse width of the strobe signal sent from the CPU is lengthened so that the noise superimposed on the strobe signal is ignored and the strobe signal can be detected by the PLL circuit as a load enable signal. With the provision of the above, the PLLIC has an effect that, when static electricity is applied, noise generated by the static electricity can be ignored, and thus malfunction of the PLL circuit can be prevented. In other words, it has the effect of preventing the disconnection of the call due to static electricity during the call of the mobile phone and during the data communication, which contributes to the improvement of the call quality.

Further, since it is not necessary to add an external circuit such as an RC filter for preventing noise as in the conventional case, the portable telephone can be made compact and lightweight.

Furthermore, when an RC filter is added, the desired STB signal is also rounded, and it is necessary to design in consideration of erroneous noise components due to electrostatic application. RC filter with effective circuit layout after confirming in advance that many verifications and experiments were required to determine the cutoff frequency that can remove noise and where in the signal line noise due to electrostatic charge is superimposed. Since it was necessary to configure the above, there was a circuit constraint and a large number of design man-hours were generated, but the circuit constraint was eliminated and layout design became easy and the design man-hour could be reduced.

When the noise is less than the desired pulse width, it is not detected as the load enable signal and can be ignored as the noise. Therefore, not only when static electricity is applied but also various unexpected electrical noises are generated in the strobe signal line. It is effective even when superimposed on.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a PLL circuit according to a first embodiment.

FIG. 2 is a configuration diagram of a PLL circuit according to a second embodiment.

FIG. 3 is a configuration diagram of a conventional PLL circuit.

FIG. 4 is a time chart of the PLL circuit according to the present invention.

FIG. 5 is a time chart of a conventional PLL circuit.

FIG. 6 is a data format of frequency setting data.

FIG. 7 is a processing flow according to the first embodiment.

FIG. 8 is a processing flow according to the second embodiment.

[Explanation of symbols]

1 PLLIC 2 Programmable RF counter 3 latch 4 shift register 5 control latch 6 CPU 7 Latch decoder 8 counter 9 Programmable reference counter 10 latch 11 Buffer circuit 12 Oscillator (OSC) 13 Latch 14 programmable counter 15 Power-on reset circuit 16 RC filter

Continued front page    F term (reference) 5J106 AA04 BB01 CC53 DD17 DD33                       DD34 DD38 DD39 DD42 GG09                       JJ05 KK27 PP03 QQ06 RR18                 5K047 AA13 AA15 GG02 MM27 MM33                       MM46 MM56

Claims (6)

[Claims] 1. A PLL circuit for receiving a frequency setting data and a destination address to which the frequency setting data is to be set by a data signal, a clock signal, and a strobe pulse sent from a CPU, comprising a shift register circuit and a latch decoder circuit. The shift register circuit receives the frequency setting data sent in synchronization with the clock signal and temporarily stores the frequency setting data, and the latch decoder circuit outputs the frequency setting data sent in synchronization with the clock signal. The counter circuit starts counting the reference frequency signal from the leading edge of the strobe pulse and is reset at the trailing edge of the strobe pulse, and the count value is set to the specified value. When the count value is reached,
Outputting a load enable signal, and using the load enable signal as a control signal, setting the frequency setting data accumulated in the shift register circuit to a designated place in the PLL circuit designated by the destination address accumulated in the latch decoder circuit. A PLL circuit characterized by: 2. A PLL circuit for receiving a frequency setting data and a destination address to which the frequency setting data is to be set by a data signal, a clock signal, and a strobe pulse sent from a CPU, comprising a shift register circuit and a latch decoder circuit. Equipped with a programmable counter circuit, the shift register circuit receives and temporarily stores the frequency setting data sent in synchronization with the clock signal, and the latch decoder circuit outputs the frequency setting data in synchronization with the clock signal. The programmable counter circuit starts counting the reference frequency signal from the leading edge of the strobe pulse, is reset at the trailing edge of the strobe pulse, and the count value is programmable counter. When the specified count value preset in the circuit is reached Outputting a load enable signal, and using the load enable signal as a control signal, setting the frequency setting data accumulated in the shift register circuit to a designated place in the PLL circuit designated by the destination address accumulated in the latch decoder circuit. A PLL circuit characterized by: 3. The frequency setting data includes at least frequency data regarding a comparison frequency division number for a programmable RF counter and frequency data regarding a reference frequency division number for a programmable reference counter. PLL circuit. 4. The PLL circuit according to claim 2, wherein the frequency setting data includes at least a specified count value of a strobe pulse width for a programmable counter circuit. 5. The PLL circuit according to claim 2, wherein the specified count value of the strobe pulse width of the programmable counter circuit is automatically initialized to 1 when the power is turned on. 6. The CP corresponding to the setting of the specified count value of the strobe pulse width for the programmable counter circuit.
3. The PLL circuit according to claim 2, wherein the pulse width of the strobe pulse sent from U is automatically set to be a specified count value times the reference frequency signal period.