CN100530969C - Phaselocked integrated circuit for supporting clock signal update during blind spot compensated time interval - Google Patents

Abstract

PLL integrated circuits include a charge pump having first and second input terminals that are configured to receive UP and DOWN control signals, respectively. A phase detector is also provided. The phase detector is configured to generate the UP and DOWN control signals at active levels during a dead zone compensation time interval using a control circuit that is responsive to at least one signal generated by said charge pump. The control circuit is further configured to support reference clock signal and/or feedback clock signal updates to the phase detector during the dead zone compensation time interval.

Description

Support the phase-locked loop intergrated circuit of clock signal update in the dead area compensation time interval

Technical field

The present invention relates to integrated circuit (IC) apparatus, more particularly, relate to the integrated circuit (IC) apparatus of when producing periodic signal, utilizing phase discriminator.

Background technology

Phase-locked loop (PLL) integrated circuit often is applied to be created in the high accuracy internal clock signal on the integrated circuit substrate.As shown in Figure 1, a kind of traditional PLL integrated circuit 10 can comprise: phase discriminator 12, charge pump (charge pump) 14, loop filter 16, voltage controlled oscillator (VCO) 18, clock decoder and buffer 20 and frequency divider 22.Phase discriminator 12 can be set in response to a reference clock signal (CKREF) and a feedback clock signal (CKVCO) and produce UP and DOWN control signal.Especially, phase discriminator 12 can be set at the phase place of comparison clock signal, and produces an effective UP signal or an effective DOWN signal during in reference clock signal CKREF when feedback clock signal CKVCO lag or lead.As can being understood by those skilled in the art, reference clock signal (CKREF) can be the buffering form of the external timing signal (not shown) that received by integrated circuit (IC) chip.Charge pump 14 can be effectively be converted to simulation output (POUT) with the UP of digital decoding and DOWN control signal, and this is output as source electric current that flows into loop filter 16 and the reverse current that flows out loop filter 16.Loop filter 16 is described to produce control voltage (Vcontrol), and this voltage is as the input to VCO 18.VCO 18 can produce a plurality of outputs, and these outputs are provided for clock decoder and buffer 20.An output of clock decoder and buffer 20 (is expressed as clock signal ) can be used as to the input of frequency divider 22, this frequency divider produces feedback clock signal CKVCO.One effective UP signal operation is to increase the value of Vcontrol, and this value is quickened VCO 18 and made feedback clock signal CKVCO catch up with reference clock signal CKREF.On the other hand, slow down VCO 18 and to eliminate the phase place of feedback clock signal CKVCO leading of an effective DOWN signal.These and other aspects of PLL 10 shown in Figure 1 are set forth in the textbook 9.5.2 of Jan M.Rabaey part fully, this title is Digital Intergrated Circuits:A Design Perspective, Prentice-Hall, ISBN0-13-178609-1, the 540-542 page or leaf.

Fig. 2 draws (pull-up) and drop-down (pull-down) two-part traditional charge pump 14 on showing and having.Last pull portion comprises a NMOS pull-down transistor N1 who connects with resistance R 1.PMOS transistor P1 and P2 provide the pull-up current mirror image.NMOS pull-down transistor N1 is in response to the UP control signal.When the UP control signal is effective logical one level, grid and the drain electrode of NMOS pull-down transistor N1 conducting and drop-down PMOS transistor P1.Feedback signal line NMOS_ON is also from high-low conversion.Cause the equal conducting of PMOS transistor P1 and P2 like this and source electric current (I is provided _SOURCE) to the lead-out terminal (POUT) of charge pump 14.The pull-down section branch comprises the PMOS that connects with resistance R 2 P3 that pulls up transistor.Nmos pass transistor N2 and N3 provide the pull-down current mirror image.The pull up transistor grid of P3 of PMOS is connected in the output of phase inverter I1, and this phase inverter receives the DOWN control signal.When the DOWN control signal is effective logical one level, PMOS pull up transistor the P3 conducting and on draw the drain and gate of nmos pass transistor N2.Feedback signal line PMOS_ON is a high level from low transition also.Cause nmos pass transistor N2 and N3 conducting like this and cancel reverse current (I from lead-out terminal POUT _Sink).When control signal UP and DOWN are effective logical one level, on draw with drop-down part simultaneously effectively.Draw on the charge pump with drop-down part and reach balance so that I _SourceEqual I _SinkAnd do not have net current to be provided to or cancel from lead-out terminal POUT.A kind of similar charge pump is at the U.S. patent No.6 of the Rhu of " digital pll device with wild phase bit error compensating circuit " (Digital Phase-Locked Loop ApparatusWith Enhanced Phase Error Compensating Circuit) by name, 430, shown in Fig. 4 of 244, its content is hereby expressly incorporated by reference.

Fig. 3 A illustrates a kind of traditional phase discriminator 12 that utilizes time-delay mechanism D1, so that the dead area compensation time interval to be provided, during this time every during UP and DOWN control signal all effectively interim.Keeping UP and DOWN control signal in interim overlapping time is the appearance that significant level has prevented the dead band, accurately aimed at so that the generation of any effective UP control signal will be cancelled by the generation of any effective DOWN control signal immediately when the phase place of reference clock signal CKREF and the phase place of feedback clock signal CKVCO, vice versa.As U.S. Patent No. 4322 at Prescar, 643 and the U.S. Patent No. 6 of Herrmann et al, 192,094, and the article that is entitled as " analysis and verification onside effcct of anti-backlash desay in phase-frequency detector " that X.Zhang did, microwave theory and technological associations (MTT-S) summary, described in the international microwave 8-13 in June of forum (2003) pp.17-20 of IEEE, also can call time-delay mechanism D1 " antibacklass (anti-backlash) " delay unit.Phase discriminator 12 is described to comprise a pair of D flip-flop (DFF1 and DFF2), a NAND gate DN1, a phase inverter 12 and a time-delay mechanism D1.D flip-flop and reference and feedback clock signal CKREF and CKVCO are synchronous.The rising edge of reference clock signal CKREF will make the real output Q1 of DEF1 be converted to high level, and the rising edge of feedback clock signal CKVCO will make the reality output of DFF2 be converted to high level.Work for fear of the dead band, when the rising edge of reference clock signal CKREF is recorded (by DFF1) the DOWN control signal is effective simultaneously, or when the rising edge of feedback clock signal CKVCO was recorded (by DFF2) simultaneously the UP control signal is effective, UP and DOWN control signal were effective.Be provided with UP and DOWN control signal will make NAND gate ND1 for the logical one level output from high-low conversion and the output that makes phase inverter 12 from low-Gao conversion.The conversion from low-Gao of the output of phase inverter 12 is delayed one of device D1 delay and equals T ₁Set time amount.In some cases, postpone T ₁It can be about 5 nanoseconds.The output of phase inverter I2 in response to effectively UP and DOWN control signal after low-Gao conversion sometime, will change from low-Gao at the reset signal RST of the output of deferred mount D1.When effective, reset signal RST works with reset flip-flop DFF1 and DFF2 (Q1=Q2=0).In case reset, UP and DOWN control signal will be transformed into inactive level, and the output POUT of the charge pump 14 of Fig. 2 will be in high impedance status.The operation of the phase discriminator 12 of Fig. 3 A is described in more detail now with reference to Fig. 3 B-3C.

In Fig. 3 B, first rising edge of reference clock signal CKREF makes to be changed from low-Gao in the UP control signal of the reality output (true output) of DFF1.Thereupon, first rising edge of feedback clock signal CKVCO makes and changes from low-Gao in the real DOWN control signal of exporting of DFF2.Effectively this initial overlapping of UP and DOWN control signal makes the input of deferred mount D1 be converted to high level.Then, equaling about T ₁If (perhaps ignore the delay relevant with I2 then equal T with described logic element ND1 ₁) time durations after, reset signal RST is from low-Gao conversion.This time durations T1 represents the duration in the dead area compensation time interval, and at this duration, control signal UP and DOWN remain on significant level, to prevent that the phase place of working as CKREF and CKVCO from critically being operated punctual dead band.In response to the transition from low-Gao of reset signal RST, real output Q1 and Q2 are by from high-low conversion, and the output of phase inverter I2 is from high-low conversion then.Equaling T ₁The time interval after, the output of phase inverter I2 from height-low transition be reflected in reset signal RST from height-low transition.Unfortunately, the overlapping about T of effective UP and DOWN control signal (promptly real output Q1 and Q2) ₁Duration make the phase discriminator 12 of Fig. 3 A miss the rising edge of input reference clock signal CKREF at interval in overlapping time.This edge that misses is highlighted in Fig. 3 B.As the skilled person will appreciate, the fault of the rising edge of this identification input reference clock signal CKREF can cause the minimizing of the locking time of gain inversion and phase discriminator 12.When the control signal of phase discriminator 12 output errors and when making phase difference between reference clock signal CKREF and the feedback clock signal CKVCO increase rather than reduce, gain inversion takes place.This reflects by can't remain valid the UP control signal during the time interval of extending between first and second rising edges of feedback clock signal CKVCO in Fig. 3 B.Therefore, when obtaining second rising edge of feedback clock signal CKVCO, the DOWN control signal becomes effectively (make thus gain inversion), simultaneously the UP control signal keep invalid (when it should be effective in response to the clock signal update that misses the time).

This gain inversion problem also may appear at dead area compensation outside the time interval.Especially, Fig. 3 C has illustrated in the interim when reset signal RST keeps low for high and real output Q1 and Q2, may how to have missed clock signal update.Therefore, shown in Fig. 3 C, has about 2T ₁The time interval of duration is illustrated in the interval of the interior impossible refresh clock signal of phase discriminator of Fig. 3 A.

Summary of the invention

Phase-locked loop (PLL) integrated circuit according to first embodiment of the invention comprises a phase discriminator, and it was configured to and produces overlapping UP and the DOWN control signal that is in significant level during the dead area compensation time interval.In order to prevent the appearance of gain inversion incident, a kind of reference clock signal of described phase discriminator and control circuit that feedback clock signal is upgraded supported during the dead area compensation time interval is provided, wherein said control circuit has at least one gate, be configured to the forward position that produces a reset signal, the beginning in the dead area compensation time interval is triggered in described forward position.Described PLL integrated circuit also comprises a charge pump, and described charge pump is configured to reception by UP and DOWN control signal that described phase discriminator produced.In certain embodiments, described control circuit comprises a transducer, and described transducer is arrived described charge pump by electrical couplings.This transducer is configured in response to the reception that is detected overlapping UP and DOWN control signal by described charge pump, produces dead band termination signal (END).In interchangeable embodiment, described transducer can also be configured in response to the generation in detected overlapping UP of the output of described phase discriminator and DOWN control signal, produces the dead band termination signal.

The PLL integrated circuit comprises according to another embodiment of the present invention: a charge pump, and it is in response to UP and DOWN control signal; And a phase discriminator, it was configured to and produces UP and the DOWN control signal that is in significant level during the dead area compensation time interval.Described phase discriminator comprises a control circuit, and described control circuit supports the reference clock signal of described phase discriminator and/or feedback clock signal to upgrade during the dead area compensation time interval.Described control circuit comprises a device, this device is in response to described reference clock signal and described feedback clock signal, be used to produce one and have the reset signal of forward position (leading edge), the beginning in the dead area compensation time interval is triggered in described forward position, and producing the version of the delay of reset signal with forward position, the termination in the dead area compensation time interval is triggered in described forward position.

A kind of PLL integrated circuit is provided according to another embodiment of the present invention, this PLL integrated circuit comprises a charge pump, have and be configured to first and second input terminals that receive UP and DOWN control signal respectively, and have and be configured to first and second control terminals that produce first and second feedback signals (for example NMOS_ON and PMOS_ON).These feedback signals indication when described UP and DOWN control signal is effective.One phase discriminator is provided.Described phase discriminator is configured to and utilizes a control circuit to produce UP and the DOWN control signal that is in significant level during the dead area compensation time interval, and described control signal is in response to first and second feedback signals by described charge pump produced.Described control circuit was configured to and supports the reference clock signal of described phase discriminator and/or the renewal of feedback clock signal during the dead area compensation time interval, wherein said control circuit has at least one gate, be configured to the forward position that produces a reset signal, the beginning in the dead area compensation time interval is triggered in described forward position.

Description of drawings

Fig. 1 is the block diagram of traditional phase-locked loop.

Fig. 2 is the electrical schematic diagram that can be used in the traditional charge pump in the phase-locked loop of Fig. 1.

Fig. 3 A is the electrical schematic diagram that can be used in the traditional phase discriminator in the phase-locked loop of Fig. 1.

Fig. 3 B is the sequential chart of explanation in the operation of the phase discriminator of first definition status figure below 3A.

Fig. 3 C is the sequential chart of explanation in the operation of the phase discriminator of second definition status figure below 3A.

Fig. 4 A is the electrical schematic diagram according to the phase discriminator of first embodiment of the invention.

Fig. 4 B is the operation of phase discriminator of key diagram 4A and the sequential chart of the reception of clock signal update during the dead area compensation time interval.

Fig. 5 is the electrical schematic diagram according to the phase discriminator of second embodiment of the invention.

Fig. 6 is the electrical schematic diagram according to the phase discriminator of third embodiment of the invention.

Embodiment

By describing the present invention in more detail hereinafter, the preferred embodiments of the present invention have wherein been provided by accompanying drawing.Yet the present invention can realize by multiple different embodiment, be not limited to embodiment discussed here; On the contrary, provide these embodiment so that the disclosure will be thorough and comprehensive, and will pass on scope of the present invention to those skilled in the art fully.Run through embodiment and use identical reference number to represent same element, and holding wire and on signal can be by identical character representation.Signal can be by synchronously and/or carry out small Boolean calculation (for example, counter-rotating), and do not consider unlike signal.The suffix B of signal name (or prefix sign "/") also can represent for example complementary data (complementary data) or information signal or effective low control signal.

With reference now to Fig. 4 A,, comprises the input stage of the reception in the forward position of discerning a pair of clock signal according to the phase discriminator 40 of first embodiment of the invention.These clock signals are illustrated as reference clock signal CKREF and feedback clock signal CKVCO.Also can provide other clock signal.This input stage is illustrated as and comprises first D flip-flop, is represented by DFF1 and DFF2.In response to reference clock signal CKREF from low-flash edge, the real output Q1 of the first trigger DFF1 is latched as height.In response to feedback clock signal CKVCO from low-flash edge, the real output Q2 of the second trigger DFF2 is latched as height.The real output Q1 and the Q2 of trigger are coupled to control circuit 42, and described control circuit 42 provides dead area compensation and eliminates the enhancing dead band operation of gain inversion behavior.One embodiment of this control circuit 42 will be described now.Phase inverter 13 produces a complementary signal (complementary signal) Q1B, and this complementary signal Q1B is provided as the input of NAND gate ND2 and NOR gate NR1.Phase inverter 14 produces a complementary signal Q2B, and this complementary signal Q2B is provided as the input of NAND gate ND3 and NOR gate NR1.When output Q1 and Q2 were set to high level in fact, " resetting " output RST of NOR gate NR1 was from low-Gao conversion, and work is so that automatically reset trigger DFF1 and DFF2.Therefore, when Q2 when high Q1 from the conversion of low-Gao or when Q1 when high Q2 this means that from almost the resetting at once that the conversion of low-Gao will cause trigger DFF1 and DFF2 the output of NOR gate NR1 produces the logical one pulse of lacking the duration relatively.In case reset, the first trigger DFF1 can discern any forward position subsequently of reference clock signal CKREF.Equally, in case reset, the second trigger DFF2 can discern any forward position subsequently of feedback clock signal CKVCO.This " immediately " reset feature (its sequential chart with reference to Fig. 4 B is described in more detail) makes control circuit 42 to support the reference clock signal CKREF of phase discriminator 40 and feedback clock signal CKVCO to upgrade in the dead area compensation time interval.By during the dead area compensation time interval, supporting clock signal update, can eliminate the gain inversion behavior of type as mentioned above about Fig. 3 A-3B.

Complementary signal Q1B is set to hang down and makes the output of NAND gate ND2 can convert height to and can produce effective UP control signal.Equally, complementary signal Q2B is set to hang down and makes the output of NAND gate ND3 can convert height to and produce effective DOWN control signal.Although be somebody's turn to do " immediately " reset feature, these control signals were remained valid during the dead area compensation time interval.Especially, the latch work by phase inverter 15 and 16 is provided afterwards, keeps the dead area compensation time interval so that be converted into height (then for low) at the condition reseting signal line RST in response to Q1=Q2=1.When reseting signal line RST from low-during the Gao transition, be pulled down to low (and remaining low) by nmos pass transistor N4 by the output node X of phase inverter 15 and 16 defined latchs.Therefore, although transition from low-Gao in response to reseting signal line RST, the real output Q1 and the Q2 of trigger are reset to the logical zero level, are in the overlapping UP of significant level and the control signal of DOWN but the forward position of reset pulse RST makes NAND gate ND2 and ND3 continue to produce.The transition from low-Gao of reseting signal line RST is delayed device D2 (delay=T ₂) postpone.Reset signal RST from low-Gao conversion then after high-low conversion, the output of deferred mount D2 produces logical one pulse (being shown a signal END) scheduled time.Effective duration of representing the dead area compensation time interval from the rising edge of reset signal RST to the duration in the time interval of the rising edge of END signal.When the END signal from low-Gao conversion, nmos pass transistor N5 connect and output node X from low-Gao conversion (XB is from high-low conversion), and the dead area compensation time interval be terminated.In case the dead area compensation time interval is terminated, control signal UP will reflect the value of the real output Q1 of first trigger, and control signal DOWN will reflect the value of the real output Q2 of second trigger.

The phase discriminator 40 of Fig. 4 A has begun then to provide resetting immediately of trigger DFF1 and DFF2 to eliminate the gain inversion incident by needing only the dead area compensation time interval.This sequential chart by Fig. 4 B further specifies, and Fig. 4 B shows signal: CKREF, CKVCO, Q1, Q2, RST, X, END, UP and DOWN.In Fig. 4 B, output signal X (coming the output node X of the latchs of phase inverter 15 among free Fig. 4 A and 16 definition) from high-low and identified the beginning and the termination in the dead area compensation time interval from the transition of low-Gao.During this time interval, any rising edge of reference clock signal CKREF (or feedback clock signal CKVCO) will this means that clock signal update will be received by phase discriminator 40 by the first trigger DFF1 (or second trigger DFF2) identification.As above described about Fig. 4 A, when satisfying following condition: Q1=Q2=1, reset pulse RST is triggered, and the END pulsion phase is delayed for reset pulse RST and equals T ₂Amount, i.e. effective duration in the dead area compensation time interval.In response to the rising edge of reset pulse RST, output node X is pulled down to low and keeps low up to producing the rising edge that respectively finishes pulse END.During the dead area compensation time interval (working as X=0), UP and DOWN control signal are all effective, and not influenced by the variation (being resetting of DFF1 and DFF2) of the value of Q1 and Q2.

Fig. 5 illustrates the phase discriminator 50 according to second embodiment of the invention.This phase discriminator 50 is similar with the phase discriminator of Fig. 4 A, yet, finish pulse END and be a more wide pulse that is produced by deferred mount D3.As directed, control circuit 52 comprises: phase inverter 17 and NAND gate ND4, their common actuating logic AND operations.Deferred mount D3, phase inverter 17 and NAND gate ND4 form transducer 54 jointly, in response to the appearance in detected overlapping UP of the output of phase discriminator 50 and DOWN control signal, produce the END pulse.Here, the signal of the termination in the dead area compensation time interval is specified in END pulse representative.Based on this structure of transducer 54, when satisfying following condition: UP=DOWN=1, the output of phase inverter 17 is from low-Gao conversion (and keeping high).The forward position of END pulse makes nmos pass transistor N5 connect and nodes X B is converted to low.The output of nodes X is also changed paramount, so that the level of holding wire Q1B and Q2B can be reflected (with anti-phase form) at the output UP and the DOWN of phase discriminator 50.In addition, the operation of phase discriminator 50 equals the operation by the phase discriminator 40 shown in Fig. 4 A-4B.In Fig. 6, has the control circuit 62 of needs deferred mount not according to the phase discriminator 60 of third embodiment of the invention.Replace, a transducer 64 is provided, to monitor the feedback signal (NMOS_ON and PMOS_ON) that is produced by charge pump 14 (for example referring to Fig. 2).This transducer 64 comprises: a phase inverter 18, a NAND gate ND4 and a phase inverter 17.When in response to effectively UP and DOWN control signal, feedback signal NMOS_ON is converted to low and feedback signal PMOS_ON is converted when paramount, and the END signal will be from low-Gao conversion, and the output node X of latch will be converted and keep high.Therefore, the termination in each dead area compensation time interval can be controlled by the built-in function in the charge pump 14.This built-in function provides one to postpone own quantity, and this delay own quantity supports the sufficiently long time interval to prevent the dead band operation.

In drawing and description, typical preferred embodiment of the present invention is disclosed, although used particular term, they only are used in general and descriptive meaning, rather than the purpose in order to limit, scope of the present invention is given by appended claims.

Claims (13)

1. phase-locked loop intergrated circuit comprises:

One phase discriminator, it is configured to utilize control circuit to produce overlapping UP and the DOWN control signal that is in significant level during the dead area compensation time interval, described control circuit supports the reference clock signal of described phase discriminator and/or feedback clock signal to upgrade during the dead area compensation time interval

Wherein said control circuit has at least one gate, is configured to the forward position that produces a reset signal, and the beginning in the dead area compensation time interval is triggered in described forward position.

2. phase-locked loop intergrated circuit as claimed in claim 1 also comprises:

One charge pump is configured to reception by UP and DOWN control signal that described phase discriminator produced.

3. phase-locked loop intergrated circuit as claimed in claim 2, wherein said control circuit comprises a transducer, it, and is configured so that receive overlapping UP and DOWN control signal and produce the dead band termination signal in response to detecting by described charge pump to described charge pump by electrical couplings.

4. phase-locked loop intergrated circuit as claimed in claim 1, wherein said control circuit comprises a transducer, it is configured so that detect the generation of overlapping UP and DOWN control signal in response to the output at described phase discriminator, and produces the dead band termination signal.

5. phase-locked loop intergrated circuit as claimed in claim 4, wherein said transducer comprises a delay element, it is configured to the termination signal forward position, dead band that separates with respect to the reset signal forward position of the beginning of representing the dead area compensation time interval.

6. phase-locked loop intergrated circuit comprises:

One charge pump has first and second input terminals, and they are configured to and receive UP and DOWN control signal respectively; And

One phase discriminator, it is configured to and utilizes a control circuit and produce UP and the DOWN control signal be in significant level during the dead area compensation time interval, described control circuit in response at least one by signal that described charge pump produced, and be configured to during the dead area compensation time interval reference clock signal and/or the feedback clock signal supported to described phase discriminator and upgrade

Wherein said control circuit has at least one gate, is configured to the forward position that produces a reset signal, and the beginning in the dead area compensation time interval is triggered in described forward position.

7. phase-locked loop intergrated circuit as claimed in claim 6, wherein said control circuit comprises a transducer, it is configured to reception by at least one signal that described charge pump produced.

8. phase-locked loop intergrated circuit as claimed in claim 7, wherein said control circuit comprises:

One latch cicuit is in response to described reset signal.

9. phase-locked loop intergrated circuit as claimed in claim 8, wherein said latch cicuit is coupled to the output of described transducer.

10. phase-locked loop intergrated circuit comprises:

One phase discriminator, it was configured to and produces UP and the DOWN control signal that is in significant level during the dead area compensation time interval, and further be configured to first clock signal and the second clock signal update of during the described dead area compensation time interval, supporting to described phase discriminator, described phase discriminator comprises:

First trigger with clock input, it is configured to and receives described first clock signal;

Second trigger with clock input, it is configured to and receives described second clock signal; And

One control circuit, its electrical couplings is to the output of described first trigger and described second trigger, described control circuit has at least one gate, is configured to begin to produce a forward position to the reset signal of described first and second triggers in the dead area compensation time interval.

11. phase-locked loop intergrated circuit as claimed in claim 10, wherein said control circuit comprises a latch cicuit, it is in response to described reset signal, described latch cicuit has an output, this output remains on first logic state during the described dead area compensation time interval, and remains on second logic state when dead area compensation not occurring.

12. phase-locked loop intergrated circuit as claimed in claim 11 also comprises a charge pump, in response to described UP and DOWN control signal; And wherein said control circuit comprises a transducer, its in response at least one by signal that described charge pump produced.

13. a phase-locked loop intergrated circuit comprises:

One charge pump, have first and second input terminals, they are configured to and receive UP and DOWN control signal respectively, and have first and second control terminals, they are configured to and produce first and second feedback signals respectively, and described first and second feedback signals indication when described UP and DOWN control signal is effective; And

One phase discriminator, it is configured to and utilizes control circuit, during the dead area compensation time interval, produce described UP and the DOWN control signal that is in significant level, described control circuit is in response to first and second feedback signals by described charge pump produced, and be configured to the reference clock signal of during the described dead area compensation time interval, supporting described phase discriminator and/or feedback clock signal is upgraded

Wherein said control circuit has at least one gate, is configured to the forward position that produces a reset signal, and the beginning in the dead area compensation time interval is triggered in described forward position.

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