JP2003133506A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the sameInfo
- Publication number
- JP2003133506A JP2003133506A JP2001328985A JP2001328985A JP2003133506A JP 2003133506 A JP2003133506 A JP 2003133506A JP 2001328985 A JP2001328985 A JP 2001328985A JP 2001328985 A JP2001328985 A JP 2001328985A JP 2003133506 A JP2003133506 A JP 2003133506A
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- JP
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- Prior art keywords
- lead
- semiconductor device
- semiconductor chip
- layer structure
- insulating substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に、ＢＧＡ（Ｂall ＧridＡrra
y）構造やＬＧＡ（Ｌand Ｇrid Ａrray）構造のパッケ
ージであるＱＦＮ（Ｑuad Ｆlat Ｎon-read Ｐackage）
型パッケージ、ＳＯＮ（Ｓmoll Ｏutlin Ｐackage）型
パッケージ等の半導体装置に適用して有効な技術に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a BGA (Ball Grid Arra).
y) structure and LGA (Land Grid Array) structure package QFN (Quad Flat Non-read Package)
The present invention relates to a technique effectively applied to a semiconductor device such as a die package and a SON (Small Outlin Package) type package.
【０００２】[0002]
【従来の技術】従来のＱＦＮ型パッケージやＳＯＮ型パ
ッケージ等を用いた半導体装置は、例えば、主面に回路
素子が形成された半導体チップがタブに搭載され、該半
導体チップの周辺にインナーリード（リード内部端子）
が前記半導体チップを囲むように配置され、前記半導体
チップ上の電極（パッド）と前記インナーリードとをボ
ンディング（金属ワイヤもしくは金属ボールで）により
電気的に接続し、少なくとも前記半導体チップ及び電気
接続部が樹脂で封止されたものである。このＱＦＮ型パ
ッケージやＳＯＮ型パッケージ等を用いた半導体装置
は、近年、小型化及び高機能化の要望が高まり、ＱＦＮ
型の高密度化が検討されている。2. Description of the Related Art In a conventional semiconductor device using a QFN type package, a SON type package, or the like, for example, a semiconductor chip having a circuit element formed on its main surface is mounted on a tab, and an inner lead ( Lead internal terminal)
Are arranged so as to surround the semiconductor chip, and electrically connect electrodes (pads) on the semiconductor chip and the inner leads by bonding (with metal wires or metal balls), and at least the semiconductor chip and the electrical connection portion. Is sealed with resin. In recent years, semiconductor devices using such QFN type packages and SON type packages have been increasingly demanded for miniaturization and higher functionality.
Higher mold density is being considered.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、ＱＦＮ
型等のリードフレームを用いた半導体装置では、小型化
及び高機能化のためにインナーリードの複数列のグリッ
ドアレイ化することが極めて困難であった。また、ピン
数を多くすると、パッケージが大型化してしまうという
問題があった。本発明の目的は、ＱＦＰ型、ＱＦＮ型等
のリードフレーム及び配線基板を用いた半導体装置にお
いて、半導体装置の小型化及び高機能化が可能な技術を
提供することにある。本発明の他の目的は、ＱＦＰ型、
ＱＦＮ型等のリードフレーム及び配線基板を用いた半導
体装置において、装置の多ピン化が可能な技術を提供す
ることにある。本発明の他の目的は、ＱＦＰ型、ＱＦＮ
型等のリードフレーム及び配線基板を用いた半導体装置
の製造方法において、製造効率の向上が可能な技術を提
供することにある。本発明の他の目的は、ＱＦＰ型、Ｑ
ＦＮ型等のリードフレーム及び配線基板を用いた半導体
装置の製造方法において、製造コストの低減が可能な技
術を提供することにある。本発明の前記ならびにその他
の目的と新規な特徴は、本明細書の記述及び添付図面に
よって明らかになるであろう。[Problems to be Solved by the Invention] However, QFN
In a semiconductor device using a lead frame such as a die, it has been extremely difficult to form a grid array of a plurality of rows of inner leads in order to reduce the size and increase the functionality. In addition, there is a problem that the package becomes large when the number of pins is increased. An object of the present invention is to provide a technique capable of downsizing and highly functionalizing a semiconductor device using a QFP type, QFN type lead frame and a wiring substrate. Another object of the present invention is the QFP type,
An object of the present invention is to provide a technique capable of increasing the number of pins in a semiconductor device using a QFN type lead frame and a wiring board. Another object of the present invention is QFP type, QFN.
It is an object of the present invention to provide a technique capable of improving manufacturing efficiency in a method of manufacturing a semiconductor device using a lead frame such as a mold and a wiring board. Another object of the present invention is QFP type, QFP
It is an object of the present invention to provide a technique capable of reducing the manufacturing cost in a method of manufacturing a semiconductor device using an FN type lead frame and a wiring substrate. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００４】[0004]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【０００５】第１の発明は、主面に回路素子が形成され
た半導体チップがタブに搭載され、該半導体チップの電
極（パッド）とリードとを電気的に接続し、少なくとも
前記半導体チップ及び電気接続部が樹脂で封止された半
導体装置であって、前記リードは、絶縁基板と、該絶縁
基板の表面と裏面にそれぞれに形成された第１の金属層
と、前記絶縁基板の表面と裏面に形成された第１の金属
層を前記絶縁基板を介在して導通させる第２の金属体と
からなる３層構造である。第２の発明は、前記第１の発
明の半導体装置において、前記３層構造のリードの第１
の金属層と第２の金属体はそれぞれ異なる材質からな
る。第３の発明は、前記第１又は２の発明の半導体装置
において、前記３層構造のリードは、１つのリードが複
数の端子に分離されている。第４の発明は、前記第３の
発明の半導体装置において、前記１つのリードを複数に
分離した端子（インナーリード）が、前記搭載された半
導体チップの近傍に延在されている。According to a first aspect of the present invention, a semiconductor chip having a circuit element formed on its main surface is mounted on a tab, and electrodes (pads) and leads of the semiconductor chip are electrically connected to each other. A semiconductor device having a connection portion sealed with a resin, wherein the lead includes an insulating substrate, a first metal layer formed on each of a front surface and a back surface of the insulating substrate, and a front surface and a back surface of the insulating substrate. Is a three-layer structure including a first metal layer formed on the first metal layer and a second metal body that conducts electricity through the insulating substrate. A second invention is the semiconductor device according to the first invention, wherein the first lead of the three-layer structure is provided.
The metal layer and the second metal body are made of different materials. A third invention is the semiconductor device according to the first or second invention, in which the lead of the three-layer structure has one lead separated into a plurality of terminals. A fourth aspect of the present invention is the semiconductor device of the third aspect, wherein a terminal (inner lead) obtained by separating the one lead into a plurality of pieces extends in the vicinity of the mounted semiconductor chip.
【０００６】第５の発明は、主面に回路素子が形成され
た半導体チップが配線基板に搭載され、該半導体チップ
の電極（パッド）と配線基板上の配線とを電気的に接続
し、少なくとも前記半導体チップ及び電気接続部が樹脂
で封止された半導体装置であって、前記配線基板は、絶
縁基板と、該絶縁基板の表面と裏面にそれぞれ形成され
た第１の金属層と、前記絶縁基板の表面と裏面の第１の
金属層を前記絶縁基板を介在して導通させる第２の金属
体とからなる３層構造である。第６の発明は、前記第５
の発明の半導体装置において、前記３層構造の配線基板
の第１の金属層と第２の金属体はそれぞれ異なる材質か
らなる。第７の発明は、前記第５又は６の発明の半導体
装置において、前記３層構造の配線基板は、１つの配線
が複数の端子に分離されている。第８の発明は、前記第
７の発明の半導体装置において、前記１つの配線を複数
に分離したインナーリード（内部端子）が、前記搭載さ
れた半導体チップの近傍に延在されている。According to a fifth aspect of the present invention, a semiconductor chip having circuit elements formed on its main surface is mounted on a wiring board, and electrodes (pads) of the semiconductor chip and wiring on the wiring board are electrically connected, and at least A semiconductor device in which the semiconductor chip and the electrical connection portion are sealed with a resin, wherein the wiring substrate includes an insulating substrate, first metal layers formed on a front surface and a back surface of the insulating substrate, and the insulating substrate. It is a three-layer structure including a second metal body that electrically connects the first metal layer on the front surface and the back surface of the substrate through the insulating substrate. A sixth invention is the fifth invention.
In the semiconductor device of the present invention, the first metal layer and the second metal body of the wiring board having the three-layer structure are made of different materials. A seventh invention is the semiconductor device according to the fifth or sixth invention, wherein in the wiring board having the three-layer structure, one wiring is separated into a plurality of terminals. An eighth invention is the semiconductor device of the seventh invention, wherein inner leads (internal terminals) obtained by separating the one wiring into a plurality of wires are extended in the vicinity of the mounted semiconductor chip.
【０００７】第９の発明は、絶縁基板の表面と裏面にそ
れぞれ形成された第１の金属層を前記絶縁基板を介在し
て導通させる第２の金属体とからなる３層構造のリード
フレーム基板を準備する工程と、前記３層構造のリード
フレーム基板（３層絶縁基板）の表面の第１の金属層か
らなるリードのインナーリード（内部端子）及びタブを
含むリードパターンを形成する工程と、前記３層構造の
リードフレーム基板の裏面の第１の金属層からなるアウ
ターリード（外部端子）のリードパターンをそれぞれ形
成する工程と、前記タブの上に半導体チップを搭載する
工程と、前記半導体チップの電極（パッド）と前記３層
構造のリードの第１の金属層からなるインナーリード
（内部端子）とをボンディングにより電気的に接続する
工程と、少なくとも前記半導体チップ及び前記電気接続
部が樹脂（パッケージ）で封止する工程とを有する半導
体装置の製造方法である。A ninth aspect of the present invention is a lead frame substrate having a three-layer structure comprising a first metal layer formed on each of a front surface and a back surface of an insulating substrate and a second metal body which conducts electricity through the insulating substrate. And a step of forming a lead pattern including inner tabs (internal terminals) of the leads made of the first metal layer on the surface of the lead frame substrate having the three-layer structure (three-layer insulating substrate) and tabs. Forming a lead pattern of outer leads (external terminals) made of a first metal layer on the back surface of the lead frame substrate having a three-layer structure; mounting a semiconductor chip on the tab; Electrically connecting the electrode (pad) and the inner lead (internal terminal) made of the first metal layer of the lead of the three-layer structure by bonding, Serial semiconductor chip and the electrical connection is a method of manufacturing a semiconductor device having a step of sealing with resin (package).
【０００８】第１０の発明は、絶縁基板の表面と裏面に
それぞれ形成された第１の金属層を前記絶縁基板を介在
して導通させる第２金属体とからなる３層構造の配線基
板を準備する工程と、前記３層構造の配線基板の表面の
第１の金属層からなるインナーリード（内部端子）を含
むリードパターンを形成する工程と、前記３層構造の配
線基板の裏面の第１の金属層からなるアウターリード
（外部端子）のリードパターンをそれぞれエッチングに
より形成する工程と、前記３層構造の配線基板の表面の
所定位置に半導体チップを搭載する工程と、前記半導体
チップの電極（パッド）と前記３層構造のリードの第１
の金属層からなるインナーリード（内部端子）とをボン
ディングにより電気的に接続する工程と、少なくとも前
記半導体チップ及び前記電気接続部が樹脂（パッケー
ジ）で封止する工程とを有する半導体装置の製造方法で
ある。A tenth aspect of the present invention provides a wiring board having a three-layer structure comprising a first metal layer formed on each of a front surface and a back surface of an insulating substrate and a second metal body which conducts electricity through the insulating substrate. And a step of forming a lead pattern including inner leads (internal terminals) made of a first metal layer on the front surface of the three-layer structure wiring board, and a first back surface of the three-layer structure wiring board. A step of forming a lead pattern of an outer lead (external terminal) made of a metal layer by etching, a step of mounting a semiconductor chip at a predetermined position on the surface of the wiring board having the three-layer structure, and an electrode (pad) of the semiconductor chip. ) And the first of the three-layered leads
A method of manufacturing a semiconductor device, which comprises a step of electrically connecting an inner lead (internal terminal) formed of the metal layer by bonding, and a step of sealing at least the semiconductor chip and the electrical connection portion with a resin (package). Is.
【０００９】前記本発明の手段によれば、（ａ）前記３
層構造のリードフレームもしくは配線基板により、１つ
のリードの端子を電気的に複数に分離することができ
る。According to the means of the present invention, (a) the above 3
The lead frame or the wiring board having a layered structure can electrically separate the terminals of one lead into a plurality of terminals.
【００１０】（ｂ）第１の金属層と第２の金属体とを異
なる材質、例えば、第１の金属層をＣｕ、第２の金属体
をＡｕ線とすることにより、第１の金属層をエッチング
する際に、第２の金属体までエッチングしてしまうこと
を防止できる。(B) The first metal layer and the second metal body are made of different materials, for example, the first metal layer is made of Cu and the second metal body is made of Au wire. It is possible to prevent the second metal body from being etched at the time of etching.
【００１１】（ｃ）前記３層構造のリードフレームを用
いてＱＦＮ型パッケージを作製することにより、ＱＦＮ
型半導体装置のリードのアウターリード（外部端子）を
グリッドアレイ構造とすることができる。また、リード
のエッチングされた部位では、樹脂が回り込むように構
成されており、リード抜けの防止もできる。(C) A QFN-type package is manufactured by using the lead frame having the three-layer structure,
The outer leads (external terminals) of the leads of the semiconductor device may have a grid array structure. Further, the resin is configured to wrap around at the etched portions of the leads, so that the leads can be prevented from coming off.
【００１２】（ｄ）前記分割された端子の表面側の第１
の金属層をそれぞれチップ搭載部位の近傍に延在するこ
とにより、ワイヤボンディング性を向上することができ
る。(D) The first on the surface side of the divided terminals
By extending each of the metal layers in the vicinity of the chip mounting portion, the wire bondability can be improved.
【００１３】（ｅ）前記配線基板の大きさ等をそのまま
で、第１の金属層の選択的なエッチングにより自由に異
なる配線パターンを形成することができるので、エッチ
ングの仕方で、一つの配線基板から複数種類の製品を作
製できる。(E) Since different wiring patterns can be freely formed by selectively etching the first metal layer while maintaining the size of the wiring board and the like, one wiring board can be formed by etching. Multiple types of products can be made from.
【００１４】（ｆ）前記３層構造の配線基板を選択的に
エッチングすることにより、リードパターンを形成する
ことができ、かつ、一括モールドでＢＧＡ型やＬＧＡ型
のパッケージを作製することにより、異なる大きさの製
品に対応が容易で、かつ効率良く作製することができ
る。(F) A lead pattern can be formed by selectively etching the wiring board having the three-layer structure, and it is different by producing a BGA type or LGA type package by collective molding. It is easy to handle large size products and can be manufactured efficiently.
【００１５】また、アウターリード（外部端子）以外の
部位は、エッチングされているため、ＢＧＡ型やＬＧＡ
型のパッケージのスタンドオフを確保することができ
る。さらに、配線基板と金型を共通化できるため、コス
ト低減にも寄与できる。Since parts other than the outer leads (external terminals) are etched, they are of BGA type or LGA type.
The standoff of the mold package can be secured. Further, since the wiring board and the mold can be shared, the cost can be reduced.
【００１６】（ｇ）配線基板の半導体チップ搭載部位に
第２の金属体を配設することにより、半導体装置の放熱
性を向上することができる。(G) By disposing the second metal body on the semiconductor chip mounting portion of the wiring board, the heat dissipation of the semiconductor device can be improved.
【００１７】前述のことから、ＢＧＡ型やＬＧＡ型のパ
ッケージの多ピン化、製造効率の向上、製造コストの低
減がはかれる。以下、本発明について、図面を参照して
実施の形態（実施例）とともに詳細に説明する。なお、
実施例を説明するための全図において、同一機能を有す
るものは同一符号を付け、その繰り返しの説明は省略す
る。From the above, it is possible to increase the number of pins of the BGA type or LGA type package, improve the manufacturing efficiency, and reduce the manufacturing cost. Hereinafter, the present invention will be described in detail with reference to the drawings together with an embodiment (example). In addition,
In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１８】[0018]
【発明の実施の形態】（実施例１）図１は、本発明の実
施例１のＱＦＮ型半導体装置の概略構成を示す図であ
り、（ａ）は封止樹脂の上半分部を除去した平面図であ
り、（ｂ）は（ａ）のＡ−Ａ’線で切った断面図であ
る。図２は、図１（ａ）の裏面の概略構成を示す平面図
である。図３は、本実施例１の３層構造のリードの概略
構成を示す斜視図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a diagram showing a schematic structure of a QFN type semiconductor device of Embodiment 1 of the present invention, in which (a) is an upper half portion of a sealing resin removed. It is a top view, (b) is sectional drawing cut | disconnected by the AA 'line of (a). FIG. 2 is a plan view showing a schematic configuration of the back surface of FIG. FIG. 3 is a perspective view showing a schematic configuration of a lead having a three-layer structure according to the first embodiment.
【００１９】本実施例１のＱＦＮ型半導体装置は、図１
乃至図３に示すように、主面に回路素子が形成された半
導体チップ１がタブ吊りリード２により支持されている
３層構造のタブ３に搭載され、前記半導体チップ１の電
極（パッド）１Ａと３層構造のリード４の第１の金属層
４Ｂからなるインナーリード（内部端子）４Ｂ１とをＡ
ｕ（金属）ワイヤ５で電気的に接続し、少なくとも前記
半導体チップ１及び前記電気接続部が樹脂（パッケー
ジ）６で封止された半導体装置である。The QFN type semiconductor device of the first embodiment is shown in FIG.
As shown in FIG. 3, a semiconductor chip 1 having a circuit element formed on its main surface is mounted on a tab 3 having a three-layer structure supported by tab suspension leads 2, and an electrode (pad) 1A of the semiconductor chip 1 is mounted. And an inner lead (internal terminal) 4B1 formed of the first metal layer 4B of the lead 4 having a three-layer structure.
The semiconductor device is electrically connected by a u (metal) wire 5, and at least the semiconductor chip 1 and the electrical connection portion are sealed with a resin (package) 6.
【００２０】前記本実施例１のＱＦＮ型半導体装置の裏
面は、図２に示すように、前記３層構造のリード４の第
１の金属層４Ｂからなるアウターリード（外部端子）４
Ｂ２のみが封止樹脂６から露出されている。このアウタ
ーリード（外部端子）４Ｂ２は、実装基板の配線端子も
しくは別の外部電子機器の端子と電気的に接続される。As shown in FIG. 2, the back surface of the QFN type semiconductor device of the first embodiment has an outer lead (external terminal) 4 formed of the first metal layer 4B of the lead 4 having the three-layer structure.
Only B2 is exposed from the sealing resin 6. The outer lead (external terminal) 4B2 is electrically connected to a wiring terminal of the mounting board or a terminal of another external electronic device.
【００２１】前記３層構造のリード４は、図３に示すよ
うに、絶縁基板（絶縁層）４Ａの表面と裏面にそれぞれ
形成された第１の金属層（Ｃｕ）からなるインナーリー
ド（内部端子）４Ｂ１とアウターリード（外部端子）４
Ｂ２とが形成されている。この絶縁基板４Ａの表面と裏
面に形成されたインナーリード（内部端子）４Ｂ１及び
アウターリード（外部端子）４Ｂ２を前記絶縁基板４Ａ
層を介在して導通させる第２の金属体４Ｃとからなる３
層構造である。各部の寸法は、例えば、リード４の幅約
０．３５ｍｍ、分割されたリード４の間隔約０．１５〜
０．２０ｍｍ、リード４のピッチ約０．５ｍｍ、絶縁基
板４Ａ及び第２の金属体（金属線）４Ｃの幅約３０μｍ
である。As shown in FIG. 3, the lead 4 having the three-layer structure is an inner lead (internal terminal) made of a first metal layer (Cu) formed on the front surface and the back surface of the insulating substrate (insulating layer) 4A, respectively. ) 4B1 and outer lead (external terminal) 4
B2 and are formed. Inner leads (internal terminals) 4B1 and outer leads (external terminals) 4B2 formed on the front and back surfaces of the insulating substrate 4A are connected to the insulating substrate 4A.
3 composed of a second metal body 4C which conducts through a layer 3
It is a layered structure. For example, the width of each lead 4 is about 0.35 mm, and the distance between the divided leads 4 is about 0.15 mm.
0.20 mm, pitch of leads 4 about 0.5 mm, width of insulating substrate 4A and second metal body (metal wire) 4C about 30 μm
Is.
【００２２】前記３層構造のリードの第１の金属層４Ｂ
と第２の金属体４Ｃはそれぞれ異なる材質からなる。例
えば、第１の金属層４ＢとしてＣｕを、第２の金属体と
してＡｕ線を用いる。また、第１の金属層４ＢとしてＮ
ｉ−Ｆｅ合金を、第２の金属体４ＣとしてＡｕ線を用い
てもよい。The first metal layer 4B of the lead having the three-layer structure
And the second metal body 4C are made of different materials. For example, Cu is used as the first metal layer 4B and Au wire is used as the second metal body. Further, as the first metal layer 4B, N
You may use an i-Fe alloy and Au wire as 2nd metal body 4C.
【００２３】図４は、前記ＱＦＮ型用の３層構造のリー
ドフレームの概略構成を示す図であり、（ａ）は平面
図、（ｂ）は（ａ）図のＡ−Ａ’で切った断面である。
図４に示すように、前記ＱＦＮ型用の３層構造のリード
フレーム１０は、複数個のＱＦＮ型用の３層構造のリー
ド４をアレイ状に配列している。図４において、８は送
り穴、１０はＣｕ又はＮｉ−Ｆｅ合金からなるリードフ
レームである。FIG. 4 is a diagram showing a schematic structure of a lead frame having a three-layer structure for the QFN type. (A) is a plan view and (b) is a sectional view taken along the line AA 'in FIG. It is a cross section.
As shown in FIG. 4, the lead frame 10 having a three-layer structure for the QFN type has a plurality of leads 4 having a three-layer structure for the QFN type arranged in an array. In FIG. 4, 8 is a feed hole, and 10 is a lead frame made of Cu or Ni—Fe alloy.
【００２４】前記３層構造のリードフレーム１０は、例
えば、異方性導電フィルムを金属板で挟み込みセット圧
着することにより作製する。また、多数の金属線を埋め
込んだ絶縁基板の両面に、前記と同様に金属板を接着す
ることにより、３層構造のリードフレームを作製する。
例えば、シリコーンゴムにＡｕ線を埋め込んだ異方性導
電シートを利用する。また、絶縁基板４Ａに複数のスル
ーホールを形成し、このスルーホールに導電材料を埋め
込んだ基板を作製する。この導電材料を埋め込んだ基板
の両面に、前記と同様に金属板を接着することにより、
３層構造のリードフレーム１０を作製する。The lead frame 10 having the three-layer structure is manufactured, for example, by sandwiching an anisotropic conductive film between metal plates and press-bonding the set. Further, a metal plate is adhered to both surfaces of the insulating substrate in which a large number of metal wires are embedded in the same manner as described above to manufacture a lead frame having a three-layer structure.
For example, an anisotropic conductive sheet in which Au wire is embedded in silicone rubber is used. Further, a plurality of through holes are formed in the insulating substrate 4A, and a conductive material is embedded in the through holes to produce a substrate. By adhering metal plates to both sides of the substrate in which this conductive material is embedded in the same manner as described above,
A lead frame 10 having a three-layer structure is produced.
【００２５】次に、前記本実施例１のＱＦＮ型半導体装
置の製造方法を図５を用いて説明する。図５は、本実施
例１のＱＦＮ型半導体装置の製造方法を説明するための
図であり、（ａ）は製造工程手順を示すフロー、（ｂ）
は各工程における断面である。Next, a method of manufacturing the QFN type semiconductor device of the first embodiment will be described with reference to FIG. FIG. 5 is a diagram for explaining the method of manufacturing the QFN type semiconductor device of the first embodiment, (a) is a flow showing a manufacturing process procedure, and (b) is a flow chart.
Is a cross section in each step.
【００２６】本実施例１のＱＦＮ型半導体装置の製造方
法は、図５に示すように、３層構造のリードフレーム１
０を準備し（Ｓ１０１）、３層構造のリードフレーム基
板１０Ａの上面の第１の金属層４Ｂからなるリード４の
インナーリード（内部端子）４Ｂ１及びタブ３を含むリ
ードパターンと、裏面の第１の金属層４Ｂからなるアウ
ターリード（外部端子）４Ｂ２を含むリードパターンを
それぞれエッチング等により形成する（Ｓ１０２）。As shown in FIG. 5, the method of manufacturing the QFN type semiconductor device according to the first embodiment includes a lead frame 1 having a three-layer structure.
0 (S101), the lead pattern including the inner leads (internal terminals) 4B1 and the tabs 3 of the leads 4 formed of the first metal layer 4B on the upper surface of the lead frame substrate 10A having the three-layer structure, and the first back surface. Lead patterns including outer leads (external terminals) 4B2 made of the metal layer 4B are formed by etching or the like (S102).
【００２７】次に、前記タブ３の上に半導体チップ１を
搭載し（Ｓ１０３）、前記半導体チップ１の電極１Ａと
３層構造のリード４の第１の金属層４Ｂからなるインナ
ーリード（内部端子）４Ｂ１とをＡｕワイヤ５でワイヤ
ボンディングして電気的に接続し（Ｓ１０４）、少なく
とも前記半導体チップ１及び前記電気接続部が封止樹脂
（パッケージ）６で封止する（Ｓ１０５）。最後に、ダ
イシング又はパンチ等による切断により前記パッケージ
ングされた完成半導体装置を個々に分離する（Ｓ１０
６）。Next, the semiconductor chip 1 is mounted on the tab 3 (S103), and an inner lead (internal terminal) composed of the electrode 1A of the semiconductor chip 1 and the first metal layer 4B of the lead 4 having a three-layer structure. ) 4B1 is electrically connected by wire bonding with the Au wire 5 (S104), and at least the semiconductor chip 1 and the electrical connection portion are sealed with the sealing resin (package) 6 (S105). Finally, the packaged completed semiconductor devices are individually separated by dicing or cutting with a punch or the like (S10).
6).
【００２８】前記３層構造のリードフレーム基板１０
を、図３に示すように、第１の金属層４Ｂを選択的にエ
ッチング、例えば、前記第１の金属層４Ｂがリード４の
中央で分離されるようにエッチングする。これによっ
て、３層構造のリードのエッチングにより分離された領
域に異なるインナーリード（内部端子）４Ｂ１が形成で
きる。これにより、グリッドアレイ構造のＱＦＮが実現
できる。また、タブ３が封止樹脂（パッケージ）６下に
露出されているので、放熱性を向上することができる。The lead frame substrate 10 having the three-layer structure.
As shown in FIG. 3, the first metal layer 4B is selectively etched, for example, so that the first metal layer 4B is separated at the center of the lead 4. As a result, different inner leads (internal terminals) 4B1 can be formed in the regions separated by the etching of the three-layer structure lead. As a result, a QFN having a grid array structure can be realized. Further, since the tab 3 is exposed under the sealing resin (package) 6, heat dissipation can be improved.
【００２９】（タブの変形例１）前記実施例１のタブ３
の変形例１は、図６（ａ）に示すように、前記タブ３の
実装面側の第１の金属層４Ｂをエッチングにより除去し
たものである。このようにすることにより、従来のハー
フエッチングと同様の効果が得られる。また、３層構造
のリード４の実装面側のエッチングされた部位へ封止樹
脂６が回り込むことにより、リード抜けを防止すること
ができる。(Modification 1 of Tab) Tab 3 of the first embodiment
6A, the first metal layer 4B on the mounting surface side of the tab 3 is removed by etching, as shown in FIG. By doing so, the same effect as the conventional half etching can be obtained. Moreover, the lead-out can be prevented by the sealing resin 6 wrapping around the etched portion of the mounting surface side of the lead 4 having the three-layer structure.
【００３０】（タブの変形例２）本実施例１のタブ３の
変形例２は、図６（ｂ）に示すように、前記実施例１の
タブ３の両面の第１の金属層４Ｂをエッチングにより除
去したものである。このようにすることにより、リード
４の実装面側のエッチングされた部位へ樹脂が回り込む
ことにより、リード抜けをさらに防止することができ、
かつ、パッケージの薄型化をはかることができる。Modified Example 2 of Tab In modified example 2 of the tab 3 of the first embodiment, as shown in FIG. 6B, the first metal layer 4B on both sides of the tab 3 of the first embodiment is provided. It was removed by etching. By doing so, it is possible to further prevent the lead from coming off by the resin flowing around to the etched portion on the mounting surface side of the lead 4.
In addition, the package can be made thinner.
【００３１】（タブの変形例３）本実施例１のタブ３の
変形例３は、図６（ｃ）に示すように、前記実施例１の
タブ３の半導体チップ側の第１の金属層４Ｂをエッチン
グにより除去したものである。このようにすることによ
り、パッケージの薄型化をはかり、かつ、タブ３の実装
面側の第１の金属層４Ｂが封止樹脂（パッケージ）６下
に露出されているので、放熱性を向上することができ
る。図７は前記変形例の裏面のアウターリード（外部端
子）とタブ３の形状を示す図であり、（ａ）はタブ３が
露出していないタイプであり、（ｂ）はタブ３が露出し
ているタイプである。(Third Modification of Tab) In a third modification of the tab 3 of the first embodiment, as shown in FIG. 6C, the first metal layer on the semiconductor chip side of the tab 3 of the first embodiment is used. 4B is removed by etching. By doing so, the package can be made thinner, and the first metal layer 4B on the mounting surface side of the tab 3 is exposed under the sealing resin (package) 6, so that heat dissipation is improved. be able to. 7A and 7B are views showing the outer leads (external terminals) on the back surface and the tabs 3 of the modified example. FIG. 7A is a type in which the tabs 3 are not exposed, and FIG. It is a type.
【００３２】（実施例２）図８は、本発明の実施例２の
ＱＦＮ型半導体装置の概略構成を示す図であり、（ａ）
は封止樹脂の上部を除去した平面図、（ｂ）は（ａ）図
のＢ−Ｂ’線で切った断面図である。(Embodiment 2) FIG. 8 is a diagram showing a schematic structure of a QFN type semiconductor device according to Embodiment 2 of the present invention.
Is a plan view in which the upper portion of the sealing resin is removed, and (b) is a cross-sectional view taken along the line BB ′ of FIG.
【００３３】図９は、本実施例２の３層構造のリードの
概略構成を示す斜視図であり、（ａ）はリード領域をエ
ッチングにより２つの領域に分割したもの、（ｂ）はリ
ード領域をエッチングにより３つの領域に分割したもの
である。（ｂ）図において、（ａ）’は縦方向に３つの
領域に分割したもの、（ｂ）’は横方向に３つの領域に
分割し、インナーリードのボンディング点が半導体チッ
プの周辺に配置するようにしたもの、（ｃ）’は
（ｂ）’の形状を変えたものである。9A and 9B are perspective views showing a schematic structure of a lead having a three-layer structure according to the second embodiment. FIG. 9A shows a lead region divided into two regions by etching, and FIG. 9B shows a lead region. Is divided into three regions by etching. In the figure (b), (a) 'is vertically divided into three regions, (b)' is horizontally divided into three regions, and the bonding points of the inner leads are arranged around the semiconductor chip. In this case, (c) 'is a modification of the shape of (b)'.
【００３４】本発明の実施例２のＱＦＮ型半導体装置
は、図８及び図９（ａ）に示すように、前記実施例１の
３層構造のリードフレーム基板１０の前記第１の金属層
４Ｂを選択的にエッチングして３層構造のリード４の領
域を２つに分離し、この分離された領域に異なるインナ
ーリード（内部端子）４Ｂ１を形成したものである。こ
のようにすることにより、３層構造のリード４のワイヤ
ボンディング領域であるインナーリード（内部端子）４
Ｂ１を半導体チップ１の周辺に配列し、裏面にアウター
リード（外部端子）４Ｂ２をグリッドアレイ構造に配列
することができる。これにより、ワイヤボンディングの
効率及び信頼性を向上することができる。As shown in FIGS. 8 and 9A, the QFN type semiconductor device according to the second embodiment of the present invention includes the first metal layer 4B of the lead frame substrate 10 having the three-layer structure of the first embodiment. Is selectively etched to separate the region of the lead 4 having a three-layer structure into two, and different inner leads (internal terminals) 4B1 are formed in the separated region. By doing so, the inner lead (internal terminal) 4 which is the wire bonding region of the lead 4 having the three-layer structure is formed.
B1 can be arranged around the semiconductor chip 1, and outer leads (external terminals) 4B2 can be arranged on the back surface in a grid array structure. Thereby, the efficiency and reliability of wire bonding can be improved.
【００３５】（インナーリードの変形例）前記本実施例
２のＱＦＮ型半導体装置は、図９（ｂ）に示すように、
前記実施例２の３層構造のリードフレーム基板１０の第
１の金属層４Ｂを選択的にエッチングして３層構造のリ
ード４を３領域に分離し、この分離された領域に異なる
インナーリード（内部端子）４Ｂ１を形成したものであ
る。特に、図９（ｂ）の（ｂ）’及び（ｃ）’に示すよ
うに、横方向に３つの領域に分割し、インナーリードの
ボンディング点が半導体チップの周辺に配置するように
する。このようにすることにより、３層構造のリード４
のワイヤボンディング領域であるインナーリード（内部
端子）４Ｂ１を半導体チップ１の周辺にグリッドアレイ
構造に配列することができる。これにより、ピン数を増
加することができる。この場合、実装面側のアウターリ
ード（外部端子）４Ｂ２は３列に配置される。(Modification of Inner Lead) As shown in FIG. 9B, the QFN type semiconductor device of the second embodiment has the following structure.
The first metal layer 4B of the lead frame substrate 10 having the three-layer structure of Example 2 is selectively etched to divide the lead 4 having the three-layer structure into three regions, and different inner leads ( The internal terminal) 4B1 is formed. In particular, as shown in (b) ′ and (c) ′ of FIG. 9B, it is divided into three regions in the lateral direction so that the bonding points of the inner leads are arranged around the semiconductor chip. By doing so, the lead 4 having a three-layer structure is formed.
The inner leads (internal terminals) 4B1 which are the wire bonding regions can be arranged around the semiconductor chip 1 in a grid array structure. Thereby, the number of pins can be increased. In this case, the outer leads (external terminals) 4B2 on the mounting surface side are arranged in three rows.
【００３６】本実施例１、２では、グリッドアレイ構造
にする場合について説明したが、千鳥配置構造としても
良い。千鳥配置によっては端子間のショート不良等の可
能性を低減することができる。In the first and second embodiments, the grid array structure is described, but the staggered structure may be used. Depending on the zigzag arrangement, it is possible to reduce the possibility of a short circuit between terminals or the like.
【００３７】（実施例３）図１０は、本発明の実施例３
のＱＦＮ型半導体装置の概略構成を示す図であり、
（ａ）は封止樹脂の上部を除去した平面図、（ｂ）は
（ａ）図のＣ−Ｃ’線で切った断面図である。図１１
は、本実施例３のＱＦＮ型半導体装置の３層構造のリー
ドフレームの概略構成を示す図であり、（ａ）はタブの
みを形成した平面図、（ｂ）は（ａ）にインナーリード
を形成した平面図である。本発明の実施例３のＱＦＮ型
半導体装置は、図１０に示すように、前記実施例１の構
成と基本的には同じであり、３層構造のリードパターン
のみが異なるものである。(Third Embodiment) FIG. 10 shows a third embodiment of the present invention.
2 is a diagram showing a schematic configuration of a QFN type semiconductor device of FIG.
(A) is a plan view in which an upper portion of the sealing resin is removed, and (b) is a cross-sectional view taken along the line CC ′ of FIG. Figure 11
9A and 9B are diagrams showing a schematic configuration of a lead frame having a three-layer structure of the QFN semiconductor device of the third embodiment, where FIG. 13A is a plan view in which only tabs are formed, and FIG. It is the top view formed. As shown in FIG. 10, the QFN type semiconductor device of the third embodiment of the present invention is basically the same as the structure of the first embodiment and is different only in the lead pattern of the three-layer structure.
【００３８】本実施例３の３層構造のリードフレーム
は、図１１に示すように、３層構造のリードフレーム基
板１０Ａから複数の３層構造のリードフレーム１０を一
括で形成する。すなわち、図１１（ａ）に示すように、
３層構造のリードフレーム基板１０Ａをエッチングによ
りリード４Ｂを一括で形成する。この場合、パターン金
型によるプレス加工でタブ３を形成してもよい。次に、
図１１（ｂ）に示すように、３層構造のリードフレーム
基板１０Ａの表面の第１の金属層４Ｂのリード領域を選
択的にエッチングして複数組のインナーリード（内部端
子）４Ｂ１を一括で形成する。その後、３層構造のリー
ドフレーム基板１０Ａの裏面の第１の金属層４Ｂのリー
ド領域を選択的にエッチングして複数組のアウターリー
ド（外部端子）４Ｂ１を一括で形成して、複数の３層構
造のリードフレーム１０を製作する。このようにするこ
とにより、１つのリードフレームでピン数の異なる製品
へのリードフレームの利用が可能となる。半導体装置の
製造効率を向上することができる。In the lead frame having a three-layer structure of the third embodiment, as shown in FIG. 11, a plurality of lead frames 10 having a three-layer structure are collectively formed from a lead frame substrate 10A having a three-layer structure. That is, as shown in FIG.
Leads 4B are collectively formed by etching the lead frame substrate 10A having a three-layer structure. In this case, the tab 3 may be formed by pressing with a pattern die. next,
As shown in FIG. 11B, the lead region of the first metal layer 4B on the surface of the lead frame substrate 10A having a three-layer structure is selectively etched to collectively form a plurality of sets of inner leads (internal terminals) 4B1. Form. After that, the lead region of the first metal layer 4B on the back surface of the lead frame substrate 10A having a three-layer structure is selectively etched to collectively form a plurality of sets of outer leads (external terminals) 4B1. The lead frame 10 having the structure is manufactured. By doing so, one lead frame can be used for products having different pin numbers. The manufacturing efficiency of the semiconductor device can be improved.
【００３９】（実施例４）図１２は、本発明の実施例４
のＱＦＮ型半導体装置の製造方法の各工程における断面
図である。図１３は３層構造のリードフレームの概略構
成を示す図であり、（ａ）は表面（上面）用のリードフ
レーム（Ｌ／Ｆ１）の平面構成図、（ｂ）は裏面（下
面）用のリードフレーム（Ｌ／Ｆ２）の構成平面図であ
る。図１３において、８はフレーム送り穴である。図１
３（ａ）のＤ−Ｄ’線で切った断面が図１２のリードフ
レーム（Ｌ／Ｆ１）１１Ａであり、図１３（ｂ）のＥ−
Ｅ’線で切った断面が図１２のリードフレーム（Ｌ／Ｆ
２）１１Ｂである。(Fourth Embodiment) FIG. 12 shows a fourth embodiment of the present invention.
FIG. 6 is a cross-sectional view in each step of the method for manufacturing the QFN semiconductor device in FIG. 13A and 13B are diagrams showing a schematic structure of a lead frame having a three-layer structure. FIG. 13A is a plan view of a lead frame (L / F1) for the front surface (upper surface), and FIG. 13B is a back surface (lower surface). It is a structure top view of a lead frame (L / F2). In FIG. 13, reference numeral 8 is a frame feed hole. Figure 1
The cross section taken along the line 3-3 of FIG. 3A is the lead frame (L / F1) 11A of FIG. 12, and the cross section E- of FIG.
The cross section taken along the line E'is the lead frame (L / F
2) 11B.
【００４０】本発明の実施例４のＱＦＮ型半導体装置の
製造方法を図１２を用いて説明する。まず最初に、例え
ば、図１３（ａ）に示すようなＣｕ又はＮｉ−Ｆｅ合金
からなる表面（上面）用のリードフレーム（Ｌ／Ｆ１）
１１Ａと、図１３（ｂ）に示すようなＣｕ又はＮｉ−Ｆ
ｅ合金からなる表面（上面）用のリードフレーム（Ｌ／
Ｆ１）１１Ｂとを用意する（Ｓ２０１）。次に、前記リ
ードフレーム（Ｌ／Ｆ１）１１Ａと１１Ｂ（Ｌ／Ｆ２）
のリード領域のそれぞれの間に、絶縁基板４Ａを選択的
に導通させる第２の金属体（Ａｕ線）４Ｃが埋め込まれ
た基板を挟み込み圧力接着して複数の３層構造のリード
フレームを一括で形成する（Ｓ２０２）。A method of manufacturing the QFN semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIG. First, for example, a lead frame (L / F1) for a surface (upper surface) made of Cu or a Ni—Fe alloy as shown in FIG.
11A and Cu or Ni-F as shown in FIG.
Lead frame (L / L) for surface (upper surface) made of e alloy
F1) 11B are prepared (S201). Next, the lead frames (L / F1) 11A and 11B (L / F2)
Between the respective lead regions, a substrate in which a second metal body (Au wire) 4C for selectively conducting the insulating substrate 4A is embedded is sandwiched and pressure-bonded to collectively form a plurality of lead frame layers having three layers. It is formed (S202).
【００４１】次に、リードフレーム（Ｌ／Ｆ１）１１Ａ
と１１Ｂ（Ｌ／Ｆ２）のそれぞれのリード領域を選択的
にエッチングして複数組のインナーリード（内部端子）
４Ｂ１を一括で形成する。その後、３層構造のリードフ
レーム基板１０Ａの裏面の第１の金属層４Ｂのリード領
域を選択的にエッチングして複数組のアウターリード
（外部端子）４Ｂ１を一括で形成して、複数の３層構造
のリードフレーム１０を製作する（Ｓ２０３）。Next, the lead frame (L / F1) 11A
And 11B (L / F2) lead regions are selectively etched to form a plurality of pairs of inner leads (internal terminals)
4B1 is collectively formed. After that, the lead region of the first metal layer 4B on the back surface of the lead frame substrate 10A having a three-layer structure is selectively etched to collectively form a plurality of sets of outer leads (external terminals) 4B1. The lead frame 10 having the structure is manufactured (S203).
【００４２】次に、前記タブ３の上に半導体チップ１を
搭載し（Ｓ２０４）、前記半導体チップ１の電極１Ａと
３層構造のリード４の第１の金属層４Ｂからなるインナ
ーリード（内部端子）４Ｂ１とをＡｕワイヤ５でワイヤ
ボンディングして電気的に接続し（Ｓ２０５）、少なく
とも前記半導体チップ１及び前記電気接続部が封止樹脂
（パッケージ）６で封止する（Ｓ２０６）。最後に、ダ
イシング又はパンチ等による切断により前記パッケージ
ングされた完成半導体装置を個々に分離する（Ｓ２０
７）。Next, the semiconductor chip 1 is mounted on the tab 3 (S204), and an inner lead (internal terminal) composed of the electrode 1A of the semiconductor chip 1 and the first metal layer 4B of the lead 4 having a three-layer structure is formed. 4B1 is wire-bonded with Au wire 5 for electrical connection (S205), and at least the semiconductor chip 1 and the electrical connection portion are sealed with a sealing resin (package) 6 (S206). Finally, the packaged completed semiconductor devices are individually separated by dicing or cutting with a punch or the like (S20).
7).
【００４３】前記リードフレーム（Ｌ／Ｆ１）１１Ａと
１１Ｂ（Ｌ／Ｆ２）のそれぞれパターンは、エッチング
により複数個を一括で形成する。また、このパターン形
成は、パターン金型によるプレス加工で形成してもよ
い。このようにすることにより、半導体装置の製造効率
を向上することができる。A plurality of lead frame (L / F1) 11A and 11B (L / F2) patterns are collectively formed by etching. Further, this pattern formation may be performed by pressing with a pattern die. By doing so, the manufacturing efficiency of the semiconductor device can be improved.
【００４４】（実施例５）図１４は、本発明の実施例５
のＱＦＮ型半導体装置の概略構成を示す図であり、
（ａ）は上部封止樹脂を除去した平面図、（ｂ）は
（ａ）図のＦ−Ｆ’線で切った断面図である。図１５は
本実施例５のＱＦＮ型半導体装置の製造方法の各工程に
おける断面図である。本実施例５のＱＦＮ型半導体装置
は、前記実施例１〜４のＱＦＮ型半導体装置において、
３層構造のリードフレーム基板１０Ａの代りに配線基板
１０Ｂを用いたものである。すなわち、図１４に示すよ
うに、タブ３を用いないで配線基板１０Ｂの上に直接半
導体チップ１を搭載したものである。(Fifth Embodiment) FIG. 14 shows a fifth embodiment of the present invention.
2 is a diagram showing a schematic configuration of a QFN type semiconductor device of FIG.
(A) is a plan view from which the upper sealing resin has been removed, and (b) is a cross-sectional view taken along the line FF ′ in (a). FIG. 15 is a cross-sectional view in each step of the method for manufacturing the QFN semiconductor device of the fifth embodiment. The QFN semiconductor device of the fifth embodiment is the same as the QFN semiconductor device of the first to fourth embodiments,
A wiring board 10B is used instead of the lead frame board 10A having a three-layer structure. That is, as shown in FIG. 14, the semiconductor chip 1 is directly mounted on the wiring board 10B without using the tab 3.
【００４５】本実施例５のＱＦＮ型半導体装置の製造方
法を図１５を用いて説明する。まず最初に、３層構造の
配線基板１０Ｂを準備し（Ｓ３０１）、３層構造のリー
ドフレーム基板１０Ｂの上面の第１の金属層４Ｂからな
るリード４のインナーリード（内部端子）４Ｂ１のリー
ドパターンと、裏面の第１の金属層４Ｂからなるアウタ
ーリード（外部端子）４Ｂ２のリードパターンをそれぞ
れエッチングにより形成する（Ｓ３０２）。A method of manufacturing the QFN type semiconductor device of the fifth embodiment will be described with reference to FIG. First, the wiring board 10B having a three-layer structure is prepared (S301), and the lead pattern of the inner lead (internal terminal) 4B1 of the lead 4 formed of the first metal layer 4B on the upper surface of the lead frame substrate 10B having a three-layer structure. Then, the lead patterns of the outer leads (external terminals) 4B2 made of the first metal layer 4B on the back surface are formed by etching (S302).
【００４６】次に、前記第２の金属線（Ａｕ）を埋め込
んだ絶縁基板４Ａの上に直接半導体チップ１を搭載し
（Ｓ３０３）、前記半導体チップ１の電極１Ａと３層構
造のリード４の第１の金属層（Ｃｕ又はＮｉ−Ｆｅ合
金）４Ｂからなるインナーリード（内部端子）４Ｂ１と
をＡｕワイヤ５でワイヤボンディングして電気的に接続
し（Ｓ３０４）、少なくとも前記半導体チップ１及び前
記電気接続部が封止樹脂（パッケージ）６で封止する。
本例の場合、一括モールド法と呼ばれる方法により、複
数の半導体チップ１を一体に封止する。（Ｓ３０５）。
最後に、回転カッタ９で封止樹脂６と絶縁基板４Ａとを
ダイシングして前記パッケージングされた完成半導体装
置２０を個々に分離する（Ｓ３０６）。Next, the semiconductor chip 1 is directly mounted on the insulating substrate 4A in which the second metal wire (Au) is embedded (S303), and the electrode 1A of the semiconductor chip 1 and the lead 4 of the three-layer structure are formed. An inner lead (internal terminal) 4B1 made of the first metal layer (Cu or Ni—Fe alloy) 4B is wire-bonded with an Au wire 5 to be electrically connected (S304), and at least the semiconductor chip 1 and the electricity The connecting portion is sealed with the sealing resin (package) 6.
In the case of this example, a plurality of semiconductor chips 1 are integrally sealed by a method called a collective molding method. (S305).
Finally, the rotary cutter 9 dices the sealing resin 6 and the insulating substrate 4A to separate the packaged completed semiconductor devices 20 (S306).
【００４７】前記本実施例５によれば、前記３層構造の
配線基板１０Ｂは、配線基板１０Ｂの大きさ等をそのま
まで、第１の金属層４Ｂの選択的なエッチングにより、
自由に異なるサイズあるいは異なるピン数の配線パター
ンに対応でき、エッチングの仕方で、一つの配線基板か
ら複数種類の製品に対応可能である。さらには一つの配
線基板で、サイズおよびピン数などの異なる形状の製品
を同時に作製することも可能となる。According to the fifth embodiment, the wiring board 10B having the three-layer structure is formed by selectively etching the first metal layer 4B while keeping the size and the like of the wiring board 10B.
It is possible to deal with wiring patterns of different sizes or different numbers of pins, and it is possible to deal with a plurality of types of products from one wiring board by etching. Further, it is possible to simultaneously manufacture products of different shapes such as size and number of pins with one wiring board.
【００４８】（実施例６）図１６は、本発明の実施例６
の通常の面付け（フラット）構造のＱＦＰ型半導体装置
に適用した場合を示す図であり、（ａ）は上部封止樹脂
を除去した平面図、（ｂ）は（ａ）図のＧ−Ｇ’線で切
った断面図である。本発明の実施例６の通常の面付け
（フラット）構造のＱＦＰ型半導体装置は、前記実施例
１の３層構造のリードフレーム１０を用いた変形例の構
造と基本的には同じであり、アウターリード４Ｂ２の形
状がＱＦＮ型でなく、通常の面付け（フラット）構造の
ＱＦＰ型になっている。(Sixth Embodiment) FIG. 16 shows a sixth embodiment of the present invention.
It is a figure which shows the case where it applies to the QFP type semiconductor device of the usual imposition (flat) structure, (a) is a top view which removed the upper sealing resin, (b) is GG of (a) figure. It is a sectional view taken along the line '. The normal imposition (flat) structure QFP type semiconductor device of the sixth embodiment of the present invention is basically the same as the structure of the modification using the lead frame 10 having the three-layer structure of the first embodiment, The shape of the outer lead 4B2 is not the QFN type but the QFP type having a normal imposition (flat) structure.
【００４９】以上、本発明を、前記実施例に基づき具体
的に説明したが、本発明は、前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲において種々変
更可能であることは勿論である。例えば、前述したＱＦ
Ｎに半田バンプを設けるように構成してもよい。Although the present invention has been specifically described based on the above embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course. For example, the above-mentioned QF
You may comprise so that a solder bump may be provided in N.
【００５０】[0050]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、以
下のとおりである。
（１）前記３層構造のリードフレームにより、リードを
電気的に分離することができる。
（２）第１の金属層と第２の金属体を異なる材質とした
ことにより、第１の金属層をエッチングする際に、第２
の金属体までエッチングしてしまうことを防止できる。
（３）前記３層構造のリードフレームを用いてＱＦＮの
外部端子をグリッドアレイ構造とすることができる。ま
たリードのエッチングされた部位では、樹脂が回り込む
ように構成されており、リード抜け防止もできる。
（４）分割された上側の第１の金属層（インナーリー
ド）をそれぞれ半導体チップ搭載部位の近傍まで延在さ
せたことにより、ボンディング性を向上することができ
る。
（５）前記配線基板の大きさ等をそのままで、第１の金
属層の選択的なエッチングにより自由に異なる配線パタ
ーンを形成できるので、エッチングの仕方で、一つの配
線基板から複数種類の製品を作製できる。
（６）３層構造の配線基板を選択的にエッチングするこ
とにより、パターン形成し、一括モールドでＢＧＡ型や
ＬＧＡ型のパッケージを作製することができる。これに
より、異なる大きさの製品に対応が容易で、かつ効率良
く作製することができる。また、外部端子以外の部位
は、エッチングされているため、ＢＧＡ型やＬＧＡ型の
パッケージのスタンドオフを確保することができる。さ
らに、配線基板と金型を共通化できるため、コスト低減
にも寄与できる。
（７）配線基板のチップ搭載部位に第２の金属体を配設
することにより、半導体装置の放熱性を向上することが
できる。
前述のことから、ＢＧＡ構造やＬＧＡ構造のＱＦＮ型パ
ッケージの多ピン化、製造効率の向上、製造コストの低
減がはかれる。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) The leads can be electrically separated by the lead frame having the three-layer structure. (2) When the first metal layer and the second metal body are made of different materials, the second metal body is not etched when the first metal layer is etched.
It is possible to prevent the metal body from being etched. (3) The external terminals of the QFN can have a grid array structure using the lead frame having the three-layer structure. Further, the resin is configured to wrap around at the etched portion of the lead, and the lead can be prevented from coming off. (4) Bondability can be improved by extending the divided upper first metal layers (inner leads) to the vicinity of the semiconductor chip mounting portion. (5) Since different wiring patterns can be freely formed by selectively etching the first metal layer while maintaining the size of the wiring board and the like, a plurality of types of products can be produced from one wiring board by etching. Can be made. (6) By selectively etching a wiring board having a three-layer structure, a pattern can be formed and a BGA type or LGA type package can be manufactured by collective molding. As a result, products of different sizes can be easily manufactured and can be efficiently manufactured. Further, since the parts other than the external terminals are etched, it is possible to secure the standoff of the BGA type or LGA type package. Further, since the wiring board and the mold can be shared, the cost can be reduced. (7) By disposing the second metal body on the chip mounting portion of the wiring board, the heat dissipation of the semiconductor device can be improved. From the above, it is possible to increase the number of pins in the QFN type package having the BGA structure or the LGA structure, improve the manufacturing efficiency, and reduce the manufacturing cost.
【図１】本発明の実施例１のＬＧＡ構造のＱＦＮ型半導
体装置の概略構成を示す図である。FIG. 1 is a diagram showing a schematic configuration of a QFN type semiconductor device having an LGA structure according to a first embodiment of the present invention.
【図２】図１（ａ）の裏面の概略構成を示す平面図であ
る。FIG. 2 is a plan view showing a schematic configuration of the back surface of FIG.
【図３】本実施例１の３層構造のリードの概略構成を示
す斜視図である。FIG. 3 is a perspective view showing a schematic configuration of a lead having a three-layer structure according to the first embodiment.
【図４】本実施例１のＱＦＮ型用の３層構造のリードフ
レームの概略構成を示す図である。FIG. 4 is a diagram showing a schematic configuration of a lead frame having a three-layer structure for the QFN type according to the first embodiment.
【図５】本実施例１のＱＦＮ型半導体装置の製造方法を
説明するための図である。FIG. 5 is a drawing for explaining the manufacturing method for the QFN semiconductor device of the first embodiment.
【図６】本実施例１のタブの変形例を示す図である。FIG. 6 is a diagram showing a modified example of the tab according to the first embodiment.
【図７】本実施例１のタブの変形例を示す図である。FIG. 7 is a diagram showing a modified example of the tab according to the first embodiment.
【図８】本発明の実施例２のＱＦＮ型半導体装置の概略
構成を示す図である。FIG. 8 is a diagram showing a schematic configuration of a QFN type semiconductor device according to a second embodiment of the invention.
【図９】本実施例２の３層構造のリードフレームの第１
の金属層４Ｂを選択的にエッチングして３層構造のリー
ドを複数領域に分離した概略構成を示す図である。FIG. 9 is a first lead frame having a three-layer structure according to the second embodiment.
FIG. 6 is a diagram showing a schematic configuration in which the metal layer 4B of 1) is selectively etched to divide the lead of a three-layer structure into a plurality of regions.
【図１０】本発明の実施例３のＱＦＮ型半導体装置の概
略構成を示す図である。FIG. 10 is a diagram showing a schematic configuration of a QFN type semiconductor device of Example 3 of the present invention.
【図１１】本実施例３のＱＦＮ型半導体装置の３層構造
のリードフレームの概略構成を示す図である。FIG. 11 is a diagram showing a schematic configuration of a lead frame having a three-layer structure of the QFN type semiconductor device of the third embodiment.
【図１２】本発明の実施例４のＱＦＮ型半導体装置の製
造方法の各工程における断面図である。FIG. 12 is a sectional view in each step of the method for manufacturing the QFN semiconductor device according to the fourth embodiment of the present invention.
【図１３】本実施例４の３層構造のリードフレームの概
略構成を示す図である。FIG. 13 is a diagram showing a schematic configuration of a lead frame having a three-layer structure according to a fourth embodiment.
【図１４】本発明の実施例５のＱＦＮ型半導体装置の概
略構成を示す図である。FIG. 14 is a diagram showing a schematic configuration of a QFN type semiconductor device of Example 5 of the invention.
【図１５】本実施例５のＱＦＮ型半導体装置の製造方法
の各工程における断面図である。FIG. 15 is a cross-sectional view in each step of the method for manufacturing the QFN semiconductor device of the fifth embodiment.
【図１６】本発明の実施例６の通常の面付け（フラッ
ト）構造のＱＦＰ型半導体装置の概略構成を示す図であ
る。FIG. 16 is a diagram showing a schematic configuration of a QFP type semiconductor device having a normal imposition (flat) structure according to a sixth embodiment of the present invention.
１…半導体チップ １Ａ…半導体チ
ップの電極
２…タブ吊りリード ３…タブ
４…３層構造のリード ４Ａ…絶縁基板
４Ｂ…第１の金属層 ４Ｂ１…３層構
造のリードの内部端子
４Ｂ２…３層構造のリードの外部端子 ５…ワイヤ
６…封止樹脂（パッケージ） ８…フレーム送
り穴
９…回転カッタ １０…３層構造
のリードフレーム
１０Ａ…３層構造のリードフレーム基板
１０Ｂ…３層構造の配線基板 １１Ａ…リード
フレーム（Ｌ／Ｆ１）
１１Ｂ…リードフレーム（Ｌ／Ｆ２） ２０…完成半導
体装置DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 1A ... Electrode of semiconductor chip 2 ... Tab suspension lead 3 ... Tab 4 ... Lead of 3 layer structure 4A ... Insulating substrate 4B ... 1st metal layer 4B1 ... Internal terminal 4B2 of 3 layer structure ... 3 layers External terminal of lead of structure 5 ... Wire 6 ... Sealing resin (package) 8 ... Frame feed hole 9 ... Rotating cutter 10 ... Lead frame 10A of three-layer structure ... Lead frame substrate 10B of three-layer structure ... Wiring of three-layer structure Substrate 11A ... Lead frame (L / F1) 11B ... Lead frame (L / F2) 20 ... Completed semiconductor device
───────────────────────────────────────────────────── フロントページの続き (72)発明者 渡辺 文友 秋田県南秋田郡天王町天王字長沼64 アキ タ電子株式会社内 Ｆターム(参考） 5F067 AA02 AB03 AB04 BE04 BE10 CB06 CB07 CC02 DE01 DF01 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Fumito Watanabe 64 Naganuma, Tenno character, Tenno-cho, Minami-Akita-gun, Akita Prefecture Ta Denshi Co., Ltd. F-term (reference) 5F067 AA02 AB03 AB04 BE04 BE10 CB06 CB07 CC02 DE01 DF01
Claims (10)
プがタブに搭載され、該半導体チップの電極とリードと
を電気的に接続し、少なくとも前記半導体チップ及び電
気接続部が樹脂で封止された半導体装置であって、前記
リードは、絶縁基板と、該絶縁基板の表面と裏面にそれ
ぞれに形成された第１の金属層と、前記絶縁基板の表面
と裏面に形成された第１の金属層を前記絶縁基板を介在
して導通させる第２の金属体とからなる３層構造である
ことを特徴とする半導体装置。1. A semiconductor chip having a circuit element formed on a main surface is mounted on a tab, and an electrode and a lead of the semiconductor chip are electrically connected to each other, and at least the semiconductor chip and the electrical connection portion are sealed with a resin. In the semiconductor device, the lead includes an insulating substrate, a first metal layer formed on a front surface and a back surface of the insulating substrate, and a first metal layer formed on a front surface and a back surface of the insulating substrate. A semiconductor device having a three-layer structure including a second metal body that conducts a metal layer through the insulating substrate.
第２の金属体はそれぞれ異なる材質からなることを特徴
とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the first metal layer and the second metal body of the lead having the three-layer structure are made of different materials.
が複数の端子に分離されていることを特徴とする請求項
１又は２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein in the lead having the three-layer structure, one lead is separated into a plurality of terminals.
が、前記搭載された半導体チップの近傍に延在されてい
ることを特徴とする請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein a terminal obtained by separating the one lead into a plurality of pieces extends in the vicinity of the mounted semiconductor chip.
プが配線基板に搭載され、該半導体チップの電極と配線
基板上の配線とを電気的に接続し、少なくとも前記半導
体チップ及び電気接続部が樹脂で封止された半導体装置
であって、前記配線基板は、絶縁基板と、該絶縁基板の
表面と裏面にそれぞれ形成された第１の金属層と、前記
絶縁基板の表面と裏面の第１の金属層を前記絶縁基板を
介在して導通させる第２の金属体とからなる３層構造で
あることを特徴とする半導体装置。5. A semiconductor chip having a circuit element formed on a main surface is mounted on a wiring board, and electrodes of the semiconductor chip and wirings on the wiring board are electrically connected to each other, and at least the semiconductor chip and the electrical connection portion are provided. Is a semiconductor device sealed with a resin, the wiring substrate includes an insulating substrate, a first metal layer formed on a front surface and a back surface of the insulating substrate, and a first metal layer on the front surface and a back surface of the insulating substrate. A semiconductor device having a three-layer structure including a first metal layer and a second metal body that conducts electricity through the insulating substrate.
と第２の金属体はそれぞれ異なる材質からなることを特
徴とする請求項５に記載の半導体装置。6. The semiconductor device according to claim 5, wherein the first metal layer and the second metal body of the wiring substrate having the three-layer structure are made of different materials.
が複数の端子に分離されていることを特徴とする請求項
５又は６に記載の半導体装置。7. The semiconductor device according to claim 5, wherein one wiring is separated into a plurality of terminals in the wiring board having the three-layer structure.
が、前記搭載された半導体チップの近傍に延在されてい
ることを特徴とする請求項７に記載の半導体装置。8. The semiconductor device according to claim 7, wherein a terminal obtained by separating the one wiring into a plurality of pieces extends in the vicinity of the mounted semiconductor chip.
れた第１の金属層を前記絶縁基板を介在して導通させる
第２の金属体とからなる３層構造のリードフレーム基板
を準備する工程と、前記３層構造のリードフレーム基板
の表面の第１の金属層からなるインナーリード及びタブ
を含むリードパターンを形成する工程と、前記３層構造
のリードフレーム基板の裏面の第１の金属層からなるア
ウターリードのリードパターンをそれぞれ形成する工程
と、前記タブの上に半導体チップを搭載する工程と、前
記半導体チップの電極と前記３層構造のリードの第１の
金属層からなるインナーリードとをボンディングにより
電気的に接続する工程と、少なくとも前記半導体チップ
及び前記電気接続部が樹脂で封止する工程とを有するこ
とを特徴とする半導体装置の製造方法。9. A step of preparing a lead frame substrate having a three-layer structure comprising a first metal layer formed on each of a front surface and a back surface of an insulating substrate and a second metal body which conducts electricity through the insulating substrate. And a step of forming a lead pattern including inner leads and tabs made of a first metal layer on the surface of the three-layer lead frame substrate, and a first metal layer on the back surface of the three-layer lead frame substrate. A step of forming a lead pattern of an outer lead, a step of mounting a semiconductor chip on the tab, and an inner lead formed of an electrode of the semiconductor chip and a first metal layer of the lead of the three-layer structure. And a step of electrically connecting the semiconductor chip and the electrical connection portion with a resin. Body device manufacturing method.
された第１の金属層を前記絶縁基板を介在して導通させ
る第２の金属体とからなる３層構造の配線基板を準備す
る工程と、前記３層構造の配線基板の表面の第１の金属
層からなるインナーリード（内部端子）を含むリードパ
ターンを形成する工程と、前記３層構造の配線基板の裏
面の第１の金属層からなるアウターリード（外部端子）
のリードパターンをそれぞれエッチングにより形成する
工程と、前記３層構造の配線基板の表面の所定位置に半
導体チップを搭載する工程と、前記半導体チップの電極
と前記３層構造のリードの第１の金属層からなるインナ
ーリードとをボンディングにより電気的に接続する工程
と、少なくとも前記半導体チップ及び前記電気接続部が
樹脂で封止する工程とを有することを特徴とする半導体
装置の製造方法。10. A step of preparing a wiring board having a three-layer structure, which comprises a second metal body for electrically connecting a first metal layer formed on each of a front surface and a back surface of the insulating substrate with the insulating substrate interposed therebetween. A step of forming a lead pattern including inner leads (internal terminals) formed of a first metal layer on the front surface of the three-layer wiring board, and a step of forming a lead pattern from the first metal layer on the back surface of the three-layer wiring board. Outer leads (external terminals)
Forming respective lead patterns by etching, mounting a semiconductor chip at a predetermined position on the surface of the wiring substrate having the three-layer structure, electrodes of the semiconductor chip and the first metal of the lead having the three-layer structure A method of manufacturing a semiconductor device, comprising: a step of electrically connecting an inner lead made of a layer by bonding; and a step of sealing at least the semiconductor chip and the electrical connection portion with a resin.
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|---|---|---|---|
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001328985A JP3766312B2 (en) | 2001-10-26 | 2001-10-26 | Semiconductor device and manufacturing method thereof |
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| JP3766312B2 JP3766312B2 (en) | 2006-04-12 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004031388A (en) * | 2002-06-21 | 2004-01-29 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2013179246A (en) * | 2012-02-08 | 2013-09-09 | Mitsumi Electric Co Ltd | Electronic component module and manufacturing method of the same |
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|---|---|---|---|---|
| CN103594380B (en) * | 2013-10-24 | 2016-01-27 | 天水华天科技股份有限公司 | Tape welding spherical array flat-four-side pin-less packaging part preparation method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004031388A (en) * | 2002-06-21 | 2004-01-29 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2013179246A (en) * | 2012-02-08 | 2013-09-09 | Mitsumi Electric Co Ltd | Electronic component module and manufacturing method of the same |
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| Publication number | Publication date |
|---|---|
| JP3766312B2 (en) | 2006-04-12 |
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