JP2003133503A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003133503A
JP2003133503A JP2001322216A JP2001322216A JP2003133503A JP 2003133503 A JP2003133503 A JP 2003133503A JP 2001322216 A JP2001322216 A JP 2001322216A JP 2001322216 A JP2001322216 A JP 2001322216A JP 2003133503 A JP2003133503 A JP 2003133503A
Authority
JP
Japan
Prior art keywords
semiconductor element
lead
cream solder
semiconductor
lead portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001322216A
Other languages
Japanese (ja)
Inventor
Kenji Takaya
健次 貴家
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Electronics Co Ltd
Original Assignee
Citizen Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Electronics Co Ltd filed Critical Citizen Electronics Co Ltd
Priority to JP2001322216A priority Critical patent/JP2003133503A/en
Publication of JP2003133503A publication Critical patent/JP2003133503A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which ensures the prevention of short circuitings between adjacent lead portions by suppressing cream solder from flowing out of the lead portions, while retaining the sufficient coating amount of the cream solder in conducting the actual mounting of a semiconductor chip on a substrate and not permitting bond strength between the two to lower. SOLUTION: The semiconductor device 21 is provided with a semiconductor element 22, a lead frame having a plurality of lead portions 23 which extend to the semiconductor element 22, and a resin material 24 for sealing the semiconductor element 22 and the lead portions 23. The lead portions 23 extend to the under surface of the semiconductor element 22, and electrodes 25 of the semiconductor element 22 are mounted to the ends of the extending leads 23. A groove 33 for collecting solder is formed on the under surface of each lead portion 23.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、リードフレームを
用いたチップ型の半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type semiconductor device using a lead frame.

【0002】[0002]

【従来の技術】従来、複数の素子電極部を備えたチップ
型の半導体装置(以下、半導体チップという)は、複数
のリード部を備えた金属製のリードフレーム上に半導体
素子を設置し、その上を樹脂材で封止することで形成さ
れている。前記各リード部は、半導体素子の各素子電極
部に導通接続されると共に、裏面がマザーボード等の基
板に接続される外部電極部となっている。このような半
導体チップを前記基板上に実装するには、予め実装する
基板の所定位置にクリーム半田を適量塗布しておき、そ
の上に半導体チップの各リード部の裏面を載置する。そ
して、リフロー処理を施すことによって半導体チップが
基板上に接合される。
2. Description of the Related Art Conventionally, a chip type semiconductor device having a plurality of element electrode portions (hereinafter referred to as a semiconductor chip) has a semiconductor element mounted on a metal lead frame having a plurality of lead portions, It is formed by sealing the top with a resin material. Each of the lead portions is electrically connected to each element electrode portion of the semiconductor element, and the back surface thereof is an external electrode portion connected to a substrate such as a mother board. To mount such a semiconductor chip on the substrate, an appropriate amount of cream solder is applied to a predetermined position of the substrate to be mounted in advance, and the back surface of each lead portion of the semiconductor chip is placed thereon. Then, a reflow process is performed to bond the semiconductor chip to the substrate.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記の
半導体チップをクリーム半田を介して基板に実装する場
合、半導体チップの外部電極部となるリード部が小さか
ったり、クリーム半田の塗布量が多過ぎると、余分なク
リーム半田がはみ出してしまう。特に、小型の半導体チ
ップではリード部自体が極小化されると共に、配置密度
を高めるために隣接するリード部同士の間隔が非常に狭
いものとなっている。また、リード部の裏面及び実装す
る基板がともに平坦面となっているので、半液状化され
たクリーム半田をリード部の裏面と基板との間で挟むこ
とによって周囲に広がり易い。このため、リフロー処理
によって加熱溶融されたクリーム半田が広がってはみ出
し、隣接して配置されたリード部同士が前記クリーム半
田でショートするおそれがある。従来にあっては、クリ
ーム半田の塗布量を少なくすることで半田のはみ出しを
抑えるなどの方策がとられていたが、逆にクリーム半田
の塗布量が少な過ぎると半導体チップと基板との接合強
度が弱くなってしまうといった問題があった。
However, when the above-mentioned semiconductor chip is mounted on a substrate via cream solder, if the lead portion which is an external electrode portion of the semiconductor chip is small or the amount of cream solder applied is too large. , Excessive cream solder overflows. In particular, in a small-sized semiconductor chip, the lead portion itself is minimized, and the space between adjacent lead portions is very narrow in order to increase the arrangement density. Further, since the back surface of the lead portion and the board to be mounted are both flat surfaces, it is easy to spread the semi-liquefied cream solder to the surroundings by sandwiching it between the back surface of the lead portion and the board. Therefore, the cream solder heated and melted by the reflow process may spread and protrude, and adjacent lead portions may be short-circuited by the cream solder. In the past, measures such as suppressing solder squeeze out by reducing the amount of cream solder applied were taken, but conversely, if the amount of cream solder applied is too small, the bonding strength between the semiconductor chip and the substrate is increased. There was a problem that became weak.

【0004】そこで、本発明の目的は、基板に実装する
際に、クリーム半田の塗布量を十分に確保して基板との
接合強度を低下させることがなく、また塗布されたクリ
ーム半田がリード部からはみ出すのを抑えて、隣接する
リード部同士のショートを確実に防止するようにした半
導体装置を提供することである。
Therefore, an object of the present invention is to secure a sufficient amount of cream solder to be applied when mounting it on a board without lowering the bonding strength with the board, and to apply the applied cream solder to the lead portion. It is an object of the present invention to provide a semiconductor device in which the protrusion of the lead portions is suppressed and a short circuit between adjacent lead portions is reliably prevented.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
に、本発明の請求項1に係る半導体装置は、半導体素子
と、この半導体素子に向けて延びる複数のリード部を有
するリードフレームと、前記半導体素子及びリード部を
封止する樹脂材とを備えた半導体装置において、前記リ
ード部が半導体素子の下面側に延び、その延びた先端部
に半導体素子の素子電極部が載置されると共に、前記リ
ード部の裏面に半田溜りを形成したことを特徴とする。
In order to solve the above-mentioned problems, a semiconductor device according to claim 1 of the present invention includes a semiconductor element and a lead frame having a plurality of lead portions extending toward the semiconductor element. In a semiconductor device including the semiconductor element and a resin material that seals the lead section, the lead section extends to a lower surface side of the semiconductor element, and an element electrode section of the semiconductor element is mounted on the extended tip section. A solder pool is formed on the back surface of the lead portion.

【0006】この発明によれば、半導体チップをマザー
ボード等の基板上にクリーム半田を介して接合する際
に、リード部の裏面に形成した半田溜りに流動化したク
リーム半田の一部が逃げ込むことができるので、クリー
ム半田がリード部からはみ出すのを有効に抑えることが
できる。
According to the present invention, when the semiconductor chip is bonded onto the substrate such as the mother board via the cream solder, a part of the fluidized cream solder may escape into the solder pool formed on the back surface of the lead portion. Therefore, the solder paste can be effectively prevented from protruding from the lead portion.

【0007】前記半田溜りは、リード部の裏面に設けた
凹み部によって形成されるのが望ましい。この凹み部は
リードフレームを成形する際に、エッチング処理などで
容易に形成することができる。凹み部の具体的な例とし
ては、例えばリード部の裏面に設けた凹溝や凹所、ある
いはリード部の裏面全体をエッチング処理で荒らして粗
面とすることなどがある。前記凹溝や凹所の深さや個
数、位置、形状などは適宜設定することができるが、例
えばクリーム半田が逃げ易いリード部の裏面両端部に形
成した場合にはその効果が大きい。
The solder pool is preferably formed by a recess provided on the back surface of the lead portion. The recess can be easily formed by etching or the like when molding the lead frame. As a concrete example of the recessed portion, for example, a recessed groove or a recess provided on the back surface of the lead portion, or the entire back surface of the lead portion is roughened by an etching process to make it a rough surface. The depth, number, position, shape, etc. of the recessed grooves or recesses can be set as appropriate, but the effect is great when they are formed on both ends of the back surface of the lead portion where cream solder easily escapes.

【0008】[0008]

【発明の実施の形態】以下、添付図面に基づいて本発明
に係る半導体装置の実施形態を詳細に説明する。図1は
第1実施形態に係る半導体チップを示す斜視図であり、
図2は前記半導体チップを基板に実装する前の状態を示
す断面図であり、図3は前記半導体チップを基板に実装
した後の状態を示す断面図である。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a perspective view showing a semiconductor chip according to the first embodiment,
2 is a sectional view showing a state before the semiconductor chip is mounted on a substrate, and FIG. 3 is a sectional view showing a state after the semiconductor chip is mounted on the substrate.

【0009】図1及び図2に示したように、この実施形
態に係る半導体チップ21は、半導体素子22と、該半
導体素子22を載置する4個のリード部23と、該リー
ド部23と半導体素子22とを封止する樹脂材24とで
構成されている。前記半導体素子22は、シリコン結晶
体の正方形の薄板であり、四隅に素子電極部25を備え
ている。
As shown in FIGS. 1 and 2, a semiconductor chip 21 according to this embodiment includes a semiconductor element 22, four lead portions 23 on which the semiconductor element 22 is mounted, and the lead portion 23. It is composed of a resin material 24 that seals the semiconductor element 22. The semiconductor element 22 is a square thin plate of silicon crystal, and has element electrode portions 25 at four corners.

【0010】前記リード部23は、図4に示したような
帯板状のリードフレーム31にエッチング加工などで形
成されたものであり、フレーム本体32から半導体素子
22の載置方向へ先端が向かい合うように延びている。
このリード部23の先端は半導体素子22の四隅に形成
された素子電極部25の下方側にまで延び、その先端上
面には半導体素子22の端部が載置される凹設面28が
形成されている。また、前記各リード部23の裏面29
には前端及び後端にそれぞれ矩形状断面の凹溝33が形
成されている。これらの凹溝33は、図2及び図3に示
すように、基板12にリード部23を接合するときに、
両者間に挟まれたクリーム半田13の一部が逃げ込む半
田溜りとなるものである。前記凹溝33を裏面29の前
端と後端にそれぞれ形成することによって、クリーム半
田13がリード部23の前後端からはみ出すのを効果的
に抑えることができる。
The lead portion 23 is formed on a strip-shaped lead frame 31 as shown in FIG. 4 by etching or the like, and the tips thereof face the frame body 32 in the mounting direction of the semiconductor element 22. Is extended.
The tip of the lead portion 23 extends to the lower side of the element electrode portions 25 formed at the four corners of the semiconductor element 22, and a concave surface 28 on which the end portion of the semiconductor element 22 is placed is formed on the upper surface of the tip. ing. In addition, the back surface 29 of each lead portion 23
A concave groove 33 having a rectangular cross section is formed at each of the front end and the rear end of the. As shown in FIGS. 2 and 3, these recessed grooves 33 are formed when the lead portion 23 is bonded to the substrate 12.
A part of the cream solder 13 sandwiched between the two serves as a solder pool that escapes. By forming the groove 33 at the front end and the rear end of the back surface 29, it is possible to effectively prevent the cream solder 13 from protruding from the front and rear ends of the lead portion 23.

【0011】なお、前記半導体素子22は、素子電極部
25に形成した半田バンプ26によって、リード部23
の凹設面28に接合されると同時に電気的導通が図られ
る。また、前記半導体素子22及びリード部23の上面
側を樹脂材24によって封止することで半導体チップ2
1が形成されるが、樹脂封止時に樹脂材24が凹溝33
内に流れ込まないようにマスキングすることが望まし
い。
In the semiconductor element 22, the lead portion 23 is formed by the solder bumps 26 formed on the element electrode portion 25.
At the same time when it is joined to the recessed surface 28, electrical conduction is achieved. Further, by sealing the upper surfaces of the semiconductor element 22 and the lead portion 23 with the resin material 24, the semiconductor chip 2
1 is formed, but the resin material 24 does not have the groove 33 when the resin is sealed.
It is desirable to mask so that it does not flow inside.

【0012】図2及び図3は、前記構成の半導体チップ
21を基板12に実装する場合を示したものである。先
ず、基板12の電極面にクリーム半田13を塗布する
が、このクリーム半田13は、塗布した状態では流動性
を備えた半固体形状をしており、リフロー等の加熱処理
を施すことによって液状化して両者に付着し、その状態
で固化する性質を備えている。次いで、クリーム半田1
3の上にリード部23が位置するように半導体チップ2
1を載置し、これをリフロー炉に通してクリーム半田1
3を溶融固化させて半導体チップ21を基板12に接合
する。リフロー炉の内部ではクリーム半田13が溶融し
て液状化するために、リード部23の裏面29ではクリ
ーム半田13が一面に広がるが、凹溝33が裏面29の
前端と後端に形成されているために、外方に広がろうと
するクリーム半田13が凹溝33内に逃げ込み、リード
部23の裏面29からはみ出すことなくクリーム半田1
3が固化する。前記クリーム半田13の塗布量はリード
部23の裏面29の広さに応じて適宜調整されるが、凹
溝33が形成されているので多少多めに塗布しても裏面
29からのはみ出しを抑えることができる。このよう
に、クリーム半田13の塗布量が従来のように少な過ぎ
るといったことがなくなるので、半導体チップ21の接
合強度を十分に確保できることになる。
2 and 3 show the case where the semiconductor chip 21 having the above-mentioned structure is mounted on the substrate 12. First, the cream solder 13 is applied to the electrode surface of the substrate 12. The cream solder 13 has a semi-solid shape having fluidity in the applied state, and is liquefied by applying heat treatment such as reflow. It adheres to both sides and solidifies in that state. Next, cream solder 1
So that the lead portion 23 is located on the semiconductor chip 2
1 is placed and passed through a reflow oven to make cream solder 1
3 is melted and solidified to bond the semiconductor chip 21 to the substrate 12. Since the cream solder 13 is melted and liquefied inside the reflow furnace, the cream solder 13 spreads over the back surface 29 of the lead portion 23, but the concave grooves 33 are formed at the front and rear ends of the back surface 29. Therefore, the cream solder 13 that tries to spread outward escapes into the concave groove 33 and does not protrude from the back surface 29 of the lead portion 23.
3 solidifies. The amount of the cream solder 13 applied is appropriately adjusted according to the size of the back surface 29 of the lead portion 23, but since the concave groove 33 is formed, it is possible to suppress the protrusion from the back surface 29 even if a slightly larger amount is applied. You can As described above, the amount of cream solder 13 applied is not too small as in the conventional case, so that the bonding strength of the semiconductor chip 21 can be sufficiently secured.

【0013】図5は本発明に係る半導体チップの第2実
施形態を示したものである。この実施形態に係る半導体
チップ41は、リード部43の裏面46に前後一対の凹
所44を形成し、この凹所44を半田溜りとしたもので
ある。この凹所44は、前記の凹溝33とは異なって密
閉空間を構成するので、凹所44内に逃げ込んだクリー
ム半田13を閉じ込めることができ、リード部43から
のはみ出しをより効果的に抑えることができる。また、
樹脂封止する際にもマスキングなどの工程が不要とな
る。
FIG. 5 shows a second embodiment of the semiconductor chip according to the present invention. In the semiconductor chip 41 according to this embodiment, a pair of front and rear recesses 44 are formed on the back surface 46 of the lead portion 43, and the recesses 44 are used as solder reservoirs. Since the recess 44 forms a closed space unlike the recessed groove 33, the cream solder 13 that has escaped into the recess 44 can be confined, and the protrusion from the lead portion 43 can be suppressed more effectively. be able to. Also,
A step such as masking is not required even when the resin is sealed.

【0014】図6は本発明に係る半導体チップの第3実
施形態を示したものである。この実施形態に係る半導体
チップ51は、リード部53の裏面56をエッチング加
工などによって荒らし、裏面56全体に凸凹状の粗面5
4を形成したものである。粗面54の凹み部を半田溜り
とすることで、基板12上に塗布されたクリーム半田1
3は裏面56全体に形成された粗面54の凹み部に逃げ
込むことができるので、クリーム半田13のはみ出しを
効果的に抑えることができると共に、半導体チップ51
と基板12との接合強度も同時に高めることができる。
FIG. 6 shows a third embodiment of the semiconductor chip according to the present invention. In the semiconductor chip 51 according to this embodiment, the back surface 56 of the lead portion 53 is roughened by etching or the like, and the entire back surface 56 has a rough surface 5 having an uneven shape.
4 is formed. By using the concave portion of the rough surface 54 as a solder pool, the cream solder 1 applied on the substrate 12
3 can escape into the recessed portion of the rough surface 54 formed on the entire back surface 56, so that the cream solder 13 can be effectively prevented from protruding and the semiconductor chip 51 can be prevented.
The joint strength between the substrate 12 and the substrate 12 can be increased at the same time.

【0015】上述したように、本発明の半導体チップ2
1,41,51は、基板12との接合面となるリード部
23,43,53の裏面29,46,56に凹溝33や
凹所44、凸凹状の粗面54等からなる半田溜りを設け
たので、これらの半田溜りに余分なクリーム半田13を
逃がすことによって、液状化したクリーム半田13のは
み出しが効果的に抑えられる。また、クリーム半田13
の塗布量を十分に確保することができるので、半導体チ
ップ21,41,51と基板12との接合強度を低下さ
せることがない。
As described above, the semiconductor chip 2 of the present invention
1, 41 and 51 have solder pools composed of recessed grooves 33, recesses 44 and roughened surfaces 54 on the back surfaces 29, 46 and 56 of the lead portions 23, 43 and 53, which are joint surfaces with the substrate 12. Since the cream solder 13 is provided, excess cream solder 13 is allowed to escape into these solder pools, so that the liquefied cream solder 13 is effectively prevented from protruding. Also, cream solder 13
Since a sufficient coating amount can be secured, the bonding strength between the semiconductor chips 21, 41, 51 and the substrate 12 is not reduced.

【0016】なお、上述した各実施形態の半導体チップ
21,41,51は、いずれも半導体素子22の素子電
極部25が4極の場合について説明したが、本発明は4
極のみに限定されるものではない。また、リード部2
3,43,53の個数も搭載する半導体素子の極数に応
じて変わり得る。さらに、上記実施形態のいずれも半導
体素子22の実装形態として、半田バンプ26によるフ
リップチップ実装について示したが、ボンディングワイ
ヤによる実装形態をとる半導体チップにも適用できるこ
とは勿論である。
The semiconductor chips 21, 41, 51 of each of the above-described embodiments have been described for the case where the device electrode portion 25 of the semiconductor device 22 has four poles.
It is not limited to only poles. In addition, the lead portion 2
The number of 3, 43, 53 can also change depending on the number of poles of the semiconductor element to be mounted. Further, in each of the above-described embodiments, flip chip mounting using the solder bumps 26 is shown as the mounting form of the semiconductor element 22, but it goes without saying that the present invention can also be applied to a semiconductor chip using a bonding wire.

【0017】[0017]

【発明の効果】以上説明したように、本発明に係る半導
体装置によれば、半導体装置をマザーボード等の基板上
にクリーム半田を介して接合する際に、リード部の裏面
に形成した半田溜りにクリーム半田の一部を逃がすこと
で、クリーム半田がリード部からはみ出すのを有効に抑
えることができる。
As described above, according to the semiconductor device of the present invention, when the semiconductor device is bonded to the substrate such as the mother board via the cream solder, the solder pool is formed on the back surface of the lead portion. By letting a part of the cream solder escape, it is possible to effectively prevent the cream solder from protruding from the lead portion.

【0018】また、従来のようにクリーム半田の塗布量
が少な過ぎるといったことがなくなるので、半導体装置
の接合強度を十分に確保できる。
Further, since the amount of cream solder applied is not too small as in the conventional case, the bonding strength of the semiconductor device can be sufficiently secured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体装置の第1実施形態を示す
斜視図である。
FIG. 1 is a perspective view showing a first embodiment of a semiconductor device according to the present invention.

【図2】上記図1の半導体装置を基板に実装する前の状
態を示す断面図である。
FIG. 2 is a cross-sectional view showing a state before the semiconductor device of FIG. 1 is mounted on a substrate.

【図3】上記図1の半導体装置を基板に実装した後の状
態を示す断面図である。
3 is a cross-sectional view showing a state after the semiconductor device of FIG. 1 is mounted on a substrate.

【図4】上記図1の半導体装置の土台となるリードフレ
ームの斜視図である。
4 is a perspective view of a lead frame which is a base of the semiconductor device of FIG.

【図5】本発明に係る半導体装置の第2実施形態を示す
斜視図である。
FIG. 5 is a perspective view showing a second embodiment of the semiconductor device according to the present invention.

【図6】本発明に係る半導体装置の第3実施形態を示す
断面図である。
FIG. 6 is a sectional view showing a third embodiment of the semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

21,41,51 半導体装置(半導体チップ) 22 半導体素子 23,43,53 リード部 24 樹脂材 29,46,56 裏面 31 リードフレーム 33 凹溝 44 凹所 54 粗面 21, 41, 51 Semiconductor device (semiconductor chip) 22 Semiconductor element 23,43,53 Lead part 24 Resin material 29,46,56 back side 31 lead frame 33 groove 44 recess 54 rough surface

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子と、この半導体素子に向けて
延びる複数のリード部を有するリードフレームと、前記
半導体素子及びリード部を封止する樹脂材とを備えた半
導体装置において、 前記リード部が半導体素子の下面側に延び、その延びた
先端部に半導体素子の素子電極部が載置されると共に、
前記リード部の裏面に半田溜りを形成したことを特徴と
する半導体装置。
1. A semiconductor device comprising a semiconductor element, a lead frame having a plurality of lead portions extending toward the semiconductor element, and a resin material for sealing the semiconductor element and the lead portion, wherein the lead portion is Extending to the lower surface side of the semiconductor element, the element electrode portion of the semiconductor element is mounted on the extended tip portion,
A semiconductor device, wherein a solder pool is formed on the back surface of the lead portion.
【請求項2】 前記半田溜りがリード部の裏面に設けた
凹み部によって形成されてなる請求項1記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein the solder pool is formed by a recessed portion provided on the back surface of the lead portion.
JP2001322216A 2001-10-19 2001-10-19 Semiconductor device Pending JP2003133503A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001322216A JP2003133503A (en) 2001-10-19 2001-10-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001322216A JP2003133503A (en) 2001-10-19 2001-10-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2003133503A true JP2003133503A (en) 2003-05-09

Family

ID=19139296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001322216A Pending JP2003133503A (en) 2001-10-19 2001-10-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2003133503A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020004799A (en) * 2018-06-26 2020-01-09 京セラ株式会社 Wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020004799A (en) * 2018-06-26 2020-01-09 京セラ株式会社 Wiring board
JP7088757B2 (en) 2018-06-26 2022-06-21 京セラ株式会社 Wiring board

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