JP2003133313A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem, when copper wiring is formed by the conventional damascene or dual-damascene method, the chip acquisition ratio per wafer becoming low, because chips on the outer periphery of a wafer and its vicinity are not able to be exposed to light for preventing copper contamination. SOLUTION: At the time of forming a wiring groove pattern, a negative resist is used as a resist and the outer peripheral section of the wafer is exposed to light before development. In addition, at formation of a wiring hole pattern a positive resist is used as a resist and wiring holes in the outer peripheral section of the wafer are crushed, by selectively heat-treating the outer peripheral section, after and development following the resist exposure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a high yield of chips and a high chip acquisition rate.

[0002]

2. Description of the Related Art In recent years, for the purpose of improving the operating speed of semiconductor devices, copper wiring semiconductor devices using copper as a wiring material and having a reduced wiring resistance have been mass-produced. As a method of forming a copper wiring, a wiring pattern and a wiring hole are formed in an insulating film using a resist pattern as a mask, copper is embedded in the groove and the hole, and then the chemical mechanical polishing (CMP, Ch) of the embedded copper is performed.
mechanical Mechanical Polish
ng) to form a copper wiring is used. Alternatively, a dual damascene method is used in which a wiring hole and a wiring groove are formed and then copper is embedded to perform CMP to simultaneously form a wiring and a connection wiring. The dual damascene method is described in, for example, JP 2001-257260 A.
It is described in the official gazette.

[0003]

In the conventional damascene or dual damascene method described above, when copper is CMP, copper wiring remains on the outer periphery of the wafer, and the copper is exposed in the subsequent process due to mechanical contact or the like. The problem of copper contamination of semiconductors has occurred, which has reduced the yield. In order to prevent this problem, a positive resist is used as a resist, and the resist is left on the outer peripheral portion of the wafer without performing chip exposure near the outer peripheral portion of the wafer, and copper is not left on the outer peripheral portion of the wafer. However, this method, which does not perform chip exposure on the outer peripheral portion of the wafer, has a problem that the number of exposed chips is reduced and the chip acquisition rate per wafer is reduced. It is an object of the present invention to provide a manufacturing method capable of increasing the yield of semiconductor devices (chips) having a fine circuit pattern and increasing the chip acquisition rate per wafer.

[0004]

In the present invention, a negative resist is used as a resist for forming a wiring groove pattern, and the outer peripheral portion of the wafer is exposed before development. In addition, a positive resist is used as a resist when forming the wiring hole pattern, and after the pattern exposure, the peripheral portion of the wafer is selectively heat-treated after development to crush the wiring hole in the peripheral portion of the wafer.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) In Embodiment 1, FIG. 1 is a process chart showing a manufacturing process of a semiconductor device.
A method of forming a copper trench wiring by the single damascene method will be described with reference to FIGS. 2A to 2H and FIG. 2 which is an explanatory view illustrating the outline of the main part processing method. First, as shown in FIG. 1A, an insulating film 101 and a negative photoresist 102 were formed on a wafer 100. Here, the processed film 101
An oxide film was used as the. However, this is only an example, an insulating film such as a nitride film, an organic film such as SiLK (DuPont),
A coating film such as SOG may be used. As the negative resist 102, a polarity conversion type chemical amplification type resist obtained by adding an acid generator to an alicyclic compound containing δ-hydroxycarboxylic acid was used. Details of this material are described in Japanese Patent Application No. 11-3569.
69. However, the material is not limited to this material, and may be a cross-linking type chemically amplified negative resist or a non-chemically amplified negative resist. Then Figure 1
As shown in (b), the light irradiation device 103 is provided on the outer peripheral portion of the wafer.
By irradiating the light 104 by the
05 is exposed. Here, the exposure light has a wavelength of 250n
m DUV light was used. However, this is just an example and may be light that the negative resist 102 is exposed to. In this example ArF
Excimer laser light (wavelength 193 nm) or KrF excimer laser light (wavelength 248 nm) may be used. This exposure method will be described with reference to FIG. FIG. 2A is a view of the wafer viewed from the cross section, and FIG. 2B is a view of the wafer viewed from the top. The wafer 100 is vacuum sucked and placed on the spin chuck 120, and the rotation of the spin chuck also rotates the wafer. A light irradiation device 103 is placed above the wafer 100, and the position of the light irradiation unit can be moved in the wafer radial direction. Therefore, it is possible to expose the outer peripheral portion of the wafer to a ring shape having an arbitrary width. Thereafter, as shown in FIG. 1C, exposure light 107 was irradiated through a photomask 106 having a desired wiring groove pattern formed thereon and a projection lens (not shown). Here, the exposure light has a wavelength of 193 nm.
Although the ArF excimer laser light of was used, the present invention is not limited to this, and KrF excimer laser light of a wavelength of 248 nm can also be used. By exposure, a latent image 105 is formed on the resist film at a desired position. Then, after performing a usual post-exposure heat treatment (post-exposure bake), FIG.
As shown in (d), ordinary development was performed to form a resist pattern 108. The resist 109 remains on the outer peripheral portion of the wafer due to the exposure effect on the outer peripheral portion of the wafer. Next, Figure 1
As shown in (e), the insulating film 101 was etched using the resist pattern 108 as a mask, and the resist pattern was removed by a usual method to form an insulating film groove pattern 110 as shown in FIG. 1 (f). After that, copper was deposited as shown in FIG. 1G and CMP was performed to form a copper wiring 112 as shown in FIG. 1H. By this method, it was possible to form a copper wiring with no copper remaining on the outer peripheral portion of the wafer. Therefore, copper is not scattered and does not become a pollution source even in the mechanical contact of the outer peripheral portion of the wafer that occurs during the subsequent semiconductor device manufacturing process, and the yield is high. This mechanical contact is caused by, for example, rubbing with the wafer cassette, a pressing ring during etching or CVD, holding during wafer transfer, and the like. Copper pollution prevention is not only a case where the wafer is damaged, but also a line pollution source, so the damage is great. FIG. 8 shows a chip acquisition state per wafer, and 700 is the outer periphery of the wafer. Reference numeral 701 denotes a pattern boundary line. It is allowed that there is a pattern inside and there is no resist on the inside, but if there is no resist on the outside and copper remains as a result, copper contamination occurs when mechanical contact is received. Yields are reduced. The 3 × 3 matrix represents one shot area of the exposure apparatus, and each cell represents each chip. The case of exposure by a stepper is shown. FIG. 8A shows a conventional exposure method using a positive resist, and chip acquisition is limited to the area 702. The number of chips is 108 chips. When the area outside the area 702 is exposed, the resist in the area outside the area 701 is pattern-exposed and a part without the resist is generated. In the subsequent process, copper remains in this portion and becomes a contamination source, so that this area cannot be exposed. FIG. 8B shows a case where the present invention is used, a negative resist is used, and since the outside of 701 is exposed, the resist remains in this portion, and therefore copper does not remain. Therefore, it becomes possible to perform exposure outside the area 702 as well.
It has become possible to acquire more 44 chips shown in 703. 1 chip acquisition per wafer according to the present invention
It was possible to increase the number from 08 chips to 152 chips significantly.

(Embodiment 2) In Embodiment 2, FIGS. 3A to 3H which are process diagrams showing a manufacturing process of a semiconductor device, and an explanatory view for explaining an outline of a main part processing method. A method of forming a copper via wiring by the single damascene method will be described with reference to FIG. First, as shown in FIG. 3A, an insulating film 101 and a normal positive photoresist 202 were formed on a wafer 100. Here, an oxide film is used as the film to be processed 101. However, this is only an example, an insulating film such as a nitride film, an organic film such as SiLK (DuPont), an S
A coating formation film such as OG may be used. Then Fig. 3
As shown in (b), the exposure light 107 was irradiated through a photomask 106 having a desired wiring hole pattern formed by a usual method and a projection lens (not shown). Next, after a normal post-exposure heat treatment (post-exposure bake), a normal development was carried out to form a resist pattern 203, as shown in FIG. Since the outer peripheral portion of the wafer is also exposed, a hole pattern is also formed on the outer peripheral portion of the wafer at this stage. After that, as shown in FIG. 3D, light 205 is irradiated to the outer peripheral portion of the wafer by a heat ray (infrared) irradiation device 204, and the resist holes formed in the outer peripheral portion of the wafer are subjected to heat flow to form resist 206 having a crushed hole. . Since it is a fine hole, it can be sufficiently filled with heat flow. This heat flow method will be described with reference to FIG. FIG. 4A is a view of the wafer viewed from the cross section, and FIG. 4B is a view of the wafer viewed from the top. The wafer 100 is vacuum sucked and placed on the spin chuck 120, and the rotation of the spin chuck also rotates the wafer. Above the wafer 100, the heat ray irradiation device 2
04 is placed, and the position of the light irradiation part can be moved in the radial direction of the wafer. For this reason, it is possible to heat-flow the resist on the outer peripheral portion of the wafer in a band shape having an arbitrary width. As a result, a resist 206 having no pattern remains along the outer circumference of the wafer. Next, as shown in FIG. 3E, the insulating film 101 is etched using a resist as a mask, the resist pattern is removed by a usual method, and the insulating film 207 having a hole pattern is formed as shown in FIG. 1F. Was formed. After that, copper was deposited as shown in FIG. 3G and CMP was performed to form a copper via wiring 209 as shown in FIG. 3H.
By this method, it was possible to form a copper via wiring in which no copper remained on the outer peripheral portion of the wafer. Therefore, copper is not scattered and does not become a pollution source even in the mechanical contact of the outer peripheral portion of the wafer that occurs during the subsequent semiconductor device manufacturing process, and the yield is high. FIG. 9 shows the chip acquisition state per wafer, and 700 is the outer periphery of the wafer. A resist boundary line 701 is allowed to have a resist opening portion inside thereof, but if there is an opening portion outside thereof, copper remains in the opening portion in the subsequent process. The outer peripheral portion of the wafer is mechanically contacted by rubbing against the wafer cassette or the like. If copper remains on the outer peripheral portion of the wafer due to the mechanical contact, the copper is scattered to cause copper contamination. As a result, the yield is reduced. 3x3
Matrix indicates one shot area of the exposure apparatus,
Each cell represents one chip. The case of exposure by a stepper is shown. FIG. 9A shows the case where the conventional wafer outer peripheral portion is not heat-treated, and chip acquisition is limited to the area 802. The number of chips is 108 chips. Exposing the area outside 802 forms a hole pattern, leaving copper behind. This area cannot be exposed because it becomes a contamination source. FIG. 9B shows a case where the present invention is used, and the resist pattern on the outside of 801 is crushed by a heat flow, so that copper does not remain. Therefore, it is possible to perform exposure outside the area of 802 as well, and it is possible to acquire more 44 chips shown in 803. The present invention makes it possible to significantly increase the number of chips acquired per wafer from 108 chips to 152 chips. In the formation of via wiring, since a hole pattern with a small opening area is formed, lithography using a positive resist that is less likely to cause mask defects is extremely effective in terms of yield.

(Third Embodiment) In the third embodiment, a method of forming a copper wiring by a dual damascene method will be described with reference to FIGS. 5A to 5H, which are process diagrams showing a manufacturing process of a semiconductor device. explain. First, as shown in FIG. 5A, the resist pattern 3 is formed on the sample on which the insulating film 301, the wiring 302, the etching stopper 303, the interlayer insulating film 304, the intermediate film 305, and the interlayer insulating film 306 are formed on the wafer 100.
07 is formed. Fine holes 3 are formed in the resist pattern 307.
08 is formed. Here, the hole pattern on the outer peripheral portion of the wafer is crushed by using the heat flow method using the heat rays shown in the second embodiment. The resist is a positive resist. A silicon nitride film, a silicon carbide film, or the like is used as the etching stopper 303 and the intermediate film 305, but the etching stopper 303 and the intermediate film 305 are not limited thereto. Although a silicon oxide film is used here as the interlayer insulating film, the insulating film is not limited to this, and a coating film such as SOG or SiLK (DuPont) may be used. Next, the interlayer insulating film 306 and the intermediate film 305 are etched using the resist 307 having the hole pattern 308 as a mask to form the interlayer insulating film 306 ′ and the intermediate film 305 ′ having fine holes. Figure 5
After removing the resist as shown in (c), FIG.
A resist 309 having a wiring groove pattern 310 is formed as shown in FIG. Here, a negative resist was used as the resist, and the outer periphery of the wafer was exposed in the same manner as in Embodiment 1 to form a resist pattern in which no opening was formed in the outer periphery of the wafer. After that, the interlayer insulating film 306 is etched using the resist 309 as a mask, and then the interlayer insulating film 304 is etched using the intermediate film 305 ′ having fine holes formed as a mask, and as shown in FIG. An interlayer insulating film 306 ″ having a groove pattern and an interlayer insulating film 304 ′ having a via pattern are formed. At this time, the wiring 302 is not etched by the etching stopper 303. After that, the etching stopper 303 is formed.
Etching is performed to form an etching stopper 303 ′ having an opening formed in a fine hole. During this etching, the intermediate film in the groove portion was removed to become an intermediate film 305 ″ having an opening formed in the groove portion. Then, the resist was removed.
(FIG. 5 (f)) After that, as shown in FIG.
1 was deposited and CMP was performed to form a copper wiring 312 by dual damascene. (FIG. 5 (h)) By this method, it was possible to form dual damascene copper wiring with no copper remaining on the outer peripheral portion of the wafer. Therefore, copper is not scattered and does not become a pollution source even in the mechanical contact of the outer peripheral portion of the wafer that occurs during the subsequent semiconductor device manufacturing process, and the yield is high. Furthermore, since the chip exposure around the wafer can be performed without worrying about copper contamination, the first embodiment
The chip acquisition rate was improved as in the cases 1 and 2.

Further, in this method, as shown in FIG. 5 (d), the lithography for forming the wiring groove is performed after the fine holes are formed. However, since a negative resist is used in this step, it is difficult for the exposure light to pass through. The resist in this portion can be removed by development without exposing the hole. Therefore, since the exposure condition can be fitted to the wiring groove pattern formation, there is a feature that the wiring groove pattern formation accuracy can be easily obtained.

(Embodiment 4) In Embodiment 4, a method of forming a copper wiring by a dual damascene method will be described with reference to FIGS. 6A to 6H which are process diagrams showing a manufacturing process of a semiconductor device. explain. First, as shown in FIG. 6A, a resist pattern 405 is formed on the wafer 100 on which the insulating film 401, the wiring 402, the first interlayer insulating film 403, and the second interlayer insulating film are formed. Resist pattern 405
A wiring groove pattern 406 is formed on the. Here, when forming the resist pattern, the exposure of the outer peripheral portion of the wafer described in the first embodiment is performed. The resist is a negative resist. Here, a silicon oxide film is used here as the interlayer insulating film, but the present invention is not limited to this, and a coating film such as SOG may be used.
Next, a resist 405 on which the wiring groove pattern 406 is formed
The first interlayer insulating film 404 is etched by using as a mask to form an interlayer insulating film 404 ′ having an open wiring groove. (Fig. 6
(B)) After removing the resist as shown in FIG. 6C, a resist 405 having a via pattern 406 is formed as shown in FIG. 6D. Here, as the resist, a positive resist was used, and similarly to the second embodiment, after development, the outer peripheral portion of the wafer was irradiated with heat rays to form a resist pattern having no openings formed in the outer peripheral portion of the wafer. After that, the second interlayer insulating film 403 was etched using the resist 405 as a mask to form an interlayer insulating film 403 ′ in which fine holes were formed. (FIG. 6E) After that, the resist is removed.
(FIG. 6 (f)) and copper 407 as shown in FIG. 6 (g).
And CMP were performed to form a copper wiring 408 by dual damascene. (FIG. 6 (h)) By this method, it was possible to form the dual damascene copper wiring with no copper remaining on the outer peripheral portion of the wafer. Therefore, copper is not scattered and does not become a pollution source even in the mechanical contact of the outer peripheral portion of the wafer that occurs during the subsequent semiconductor device manufacturing process, and the yield is high. Further, since chip exposure around the wafer can be performed without worrying about copper contamination, the chip acquisition rate is improved as in the first and second embodiments.

Further, this method has a feature that an intermediate layer between the first-layer building insulating film and the second-layer building insulating film is unnecessary and the process is short.

(Fifth Embodiment) In the fifth embodiment, a method for forming a copper wiring by a dual damascene method will be described with reference to FIGS. 7A to 7H, which are process diagrams showing a manufacturing process of a semiconductor device. explain. First, as shown in FIG. 7A, the insulating film 501, the wiring 502, the etching stopper 503, the first interlayer insulating film 504, and the intermediate film 50 are formed on the wafer 100.
5, the second interlayer insulating film 506 and the hard mask 507 are formed, and then a resist pattern 508 is formed. A wiring groove pattern 509 is formed on the resist pattern 508. Here, when forming the resist pattern, the exposure of the outer peripheral portion of the wafer described in the first embodiment is performed. The resist is a negative resist. As the etching stopper 502, the intermediate film 505, and the hard mask 507, a silicon nitride film, a silicon carbide film, or the like is used, but the invention is not limited to this. Although a silicon oxide film is used here as the first and second interlayer insulating films, the present invention is not limited to this. For example, organic SOG or Si.
It is also possible to use a coating film such as LK (DuPont).
Next, a resist 508 having a wiring groove pattern 509 formed thereon
Is used as a mask to form a hard mask 507 'having a groove. (FIG. 7B) After removing the resist, a resist 510 having a via pattern is formed as shown in FIG. 7C. Here, as the resist, a positive resist was used, and similarly to the second embodiment, after development, the outer peripheral portion of the wafer was irradiated with heat rays to form a resist pattern in which no opening was formed in the outer peripheral portion of the wafer. Then, using the resist as a mask, the second interlayer film 506 and the intermediate film 505 are etched to form an interlayer insulating film 506 'and an intermediate film 505' having via holes. (FIG. 7D) After removing the resist, etching is performed to form a second interlayer film 506 ″ having a wiring groove formed therein and a first interlayer insulating film 504 ′ having a via hole formed therein (FIG. 7D). (E)) Here, the etching stopper 5
The wiring 502 is protected by 07 from this etching. Thereafter, as shown in FIG. 7F, the etching stopper 503 is etched to remove the insulating film on the wiring 502. The intermediate layer exposed during this etching is also scraped. Then, as shown in FIG. 7G, copper 511 is deposited, CMP is performed, and copper wiring 51 is formed by dual damascene.
Formed 2. (FIG. 7 (h)) By this method, it was possible to form the dual damascene copper wiring with no copper remaining on the outer peripheral portion of the wafer. Therefore, copper is not scattered and does not become a pollution source even in the mechanical contact of the outer peripheral portion of the wafer that occurs during the subsequent semiconductor device manufacturing process, and the yield is high. Furthermore, since the chip exposure around the wafer can be performed without worrying about copper contamination, the first embodiment
The chip acquisition rate was improved as in the cases 1 and 2.

Further, in this method, as shown in FIGS. 7B and 7C, the lithography for forming the wiring groove and the via hole is performed on the low hard mask 507 even if there is no step, so that the lithography is performed. The feature is that the precision, that is, the pattern forming precision, is extremely high.

[0013]

According to the present invention, a semiconductor device (chip) having a fine circuit pattern can be manufactured with a high yield and a high chip acquisition rate per wafer.

[Brief description of drawings]

FIG. 1 is a process drawing showing a manufacturing process of a semiconductor device by using a sectional view of a semiconductor wafer.

FIG. 2 is an explanatory diagram of wafer peripheral portion processing. (A) is sectional drawing, (b) is a top view.

FIG. 3 is a process drawing showing a manufacturing process of a second semiconductor device using a cross-sectional view of a semiconductor wafer.

FIG. 4 is an explanatory diagram of a second wafer outer peripheral portion process.
(A) is sectional drawing, (b) is a top view.

FIG. 5 is a process drawing showing a manufacturing process of a third semiconductor device by using a sectional view of a semiconductor wafer.

FIG. 6 is a process drawing showing a manufacturing process of a fourth semiconductor device using a cross-sectional view of a semiconductor wafer.

FIG. 7 is a process drawing showing a manufacturing process of a fifth semiconductor device by using a sectional view of a semiconductor wafer.

FIG. 8 is an explanatory diagram illustrating a chip acquisition rate of a semiconductor device.

[Explanation of symbols]

100 ... Wafer, 101 ... Insulating film, 102 ... Negative resist film, 103 ... Light irradiation device, 104 ... Light, 105 ... Photosensitive part, 106 ... Mask, 107 ... Exposure light, 108 ... Resist pattern, 109 ... Resist, 110 ... Groove pattern,
111 ... Copper, 112 ... Copper wiring, 120 ... Spinner, 20
2 ... Positive resist, 203 ... Wiring hole pattern, 204 ...
Heat ray irradiation device, 205 ... Heat ray (infrared ray), 206 ... Resist, 207 ... Wiring hole, 208 ... Copper, 209 ... Copper via wiring, 301 ... Insulating film, 302 ... Wiring, 303 ... Etching stopper, 304 ... Interlayer insulating film, 305 ... Intermediate film, 3
06 ... Interlayer insulating film, 307 ... Positive resist, 308 ... Hole pattern, 309 ... Negative resist, 310 ... Wiring groove pattern, 311 ... Copper, 312 ... Dual damascene copper wiring,
401 ... Insulating film, 402 ... Wiring, 403 ... Interlayer insulating film,
404 ... Interlayer insulating film, 405 ... Negative resist, 406 ...
Wiring groove pattern, 407 ... Copper, 408 ... Dual damascene copper wiring, 501 ... Insulating film, 502 ... Wiring, 503 ... Etching stopper, 504 ... Interlayer insulating film, 505 ... Etching stopper, 506 ... Interlayer insulating film, 507 ... Hard mask , 508 ... Negative resist, 509 ... Wiring groove pattern, 510 ... Positive resist, 511 ... Copper, 512 ... Dual damascene copper wiring, 700 ... Wafer edge, 701 ...
Outermost position of resist deposition, 702 ... Exposure chip, 703
… Additional acquisition tip.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shoji Hotta             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center (72) Inventor Koji Hattori             1-280, Higashi Koikekubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Yoshiyuki Yokoyama             1-280, Higashi Koikekubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Kaori Kimura             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within F-term (reference) 4M104 BB04 CC01 DD07 DD15 DD16                       DD17 DD19 DD20 DD75 DD99                       FF40 HH20                 5F033 HH11 JJ01 JJ11 KK11 MM01                       MM02 QQ01 QQ09 QQ25 QQ28                       QQ37 QQ48 QQ72 QQ75 QQ83                       RR01 RR04 RR06 RR09 RR21                       SS21 XX00 XX03

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device having a copper wiring, comprising the steps of forming a negative resist on an insulating film formed on a wafer, and irradiating the outer peripheral portion of the wafer with light sensitized to the negative resist. A step of exposing a wiring pattern, a step of developing the negative resist, a step of etching the insulating film with the resist pattern as a mask to form a wiring groove, a step of removing the resist, and a step of removing copper. A method of manufacturing a semiconductor device, comprising: a step of burying in the formed wiring groove; and a step of performing chemical mechanical polishing of the copper that has been embedded. 2. A method of manufacturing a semiconductor device having a copper via wiring, wherein a positive resist is formed on an insulating film formed on a wafer, a via pattern is exposed, and the positive resist is developed. A step of performing a heat treatment on the outer peripheral portion of the wafer after the development to crush the via hole pattern on the outer peripheral portion of the wafer by a heat flow, forming a wiring hole by etching the insulating film using the via pattern as a mask, and the resist And a step of burying copper in the formed wiring hole, and a step of performing chemical mechanical polishing of the embedded copper, a method of manufacturing a semiconductor device. 3. A method of manufacturing a semiconductor device in which a copper wiring is formed by a dual damascene method, wherein a positive resist is used for forming a via pattern, and after the exposure and development of the via pattern, a heat treatment is applied to the outer peripheral portion of the wafer to form a via hole pattern in the outer peripheral portion of the wafer. And a step of irradiating the outer peripheral portion of the wafer with light that is exposed to the negative resist before developing the negative resist, and a step of crushing the negative resist with a heat flow. Device manufacturing method.