JP2003124833A - Receiving device, phase shift network circuit, and image rejection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To embody a high-sensitivity receiving circuit, to improve the degree of freedom of design by devising a connection destination of a phase element, and to realize low current consumption. SOLUTION: A device is equipped with a voltage-controlled oscillator (VCO) 12 which outputs 1st and 2nd frequencies in orthogonal relation, a 1st mixer circuit 13 which mixes a distributed received signal with the 1st frequency, a 2nd mixer circuit 16 which mixes the distributed received signal with the 2nd frequency, a 1st phase shift network (PSN) block 15 which rotates the phase of the output from the 1st mixer circuit 13 with a 90 deg. phase difference, a 2nd PSN block 18 which rotates the phase of the output from the 2nd mixer circuit 16 with a 90 deg. phase difference, and an adder 19 which adds the output from the 1st PSN block 15 and the output from the 2nd PSN block; and PSN circuits which constitute the 1st PSN block 15 and 2nd PSN block 18 are operated with differential signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver used as a GPS receiver or the like, and more particularly to a receiver using a phase shift network circuit operating with a differential signal.

[0002]

2. Description of the Related Art In a general receiving device including a GPS (Global Positioning Systems) receiver, a phase shift network (PSN: P
A system configuration using a hase Shift Network) circuit can be adopted. By adopting this PSN method, it is possible to suppress an image signal generated when a mixer circuit that performs frequency conversion is operated, and it is possible to configure a receiving circuit that can suppress this image signal. By adopting such a configuration in a general receiving device, the mixer circuit can be provided in one stage, and it is necessary, for example, when the oscillator needs to be configured on the IC and the circuit is to be as simple as possible. The configuration is preferred.

FIG. 8 is a diagram showing a circuit configuration of a PSN circuit conventionally used in a general phase shifter. Since the emitter (E) side and the collector (C) side of the transistor Q1 are in opposite phase to each other, they are added and amplified by the next-stage transistor Q2 and output. At this time, by setting the ratio between the capacitor C1 and the resistor R3, it is possible to rotate the phase by 90 degrees at the desired frequency and output the phase shift signal.

That is, as shown in FIG. 8, an input signal V1 from an input signal source is input to an amplifier circuit composed of a transistor Q1, a resistor R1 and a resistor R2. The output of the same phase as the input of this amplifier circuit is the emitter of the transistor Q1.
The output of the opposite phase is taken out from the collector (C) of the transistor Q1. When the emitter resistance of the transistor Q1 is re1, the anti-phase output gain is represented by R2 / (R1 + re1) and is generally set to 0 dB. Therefore, the resistance R1 has a value less than or equal to the resistance R2. Further, the resistance R2 needs to be set small in order to improve the frequency characteristic, and the current flowing through the transistor Q1 becomes large in order to secure the output level.

Here, the capacitor C1 and the resistor R3 are phase shifting elements that determine the amount of phase shift, and are connected to the anti-phase output and the in-phase output of the transistor Q1, respectively. On the other hand, the transistor Q2, the resistor R4, and the resistor R5 are an output circuit of a phase-shifted signal. When outputting in-phase, the transistor Q2 outputs from the emitter (E) of the transistor Q2. Output from collector (C). In this case, assuming that the emitter resistance of the transistor Q2 is re2, the gain in this case is determined by R5 / (R4 + re2).

[0006]

However, in the circuit configuration of the prior art as shown in FIG. 8, the circuit is easily affected by an interfering wave, that is, an unnecessary signal on the power supply or GND is added to the signal line. , S / N, spurious levels, etc. have a problem of deteriorating communication quality. Particularly in the field of communication equipment, in many cases, it is very sensitive to the sneak of the power supply and the GND, and the circuit configuration of the prior art cannot be used for a circuit handling a weak signal.

The output impedance of the transistor Q1 on the negative phase signal side is determined by the resistor R2.
Should be set to a small value. Further, since the output gain is set to 0 dB at the same time, the resistance R1 also becomes a small value equal to or smaller than the resistance R2, and there is a problem that the current flowing through the transistor Q1 becomes large in order to obtain a required output amplitude.

The present invention has been made to solve the above technical problems, and an object of the present invention is to realize a highly sensitive receiving circuit.

Another object of the present invention is to devise the connection destination of the phase shift element to increase the degree of freedom in design and to reduce the current consumption.

[0010]

Based on the above object, a receiving apparatus to which the present invention is applied includes a voltage controlled oscillator which outputs a first frequency and a second frequency which are in an orthogonal relationship,
In a received signal such as a PS (Global Positioning Systems) signal, a first mixer circuit that mixes one distributed received signal with a first frequency, and another distributed received signal with a second frequency To the output from the first mixer circuit, a first phase shift network block that rotates a phase with a phase difference of 90 degrees with respect to the output from the first mixer circuit, and an output from the second mixer circuit. A second phase shift network block that rotates the phase with a phase difference of 90 degrees; and an adder that adds the output from the first phase shift network block and the output from the second phase shift network block. The phase shift network circuit that constitutes the first phase shift network block and the second phase shift network block is The feature is that it operates with a differential signal.

If the first phase shift network block and the second phase shift network block are each provided with a plurality of phase shift network circuits, the width of the bandwidth to be handled can be widened. It is preferable in terms.

Further, this phase shift network circuit is excellent in that the output impedance of the negative phase signal can be set low if the negative phase signal is taken out from the in-phase side of the differential signal. There is.

On the other hand, a phase shift network (PSN) circuit to which the present invention is applied has a differential input terminal for inputting a first input signal and a second input signal on the differential side,
A first buffer amplifier that receives the first input signal that is input to the differential input terminal and a second buffer amplifier that is input to the differential input terminal
A second buffer amplifier for inputting the input signal and a phase shift element which is an element for determining a phase shift amount when the in-phase signal with respect to the first input signal is input from the first buffer amplifier. The phase shift element is characterized in that a negative phase signal is input from the second buffer amplifier.

Here, a signal on the same phase as the second input signal is input from the second buffer amplifier, and a differential side phase shift element which is an element for determining a phase shift amount is further provided. The phase shift element can be characterized in that a signal having a phase opposite to that of the second input signal is input from the first buffer amplifier.

From another point of view, the present invention is a phase shift network circuit in which the received signal and the frequency output from the voltage controlled oscillator rotate the phase with respect to the mixed IF signal. A first output means for outputting a signal phase-shifted with respect to the in-phase signal of the IF signal, and a second output means for outputting a signal phase-shifted with respect to the differential signal of the IF signal. It is characterized by having.

Further, the present invention can be understood as an image rejection method. Here, two frequencies having an orthogonal relationship are output, and each of the distributed reception signals and the two frequencies output are mixed to obtain I
Image rejection for converting to an F frequency, rotating the phase with a phase difference of 90 degrees for each of the converted IF signals, outputting a phase shift signal, and adding the output phase shift signals to suppress an image signal The method is characterized in that the phase shift signal output here is a signal having a differential relationship.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below in detail based on the embodiments shown in the accompanying drawings. FIG. 1 is a block diagram showing the configuration of a receiving apparatus to which this embodiment is applied. The receiver shown in FIG. 1 is equipped with an image rejection mixer for removing an image component when a high frequency signal and a local signal are mixed and converted into an intermediate frequency signal (IF signal) in a receiver such as GPS. It is a thing.

The receiving system shown in FIG. 1 comprises a high frequency amplifier (RFAMP) 11 for amplifying a high frequency received signal and a voltage controlled oscillator (VC) for outputting two frequencies in orthogonal relation.
O) 12, received signal amplified by RF AMP11 and V
Mixer circuits 13 and 16 for mixing (multiplying) a local signal having a quadrature phase made by the CO 12 and converting to an IF frequency, IF AMPs 14 and 17 for amplifying the IF signal converted to an IF frequency, a difference Phase shift network that moves dynamically and rotates the phase with a phase difference of 90 degrees (P
It includes SN (Phase Shift Network) blocks 15 and 18, an adder 19 for adding two orthogonal systems, a BPF 20 for band limiting, and a LIM AMP 21 for amplifying and outputting a band limited signal.

The received signal amplified by the RF AMP 11 shown in FIG. 1 is divided into two in-phase. One of the two in-phase divided signals is multiplied by the first local signal made by the VCO 12 by the mixer circuit 13, and the other is divided by the second local signal having a phase orthogonal to the first local signal made by the VCO 12. Is multiplied by the local signal of and is converted into an IF frequency. Mixer circuit 1
The IF signal converted in 3 is amplified by the IF AMP 14, the phase thereof is rotated by the PSN block 15 with a phase difference of 90 degrees, and the IF signal is input to the adder 19. On the other hand, the IF signal converted by the mixer circuit 16 is amplified by the IF AMP 17, the phase is rotated by the PSN block 18 with a phase difference of 90 degrees, and the IF signal is input to the adder 19.

Next, looking at the input section of the adder 19, the IF signal from the mixer circuit 13 and the IF signal from the mixer circuit 13 are different due to the difference between the desired frequency band and the image frequency band of the received signals input to the mixer circuits 13 and 16. The IF signal from the mixer circuit 16 becomes an in-phase signal in the IF signal frequency-converted from the desired frequency band, and becomes an anti-phase signal in the IF signal converted from the image frequency band. Therefore, the IF signal converted from the desired frequency band is output at the output added by the adder 19, but the signals in the image frequency band differ in phase by 180 degrees in total and cancel each other out. Suppressed and eliminated.

After that, the IF signal from which the signal in the image frequency band is removed is band-limited by the BPF 20 and LIM.
It is amplified by AMP21 and output.

FIG. 2 is a diagram showing the configuration of the PSN blocks 15 and 18. The PSN blocks 15 and 18 are shown in FIG.
, Multiple phase shift networks (P
A block is composed of an (SN) circuit. In FIG. 2, four PSN circuits PSN1 to PSN4 are connected in cascade. The PSN blocks 15 and 18 may have one PSN circuit instead of a plurality of stages, but the width of the band that can be handled by increasing the number of stages with respect to the band of the reception signal used in the receiving device. It is possible to spread. In the present embodiment, in PSN1 to PSN4 shown in FIG.
The band that can be handled is widened by shifting the band handled by each one and gradually changing the frequency that it handles.

Next, a PSN circuit to which this embodiment is applied will be described. FIG. 3 is a diagram for explaining the first example of the PSN circuit to which the present embodiment is applied. In the circuit shown in FIG. 3, the input signal V2 is input from the differential input terminals IN and INX. The input signal is input to the transistor Q3, the current I1, and the buffer amplifier of the transistor Q6 and the current I4 which are in a differential relationship. A resistor R6 and a capacitor C2, which are phase shift elements that determine the amount of phase shift, and a resistor R10 and a capacitor C3, which are phase shift elements on the differential side, are connected between the outputs of the buffer amplifier in the opposite phase relationship. This phase-shifted signal is transferred to the transistor Q4, the transistor Q5, the resistor R7,
The necessary amount is amplified by an amplifier composed of the resistor R8, the resistor R9, the current I2, and the current I3, and the differential output terminals OUT and OUT.
It is output as a differential signal at X. The capacitors C2 and C3, and the resistors R6 and R10 have the same value.

In the PSN circuit shown in FIG. 3, all of the input section, the buffer amplifier, the phase shift element, and the amplifier operate differentially. Therefore, even if an unnecessary signal is added from the power supply and the GND, the operation is performed in a state in which the output is less affected by the common mode rejection of the amplifier section.

Further, in the PSN circuit shown in FIG.
By extracting the negative-phase signal input to the phase-shift element from the negative-phase side buffer amplifier (point P, point Q) of the differential signal, there is a problem in the conventional PSN circuit (Fig. 8) The problem of output impedance is solved. That is, FIG.
In the PSN circuit shown in, the signal on the opposite phase side is output to the collectors of the transistors Q3 and Q6 as shown in FIG.
It is not taken from the (C) side, but from the in-phase side of the differential signal, in other words, from the emitter (E) side, which has an opposite phase relationship to each other, so that noise from the power supply and GND side is hard to get on. . That is, the output of the same phase as the input of the amplifier circuit is taken out from the emitter (E) of the transistor Q3, and the output of the opposite phase is taken out from the point P which is the emitter (E) side of the transistor Q6. On the other hand, on the differential signal side, first, the output in phase with the input (opposite phase when viewed from the input of the amplifier circuit) is taken out from the emitter (E) of the transistor Q6, and the output of opposite phase is the emitter of the transistor Q3. Q on the (E) side
Taken out from a point.

As described above, in the PSN circuit shown in FIG.
Transistor Q whose output impedance is a buffer amplifier
3. Since it is determined by the emitter resistance re of the transistor Q6, it becomes possible to determine the output impedance only by the current flowing through these transistors Q3, Q6. Therefore, in FIG. 8 which is a conventional technique, it is necessary to consider the signal amplitude and the output impedance, but according to the present embodiment, such consideration is not necessary, and a design with low current consumption is possible.

In the circuit of FIG. 3, the output is obtained from the collector side of the transistors Q4 and Q5. Although it is possible to obtain the output from the emitter side of the transistors Q4 and Q5, it is preferable to obtain the output from the collector side through the transistors Q4 and Q5 in order to adjust when the gain drops.

FIG. 4 is a diagram showing an example of a phase characteristic that can be realized when the PSN blocks 15 and 18 composed of the 4-stage PSN circuit shown in FIG. 2 are used. In FIG. 4, the horizontal axis represents frequency (Hz) and the vertical axis represents phase (deg), and the four-stage PSN circuit makes it possible to handle four bands. That is, in FIG. 4, the adder 19 shown in FIG.
Characteristics of signals in the image frequency band input to the camera
(Difference between PSN block 15 and PSN block 18) is shown, and the phase of the image signal to be canceled is shown. The signal of the image frequency band to be added is about 1 in the intermediate frequency range of about 30 KHz to about 10 MHz.
When it is 80 degrees and the phase is exactly 180 degrees (when crossing the 180 degree line), the image signal is canceled. However, depending on the circuit characteristics, 1
Since some of the characteristics are slightly deviated from 80 degrees, some remain without being canceled.

FIG. 5 is a diagram showing an example of gain characteristics of the PSN circuit, where the vertical axis represents the amount of attenuation (dB) and the horizontal axis represents the frequency (Hz).
Is. Here, the image signal gain is shown together with the desired signal gain. In this example, the image signal changes with frequency up to about −40 dB to slightly less than −70 dB. The attenuation amount of the image signal is determined by the deviation amount from 180 degrees and the deviation amount of the gain in the phase characteristic shown in FIG.

Next, a modification of the PSN circuit will be described. FIG. 6 is a diagram showing a first modification of the PSN circuit shown in FIG. Similar to FIG. 3, the configuration is such that it operates differentially, the jumping of unnecessary signals from the power supply and GND is improved, and points that are strong against disturbance are the same as in the PSN circuit of FIG. The extraction of the negative phase is similar to that of the conventional technique shown in FIG. 8, and the negative phase signal is extracted from the collector side of the transistors Q7 and Q10 in the input section. In the configuration of FIG. 6, the power supply voltage is large because the emitter sides of the transistors Q7 and Q10 need to be made of resistors without using a current source and have the same gain as the opposite phase side. The PSN circuit of FIG. 3 is more convenient when determining the operating conditions of a circuit such as a moving circuit.

FIG. 7 is a diagram showing a second modification of the PSN circuit shown in FIG. In the PSN circuit shown in FIG. 7, the number of capacitors and resistors of the phase shift element is reduced to half, while the output has a differential form. When the number of phase shift elements increases, it may be disadvantageous in area when integrated. However, according to this second modified example, the transfer element may be two elements of the resistor R20 and the capacitor C6, and
It is possible to reduce the circuit scale of the PSN circuit that covers the low frequency region. In the second modification shown in FIG. 7, the output in phase with the input of the amplifier circuit is taken out from the emitter (E) of the transistor Q11, and the output in reverse phase is from the point R on the emitter (E) side of the transistor Q13. It has been taken out. Therefore, similarly to FIG. 3, the output impedance of the negative phase signal can be set low, and the power consumption can be set low. However, since the transistor Q12 and the resistor R22, which are the output stage, do not have a differential configuration, they are more easily affected by the power supply and GND than the PSN circuit shown in FIGS.

As described above, according to the present embodiment, the GP
In the PSN circuit used in the receiving system such as S, by operating with a differential signal, it is difficult to receive an unnecessary signal from the power supply and the GND, and it is possible to realize the high sensitivity particularly required in the receiving device. Further, by extracting the negative phase signal from the negative phase side of the differential signal, the output impedance of the negative phase signal can be set low, and the power consumption can be reduced.

In the present embodiment, the PSN circuit used in the receiving system such as GPS has been described, but the present invention can be applied to other communication devices handling weak signals. For example, in voice processing such as a wiretapping prevention system for a cordless telephone, it is possible to reduce the influence of disturbance by using the PSN circuit operated by the differential signal according to the present embodiment.

[0034]

As described above, according to the present invention,
It is possible to provide a receiving device that realizes a highly sensitive receiving circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a receiving apparatus to which this embodiment is applied.

FIG. 2 is a diagram showing a configuration of a PSN block.

FIG. 3 is a first PSN circuit to which the present embodiment is applied.
FIG. 7 is a diagram for explaining an example of FIG.

FIG. 4 is a diagram showing an example of phase characteristics that can be realized when a PSN block including a 4-stage PSN circuit is used.

FIG. 5 is a diagram showing an example of gain characteristics of a PSN circuit.

6 is a diagram showing a first modification of the PSN circuit shown in FIG.

7 is a diagram showing a second modification of the PSN circuit shown in FIG.

FIG. 8 is a PS that has been conventionally adopted in a general phase shifter.
It is the figure which showed the circuit structure of N circuit.

[Explanation of symbols]

11 ... High frequency amplifier (RF AMP), 12 ... Voltage controlled oscillator (VCO), 13 ... Mixer circuit, 14 ... IF AM
P, 15 ... Phase shift network (PSN) block, 16 ... Mixer circuit, 17 ... IF AMP, 18 ... Phase shift network (PSN) block, 19 ... Adder, 20 ... BPF, 21 ... LIM AMP

Claims (11)

[Claims] 1. A first frequency and a second frequency which are in an orthogonal relationship.
A voltage-controlled oscillator that outputs the frequency, a first mixer circuit that mixes one of the distributed received signals and the first frequency that is output from the voltage-controlled oscillator, and the other received signal that is distributed. A second mixer circuit for mixing with the second frequency output from the voltage controlled oscillator; and a first phase shift for rotating the phase with a phase difference of 90 degrees with respect to the output from the first mixer circuit. A network block, a second phase shift network block that rotates a phase with a phase difference of 90 degrees with respect to an output from the second mixer circuit, an output from the first phase shift network block, and a second phase shift network block. An adder for adding the output from the phase shift network block, and the first phase shift network block and The phase-shift network circuits constituting the second phase shift network block, receiving apparatus characterized by operating in a differential signal. 2. The first phase shift network block and the second phase shift network block each include a plurality of phase shift network circuits, and the plurality of phase shift network circuits operate with differential signals. Claim 1 characterized by the above-mentioned.
The receiver described. 3. The receiving device according to claim 2, wherein the phase shift network circuit extracts the reverse phase signal from the in-phase side of the differential signal. 4. The received signal mixed by the first mixer circuit and the second mixer circuit is GP.
The receiving apparatus according to claim 1, wherein the receiving apparatus is an S (Global Positioning Systems) signal. 5. A first input signal and a second differential side.
A differential input terminal for inputting the input signal, a first buffer amplifier for inputting the first input signal input to the differential input terminal, and a second buffer input for the differential input terminal A second buffer amplifier which inputs an input signal; and a phase shift element which is an element for determining a phase shift amount when the in-phase signal with respect to the first input signal is input from the first buffer amplifier, The phase shift network circuit, wherein the phase shift element receives a negative phase signal from the second buffer amplifier. 6. The second buffer amplifier to the second buffer amplifier
A signal having the same phase as that of the input signal is input, and the differential-side phase-shifting element is an element for determining the amount of phase shift. 6. The phase shift network circuit according to claim 5, wherein the signal is input from the first buffer amplifier. 7. A phase shift network circuit, in which a received signal and a frequency output from a voltage controlled oscillator rotate a phase with respect to a mixed IF signal to shift a phase, wherein a phase shift network circuit is provided for the in-phase signal of the IF signal. Phase shifter comprising: first output means for outputting a phase-shifted signal and second output means for outputting a phase-shifted signal with respect to the differential signal of the IF signal. Network circuit. 8. The phase shift network circuit according to claim 7, wherein the first output means extracts a reverse phase signal for the phase shift element from the in-phase side of the differential signal. 9. The phase shift network circuit according to claim 7, wherein the second output means extracts a reverse phase signal for the phase shift element from the same phase side of the common mode signal. 10. Outputting two frequencies that are in an orthogonal relationship, mixing each of the distributed received signals with the two frequencies that are output, converting to an IF frequency, and converting to an IF signal converted to an IF frequency. 90 for each
Is a method of rotating a phase with a phase difference of 1 degree to output a phase shift signal, and adding the output phase shift signals to suppress an image signal. An image rejection method characterized in that they are related signals. 11. The IF for outputting the phase shift signal
11. The image rejection method according to claim 10, wherein an out-of-phase signal with respect to the signal is extracted from the in-phase side of the differential signal to generate the phase-shifted signal.