JP2006314029A - Semiconductor integrated circuit device for radio communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To sharply improve an interference wave characteristic by adjusting a differential signal (True/Bar) route in a mixer circuit. <P>SOLUTION: Transistors Tr1-Tr3, Tr4-Tr6 in a load capacity control part LC in the mixer circuit 3a are turned on/off by control signals output from a decoding circuit DEC 1. The capacitance values of all capacitance elements C1-C8 are the same, and when the number of transistors to be turned on is increased, an output load capacity value is increased. For instance when all the transistors Tr1-Tr3 of the True side are turned on, the output load capacity value becomes a value obtained by combining the capacitance values of the capacitance elements C1-C4. When the output load capacity value is varied by turning on optional transistors out of the transistors Tr1-Tr6 and the mixer circuit 3a is set to a balanced state, an AM-suppression characteristic is improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a radio signal transmission / reception technique, and more particularly to a technique that is effective when applied to an improvement in the interference wave characteristics of a mixer in a direct conversion cellular phone or the like.

  In recent years, mobile phones have become widespread as one type of mobile communication, and diversity is required for their functions. For example, a high-frequency processing module used for a mobile phone has a very strong demand for downsizing.

  For example, as a technique for realizing miniaturization of a high-frequency processing module, a radio frequency band (RF: Radio Frequency) is set to a frequency band of a baseband signal (or a frequency band of an audio band) with a single-stage mixer without passing through an intermediate frequency. ) Is a direct conversion method.

  With this direct conversion method, it is possible to reduce intermediate frequency stage mixers and associated external components such as filters and matching as in the so-called superheterodyne method.

  At the time of reception by the high-frequency processing module, the signal received by the antenna is amplified by a LNA (Low Noise Amplifier), then frequency-converted by a direct conversion mixer, and amplified to an arbitrary output level by a PGA (Programmable Gain Amplifier) unit And output to the subsequent baseband section.

  In the direct conversion mixer, the output from the mixer to the output of the PGA part is DC coupled. When the antenna input level is small, the gain of the PGA unit is increased in order to output a signal of a desired level in the baseband unit, so that even a slight DC fluctuation of the mixer output serving as the PGA input is amplified by the PGA unit. Will end up.

  Therefore, in order to cause reception sensitivity deterioration due to DC fluctuation of the PGA output, it is necessary to minimize the DC fluctuation of the mixer output.

  Since the direct conversion mixer and the PGA circuit in the subsequent stage are differential circuits, a mixer circuit that perfectly balances manufacturing variations of elements such as transistors and resistors, wiring impedance, and parasitic capacitance (hereinafter referred to as balanced state) If a DC offset occurs in the same direction and viewed differentially, the DC offset between the differentials disappears and there is no problem.

  For this purpose, the layout of the pair of elements in the mixer, the impedance of the wiring, etc. is performed so as to prevent imbalance between the I signal / Q signal and True / Bar as much as possible.

  However, the present inventor has found that the signal conversion technique using the direct conversion method as described above has the following problems.

  That is, if the direct conversion mixer is a circuit in a perfectly balanced state as described above, even if a DC offset occurs, it is canceled when viewed in a differential manner, and the DC offset disappears.

  Improvements due to layout are almost limited due to restrictions such as chip size reduction, and external factors due to signal jumps are one of the causes of deterioration. There is a problem that the DC offset cannot be completely canceled.

  An object of the present invention is to provide a technique capable of greatly improving the interference wave characteristics by adjusting a differential signal (True / Bar) path in a mixer circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor integrated circuit device of the present invention has a mixer including a Gilbert cell circuit that demodulates a received signal and converts it into a baseband signal, and the mixer arbitrarily adjusts the characteristics of the differential signal path in the output section. A characteristic control unit is provided.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the semiconductor integrated circuit device of the present invention, the characteristic control unit outputs a control to the variable capacitance unit based on the setting signal and a variable capacitance unit that arbitrarily changes the load capacitance at the output of the mixer based on the control signal. And a capacity control unit.

  In the semiconductor integrated circuit device of the present invention, the variable capacitance section includes a plurality of first capacitance elements in which one connection section is connected to the first output section of the mixer, and the first output of the mixer. A plurality of second capacitance elements having one connection portion connected to the portion, and the other connection in any of the first and second capacitance elements based on a control signal output from the capacitance control portion And a switching unit for connecting each unit to a reference potential.

  Furthermore, in the semiconductor integrated circuit device of the present invention, the characteristic control unit controls the variable resistance unit that arbitrarily changes the bias resistance value in the mixer based on the control signal and the variable resistance unit based on the setting signal. And a resistance control unit that outputs.

  In the semiconductor integrated circuit device according to the present invention, the variable resistance portion is connected to the control terminal of the upper transistor of the Gilbert cell circuit in which one connection portion is connected to the first output portion of the mixer, and the other connection A plurality of first bias resistors connected to the bias circuit, one connected to the control terminal of the upper transistor of the Gilbert cell circuit connected to the second output of the mixer, A switch that controls conduction of any of the first and second bias resistors based on a plurality of second bias resistors whose connection units are connected to the bias circuit and a control signal output from the resistance control unit It consists of parts.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since the characteristic control unit can arbitrarily adjust the characteristic of the differential signal path at the output part of the mixer, the interference wave characteristic can be greatly improved.

  (2) Due to the above (1), it is possible to improve the reception sensitivity of the received signal, and the performance of a communication system such as a mobile phone can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram illustrating an example of a reception system circuit in an RF processing unit according to an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating an example of a mixer circuit provided in the RF processing unit of FIG. 3 is an explanatory diagram illustrating an example of the generation principle of AM-suppression, FIG. 4 is an explanatory diagram illustrating an example of another generation principle of AM-suppression, and FIG. 5 is a balanced state of the mixer circuit of FIG. It is explanatory drawing which shows the simulation result at the time of operating a load capacity control part when it is not in a balance state.

  In the present embodiment, the RF processing unit (semiconductor integrated circuit device) 1 is provided in a communication system such as a mobile phone, for example, and demodulates a reception signal or modulates a transmission signal. As shown in FIG. 1, the reception system circuit in the RF processing unit 1 includes a low noise amplifier (LNA) 2, a mixer unit 3, a PGA unit 4, a signal generation unit 5, and the like.

  Although not particularly limited, the RF processing unit 1 is configured to be able to modulate and demodulate signals using, for example, a GSM (Global System for Mobile Communication) communication method.

  The low noise amplifier 2 is an amplifier that amplifies the received signal. The mixer unit 3 is composed of mixer circuits (mixers) 3a and 3b, and combines the received signal amplified by the low noise amplifier 2 with the RF local signal frequency-divided by the signal generating unit 5, thereby converting the I signal / Q signal, respectively. A demodulation circuit for demodulating.

  The PGA unit 4 includes low-pass filters LPF1 to LPF6, gain control amplifiers PGA1 to PGA6, amplifiers AMP1 and AMP2, and a DC offset cancel circuit DOC.

  The low-pass filters LPF1 to LPF3 and the gain control amplifiers PGA1 to PGA3 are alternately connected in series, and an amplifier AMP1 having a fixed gain is connected to the final stage. Output to the band circuit.

  The low pass filters LPF4 to LPF6 and the gain control amplifiers PGA4 to PGA6 are also connected in series with each other, and the amplifier AMP2 having a fixed gain is connected to the final stage, thereby amplifying the Q signal. Then, output to the baseband circuit (not shown). The DC offset cancel circuit DOC cancels the DC offset in the outputs of the amplifiers AMP1 and AMP2.

  The signal generator 5 divides the high-frequency signal generated by the high-frequency oscillation circuit (RFVCO) and outputs it as an RF local signal to the mixer circuits 3a and 3b.

  FIG. 2 is a circuit diagram showing an example of the mixer circuit 3a (3b).

  The mixer circuit 3a (, 3b) includes transistors T1 to T6, resistors R1 to R5, a load capacitance control unit (characteristic control unit) LC, bias circuits Ba1 and Ba2, and the like, and a Gilbert cell circuit is configured by the transistors T1 to T6. Has been.

  In this Gilbert cell circuit, the upper stage is constituted by transistors T1 to T4, and the lower stage is constituted by transistors T5 and T6.

  The collectors of the transistors T1 and T3 and the collectors of the transistors T2 and T4 serve as an output unit of the mixer circuit 3a (3b) and are DC-coupled (direct coupling) to the PGA unit 4.

  The RF local signals output from the signal generator 5 are connected to the bases of the transistors T1 to T4, respectively. The amplified signals output from the low noise amplifier 2 are connected to the bases of the transistors T5 and T6. Each is connected to input.

  The bias circuit Ba1 is connected to the bases of the transistors T1 to T4, respectively, and supplies a bias voltage to the transistors T1 to T4. The bias circuit Ba2 is connected to the bases of the transistors T5 and T6, and supplies a bias voltage to the transistors T5 and T6.

  The load capacitance control unit LC includes transistors (variable capacitance units, switching units) Tr1 to Tr6, capacitance elements C1 to C8, and a decode circuit (capacitance control unit) DEC1.

  One output part (True) of the mixer circuit 3a (, 3b) is connected in parallel to one connection part of the capacitance elements (variable capacitance part, first capacitance element) C1 to C4. The other output section (Bar) of the mixer circuit 3a (, 3b) is connected in parallel to one connection section of the capacitance elements (variable capacitance section, second capacitance element) C5 to C8.

  One connection portion of the transistors Tr1 to Tr3 is connected to the other connection portion of the capacitance elements C1 to C3, and the other connection portion of the capacitance elements C5 to C7 is connected to the transistors Tr4 to Tr6. Are connected to each other.

  The reference potential VSS is connected to the other connection portion of the transistors Tr1 to Tr6 and the other connection portion of the capacitive elements C4 and C8. The control signals output from the decode circuit DEC1 are connected to the gates of the transistors Tr1 to Tr6, respectively.

  For example, the decode circuit DEC1 decodes a control bit stored in a register or the like provided in the RF processing unit 1 to generate a control signal, and controls the operation of the transistors Tr1 to Tr6.

  The transistors Tr1 to Tr6 perform an ON / OFF operation based on the control signal output from the decode circuit DEC1, and arbitrarily change the load capacitance.

  Next, the operation of the mixer circuit 3a (3b) in the present embodiment will be described.

  First, the operation of the load capacity control unit LC in the mixer circuit 3a (, 3b) will be described with reference to FIG.

  The transistors Tr1 to Tr3 and Tr4 to Tr6 are turned on / off by a control signal output from the decode circuit DEC1. The electrostatic capacitance elements C1 to C8 all have the same electrostatic capacitance value, and the output load capacitance value increases as the number of ON transistors increases.

  However, the capacitance values of the capacitance elements C1 to C8 need not all be the same, and for example, weighting such as N times or N times 2 (N is a natural number) based on C1 may be performed. . By weighting, it is possible to adjust the load capacity in a wider range compared to the case where the same number of capacitances as described above are installed.

  For example, when all the transistors Tr1 to Tr3 on the True (first output unit) side are turned on, the output load capacitance value is a combination of the capacitance values of the capacitance elements C1 to C4. Further, ON / OFF control of the transistors Tr1 to Tr3 on the True side and the transistors Tr4 to Tr6 on the Bar (second output unit) side can be performed independently.

  Next, the interference wave characteristic (AM-suppression characteristic) will be described.

  The AM-suppression characteristic indicates a DC fluctuation characteristic when an interference wave other than the desired wave is input.

  FIG. 3 is an explanatory diagram showing the principle of generation of AM-suppression.

  From the upper side to the lower side of FIG. 3, the high frequency signal (RF input) output from the low noise amplifier 2, the RF local signal (RF Local) output from the signal generator 5, and the mixer circuit 3a (3b) are output. The spectrum of the demodulated signal (MIX output) is shown.

  As shown in the figure, when an interference wave is input to the RF input, distortion occurs in the mixer circuit 3a (3b), and a harmonic component is generated. This distortion increases as the input level of the interference wave increases, and the harmonic component increases accordingly. At this time, the harmonic of the RF Local signal and the harmonic component of the desired wave are mixed, and MIX Appears as a DC offset in the output.

  Another cause of AM-suppression is self-mixing.

  In this case, as shown in FIG. 4, the interference wave itself input to the low noise amplifier 2 or the interference wave amplified by the low noise amplifier 2, the mixer circuit 3a (3b, etc.) jumps to the RF Local side and is mixed. As a result, a DC offset occurs.

  Therefore, in the mixer circuit 3a (, 3b), any of the transistors Tr1 to Tr6 is turned on based on a control signal output from the decoding circuit DEC of the load capacitance control unit LC, and the output load capacitance value is varied. The circuit 3a (3b) is set to be in a balanced state, and the AM-suppression characteristic is improved.

  FIG. 5 is an explanatory diagram showing a simulation result when the load capacity control unit LC is operated when the mixer circuit 3a is in the balanced state and not in the balanced state.

  In the simulation, since the AM-suppression characteristic cannot be evaluated, the evaluation is performed using the secondary input intercept point (IIP2) that is correlated with the AM-suppression characteristic.

  In FIG. 5, the vertical axis represents IIP2, and the horizontal axis represents the change in the output load capacity value. On the horizontal axis, the difference between the True load output capacity value and the Bar output load capacity value of the mixer circuit 3a increases as the number increases from X axis = 0 to the right side (X axis = 1-3). It shows that it will go.

  For example, when the X axis = 0, the difference between the load capacity values on the True side / Bar side is the smallest, that is, the load capacity values on the True side / Bar side need only be the same. All transistors Tr1 to Tr3 and all transistors Tr4 to Tr6 on the Bar side are in an OFF state, or transistors Tr1 and Tr4, transistors Tr1 to Tr2, transistors Tr4 to Tr5, transistors Tr1 to Tr3, and transistor Tr4 Any state may be used as long as it is turned on by a combination of .about.Tr6.

  In the case of X axis = 1, the transistor Tr1 to which the True capacitance element C1 in the mixer circuit 3a is connected is ON, and all the Bar transistors Tr4 to Tr6 are OFF. Yes. Thereby, the difference between the load capacity values on the True side / Bar side is, for example, about apF, and the load capacity value on the True side is set to be one step larger than the load capacity value on the Bar side.

  In this case, the ON / OFF combination of the transistors Tr1 to Tr6 is other than this, as long as the load capacity value on the True side can be set so that the difference between the load capacity values on the True side / Bar side becomes apF. Also good.

  Further, when the X axis = 2, the transistors M1 and M2 to which the capacitance element C1 on the True side and the capacitance element C2 in the mixer circuit 3a are connected are turned on, and all the transistors Tr4 to Tr6 on the Bar side are turned on. It shows a state of being turned off. Thereby, the difference between the load capacity values on the True side / Bar side is, for example, about 2 apF, and the load capacity value on the True side is set to be two steps larger than the load capacity value on the Bar side.

  In this case, the ON / OFF combination of the transistors Tr1 to Tr6 is other than this if the load capacity value on the True side can be set to be large so that the difference between the load capacity values on the True side / Bar side is 2apF. Also good.

  When the X axis = 3, all the transistors Tr1 to Tr3 on the True side to which the capacitance elements C1 to C3 on the True side in the mixer circuit 3a are connected are turned on, and all the transistors Tr4 to Tr6 on the Bar side are turned off. It shows the state. Thereby, the difference between the load capacity values on the True side / Bar side is, for example, about 3 apF, and the load capacity value on the True side is set to be 3 steps larger than the load capacity value on the Bar side.

  When the X axis is −3, all the transistors Tr1 to Tr3 on the True side in the mixer circuit 3a are OFF, and all the transistors Tr4 to the Bar side to which the Bar side capacitance elements C4 to C6 are connected are connected. The state where Tr6 is ON is shown. As a result, the difference between the load capacity values on the True side and the Bar side is, for example, about 3 apF, and the Bar side load capacity value is set to be three steps larger than the True side load capacity value.

  Furthermore, in the figure, the dotted line indicates the IIP2 characteristic in the mixer circuit 3a in the balanced state, and the solid line indicates the mixer circuit when the output load capacitance value is varied by the load capacitance control unit LC in the mixer circuit 3a that is not in the balanced state. The IIP2 characteristic of 3a is shown.

  As indicated by the dotted line, the mixer circuit 3a in a balanced state has the best IIP2 characteristics when the output load capacitance value is not changed to either the True side or the Bar side (X axis = 0). It can be seen that the IIP2 characteristics deteriorate even if the capacitance value is changed to either the True side or the Bar side (not in a balanced state).

  On the other hand, in the case of the mixer circuit 3a that is not in a balanced state, the IIP2 characteristic is degraded when the output load capacitance value is not changed to either the True side or the Bar side (X axis = 0) as indicated by the solid line.

  By changing the output load capacitance value of the deteriorated IIP2 characteristic by the load capacitance control unit LC, the mixer circuit 3a is set in a balanced state, and the IIP2 characteristic is improved. In FIG. 5, when the output load capacity value on the True side is increased by one step (X axis = 1), the IIP2 characteristic is the most, and the difference between the True side and the Bar side of the output load capacity value is More or less (X axis = −3 to 0, 2, 3), the IIP2 characteristics are degraded.

  Therefore, only the transistor Tr1 of the load capacitance control unit LC is turned on to increase the output load capacitance value by one step (X axis = 1), and the other transistors Tr2 to Tr6 are controlled to be turned off. The IIP2 characteristic in 3a, that is, the AM-suppression characteristic can be improved.

  Thus, according to the present embodiment, the load capacity control unit LC can adjust the output load capacity value so that the mixer circuits 3a and 3b are in a balanced state. Therefore, the AM− of the mixer circuits 3a and 3b can be adjusted. The suppression characteristics can be greatly improved.

  In the present embodiment, the technique of adjusting the output load capacitance value by the load capacitance control unit LC is described. For example, a connection is made between the gates of the upper transistors T1 to T4 constituting the Gilbert cell circuit and the bias circuit Ba1. By changing the resistance value of the bias resistor, the operating point of the mixer circuit 3a may be balanced to improve the AM-suppression characteristic.

  In this case, the mixer circuit 3a (3b) includes transistors T1 to T6, resistors R1 to R5, a bias resistance control unit (characteristic control unit) BC, and bias circuits Ba1 and Ba2, as shown in FIG. Yes. The bias resistance control unit BC is connected between the bias circuit Ba1 and the bases of the transistors T1 to T4, and other circuit configurations are the same as those in FIG.

  The bias resistance control unit BC includes switches (variable resistance units, switch units) SW1 to SW8, resistors Rb1 to Rb8, and a decode circuit (resistance control unit) DEC2. The bases of the transistors T1 and T4 are respectively connected to one connection portion of the resistors (variable resistor portion, first bias resistor) Rb1 to Rb4, and the resistors (variable resistor portion, second bias resistor) are connected. The bases of the transistors T2 and T3 are connected to one connection portion of Rb5 to Rb8, respectively.

  One connection portion of the switches SW1 to SW8 is connected to the other connection portion of the resistors Rb1 to Rb8, and the output portion of the bias circuit Ba1 is connected to the other connection portion of the switches SW1 to SW8. Has been.

  The control terminals of the switches SW1 to SW8 are connected so that the control signal output from the decode circuit DEC2 is input. The switches SW1 to SW8 are connected to the control signal output from the decode circuit DEC2. Based on this, an ON (conduction) / OFF (non-communication) operation is performed.

  For example, the decode circuit DEC2 decodes a control bit stored in a register or the like provided in the RF processing unit 1, generates a control signal, and controls the operation of the switches SW1 to SW8.

  The resistances Rb1 to Rb4 on the True side have different resistance values, and the resistance values satisfy Rb1 <Rb2 <Rb3 <Rb4. Similarly, the Bar-side resistors Rb5 to Rb8 have different resistance values, and the resistance values are Rb5 <Rb6 <Rb7 <Rb8.

  The resistors Rb1 and Rb5, the resistors Rb2 and Rb6, the resistors Rb3 and Rb7, and the resistors Rb4 and Rb8 have the same resistance value. The bias resistance value is adjusted by independently controlling the switches SW1 to SW4 and the switches SW5 to SW8.

  For example, when the bias resistance value on the True side is maximized, the bias resistance value is maximized by controlling so that only the switch SW4 is turned on.

  FIG. 7 is an explanatory diagram illustrating a simulation result when the bias resistance control unit BC is operated when the mixer circuit 3a is in the balanced state and is not in the balanced state.

  Also in this case, since the AM-suppression characteristic cannot be evaluated in the simulation, the evaluation is performed by the secondary input intercept point (IIP2) correlated with the AM-suppression characteristic.

  In FIG. 7, the vertical axis represents IIP2, and the horizontal axis represents the change in the bias resistance value. In the horizontal axis, the difference between the True side bias resistance value and the Bar side bias resistance value of the mixer circuit 3a increases as the number increases from the X axis = 0 to the right side (X axis = 1-3). Show.

  For example, when the X axis = 0, the switch SW4 to which the resistor Rb4 having the largest bias resistance value on the True side in the mixer circuit 3a is connected and the resistor Rb8 having the largest bias resistance value on the Bar side are connected. The switch SW8 is turned on. Therefore, the difference in bias resistance value between the True side and the Bar side is about 0Ω.

  In this case, the bias resistance values on the True side and the Bar side need only be the same, so that either the switch SW1 and the switch SW5, the switch SW2 and the switch SW6, or the switch SW3 and the switch SW7 are on. That's fine.

  When the X axis = 1, the switch SW2 to which the resistor Rb2 having the second smallest bias resistance value is connected on the True side in the mixer circuit 3a and the resistor Rb5 having the smallest bias resistance value on the Bar side are connected. This shows a state in which the switch SW5 is turned on. As a result, the difference in bias resistance value between the True side and the Bar side is, for example, about aΩ, and the True side bias resistance value is set to be one step larger than the Bar side bias resistance value.

  In this case, as long as the bias resistance value on the True side can be set so that the difference between the bias resistance values on the True side / Bar side becomes aΩ, the ON / OFF combination of the switches SW1 to SW8 is not limited to this. Good.

  Further, in the case of X axis = 2, the switch SW3 connected to the third resistor Rb3 having the smallest bias resistance value on the True side in the mixer circuit 3a and the resistor Rb5 having the smallest bias resistance value on the Bar side are connected. This shows a state in which the switch SW5 is turned on.

  Thus, the difference between the bias resistance values on the True side / Bar side is, for example, about 2 aΩ, and the bias resistance value on the True side is set to be two steps larger than the bias resistance value on the Bar side.

  In this case, if the bias resistance value on the True side can be set to be large so that the difference between the bias resistance values on the True side / Bar side is 2 aΩ, the ON / OFF combination of the switches SW1 to SW8 is not limited to this. Good.

  When the X axis = 3, the switch SW4 to which the resistor Rb4 having the largest bias resistance value on the True side in the mixer circuit 3a is connected is ON, and the resistor Rb5 having the smallest bias resistance value on the Bar side is turned on. The state where the connected switch SW4 is ON is shown.

  Thus, the difference between the bias resistance values on the True side / Bar side is, for example, about 3 aΩ, and the bias resistance value on the True side is set to be three steps larger than the bias resistance value on the Bar side.

  When the X axis is −3, the switch SW1 to which the resistor Rb1 having the smallest bias resistance value on the True side is connected is ON, and the resistor Rb8 having the largest bias resistance value on the Bar side is connected. This shows a state where the switch SW8 being turned on is ON.

  Thus, the difference between the bias resistance values on the True side / Bar side is, for example, about 3 aΩ, and the bias resistance value on the Bar side is set to be three steps larger than the bias resistance value on the True side.

  However, the difference in the bias resistance value shows a case where it changes by an integral multiple every time one step is changed with respect to X axis = 0. For example, weighting such as 2 times N (N is a natural number) is performed. May be. By weighting, it is possible to adjust the bias resistance in a wider range compared to the case where the same number of bias resistors as described above are installed.

  In FIG. 7, the dotted line indicates the IIP2 characteristic in the mixer circuit 3a in the balanced state, and the solid line indicates the mixer circuit 3a when the bias resistance value is varied by the bias resistance control unit BC in the mixer circuit 3a that is not in the balanced state. IIP2 characteristics are shown.

  As shown by the dotted line, in the mixer circuit 3a in the balanced state, the IIP2 characteristic is the best when the bias resistance value is not changed to either the True side or the Bar side (X axis = 0). It can be seen that the IIP2 characteristics deteriorate even if the value is changed to either the True side or the Bar side (not in a balanced state).

  On the other hand, in the mixer circuit 3a that is not in the balanced state, the IIP2 characteristic is degraded when the bias resistance value is not changed to either the True side or the Bar side (X axis = 0) as indicated by the solid line.

  By changing the bias resistance value of the deteriorated IIP2 characteristic by the bias resistance control unit BC and setting the mixer circuit 3a in a balanced state, the IIP2 characteristic is improved.

  In FIG. 7, when the bias resistance value on the True side is increased by one step (X axis = 1), the IIP2 characteristic is the most, and the difference between the True side and the Bar side of the bias resistance value is more than that. Or less (X axis = −3 to 0, 2, 3), the IIP2 characteristics are degraded.

  Therefore, the IIP2 characteristic in the mixer circuit 3a, that is, the AM-suppression characteristic can be improved by turning on the switches SW2 and SW5 of the bias resistance control unit BC and increasing the bias resistance value by one step (X axis = 1).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for improving the AM-suppression characteristics of a mixer in a direct conversion system.

It is a block diagram which shows an example of the receiving system circuit in the RF process part by one embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of a mixer circuit provided in the RF processing unit of FIG. 1. It is explanatory drawing which showed an example of the generation principle of AM-Suppression. It is explanatory drawing which showed the example of the other generation | occurrence | production principle of AM-Suppression. It is explanatory drawing which shows the simulation result at the time of operating a load capacity | capacitance control part when the mixer circuit of FIG. 2 is not a balance state and a balance state. It is the circuit diagram which showed an example of the mixer circuit provided in the RF process part by one embodiment of this invention. It is explanatory drawing which shows the simulation result at the time of operating a load capacity | capacitance control part when the mixer circuit of FIG. 6 is not a balance state and a balance state.

Explanation of symbols

1 RF processing unit (semiconductor integrated circuit device)
2 Low noise amplifier 3 Mixer section 3a, 3b Mixer circuit (mixer)
4 PGA unit 5 Signal generation unit LPF1 to LPF6 Low pass filter PGA1 to PGA6 Gain control amplifier AMP1, AMP2 Amplifier DOC DC offset cancellation circuit T1 to T6 Transistor R1 to R5 Resistance LC Load capacitance control unit (characteristic control unit)
Ba1, Ba2 Bias circuits Tr1 to Tr6 Transistors (variable capacitors, switching units)
C1 to C4 capacitance elements (variable resistance unit, first capacitance element)
C5 to C8 capacitance element (variable resistance unit, second capacitance element)
DEC1 decode circuit (capacity controller)
BC Bias resistance controller (characteristic controller)
SW1 to SW8 switch (variable resistor, switch)
DEC2 decode circuit (resistance control unit)
Rb1 to Rb4 resistors (variable resistor unit, first bias resistor)
Rb5 to Rb8 resistors (variable resistor unit, second bias resistor)

Claims (5)

Having a mixer consisting of a Gilbert cell circuit that demodulates the received signal and converts it to a baseband signal,
The mixer is
A semiconductor integrated circuit device for wireless communication, comprising a characteristic control unit for arbitrarily adjusting the characteristic of a differential signal path in an output unit. The semiconductor integrated circuit device for wireless communication according to claim 1,
The characteristic control unit
Based on the control signal, a variable capacitance unit that arbitrarily varies the load capacitance at the output of the mixer;
A semiconductor integrated circuit device for wireless communication, comprising: a capacitance control unit that outputs control to the variable capacitance unit based on a setting signal. The semiconductor integrated circuit device for wireless communication according to claim 2,
The variable capacitor is
A plurality of first capacitance elements having one connection connected to the first output of the mixer;
A plurality of second capacitance elements having one connection connected to the second output of the mixer;
A radio comprising: a switching unit for connecting the other connection unit of any of the first and second capacitance elements to a reference potential based on a control signal output from the capacitance control unit. Semiconductor integrated circuit device for communication. The semiconductor integrated circuit device for wireless communication according to claim 1,
The characteristic control unit
Based on a control signal, a variable resistance unit that arbitrarily varies the resistance value for bias in the mixer;
A wireless communication semiconductor integrated circuit device comprising: a resistance control unit that outputs control to the variable resistance unit based on a setting signal. The semiconductor integrated circuit device for wireless communication according to claim 3,
The variable resistance portion is
One connecting portion is connected to the control terminal of the upper transistor of the Gilbert cell circuit connected to the first output portion of the mixer, and the other connecting portion is connected to a bias circuit. Resistance for,
One connecting portion is connected to a control terminal of an upper transistor of the Gilbert cell circuit connected to the second output portion of the mixer, and a plurality of second biases having the other connecting portion connected to a bias circuit. Resistance for,
A wireless communication semiconductor integrated circuit device comprising: a switch unit that controls conduction of any of the first and second bias resistors based on a control signal output from the resistance control unit.

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