JP2003124799A - 集積回路のノードにおけるディジタル信号の遷移エッジのスルー・レートを低減する方法 - Google Patents
集積回路のノードにおけるディジタル信号の遷移エッジのスルー・レートを低減する方法Info
- Publication number
- JP2003124799A JP2003124799A JP2002215291A JP2002215291A JP2003124799A JP 2003124799 A JP2003124799 A JP 2003124799A JP 2002215291 A JP2002215291 A JP 2002215291A JP 2002215291 A JP2002215291 A JP 2002215291A JP 2003124799 A JP2003124799 A JP 2003124799A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- signal
- node
- threshold voltage
- slew rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
- H03K17/163—Soft switching
- H03K17/164—Soft switching using parallel switching arrangements
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/921,022 US6873196B2 (en) | 2001-08-02 | 2001-08-02 | Slew rate control of output drivers using FETs with different threshold voltages |
| US09/921,022 | 2001-08-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003124799A true JP2003124799A (ja) | 2003-04-25 |
| JP2003124799A5 JP2003124799A5 (https=) | 2005-10-27 |
Family
ID=25444791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002215291A Pending JP2003124799A (ja) | 2001-08-02 | 2002-07-24 | 集積回路のノードにおけるディジタル信号の遷移エッジのスルー・レートを低減する方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6873196B2 (https=) |
| JP (1) | JP2003124799A (https=) |
| SG (1) | SG116442A1 (https=) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040032412A1 (en) * | 2002-08-13 | 2004-02-19 | Odom Brian Keith | Generating a graphical program based on a timing diagram |
| US7202710B2 (en) * | 2004-04-30 | 2007-04-10 | Texas Instruments Incorporated | Apparatus and method for handling interdevice signaling |
| TWI262315B (en) * | 2004-11-17 | 2006-09-21 | Richtek Technology Corp | Detecting method of switching state for a FET-based switch |
| US20070236262A1 (en) * | 2006-04-10 | 2007-10-11 | Stmicroelectronics, Inc. | Low voltage output circuit |
| US8378742B2 (en) * | 2011-01-10 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Driver for a semiconductor chip |
| CN113810040B (zh) * | 2020-06-11 | 2024-03-22 | 台湾积体电路制造股份有限公司 | 用于转换速率控制的电路和方法 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4386286A (en) * | 1980-01-07 | 1983-05-31 | Texas Instruments Incorporated | High current static MOS output buffer circuit for power-down mode of operation |
| US4639615A (en) * | 1983-12-28 | 1987-01-27 | At&T Bell Laboratories | Trimmable loading elements to control clock skew |
| US5036222A (en) * | 1990-02-22 | 1991-07-30 | National Semiconductor Corporation | Output buffer circuit with output voltage sensing for reducing switching induced noise |
| JPH08213480A (ja) * | 1994-10-31 | 1996-08-20 | Nkk Corp | 半導体装置及びその製造方法 |
| US5581197A (en) * | 1995-05-31 | 1996-12-03 | Hewlett-Packard Co. | Method of programming a desired source resistance for a driver stage |
| US5568062A (en) * | 1995-07-14 | 1996-10-22 | Kaplinsky; Cecil H. | Low noise tri-state output buffer |
| US5877647A (en) * | 1995-10-16 | 1999-03-02 | Texas Instruments Incorporated | CMOS output buffer with slew rate control |
| EP1188237B1 (de) * | 1999-06-07 | 2004-11-03 | Infineon Technologies AG | Flipflop-schaltungsanordnung |
-
2001
- 2001-08-02 US US09/921,022 patent/US6873196B2/en not_active Expired - Fee Related
-
2002
- 2002-03-06 SG SG200201267A patent/SG116442A1/en unknown
- 2002-07-24 JP JP2002215291A patent/JP2003124799A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| SG116442A1 (en) | 2005-11-28 |
| US6873196B2 (en) | 2005-03-29 |
| US20030025542A1 (en) | 2003-02-06 |
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