JP2003124426A - High frequency power amplifier module - Google Patents
High frequency power amplifier moduleInfo
- Publication number
- JP2003124426A JP2003124426A JP2001310857A JP2001310857A JP2003124426A JP 2003124426 A JP2003124426 A JP 2003124426A JP 2001310857 A JP2001310857 A JP 2001310857A JP 2001310857 A JP2001310857 A JP 2001310857A JP 2003124426 A JP2003124426 A JP 2003124426A
- Authority
- JP
- Japan
- Prior art keywords
- high frequency
- power amplifier
- amplifier module
- frequency power
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は通信用送受信器の
送信部に使われる高周波増幅装置に関するもので、特に
携帯電話等で要求される装置の小型化に適した高周波パ
ワーアンプモジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency amplifier used in a transmitter of a communication transmitter / receiver, and more particularly to a high frequency power amplifier module suitable for downsizing of a device required for a mobile phone or the like.
【０００２】[0002]
【従来の技術】携帯電話端末はその利便性の観点から小
型、高機能化が要求されており、これに伴い、送信部に
用いられる高周波パワーアンプにおいても小型化が重要
な課題となっている。この高周波パワーアンプの小型化
手法の一つとして多層誘電体基板上に部品類を搭載した
モジュール化の方法が知られており、特開平９−２８３
７００等に記載されている。2. Description of the Related Art A portable telephone terminal is required to be small and highly functional from the viewpoint of convenience, and accordingly, miniaturization is also an important issue for a high frequency power amplifier used in a transmitting section. . As one of the miniaturization techniques for this high-frequency power amplifier, a modularization method in which components are mounted on a multilayer dielectric substrate is known.
700 etc.
【０００３】図６に上記特開平９−２８３７００の多層
基板を用いたパワーアンプモジュールを示す。図におい
て、増幅用半導体素子２−１、２−２は、６層の誘電体
層を有する多層基板１の２層分をくり貫いた凹部に搭載
され、ボンディングワイヤ８により表層の回路パタンに
接続されている。コンデンサ、インダクタ、抵抗等のチ
ップ部品６は基板１の表面に搭載されており、その上を
キャップ９で覆っている。誘電体層の２層毎に接地導体
層３を設け、その層間に線路導体層７を設け、線路用ビ
ア５により表層に設けた回路パタンやチップ部品とのコ
ンタクトをとっている。半導体素子の下には複数のサー
マルビア４を設け、熱を裏面に逃がす構造としている。FIG. 6 shows a power amplifier module using the multi-layer substrate disclosed in Japanese Patent Laid-Open No. 9-283700. In the figure, amplifying semiconductor elements 2-1 and 2-2 are mounted in a recess formed by hollowing out two layers of a multi-layer substrate 1 having six dielectric layers, and connected to a surface layer circuit pattern by a bonding wire 8. Has been done. Chip parts 6 such as capacitors, inductors, resistors, etc. are mounted on the surface of the substrate 1, and a cap 9 covers them. A ground conductor layer 3 is provided for every two dielectric layers, a line conductor layer 7 is provided between the two layers, and a contact is made with a circuit pattern or a chip component provided on the surface layer by a line via 5. A plurality of thermal vias 4 are provided under the semiconductor element so that heat is released to the back surface.
【０００４】[0004]
【発明が解決しようとする課題】一般に、多層基板を用
いたパワーアンプモジュールでは表面に半導体素子やコ
ンデンサ、インダクタ、抵抗、等のチップ部品を搭載
し、伝送線路やＤＣバイアス印加用線路の一部は層間の
導体層を使う方法がとられており、上記従来の技術で示
した例でも同様の構成となっている。Generally, in a power amplifier module using a multi-layer substrate, chip parts such as semiconductor elements, capacitors, inductors, resistors, etc. are mounted on the surface, and a part of a transmission line or a DC bias applying line is mounted. Uses a conductor layer between layers, and the example shown in the above-mentioned conventional technique has the same structure.
【０００５】しかし、上記従来例では増幅用半導体素子
の下の部分は最下層のアース導体まで全てサーマルビア
が設けられており、表層以下の層間を伝送線路やＤＣバ
イアス印加用線路として使用できるスペースは限られた
ものとなる。より小型化を目指し、使用する半導体チッ
プとモジュールの大きさが近づくほどこのスペースはほ
とんど無くなってしまう。特に半導体素子と周辺回路の
一部を半導体基板上に取り込んだＭＭＩＣチップとした
場合にはこの状態が著しくなり、多層基板を用いた小型
化の利点を生かすことができなくなるという課題があ
る。However, in the above-mentioned conventional example, thermal vias are provided in the entire lower part of the amplifying semiconductor element to the ground conductor of the lowermost layer, and a space which can be used as a transmission line or a DC bias applying line between the surface layers and below. Will be limited. This space will almost disappear as the size of the semiconductor chip and the module used become closer, aiming for further miniaturization. In particular, in the case of an MMIC chip in which a semiconductor element and a part of a peripheral circuit are incorporated on a semiconductor substrate, this state becomes remarkable, and there is a problem that the advantage of miniaturization using a multilayer substrate cannot be utilized.
【０００６】[0006]
【課題を解決するための手段】本発明は、上で述べた課
題を解決するため、増幅用半導体素子の下に設けたサー
マルビアを前記半導体素子を搭載した面の次の層のアー
ス導体層までとし、その下の層に伝送線路を設ける構造
とした。また、誘電体基板として窒化アルミニウムのよ
うな熱伝導率のよい材料を用いれば半導体素子の下に設
けるサーマルビアも特に必要無く、接地面への接続用ビ
アだけでよい。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a ground conductor layer next to the surface on which the semiconductor element is mounted with a thermal via provided under the amplifying semiconductor element. The structure is such that the transmission line is provided in the layer below. Further, if a material having a high thermal conductivity such as aluminum nitride is used as the dielectric substrate, a thermal via provided under the semiconductor element is not particularly required, and only a via for connecting to the ground plane is required.
【０００７】一般に送信用パワーアンプモジュールの性
能として重要となる効率の低下を抑えるための回路損失
低減の観点から、出力側のインピーダンス整合回路を構
成する伝送線路が最も広い面積を必要とする。より多く
のチップ部品を基板表面に搭載するには、上記出力側の
インピーダンス整合回路を構成する伝送線路を、半導体
素子の下を通るように形成することが最も有効である。
これにより多層基板の内層の面積を有効に利用でき、も
って小型な高周波パワーアンプモジュールが実現でき
る。Generally, the transmission line forming the impedance matching circuit on the output side requires the largest area from the viewpoint of reducing the circuit loss for suppressing the decrease in efficiency which is generally important for the performance of the power amplifier module for transmission. In order to mount a larger number of chip components on the surface of the substrate, it is most effective to form the transmission line forming the impedance matching circuit on the output side so as to pass under the semiconductor element.
As a result, the area of the inner layer of the multi-layer substrate can be effectively used, and a small high frequency power amplifier module can be realized.
【０００８】[0008]
【発明の実施の形態】以下、本発明の実施例について詳
細に説明する。図１は本発明の高周波パワーアンプモジ
ュールの上面図であり、図２は上記高周波パワーアンプ
モジュールのＡ−Ｂ断面図である。本実施例において、
出力側のインピーダンス整合回路を構成する伝送線路
は、その一部が増幅用半導体素子および周辺回路の一部
を組み込んだＭＭＩＣチップの下を通る構造となってい
る。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below. FIG. 1 is a top view of a high frequency power amplifier module of the present invention, and FIG. 2 is a cross-sectional view of the high frequency power amplifier module taken along the line AB. In this example,
A part of the transmission line forming the impedance matching circuit on the output side passes under the MMIC chip incorporating the amplifying semiconductor element and part of the peripheral circuit.
【０００９】図１、図２において多層基板１−１〜１−
４の最上層の誘電体基板１−１上にＭＭＩＣチップ２、
やコンデンサ、インダクタ、抵抗等の受動チップ部品４
−１〜４−６が搭載されている。高周波信号はモジュー
ルの裏面に設けられた高周波信号入力端１２からビア６
−１を通り、表層の入力端子５からボンディングワイヤ
８−１を通り、ＭＭＩＣの入力パッド側に入り、ＭＭＩ
Ｃ出力側のボンディングワイヤ８−２を経て出力側のイ
ンピーダンス整合回路を形成するマイクロストリップ線
路７に出力され、ビア６−２を通り誘電体の２層と３層
の間に設けたストリップ線路３を経て再びビア６−３を
通り、表層に設けたチップコンデンサ４−３を経た後、
再びビアを通りモジュールの裏面に設けた出力端子１３
に至る。1 and 2, the multilayer substrates 1-1 to 1-
4 on top of the dielectric substrate 1-1 of MMIC chip 2,
Chip components such as capacitors, inductors, and resistors 4
-1 to 4-6 are mounted. The high frequency signal is transmitted from the high frequency signal input end 12 provided on the back surface of the module to the via 6
-1, through the input terminal 5 on the surface layer, through the bonding wire 8-1 and into the input pad side of the MMIC,
It is output to the microstrip line 7 forming the impedance matching circuit on the output side via the bonding wire 8-2 on the C output side, and passes through the via 6-2 to be provided between the two and three layers of the dielectric strip line 3. After passing through the via 6-3 and the chip capacitor 4-3 provided on the surface layer,
The output terminal 13 which is provided on the back side of the module through the via again
Leading to.
【００１０】本実施例では、誘電体の１層目と２層目の
間に第１接地導体層９および３層目と４層目の間に第２
接地導体層１０を設け、最下層のモジュールのグランド
となるグランド層１１と多数のビアで接続している。ま
たＭＭＩＣチップの下面には、第１接地導体層との間に
多数のサーマルビア６−４を設けて熱抵抗の低減をはか
っている。In this embodiment, the first ground conductor layer 9 is provided between the first and second dielectric layers and the second ground conductor layer 9 is provided between the third and fourth dielectric layers.
The ground conductor layer 10 is provided, and is connected to the ground layer 11 serving as the ground of the lowest module by a large number of vias. Further, a large number of thermal vias 6-4 are provided between the lower surface of the MMIC chip and the first ground conductor layer to reduce thermal resistance.
【００１１】図３は図１、図２に示した高周波パワーア
ンプモジュールの誘電体基板の２層目と３層目の間に設
けた出力側インピーダンス整合回路用ストリップ線路を
示す図である。図において３層目誘電体基板１−３の上
にストリップ線路導体３が、基板表層に取り付けられた
ＭＭＩＣチップ２の真下を通るように設けられている。
ＭＭＩＣからの高周波信号は表層からビア６−２を通
り、ストリップ線路３、ビア６−３を経て再び表層に現
れる。FIG. 3 is a diagram showing an output side impedance matching circuit strip line provided between the second and third layers of the dielectric substrate of the high frequency power amplifier module shown in FIGS. 1 and 2. In the figure, the strip line conductor 3 is provided on the third-layer dielectric substrate 1-3 so as to pass directly under the MMIC chip 2 attached to the surface layer of the substrate.
The high-frequency signal from the MMIC passes through the via 6-2 from the surface layer, passes through the strip line 3 and the via 6-3, and then appears on the surface layer again.
【００１２】また、ストリップ線路の途中にビア６−４
が設けられており、基板表層に設けたインピーダンス整
合用のチップコンデンサと接続されている。３層目誘電
体基板を貫通する形でサーマルビア６−５がストリップ
線路を避ける形で設けられている。なお、多層誘電体基
板材料を窒化アルミニウムとすれば、基板の熱抵抗が低
減され、サーマルビアを設けなくてもよくなる。ただ
し、グランドをとるためのビアは必要であり、グランド
までのインダクタンスを低減するにはあまり数を減らす
のは得策ではない。Also, a via 6-4 is provided in the middle of the strip line.
Is provided and is connected to a chip capacitor for impedance matching provided on the surface layer of the substrate. Thermal vias 6-5 are provided so as to penetrate the third-layer dielectric substrate so as to avoid the strip line. If the material of the multilayer dielectric substrate is aluminum nitride, the thermal resistance of the substrate is reduced, and it is not necessary to provide a thermal via. However, vias are required for grounding, and it is not a good idea to reduce the number too much to reduce the inductance to ground.
【００１３】図４は図３で示した出力側インピーダンス
整合回路用ストリップ線路の他の実施例を示す図であ
る。図においてストリップ線路３の出力側ビア６−３の
位置が同じで入力側ビア６−２の位置が９０度違う場合
である。図３または図４の構成は、ストリップ線路が必
要とする長さにより選択できる。FIG. 4 is a diagram showing another embodiment of the output side impedance matching circuit strip line shown in FIG. In the figure, the position of the output side via 6-3 of the strip line 3 is the same, but the position of the input side via 6-2 is different by 90 degrees. The configuration of FIG. 3 or 4 can be selected depending on the length required by the strip line.
【００１４】図５は本発明の高周波パワーアンプモジュ
ールの回路構成図である。図においてモジュール２１の
高周波信号入力端子２４からの高周波信号は２段アンプ
からなるＭＭＩＣ２２に入り、初段のトランジスタ２６
出力段のトランジスタ２７を経て出力側のインピーダン
ス整合回路を構成するストリップ線路２３に入りモジュ
ールの出力端子２５から出力される。各トランジスタに
はＤＣバイアスがＤＣバイアス端子２８−１〜２８−４
から印加される。図において出力側のストリップ線路の
一部（斜線部）がＭＭＩＣチップの下の内層に形成され
る部分である。FIG. 5 is a circuit diagram of the high frequency power amplifier module of the present invention. In the figure, the high frequency signal from the high frequency signal input terminal 24 of the module 21 enters the MMIC 22 composed of a two-stage amplifier, and the first stage transistor 26
After passing through the output stage transistor 27, it enters the strip line 23 forming the impedance matching circuit on the output side and is output from the output terminal 25 of the module. DC bias is applied to each transistor by DC bias terminals 28-1 to 28-4.
Applied from. In the figure, a part of the strip line on the output side (hatched part) is a part formed in the inner layer below the MMIC chip.
【００１５】[0015]
【発明の効果】本発明によれば、多層基板を用いたパワ
ーアンプモジュールにおいて、増幅用半導体素子を含む
半導体チップの下の層に伝送線路、特に最も広い面積を
必要とする出力側のインピーダンス整合回路を構成する
伝送線路の一部を設ける。これにより多層基板の内層の
面積を有効に利用できると共に表層をチップ部品搭載用
として有効活用でき、もって小型な高周波パワーアンプ
モジュールの実現が可能になった。According to the present invention, in a power amplifier module using a multi-layer substrate, a transmission line is formed in a layer below a semiconductor chip including a semiconductor element for amplification, and impedance matching on the output side which requires the widest area in particular. A part of the transmission line that constitutes the circuit is provided. As a result, the area of the inner layer of the multi-layer substrate can be effectively used and the surface layer can be effectively used for mounting chip components, thereby realizing a compact high-frequency power amplifier module.
【図１】本発明の一実施例の高周波パワーアンプモジュ
ールを示す平面図。FIG. 1 is a plan view showing a high frequency power amplifier module according to an embodiment of the present invention.
【図２】本発明の一実施例の高周波パワーアンプモジュ
ールの断面図。FIG. 2 is a cross-sectional view of a high frequency power amplifier module according to an embodiment of the present invention.
【図３】３層目誘電体基板上に構成したストリップ線路
の平面図。FIG. 3 is a plan view of a strip line formed on a third-layer dielectric substrate.
【図４】３層目誘電体基板上に構成したストリップ線路
の平面図。FIG. 4 is a plan view of a strip line formed on a third-layer dielectric substrate.
【図５】高周波パワーアンプモジュールの回路図。FIG. 5 is a circuit diagram of a high frequency power amplifier module.
【図６】従来の高周波パワーアンプモジュールの一例を
示す断面図。FIG. 6 is a cross-sectional view showing an example of a conventional high frequency power amplifier module.
１…多層誘電体基板、２…ＭＭＩＣチップ、３…高周波
伝送線路、４…受動チップ部品、５…入力パッド、６…
ビア、７…出力パッド、８…ボンディングワイヤ、９…
接地導体層１、１０…接地導体層２、１１…グランド
層。1 ... Multilayer dielectric substrate, 2 ... MMIC chip, 3 ... High-frequency transmission line, 4 ... Passive chip component, 5 ... Input pad, 6 ...
Via, 7 ... Output pad, 8 ... Bonding wire, 9 ...
Ground conductor layers 1, 10 ... Ground conductor layers 2, 11 ... Ground layer.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/12 Ｂ Ｆターム(参考） 5J067 AA01 AA04 AA41 CA92 FA16 HA02 HA25 HA29 HA33 KA29 KA66 KA68 KS11 LS12 QA04 QS04 SA14 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme coat (reference) H01L 23/12 BF term (reference) 5J067 AA01 AA04 AA41 CA92 FA16 HA02 HA25 HA29 HA33 KA29 KA66 KA68 KS11 LS12 QA04 QS04 SA14
Claims (6)
号増幅用半導体素子とその周辺にチップコンデンサやチ
ップインダクタ、チップ抵抗および高周波伝送線路等の
受動素子からなるインピーダンス整合回路やＤＣバイア
ス供給回路を搭載した高周波アンプモジュールにおい
て、前記誘電体基板を多層基板とすると共に半導体素子
の出力側に設けるインピーダンス整合回路を構成する伝
送線路の一部を、前記半導体素子を搭載した位置の下層
を通る様に配置したことを特徴とする高周波パワーアン
プモジュール。1. An impedance matching circuit or a DC bias supply circuit comprising a high frequency signal amplifying semiconductor element such as a transistor and a passive element such as a chip capacitor, a chip inductor, a chip resistor and a high frequency transmission line on a periphery of the dielectric substrate. In the mounted high-frequency amplifier module, the dielectric substrate is a multilayer substrate, and a part of the transmission line that constitutes the impedance matching circuit provided on the output side of the semiconductor element is arranged so as to pass through the lower layer where the semiconductor element is mounted. High-frequency power amplifier module characterized by being arranged.
ュールにおいて、高周波信号増幅用半導体素子の下層を
通る様に配置した伝送線路を、上下に接地導体層を設け
たストリップ線路構造としたことを特徴とする高周波パ
ワーアンプモジュール。2. The high frequency power amplifier module according to claim 1, wherein the transmission line arranged so as to pass through the lower layer of the semiconductor element for high frequency signal amplification has a strip line structure in which ground conductor layers are provided above and below. Characteristic high frequency power amplifier module.
ュールにおいて、高周波信号増幅用半導体素子を誘電体
基板の第１層上に搭載し、第２層上に接地導体層を設
け、半導体素子の下面から前記第２層の接地導体層にサ
ーマルビアを設けたことを特徴とする高周波パワーアン
プモジュール。3. The high frequency power amplifier module according to claim 1, wherein the semiconductor element for high frequency signal amplification is mounted on the first layer of the dielectric substrate, and the ground conductor layer is provided on the second layer. A high frequency power amplifier module, characterized in that a thermal via is provided from the bottom surface to the second ground conductor layer.
ュールにおいて、高周波信号増幅用半導体素子の下層を
通る様に配置した伝送線路の一部にビアを設け、表層に
設けたチップ部品と接続したことを特徴とする高周波パ
ワーアンプモジュール。4. The high frequency power amplifier module according to claim 1, wherein a via is provided in a part of a transmission line arranged so as to pass through a lower layer of the semiconductor element for amplifying a high frequency signal, and is connected to a chip component provided in a surface layer. A high-frequency power amplifier module characterized in that
ュールにおいて、高周波信号増幅用半導体素子単体の周
辺に出力段の出力側インピーダンス整合回路以外のイン
ピーダンス整合回路やＤＣバイアス供給回路の一部を取
り込んだＭＭＩＣチップ構成としたことを特徴とする高
周波パワーアンプモジュール。5. The high frequency power amplifier module according to claim 1, wherein a part of an impedance matching circuit other than an output side impedance matching circuit of an output stage and a DC bias supply circuit are incorporated around a single high frequency signal amplifying semiconductor element. A high-frequency power amplifier module characterized by having an MMIC chip configuration.
ュールにおいて、ＭＭＩＣチップや受動素子を搭載する
誘電体基板を窒化アルミニウムで構成したことを特徴と
する高周波パワーアンプモジュール。6. The high frequency power amplifier module according to claim 1, wherein the dielectric substrate on which the MMIC chip and the passive element are mounted is made of aluminum nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001310857A JP4530322B2 (en) | 2001-10-09 | 2001-10-09 | High frequency power amplifier module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001310857A JP4530322B2 (en) | 2001-10-09 | 2001-10-09 | High frequency power amplifier module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003124426A true JP2003124426A (en) | 2003-04-25 |
| JP4530322B2 JP4530322B2 (en) | 2010-08-25 |
Family
ID=19129779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001310857A Expired - Fee Related JP4530322B2 (en) | 2001-10-09 | 2001-10-09 | High frequency power amplifier module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4530322B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005024946A1 (en) * | 2003-09-04 | 2005-03-17 | Renesas Technology Corp. | Semiconductor device and method for manufacturing same |
| JPWO2006048932A1 (en) * | 2004-11-04 | 2008-05-22 | 株式会社ルネサステクノロジ | Electronic equipment |
| US20150135526A1 (en) * | 2011-06-27 | 2015-05-21 | Intel Corporation | Secondary device integration into coreless microelectronic device packages |
-
2001
- 2001-10-09 JP JP2001310857A patent/JP4530322B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005024946A1 (en) * | 2003-09-04 | 2005-03-17 | Renesas Technology Corp. | Semiconductor device and method for manufacturing same |
| JPWO2006048932A1 (en) * | 2004-11-04 | 2008-05-22 | 株式会社ルネサステクノロジ | Electronic equipment |
| US20150135526A1 (en) * | 2011-06-27 | 2015-05-21 | Intel Corporation | Secondary device integration into coreless microelectronic device packages |
| US9686870B2 (en) * | 2011-06-27 | 2017-06-20 | Intel Corporation | Method of forming a microelectronic device package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4530322B2 (en) | 2010-08-25 |
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