JP2003115508A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003115508A
JP2003115508A JP2001307444A JP2001307444A JP2003115508A JP 2003115508 A JP2003115508 A JP 2003115508A JP 2001307444 A JP2001307444 A JP 2001307444A JP 2001307444 A JP2001307444 A JP 2001307444A JP 2003115508 A JP2003115508 A JP 2003115508A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
high frequency
frequency signal
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001307444A
Other languages
Japanese (ja)
Inventor
Toshinori Hirashima
利宣 平島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2001307444A priority Critical patent/JP2003115508A/en
Publication of JP2003115508A publication Critical patent/JP2003115508A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve high-frequency characteristics by reducing the number of inductors of a semiconductor device for processing a high-frequency signal, and prevent the reduction of the number of external terminals. SOLUTION: In a semiconductor device wherein leads turning to the external terminals are connected with the external electrodes of a semiconductor chip for processing the high-frequency signal, the external electrodes for the high-frequency signal of the semiconductor chip are connected with the leads by using bump electrodes, and the external electrodes except the external electrodes for the high frequency signal of the semiconductor chip are connected with the leads by using bonding wires. The number of the inductors of the semiconductor device for processing the high-frequency signal is reduced, the high-frequency characteristics are improved, the reduction of the number of external terminals is prevented, and an increase in cost can be restrained.The external electrodes for the high-frequency signal are connected with the leads by using the bump electrodes, so that the high-frequency characteristics are improved. The external electrodes except the external electrodes for the high-frequency signal are connected with the leads by using the bonding wires, so that the reduction in the number of external terminals is prevented and the increase in cost can be restrained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、特に、高周波信号の処理に用いられる半導体装置に
適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device used for processing a high frequency signal.

【０００２】[0002]

【従来の技術】半導体装置の製造では、単結晶シリコン
等のウェハに設けられた複数の素子形成領域に、半導体
素子或いは配線パターンを一括して形成して所定の回路
を構成し、隣接する素子形成領域間のスクライビング領
域にてウェハを切断して、夫々の素子形成領域を個々の
半導体チップとして分離するダイシングを行なう。2. Description of the Related Art In the manufacture of semiconductor devices, semiconductor elements or wiring patterns are collectively formed in a plurality of element forming regions provided on a wafer such as single crystal silicon to form a predetermined circuit, and adjacent elements are formed. The wafer is cut in the scribing region between the formation regions, and dicing is performed to separate each element formation region into individual semiconductor chips.

【０００３】こうしてウェハを個々の半導体チップを分
離した後に半導体装置の実装工程が行なわれる。図１及
び図２はＱＦＰ(Quad Flat Package)型半導体装置の一
例を示す平面図及び縦断面図であり、実装工程では、半
導体チップ１をタブ２に搭載し、半導体チップ１の外部
電極と、リード３の内端とをボンディングワイヤ４によ
って接続した後に、樹脂封止等の封止工程によって封止
体５を形成し、封止体５から露出するリードの外端が半
導体装置の外部端子になっており、タブ２は封止体５に
よって固定されるまで、タブ吊りリード６によって支持
されている。After the wafer is separated into individual semiconductor chips in this way, a semiconductor device mounting process is performed. 1 and 2 are a plan view and a vertical cross-sectional view showing an example of a QFP (Quad Flat Package) type semiconductor device. In the mounting process, the semiconductor chip 1 is mounted on a tab 2 and external electrodes of the semiconductor chip 1 are mounted. After connecting the inner end of the lead 3 with the bonding wire 4, the sealing body 5 is formed by a sealing process such as resin sealing, and the outer end of the lead exposed from the sealing body 5 becomes an external terminal of the semiconductor device. The tab 2 is supported by the tab suspension lead 6 until it is fixed by the sealing body 5.

【０００４】[0004]

【発明が解決しようとする課題】半導体チップ１とリー
ド３との接続に用いられているボンディングワイヤ４は
１ｎＨ〜２ｎＨ程度の寄生インダクタとなるので、周波
数が高くなり数ＧＨｚの信号を処理する場合には特性を
劣化させてしまう。例えば、移動体通信では使用周波数
の２ＧＨｚ帯への移行が予定されており、こうした高周
波信号の伝導では、導体の表面層に電流が集中し導体内
部が伝導に寄与しない表皮効果が現れるため、より一層
特性が劣化してしまう。Since the bonding wire 4 used for connecting the semiconductor chip 1 and the lead 3 becomes a parasitic inductor of about 1 nH to 2 nH, when the frequency becomes high and a signal of several GHz is processed. Will deteriorate the characteristics. For example, in mobile communication, the frequency used is expected to shift to the 2 GHz band, and in conducting such high-frequency signals, a skin effect appears in which the current concentrates on the surface layer of the conductor and the inside of the conductor does not contribute to conduction. The characteristics are further deteriorated.

【０００５】こうした特性の劣化を防止するために、バ
ンプ電極によって半導体チップの外部電極とリードとを
直接接続する方法もあるが、ボンディングワイヤは８０
μｍ程度のピッチで配置することが可能であるのに対し
て、リードでは０．１２ｍｍ程度のピッチで配置するこ
とになるため、必要な数の外部電極を半導体チップの周
縁部に配置することが困難になる。In order to prevent such deterioration of characteristics, there is a method of directly connecting the external electrode of the semiconductor chip and the lead with a bump electrode, but the bonding wire is 80
The leads can be arranged at a pitch of about 0.12 mm, while it can be arranged at a pitch of about μm. Therefore, it is possible to arrange a necessary number of external electrodes at the peripheral portion of the semiconductor chip. It will be difficult.

【０００６】このため外部電極とリードとを直接に接続
せず、外部電極とリードとをテープ基板を介して接続す
る或いは外部端子となるバンプ電極と接続する配線を形
成した基板に半導体チップを搭載する等の方法が考えら
れる。For this reason, the semiconductor chip is mounted on a substrate on which wiring is formed, which does not directly connect the external electrodes to the leads but connects the external electrodes to the leads via the tape substrate or the bump electrodes serving as external terminals. A method such as doing is possible.

【０００７】しかし、こうした方法では、価格の高い基
板が必要となる或いは多くのバンプ電極を形成するため
に費用及び時間を要するため、コストが重視される移動
体通信の端末機等には採用することが難しい。また、配
線を形成した基板は、配線の変更等を行なうためには基
板自体を作り直さなければならないため自由度が低くな
る。However, such a method requires a high-priced substrate or requires a lot of cost and time to form a large number of bump electrodes. Therefore, this method is used for a mobile communication terminal or the like where cost is important. Difficult to do. In addition, the substrate on which the wiring is formed has a low degree of freedom because the substrate itself must be recreated in order to change the wiring.

【０００８】本発明の課題は、これらの問題点を解決
し、高周波信号を処理する半導体装置のインダクタを低
減して高周波特性を向上させ、併せて外部端子の数の減
少を防止し、コストの増加を抑制することが可能な技術
を提供することにある。本発明の前記ならびにその他の
課題と新規な特徴は、本明細書の記述及び添付図面によ
って明らかになるであろう。An object of the present invention is to solve these problems, reduce the number of inductors in a semiconductor device that processes a high frequency signal to improve the high frequency characteristics, and at the same time prevent the number of external terminals from decreasing, thereby reducing the cost. It is to provide a technology capable of suppressing the increase. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【０００９】[0009]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。高周波信号を処理する半導体チッ
プの外部電極に外部端子となるリードを接続する半導体
装置において、前記半導体チップの高周波信号用の外部
電極とリードとをバンプ電極によって接続し、前記半導
体チップの高周波信号用以外の外部電極とリードとをボ
ンディングワイヤによって接続した。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows. In a semiconductor device in which a lead serving as an external terminal is connected to an external electrode of a semiconductor chip that processes a high frequency signal, the external electrode for the high frequency signal of the semiconductor chip and the lead are connected by a bump electrode, and the high frequency signal of the semiconductor chip is used. The external electrodes other than the above and the leads were connected by bonding wires.

【００１０】上述した本発明によれば、高周波信号用の
外部電極とリードとをバンプ電極によって接続するため
高周波特性が向上し、高周波信号用以外の外部電極とリ
ードとをボンディングワイヤによって接続するため、外
部端子の数の減少を防止し、コストの増加を抑制するこ
とができる。According to the present invention described above, since the external electrodes for high frequency signals and the leads are connected by the bump electrodes, the high frequency characteristics are improved, and the external electrodes other than those for the high frequency signals are connected by the bonding wires. It is possible to prevent a decrease in the number of external terminals and suppress an increase in cost.

【００１１】以下、本発明の実施の形態を説明する。な
お、実施の形態を説明するための全図において、同一機
能を有するものは同一符号を付け、その繰り返しの説明
は省略する。Embodiments of the present invention will be described below. In all the drawings for explaining the embodiments, the same reference numerals are given to those having the same function, and the repeated description thereof will be omitted.

【００１２】[0012]

【発明の実施の形態】例えば、図３に示すデュアルモー
ドの高周波アナログ信号処理回路では、図中破線にて囲
われた半導体装置に合計５６ピン〜６４ピン設けられる
リードの内で、高度の高周波特性が求められるリードは
ＬＮＡ（Low Noise Amp）への入力端子とＲＦ ＶＣＯと
の接続端子の合計６ピンに過ぎない。高周波信号の処理
に用いられる半導体装置であっても、その外部端子の全
てに高周波特性が求められるわけではない。従って、少
数の端子の特性を改善するために全ての端子をバンプ電
極によって接続する必要はない。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the dual mode high frequency analog signal processing circuit shown in FIG. 3, for example, a semiconductor device surrounded by a broken line in FIG. The leads whose characteristics are required are only 6 pins in total, which are the input terminal to the LNA (Low Noise Amp) and the connection terminal to the RF VCO. Even in a semiconductor device used for processing a high frequency signal, not all external terminals of the semiconductor device are required to have high frequency characteristics. Therefore, it is not necessary to connect all terminals by bump electrodes in order to improve the characteristics of a small number of terminals.

【００１３】このため、本発明の半導体装置では高周波
信号を処理する半導体チップの外部電極に外部端子とな
るリードを接続する半導体装置において、前記半導体チ
ップの高周波信号用の外部電極とリードとをバンプ電極
によって接続し、前記半導体チップの高周波信号用以外
の外部電極とリードとをボンディングワイヤによって接
続する。Therefore, in the semiconductor device of the present invention, in the semiconductor device in which the lead serving as the external terminal is connected to the external electrode of the semiconductor chip for processing the high frequency signal, the external electrode for the high frequency signal of the semiconductor chip and the lead are bumped. The electrodes are connected, and the external electrodes of the semiconductor chip other than those for high-frequency signals are connected to the leads by bonding wires.

【００１４】図４は、本発明の一実施の形態である高周
波アナログ信号の処理に用いられるＱＦＰ型の半導体装
置を示す平面図であり、図５は図４に示す半導体装置の
縦断面図である。FIG. 4 is a plan view showing a QFP type semiconductor device used for processing a high frequency analog signal according to one embodiment of the present invention, and FIG. 5 is a vertical sectional view of the semiconductor device shown in FIG. is there.

【００１５】この半導体装置では、半導体チップ１１を
バスバー１２に固定し、半導体チップ１１の外部電極
と、通常のリード１３の内端とをボンディングワイヤ１
４によって接続する。そして、図中左側のバスバー１２
に囲まれた高周波信号用のリード１５と半導体チップ１
１の外部電極とはバンプ電極１６によって接続した後に
樹脂封止等の封止工程によって封止体１７を形成し、封
止体１７から露出するバスバー１２の外端及びリード１
３，１５の外端が半導体装置の外部端子になっている。In this semiconductor device, the semiconductor chip 11 is fixed to the bus bar 12, and the external electrode of the semiconductor chip 11 and the inner end of the ordinary lead 13 are bonded to the bonding wire 1.
Connect by 4. And the bus bar 12 on the left side in the figure
High-frequency signal lead 15 surrounded by and semiconductor chip 1
The external electrode of No. 1 is connected with the bump electrode 16 and then the sealing body 17 is formed by a sealing process such as resin sealing, and the outer end of the bus bar 12 exposed from the sealing body 17 and the lead 1.
The outer ends of 3, 15 are external terminals of the semiconductor device.

【００１６】なお、バスバー１２は、半導体チップ１１
の固定の他に電源或いは接地用にも用いられ、半導体チ
ップ１１の外部電極とバンプ電極１６によって４箇所程
度接続して、半導体チップ１１を固定する。The bus bar 12 is a semiconductor chip 11.
In addition to fixing the semiconductor chip 11, the semiconductor chip 11 is fixed by connecting the external electrodes of the semiconductor chip 11 to the bump electrodes 16 at about four places.

【００１７】本実施の形態に用いられる半導体チップ１
１は平面形状が長方形であり、高周波信号用のリード１
５と接続される高周波信号用の電極は、半導体チップ１
１の短辺側の縁部に配置されている。このため高周波信
号用の電極から封止体１７の端部までの距離が短くなる
ので、高周波信号用のリード１５を他のリード１３より
も短くすることができるので高周波特性が向上する。The semiconductor chip 1 used in this embodiment
Reference numeral 1 is a rectangular planar shape, and is a lead 1 for high frequency signals.
The electrodes for high frequency signals connected to the semiconductor chip 5 are semiconductor chips 1
It is arranged at the edge of the short side of 1. For this reason, the distance from the high frequency signal electrode to the end of the sealing body 17 is shortened, so that the high frequency signal lead 15 can be made shorter than the other leads 13 and the high frequency characteristics are improved.

【００１８】更に、本実施の形態の半導体装置では、半
導体チップ１１の中心と封止体１７の中心とが平面的に
重なっておらず、高周波信号用の外部電極が配置されて
いる半導体チップ１１の前記短辺側の縁部が他の縁部よ
りも封止体１７外表面に近接させてあるので、高周波信
号用のリード１５を他のリード１３よりも更に短くする
ことができるこのように、高周波特性を必要とするリー
ド１５と半導体チップ１１との接続をバンプ電極１６と
することで、ボンディングワイヤ１４接続の場合よりも
インダクタを低減させて高周波特性を向上させることが
できる。そして、高周波特性を必要としないリード１３
と半導体チップ１１との接続をボンディングワイヤ１４
とすることで、外部端子の数を減少させることもない。Further, in the semiconductor device of the present embodiment, the center of the semiconductor chip 11 and the center of the sealing body 17 do not planarly overlap with each other, and the semiconductor chip 11 having the external electrodes for high frequency signals is arranged. Since the edge portion on the short side of the above is closer to the outer surface of the sealing body 17 than other edge portions, the lead 15 for high frequency signal can be made shorter than the other lead 13. By using the bump electrode 16 as the connection between the lead 15 and the semiconductor chip 11 which require high frequency characteristics, the inductor can be reduced and the high frequency characteristics can be improved as compared with the case where the bonding wire 14 is connected. Then, the lead 13 that does not require high frequency characteristics
Connection between the semiconductor chip 11 and the bonding wire 14
Therefore, the number of external terminals is not reduced.

【００１９】以上、本発明を、前記実施の形態に基づき
具体的に説明したが、本発明は、前記実施の形態に限定
されるものではなく、その要旨を逸脱しない範囲におい
て種々変更可能であることは勿論である。Although the present invention has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

【００２０】例えば、前述した実施の形態では、半導体
チップの平面形状が長方形であり、半導体チップの中心
とが封止体の中心と異なっている場合について説明した
が、半導体チップの平面形状が正方形である場合でも本
発明は適用が可能であり、また、半導体チップの中心と
封止体の中心とが重なっている場合でも同様に本発明は
適用が可能である。For example, in the above-described embodiments, the case where the semiconductor chip has a rectangular planar shape and the center of the semiconductor chip is different from the center of the sealing body has been described. However, the planar shape of the semiconductor chip is square. The present invention can be applied even when the above is the case, and the present invention can be similarly applied even when the center of the semiconductor chip and the center of the sealing body overlap.

【００２１】[0021]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。 （１）本発明によれば、高周波信号用の外部電極とリー
ドとをバンプ電極によって接続するため高周波特性が向
上するという効果がある。 （２）本発明によれば、高周波信号用以外の外部電極と
リードとをボンディングワイヤによって接続するため、
外部端子の数の減少を防止することができるという効果
がある。 （３）本発明によれば、半導体チップとリードとの接続
に基板等が不用であり、基板に要するコストの増加を防
止することができるという効果がある。 （４）本発明によれば、少数のバンプ電極を形成するだ
けでよいために、バンプ電極形成の費用及び時間を少な
いため、コストの増加が少ないという効果がある。 （５）本発明によれば、半導体チップとリードとの接続
に配線を形成した基板を用いないので、半導体チップと
リードとの接続の自由度が高くなるという効果がある。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, since the external electrodes for high frequency signals and the leads are connected by the bump electrodes, there is an effect that high frequency characteristics are improved. (2) According to the present invention, since the external electrodes other than those for high frequency signals are connected to the leads by the bonding wires,
This has the effect of preventing a decrease in the number of external terminals. (3) According to the present invention, a substrate or the like is unnecessary for connecting the semiconductor chip and the lead, and it is possible to prevent an increase in cost required for the substrate. (4) According to the present invention, since it is only necessary to form a small number of bump electrodes, the cost and time for forming the bump electrodes are small, and there is an effect that the increase in cost is small. (5) According to the present invention, since the substrate on which the wiring is formed is not used for connecting the semiconductor chip and the lead, there is an effect that the degree of freedom in connecting the semiconductor chip and the lead is increased.

【図面の簡単な説明】[Brief description of drawings]

【図１】従来の半導体装置を示す平面図である。FIG. 1 is a plan view showing a conventional semiconductor device.

【図２】図１に示す半導体装置の縦断面図である。FIG. 2 is a vertical cross-sectional view of the semiconductor device shown in FIG.

【図３】高周波アナログ信号処理回路の一例を示す回路
図である。FIG. 3 is a circuit diagram showing an example of a high frequency analog signal processing circuit.

【図４】本発明の一実施の形態の半導体装置を示す平面
図である。FIG. 4 is a plan view showing a semiconductor device according to an embodiment of the present invention.

【図５】図４に示す半導体装置の縦断面図である。5 is a vertical cross-sectional view of the semiconductor device shown in FIG.

【符号の説明】[Explanation of symbols]

１，１１…半導体チップ、２…タブ、３，１３…リー
ド、４，１４…ボンディングワイヤ、５，１７…封止
体、６…タブ吊りリード、１２…バスバー、１５…高周
波信号用リード、１６…バンプ電極。1, 11 ... Semiconductor chip, 2 ... Tab, 3, 13 ... Lead, 4, 14 ... Bonding wire, 5, 17 ... Sealing body, 6 ... Tab suspension lead, 12 ... Bus bar, 15 ... High frequency signal lead, 16 ... bump electrodes.

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 高周波信号を処理する半導体チップの外
部電極に外部端子となるリードを接続する半導体装置で
あって、 前記半導体チップの高周波信号用の外部電極とリードと
をバンプ電極によって接続し、前記半導体チップの高周
波信号用以外の外部電極とリードとをボンディングワイ
ヤによって接続したことを特徴とする半導体装置。1. A semiconductor device in which a lead serving as an external terminal is connected to an external electrode of a semiconductor chip for processing a high frequency signal, wherein the external electrode for the high frequency signal of the semiconductor chip and the lead are connected by a bump electrode, A semiconductor device, wherein external electrodes other than those for high frequency signals of the semiconductor chip and leads are connected by bonding wires. 【請求項２】 前記半導体装置が高周波アナログ信号の
処理に用いられることを特徴とする請求項１に記載の半
導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor device is used for processing a high frequency analog signal. 【請求項３】 前記半導体装置がＱＦＰ型であることを
特徴とする請求項１又は請求項２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the semiconductor device is a QFP type. 【請求項４】 前記半導体チップが長方形であり、その
短辺側の縁部に高周波信号用の外部電極が配置されてい
ることを特徴とする請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein the semiconductor chip has a rectangular shape, and an external electrode for a high frequency signal is arranged at an edge portion on a short side of the semiconductor chip. 【請求項５】 前記半導体チップを封止する封止体の中
心と半導体チップの中心とが異なり、高周波信号用の外
部電極が配置されている半導体チップの縁部が他の縁部
よりも封止体外表面に近接させてあることを特徴とする
請求項１乃至請求項４の何れか一項に記載の半導体装
置。5. The center of the sealing body that seals the semiconductor chip is different from the center of the semiconductor chip, and the edge portion of the semiconductor chip on which the external electrodes for high frequency signals are arranged is more sealed than the other edge portions. The semiconductor device according to claim 1, wherein the semiconductor device is arranged close to the outer surface of the stopper.
JP2001307444A 2001-10-03 2001-10-03 Semiconductor device Pending JP2003115508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001307444A JP2003115508A (en) 2001-10-03 2001-10-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001307444A JP2003115508A (en) 2001-10-03 2001-10-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2003115508A true JP2003115508A (en) 2003-04-18

Family

ID=19126907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001307444A Pending JP2003115508A (en) 2001-10-03 2001-10-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2003115508A (en)

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