JP2003114868A - Bus control system and bus control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus control system for performing the data return processing for transmission-retained data to a plurality of processors by a single return of data. SOLUTION: This bus control system comprises a bus control circuit connected to the plurality of processors through a common bus to exchange data and, as necessary, acquiring to relay data requested by the processors from an external circuit. The bus control circuit suppresses an access to the data by all processors when the data requested from the processors are acquired from the external circuit and, after acquiring the data from the external circuit, adds an instruction to release the access suppression and the information on the adresses of the data to the data and sends the instruction and information to the common bus. Each processor decides whether the data sent to the common bus is the data requested by the processor itself or not before acquisition. Thus the data can be transmitted to all processors at a stroke.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control of communication with a plurality of processors connected to a common bus, and more particularly to a bus control system and a bus for efficiently processing return processing of data requested by the processors. Regarding the control circuit.

[0002]

2. Description of the Related Art In conventional hierarchical bus control, a bus control circuit suspends data return when data that is requested by a processor connected to a common bus (data transmission request) is not held. Then, the requested data is obtained by requesting the external circuit from the external circuit.

When a data request access to the held data is sent from another processor while the data return is being held, the data return is also held to that processor. Then, after the requested data is obtained from the external circuit, the data is returned to all the processors that have made this data request access.

That is, when the requested data is not held in the internal memory, the returning process is the process of holding the request of the processor, the process of acquiring the requested data from the external circuit, and the acquired data. It was necessary to execute the process of returning to the processor that requested.

[0005]

However, in the above-mentioned conventional technique, when a plurality of data request accesses to the same address (same data) are overlapped, the data request access is performed by returning the data of the same address. In addition, the data must be returned to all the processors, and the data must be returned as many times as the data request access.

Data request access from the respective processors to the same address often overlaps. Sending the same data multiple times is an inefficient process,
There has been a demand for a system that can process more efficiently.

An object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to perform a data return process of data held for a plurality of processors by one-time data return and a bus control system. To provide a circuit.

[0008]

In order to achieve the above object, the bus control system of the present invention is connected to a plurality of processors by a common bus, and acquires data required by the processors from an external circuit as needed. In a bus control system including a bus control circuit for relaying, when the data requested by the processor is acquired from the external circuit, access to the data by each processor is suppressed, and after the data is acquired from the external circuit. The return data in which the instruction to release the access inhibition is added to the data is transmitted to the common bus.

The bus control system of the present invention according to claim 2 is
When the data requested by the processor is acquired from the external circuit, an access inhibition instruction for the data is sent to the common bus to inhibit access to the data by each processor.

The bus control system according to the present invention of claim 3 is
When each processor receives the access inhibition instruction from the bus control circuit via the common bus, it inhibits access to the access inhibition target data of the access inhibition instruction, and the bus control circuit sets the common bus to the common bus. When the return data is received via the above, the access inhibition specified in the return data is canceled.

The bus control system of the present invention according to claim 4 is
The bus control circuit sends the return data obtained by adding information for uniquely identifying the data to the data acquired from the external circuit to the common bus, and each processor is
When the return data sent to the common bus by the bus control circuit is received, by referring to the information uniquely identifying the data acquired from the external circuit included in the return data, It is characterized by determining whether or not the acquired data is data requested by the processor itself.

The bus control system according to the present invention of claim 5 is
The information that uniquely identifies the data is an address of the data.

The bus control system according to the present invention of claim 6 is
When each of the processors receives the return data sent to the common bus by the bus control circuit, the data acquired from the external circuit included in the return data is transferred to the bus control circuit by the processor. When the data is the requested data or the data whose access is being suppressed, it is determined that the data is requested by the processor itself and is acquired.

The bus control system according to the present invention of claim 7 is
The bus control circuit and the external circuit are connected by a bus other than the common bus for communication.

According to another aspect of the present invention, there is provided a bus control circuit, wherein the bus control circuit is connected to a plurality of processors through a common bus, and when necessary, the data requested by the processors is acquired from an external circuit and relayed. When acquiring the data requested by the processor from the external circuit, means for suppressing access to the data by each processor, and after acquiring the data requested by the processor from the external circuit, It is characterized in that it is provided with means for sending back the return data to which the instruction to release the access inhibition is added to the common bus.

According to a ninth aspect of the present invention, in the bus control circuit according to the present invention, when the data requested by the processor is obtained from the external circuit, an access inhibition instruction for the data is sent to the common bus to cause each of the processors. It is characterized in that access to the data in question is suppressed.

According to a tenth aspect of the present invention, there is provided the bus control circuit according to the present invention, further comprising means for transmitting the return data, which is obtained by adding information for uniquely identifying the data to the data acquired from the external circuit, to the common bus. Whether the processor refers to the information uniquely identifying the data acquired from the external circuit included in the returned data, and whether the data acquired from the external circuit is the data requested by the processor itself It is characterized in that it is determined and acquired.

A bus control circuit according to the present invention of claim 11 is characterized in that the information for uniquely identifying the data is an address of the data.

A bus control circuit according to a twelfth aspect of the present invention is characterized in that the bus control circuit communicates with the external circuit by a bus other than the common bus.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a bus control system according to the first embodiment of the present invention.

Referring to FIG. 1, in the bus control system of the present embodiment, a bus control circuit 100 and a plurality of processors 201, 202 ... Are connected via a common bus 300 to send and receive data and instructions. For example, the bus control circuit 1
00 accepts a data request access (data transmission request) for data to be recorded in the memory from each of the processors 201, 202, ... And returns the requested data.

In addition, the bus control circuit 100 includes the external bus 4
00 to the external circuit 500. When the bus control circuit 100 does not have the data requested by each processor 201, 202, ..., It requests the external circuit 500 via the external bus 400 to acquire the data, and returns the acquired data to the processor. To do.

As described above, in the present embodiment, the bus control circuit 100 is connected to the common bus 300 for communicating with the individual processors 201, 202, ... And the external bus 400 for communicating with the external circuit 500. It has a hierarchical bus structure.

The external circuit 500 is a circuit having a function of transmitting data in response to a request from the bus control circuit 100, and its structure is not particularly limited.

Although a plurality of processors 201, 202, ... Are connected to the bus control circuit 100 as shown in FIG. 1, the number of processors to be connected is not limited and may be any number.

Referring to FIG. 1, a bus control circuit 100 according to the present embodiment stores information on a memory 10 that holds data, a memory control unit 20 that controls the memory 10, and a processor that is pending data return. The information storage unit 30, the suppression instruction unit 40 for suppressing the data request access from each processor to the data for which the data return is suspended, and the response return unit 50 for returning the requested data are provided.

The memory control unit 20 includes each processor 20.
In response to the data request access from 1, 202, ..., The presence / absence of valid data which is the data requested by the processor in the memory 10 is determined by referring to the information in the memory 10.

When the valid data to be returned is not registered in the memory 10, the information storage unit 30 suspends the data return and registers the access information of the data request access. Then, the data request access is transferred to the external bus 400 in order to read the valid data required for data return from another memory.

The inhibition instruction unit 40 refers to the information of the data request access pending for the data return registered in the information storage unit 30, and causes each processor to inhibit the data request access to the same pending address. The process of inhibiting the data request access is performed by transmitting an access inhibit command to all the processors via the common bus 300.

When the valid data is registered in the memory 10, the response returning unit 50 returns the valid data in the memory 10 to the requesting processor via the common bus 300. Further, when the memory 10 does not have valid data and the external circuit 500 is requested through the external bus 400 to obtain the valid data, the obtained valid data is similarly returned through the common bus 300.

In particular, the response return unit 50 uses the external bus 400
When valid data is acquired via the
Based on 0 and the information of the inhibition instruction unit 40, data is simultaneously returned (by one data transmission) to all the processors that are inhibiting the data request access connected to the common bus 300.

Next, the bus control circuit 100 according to the present embodiment.
The operation will be explained. 2 and 3 are flowcharts for explaining the process of the data return control according to the present embodiment, FIG. 2 shows the operation when the requested data is not in the memory 10, and FIG. 3 is the requested data. Shows the operation when is in the memory 10.

First, from the processor 201, the common bus 3
A data request access is issued to the bus control circuit 100 via 00 (step 201). Then, the memory control unit 20 reads the data registration information S3 by fetching the access information S1 and transferring the address information S2 to the memory 10 that holds a part of the data necessary for data return with the processor. It is determined whether data is registered (step 202).

The operations up to this point are common operations both when the requested data is in the memory 10 (FIG. 3) and when it is not (FIG. 2), and the operations of steps 201 and 202 are shown in FIG. This is the same operation as steps 301 and 302 of.

Referring to FIG. 3, the memory control unit 20 includes
If it is determined that the valid data is registered in the memory 10 (step 303), the valid data output request S4 is made to the memory 10 and the valid data return request S5 is made to the response return unit 50. The response return unit 50,
The data S6 from the memory 10 is registered in response to the valid data return request S5 from the memory control unit 20, and the common bus 3
The data is returned to the processor 201 via 00 (step 304). As a result, the processor 201 that has performed the data request access acquires the requested data (step 305).

Referring to FIG. 2, the memory controller 20
If it is determined that the valid data is not registered in the memory 10 (step 203), the data request access is ended once S7, the data return to the processor 201 is suspended, and the access information S1 is stored in the information storage unit 30. A registration request S8 is made (step 204).

Then, the information storage unit 30 registers the access information S1 according to the registration request S8 of the access information S1 from the memory control unit 20 and reads the valid data from another memory. Transfer S9 to the external bus 400 (step 2
05), the transfer request S10 is issued to the inhibition instruction unit 40.

In response to the transfer request S10 from the information storage unit 30, the deterrence instruction unit 40 has access information S11 of the access for which the return of the data registered in the information storage unit 30 is suspended.
Of the access information S to the common bus 300.
An access inhibition instruction S12 for inhibiting the data request access of the same address as 11 is issued, and the information indicating that the data request access from the processor is inhibited is registered for the same address (step 206). .

In response to the data request access S9 transferred to the external bus 400, the return data S13 is sent to the response return unit 50.
Is transferred (step 207), the response return unit 50
Is the access information S1 registered in the information storage unit 30.
1 and the access inhibition information S14 registered in the inhibition instruction unit 40 indicate that the pending data return response is the data request access of the processor 201 and the data request from the other processor to the same address. It is determined that access is restricted, and the common bus 30
At the same time as responding to the data return to the processor 201 via 0, data return is simultaneously performed to the other processors connected to the common bus 300 (step 20).
8).

The processors 201, 202, ...
Receives a data return from the bus control circuit 100, confirms whether the data is valid data requested by its own processor, and acquires it if it is valid data requested. Here, each processor
The method of confirming whether the data is valid data requested by the processor itself can be performed by including the data used for confirmation in the format of the return data as shown in FIG.

FIG. 4 is a diagram showing an example of a format of return data 60 to each processor of the bus control circuit 100 according to this embodiment. Referring to the format of the return data 60 in the example of FIG. 4, a suppression bit 61 indicating whether or not the return data is a return pending data, and a processor indicating a processor requesting a data request access to the return data. The effective data 64 for returning the information area 62 and the address information area 63 indicating the address of the returned data
Has been added to.

The inhibition bit 61 indicates whether or not this return data is the return data of the data whose return has been suspended. For example, when the value of the inhibit bit 61 is "1", the data of which the return is suspended is It indicates that the data is return data, and if the value of the inhibition bit 61 is “0”, it indicates that the data is not the return data of the data for which the return is suspended.

When the inhibition bit 61 of the received return data 60 is "0", each processor refers to the processor information added to the processor information area 62 to request the data requested by its own processor. It is possible to determine whether or not it is the request access, and if it is the return data requested by the own processor, this is received and the data request access is ended.

Further, when the inhibition bit 61 of the received return data 60 is "1", each processor similarly refers to the processor information added to the processor information area 62, so that its own processor If it is the return data requested by the own processor, it is received, and if it is not the return data requested by the own processor, it is further added to the address information area 63. If the data request access to the address is suppressed, the address information is received and the data request access is terminated.

FIG. 5 shows an example of the format of the access inhibition instruction for the bus control circuit 100 to inhibit the data request access to the pending data from each processor. Referring to the format of the access restraint instruction in the example of FIG. 5, a restraint instruction bit 71 for indicating whether or not the data is an access restraint instruction for restraining a data request access, and an address indicating an address for restraining a data request. The information area 72 is provided.

The processor refers to the inhibition instruction bit 71 (for example, whether it is "1") to determine whether the received data is an access inhibition instruction, and if it is an access inhibition instruction. First, the data request access to the address shown in the address information area 72 is suppressed.

The release of the access inhibition on the processor side is to be released when the return of the data of the address for which the access is inhibited is received from the bus control circuit 100. That is, when the inhibition bit 61 is set in the return data 60 from the bus control circuit 100, the access inhibition for addressing shown in the address information area 63 of the return data 60 is released.

As described above, the bus control circuit 100 of the present embodiment makes a decision as to whether or not data can be immediately returned in response to a data request access from a processor connected to the common bus 300. If it is determined that the data cannot be returned immediately, the data request access is terminated once and the data return to the processor is suspended. Then, the requested data is acquired from the external circuit via the external bus 400, and the acquired data has an inhibition bit indicating that the data is the return data of the data whose return is suspended, and an address indicating the address of this return data. The return data to which the information is added is sent to the common bus 300 and sent to all the processors at once, and each processor refers to the address information of the return data to determine whether or not the data is the data requested by the own processor and obtain it. Can be made.

As a result, all of the processors that first make a data request access and the processors that inhibit the data request access are set to 1 on the common bus 300.
The requested data can be sent only by sending the data once.

Next, another embodiment of the present invention will be described.

In the first embodiment of the present invention, the format of FIG. 4 has been described as an example of the return data from the bus control circuit 100 to each processor, but it is not necessary to limit the format to that of FIG. The processor information area 62 indicating the processor requesting the data request access to the returned data may not be provided.

In the format of the return data 60 shown in FIG. 4 and the format of the access control instruction 70 shown in FIG. 5, the address information areas 63 and 72 are used to specify the addresses of the data to be returned and the access control data. Although shown, information (identifier or the like) that uniquely identifies the data may be used instead of the address of the data. In addition, the inhibition bit 61 of the return data 60 and the access inhibition instruction 7
The suppression instruction bit 71 of 0 does not have to be limited to the system indicating one bit of "0" and "1" as in the above-described embodiment.

In the format of the return data 60 shown in FIG. 4 and the format of the access inhibition instruction 70 shown in FIG. 5, the inhibition bit 61, the processor information area 62,
It is not necessary to limit the recording positions of the address information area 63, the valid data 64, the inhibition instruction bit 71, the address information area 72, etc. and the order thereof.

Further, in the bus control circuit 100 of the first embodiment shown in FIG. 1, the bus control circuit 100 is provided with the memory 10, but the memory 10 is not provided and The embodiment in which only the data of the external circuit 500 is transmitted via the external bus 400 can be similarly implemented.

Further, the bus control circuit 1 of the first embodiment
00, return data 60 and access control instruction 7
By sending 0 to the common bus 300 once, all the processors 201 connected to the bus control circuit 100,
Although the method of transmitting to 202, ... Is used, the present invention is not limited to this.

This can be similarly performed, for example, when the processor connected to the common bus 300 has a processor which is not set to receive the return data 60 and the like in advance (that is, to the bus control circuit 100). A processor that only transmits data, a processor that requests only data in the memory 10 of the bus control circuit 100, etc.).

Further, for example, a system in which a plurality of independent common buses are connected to the bus control circuit 100 and the return data 60 and the access inhibition instruction 70 are sent to each common bus can be similarly implemented. That is, of the plurality of common buses, control is performed to send the return data 60 and the access inhibition instruction 70 only to the common bus that has made a data request access that requires data acquisition from an external circuit. .

Although the present invention has been described with reference to the preferred embodiments and examples, the present invention is not necessarily limited to the above-described embodiments and examples, and various modifications are possible within the scope of the technical idea thereof. It can be modified and implemented.

[0059]

As described above, according to the bus control system and the bus control circuit of the present invention, the following effects can be achieved.

When the data return is suspended in order to obtain the requested data from the external circuit, even if a plurality of data request accesses to the suspended data are sent in duplicate, the data is requested. It is possible to process the data return to all the processors to be performed by one data return. As a result, data return can be efficiently processed, and bus traffic can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a bus control system according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating processing of data return control according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating a data return control process according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an example of a format of return data to each processor of the bus control circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an example of a format of an instruction to inhibit access to each processor of the bus control circuit according to the first embodiment of the present invention.

[Explanation of symbols]

100 bus control circuit 10 memory 20 memory controller 30 Information storage 40 Deterrence instruction section 50 Response Return Department 60 Return data 61 suppression bit 62 Processor Information Area 63 Address information area 64 valid data 70 Access control instruction 71 Suppression instruction bit 72 Address information area 201, 202, ... Processor 300 common buses 400 external bus 500 external circuit

Claims (12)

[Claims] 1. A bus control system, comprising: a bus control circuit, which is connected to a plurality of processors through a common bus, acquires data required by the processors from an external circuit and relays the data when required, in the bus control system. When data is obtained from the external circuit, the return data obtained by inhibiting access to the data by each of the processors, obtaining the data from the external circuit, and adding an instruction to release the access inhibition to the data is described above. A bus control system characterized by sending to a common bus. 2. When the data requested by the processor is obtained from the external circuit, it is possible to suppress an access to the data by each processor by sending an access suppression instruction for the data to the common bus. The bus control system of claim 1, wherein the bus control system is a bus control system. 3. When each of the processors receives the access inhibition instruction from the bus control circuit via the common bus, it inhibits access to the access inhibition target data of the access inhibition instruction, and the bus control circuit The bus control system according to claim 2, wherein, when the return data is received from the device via the common bus, the access inhibition indicated by the return data is released. 4. The bus control circuit sends the return data, in which information for uniquely identifying the data is added to the data acquired from the external circuit, to the common bus, and each of the processors has the bus control circuit. When the return data sent to the common bus is received by, by referring to the information uniquely identifying the data acquired from the external circuit included in the return data, the data acquired from the external circuit The bus control system according to any one of claims 1 to 3, wherein the bus control system acquires and determines whether or not the data is requested by the processor itself. 5. The bus control system according to claim 4, wherein the information that uniquely identifies the data is an address of the data. 6. When each of the processors receives the return data sent to the common bus by the bus control circuit, the data acquired from the external circuit included in the return data is stored in the bus by the processor. 6. The data is requested by the processor itself and is acquired when the data is requested to the control circuit or the data whose access is being suppressed. Bus control system according to. 7. The bus control circuit according to claim 1, wherein the bus control circuit and the external circuit are connected by a bus other than the common bus for communication. Bus control system. 8. A bus control circuit, which is connected to a plurality of processors through a common bus, acquires data required by the processor from an external circuit as necessary, and relays the data, wherein the data requested by the processor is transmitted to the external circuit. From the external circuit, the means for inhibiting access to the data by each processor, and the return with the instruction to release the access inhibition added to the data after the data requested by the processor is obtained from the external circuit. A bus control circuit comprising means for sending data to the common bus. 9. When obtaining the data requested by the processor from the external circuit, the access inhibition instruction of the data is sent to the common bus to inhibit the access to the data by each processor. 9. The bus control circuit according to claim 8, wherein: 10. A means for transmitting the return data, which is obtained by adding information for uniquely identifying the data to the data acquired from the external circuit, to the common bus, and is included in the return data for each processor. The information for uniquely identifying the data acquired from the external circuit is referred to, and the data acquired from the external circuit is determined to be the data requested by the processor itself and acquired. The bus control circuit according to claim 8 or 9. 11. The bus control circuit according to claim 10, wherein the information that uniquely identifies the data is an address of the data. 12. The bus control circuit according to claim 8, wherein a bus other than the common bus is used to connect to and communicate with the external circuit.