JP2003114266A - Input circuit monitoring transducer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transducer capable of monitoring an input circuit with high accuracy. SOLUTION: In the transducer with a CPU clock 10 having the input circuit 2 using an A/D converter 5 for converting an analog signal of a preset frequency into a digital signal, a test signal generation part 11 generates a digital test signal of a test frequency different from the preset frequency by dividing the frequency of a signal from the CPU clock 10, a waveform trimming circuit 12 converts it into an analog test signal and a superimposing part 3 superimposes it on an analog input signal. A generation part 13 generates a sampling signal for the A/D converter 5, of a frequency twice or more of the test frequency, by dividing the frequency of the signal from the CPU clock 10. An effective value for the test signal in the superimposed signal (the digital superimposed signal) after converted in the input circuit 2 is found by a first effective value computation part 14 and an effective value for the analog test signal after converted by the A/D converter 5 is found by a second effective value computation part 17, and the abnormality of the input circuit 2 is determined through the comparison of the outputs of both computation parts 14, 17 with each other by a determination part 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit monitoring type transducer, and more particularly to an input circuit monitoring type transducer used in a remote management control device for transmitting measurement data of an electric power system to a remote monitoring station, a command station or the like.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a measuring circuit transducer of a conventional remote monitoring and controlling apparatus for a power system. The transducer shown in the figure captures an analog measurement signal of the electric quantity of the power system from the input terminal 1, and the captured input signal is passed through an analog filter 34 to an A / D converter (hereinafter,
Sometimes referred to as an A / D converter. ) 35 to convert it to a digital signal, and the signal after digital conversion is input to the input signal calculator 37 via the digital filter 36, and the calculator 37
Calculates the measurement data necessary for monitoring and control, and transmits the calculation result from the output unit 38 to a remote monitoring station or the like.

In order to maintain the reliability of the transducer, it is necessary to inspect a circuit abnormality, and in particular, an analog filter 34 and an analog / digital converter 35 are included as compared with the digital filter 36 and the arithmetic unit 37 which are software processing. It is important to check the characteristics of input circuits for deterioration and defects. In FIG.
An input / test signal switching device 30 is provided between the input terminal 1 and the A / D converter 35, and the test signal switch 32 is made conductive during the inspection operation to apply the AC voltage of the test signal to the analog filter 34. The test signal processed by the analog filter 34, the A / D converter 35, the digital filter 36, and the input signal calculation unit 37 is input to the input circuit abnormality determination unit 39, and the abnormality determination unit 39 outputs a normal test signal. Check by judging whether or not. At times other than the inspection operation (normal operation), the test signal switch 32 of the signal switching device 30 is cut off and the input signal switch 31 is made conductive.

However, in the inspection method using the switching device 30, the normal operation by the input circuit must be interrupted when the input circuit is inspected, and in order to avoid the interruption of measurement, it is necessary to switch to the standby input circuit. Therefore, there is a problem that it takes time and labor. Further, it is difficult to find characteristic deterioration or the like that occurs during normal operation, and there is a risk that the measurement data may continue to be used with errors even during regular inspection.

In order to solve this problem, the present inventor has developed an analog input circuit monitor for continuously monitoring an analog input circuit, and disclosed it in Japanese Patent No. 2950818. Figure 4
In the monitoring device of the publication, the frequency of the analog input signal is N between the input terminal 1 and the analog filter 4.
A test signal superimposing unit 3 that continuously superimposes an analog test signal having a test frequency f _t different from a multiple (N is a natural number) on the input signal is provided, and the input signal after the test signal is superposed (hereinafter referred to as an analog superposed signal). ) Is input to the A / D converter 5 to be digitally converted, and the superposed signal after digital conversion (hereinafter referred to as a digital superposed signal) is input to the test signal separation unit 9 to separate the test signal component from the digital superposed signal. Then, the separated test signal is input to the input circuit abnormality determination section 18 to continuously monitor the abnormality of the analog input circuit. Reference numeral 6 in the figure indicates a digital filter for separating the input signal component from the digital superimposed signal.

According to the monitoring apparatus of FIG. 4, the normal operation by the input circuit and the inspection operation of the input circuit can be performed simultaneously and continuously, so that reliability can be improved by early detection of a circuit abnormality. Further, by superimposing a test signal having a frequency different from N times the frequency of the input signal, the Nth harmonic is erroneously detected as an abnormality of the input circuit even when the input signal includes the Nth harmonic of the fundamental wave. It is possible to monitor the input circuit with high accuracy without any fear of occurrence.

In the embodiment shown in FIG. 4, the test signal separating section 9
The first multiplier 19 ₁ multiplies the digital sine wave signal of the digital superimposed signal and the test frequency f _t, the second multiplier 19 ₂ which multiplies the digital cosine wave signal of the digital superimposed signal and the test frequency f _t, and the One multiplier 19 ₁ and second multiplier
19 ₂ and connected to the test signal is provided an effective value computing unit 23. To extract the component of the digital superimposed signal from the test signal represented by the following formula (1), while the second multiplier 19 ₂ by (1) and the digital cosine wave cos (omega _t t) and multiplying the (2 ) Is obtained, and in this case, the real part R of the test signal is obtained as the equation (3) by removing the terms other than the underlined terms in the equation (2) by the digital filter 22 ₂ which is a low-pass filter. In addition, the first multiplier 19 ₁ allows the equation (1) and the digital sine wave sin
(ωt _t ) is multiplied to obtain Eq. (4). In this case, the imaginary part of the test signal is removed by removing the terms other than the underlined terms in Eq. (4) by the digital filter 22 ₁ which is a low-pass filter. I is obtained as the equation (5). In the RMS calculator 23,
By substituting the real part R of the equation (3) and the imaginary part I of the equation (5) into the complex arithmetic expression of the equation (6), the effective value of the test signal component can be obtained.

On the other hand, the analog test signal is converted into an A / D converter 5
Directly input to and the effective value calculator 27 calculates the effective value of the converted digital test signal. Input circuit abnormality determination unit 18 in FIG.
Continuously monitors whether or not the analog input circuit is normal by comparing the effective values by the arithmetic units 23 and 27.

In the equations (1) to (6), V₁, ……,
V_NIs the amplitude of the fundamental wave and the Nth harmonic of the input signal, V_tIs an exam
Signal amplitude, θ₁, ……, θ_NIs the fundamental wave of the input signal and N
Initial phase of the second harmonic, θ_tIs the initial phase of the test signal and ω'is
Angular frequency of the fundamental wave of the input signal (ω '= 2πf', f'is the basic
Wave frequency. ), Ω_tIs the angular frequency of the test signal (ω_t= 2π
f _t, F_tIs the test frequency. ) Is shown.

[0010]

## EQU1 ## V (t) = V ₁ cos (ω't + θ ₁ ) ＋ …… ＋ V _N cos (Nω't + θ _N ) ＋ V _t cos (ω _t t + θ _t ) …… (1) cos (ω _t t) · V (t) = cos ( ω t t) {V 1 cos (ω't + θ 1) + ...... + V N cos (Nω't + θ N) + V t cos (ω t t + θ t)} = V 1/2 [ cos {(ω'−ω _t ) t ＋ θ ₁ } ＋ cos {(ω ′ ＋ ω _t ) t ＋ θ ₁ }] ＋ …… ＋ V _N / 2 [cos {(Nω'−ω _t ) t ＋ θ _N } + cos {(Nω '+ ω _t ) t ＋ θ _N }] ＋ V _t / 2 [cos {(ω _t −ω _t ) t ＋ θ _t } ＋ cos {(ω _t ＋ ω _t ) t ＋ θ _t }] …………………… (2) Real part R ＝ (V _t / 2) cos θ _t ………………………………………………………… (3) sin (ω _t t) ・ V (t) ＝ sin (ω _{t t) {V 1 cos (} ω't + θ 1) + ...... + V N cos (Nω't + θ N) + V t cos (ω t t + θ t)} = V 1/2 [sin {(ω '+ ω t) t + θ ₁ } −sin {(ω′−ω _t ) t ＋ θ ₁ }] ＋ …… ＋ V _N / 2 [sin {(Nω′−ω _t ) t ＋ θ _N } ＋ sin {(Nω ′ + ω _t ) t ＋ θ _N }] + V _{t / 2 [sin {(ω} t -ω t) t + θ t} + sin {(ω t + ω t) t + θ t}] ........................ (4) the imaginary part _{I = (V t / 2)} sinθ _t ............ ...................................................... (5) rms V / √2 = √ {(R 2 + I 2) × 2} ................................. ………………… (6)

[0011]

In the monitoring device of FIG. 4,
Separator 9 (or input signal calculator 7) as a test signal source
A rectangular wave signal generation unit 25 that generates a digital rectangular wave signal based on the test frequency f _t stored in the test frequency storage unit 24 of
And a sine wave shaping circuit 26 for inputting a digital rectangular wave signal and outputting an analog test signal.

However, in the monitoring device of FIG. 4, the test signal source is A
Since it is independent of the / D converter 5 and the timing of the sampling operation of the A / D converter 5 may not coincide with the clock of the test signal, there is a problem that an error may occur in the above-mentioned effective value calculation result. is there. For example, the angular frequency ω _t of the digital cosine wave cos (ω _t t) of the equation (2) is calculated by the test frequency storage unit 24
It is determined only by the test frequency f _t stored in
Since the angular frequency ω _t of the test signal in the digital superimposed signal V (t) from the converter 5 is determined by the sampling control signal of the A / D converter 5 (hereinafter sometimes referred to as a sampling signal), theoretically (Ω _t −ω _t ) in the underlined term in Eq. (2) should be zero, but if the timing of the sampling operation and the clock of the test signal do not match, they do not become zero and an error occurs. , Which causes a drop in monitoring accuracy.

When the test signal frequency is an integral multiple (for example, M times) of the sampling signal frequency, the effective value calculator 27 of FIG. The effective value of the digital test signal can be obtained by calculating the square root of the root mean square of the digital value. However, when the clock of the sampling signal of the A / D converter 5 and the clock of the test signal do not match, an error occurs in the effective value calculation result based on the continuous M digital values, which also deteriorates the monitoring accuracy. Cause.

Therefore, an object of the present invention is to provide an input circuit monitoring type transducer capable of monitoring the input circuit with high accuracy.

[0015]

With reference to the embodiment of FIG. 1, an input circuit monitoring type transducer of the present invention is an input circuit for converting an analog input signal of a predetermined frequency into a digital signal by an A / D converter 5. In a transducer with a CPU clock 10 having two CPU clocks 10
A test signal generator 11 for generating a digital test signal having a test frequency different from the predetermined frequency by dividing the signal of
A sine wave shaping circuit 12 for converting a digital test signal into an analog test signal, a test signal superimposing section 3 for continuously superimposing an analog test signal on an analog input signal, and twice the test frequency by dividing the CPU clock 10 signal. A sampling signal generator 13 for generating a sampling signal for the A / D converter 5 having the above frequency, and an input circuit 2 for the output of the superposing unit 3.
First effective value calculation unit 14 for obtaining the effective value of the test signal in the digital superposed signal after conversion by the analog test signal A
The abnormality of the input circuit 2 is determined by comparing the outputs of the second effective value calculation unit 17, which calculates the effective value of the digital test signal after conversion by the / D converter 5, and the first and second effective value calculation units 14 and 17. The determination unit 18 is provided.

Preferably, the sampling signal generating unit 13 generates a sampling signal of M times the test frequency (M is a natural number of 2 or more), and the second effective value calculating unit 17 generates M continuous digital test signals. The effective value of the test signal is calculated from the root mean square. More preferably, the test signal generating section 11 causes N of a predetermined frequency of the analog input signal.
A digital signal having a test frequency different from double (N is a natural number) is generated.

[0017]

1 shows an embodiment of an input circuit monitoring type transducer 40 of the present invention. In the illustrated example, the input circuit 2 including the analog filter 4 and the A / D converter 5 is shown. However, the input circuit 2 is the A / D converter 5
The configuration and the number of input signals of the input circuit 2 are not limited to the illustrated example. For example, the input circuit 2 may be provided with a multiplexer or the like.

According to the present invention, both the clock of the sampling signal of the A / D converter 5 and the clock of the digital test signal are generated by dividing the CPU clock 10 of the transducer. The digital test signal generator 11 generates a digital test signal having a test frequency different from the predetermined frequency of the analog input signal by dividing the signal of the CPU clock 10, and the sampling signal generator 13 divides the signal of the CPU clock 10 by A sampling signal having a frequency that is at least twice the test frequency is generated.

The digital test signal generated by the test signal generator 11 is sent to the sine wave waveform shaping circuit 12 to convert the digital test signal into an analog test signal. The converted analog test signal is sent to the test signal superposition unit 3 provided between the input terminal 1 and the input circuit 2 and between the input terminal 1 and the analog filter 4 in FIG. The test signal is continuously superimposed. The analog superimposed signal on which the test signal is superimposed is input to the input circuit 2, processed by the analog filter 4 which is, for example, a low-pass filter, and then converted into a digital signal by the A / D converter 5.

The frequency of the test signal is selected as far as possible from the frequency of the input signal in order to facilitate separation from the input signal. Preferably, the frequency of the test signal is different from N times (N is a natural number) the predetermined frequency of the analog input signal. Even if the input signal contains the Nth harmonic of the fundamental wave, by setting the test signal to a frequency different from N times the frequency of the fundamental wave, it is impossible to separate the input signal and the test signal from each other. Since interference is avoided and there is no possibility that the Nth harmonic is erroneously detected as an abnormality in the input circuit, it is possible to monitor the input circuit with high accuracy.

For example, the analog input signal is used as a measurement signal of the voltage amount, current amount, etc. of the power system, and the CPU clock is 18.432.
If it is a MHz, when the fundamental frequency 50Hz and a frequency of the test signal ^{320Hz (= 18.432 × 10 6/} 57600), the frequency of the test signal when the fundamental frequency 60Hz 384Hz (= 18.
432 × can be 10 ^6/48000). If the input signal may also include subharmonics of the 1 / Nth order (N is a natural number of 2 or more) of the fundamental wave, the frequency f of the test signal
_t can be different from 1 / N times the fundamental frequency of the input signal.

On the other hand, the sampling signal generated by the sampling signal generator 13 is input to the A / D converter 5 of the input circuit 2. By setting the frequency of the sampling signal to be at least twice the frequency of the analog superimposed signal, that is, the frequency of the input signal and the test signal, the sampling theory
Based on the above, the waveform of the analog superimposed signal can be reproduced from the converted digital superimposed signal. Preferably, the frequency of the sampling signal is M times the test frequency (M is a natural number of 2 or more) in order to facilitate the calculation of an effective value described later.
same as below. ). For example, as described above, the CPU
If the clock is 18.432MHz, the test signal frequency is 3
The sampling signal frequency is 4800 Hz (= 1 for 20 Hz)
And ^{8.432 × 10 6/3840 = 320} × 15), the frequency of the test signal 3
The sampling signal frequency is 5,760 Hz (= 1 for 84 Hz)
It can be ^{8.432 × 10 6/3200 = 384} × 15).

The digital superimposed signal is input to the input signal separating unit 6, and the input signal separating unit 6 separates the input signal component from the digital superimposed signal. An example of the input signal separation unit 6 is a digital filter such as a band-elimination filter or a low-pass filter that blocks the test frequency component of the digital superimposed signal and passes the other components without attenuating. By extracting only the input signal component in the separating unit 6, the input signal calculating unit 7 can perform the arithmetic processing on the input signal while avoiding the influence of the test signal. The calculation result of the calculation unit 7 can be transmitted from the output unit 8 to a remote monitoring station or the like, as in the case of FIGS.

Further, the digital superimposed signal is input to the first effective value calculating unit 14, and the first effective value calculating unit 14 calculates the effective value of the test signal in the digital superimposed signal. The calculation unit 14 in the illustrated example includes a test signal separation unit 15 that separates the test signal component from the digital superimposed signal, and a calculation unit 16 that calculates the effective value of the separated test signal. An example of the test signal separation unit 15 is a digital bandpass filter that passes the test frequency component of the digital superimposed signal without attenuating it and blocks the other components. When the frequency of the sampling signal is M times the test frequency, the calculation unit 16
The effective value of the test signal can be calculated from the M root mean squares that are consecutive. However, the method of calculating the effective value in the calculation unit 16 is not limited to this example. The calculated effective value is input to the input circuit abnormality determination unit 18.

Furthermore, the analog test signal output from the sine wave waveform shaping circuit 12 is directly input to the A / D converter 5, and the effective value of the digital test signal by the A / D converter 5 of the directly input test signal is determined by (2) Calculated by the effective value calculation unit 17. When the frequency of the sampling signal is M times the test frequency, the effective value of the digital test signal can be calculated by the arithmetic unit 17 from the M mean squares that are consecutive. However, the calculation unit 17
The method of calculating the effective value in is also not limited to this method. The execution value calculated by the second effective value calculation unit 17 is also input to the abnormality determination unit 18.

In the abnormality judging section 18, the abnormality of the input circuit 2 is judged by comparing the calculation results of the first and second effective value calculating sections 14 and 17. According to the abnormality determination method by comparing the test signal converted by the input circuit 2 with the test signal simply digitally converted, even if the input signal becomes unstable for some reason, there is no possibility of erroneous determination as a circuit abnormality, and the circuit abnormality Higher accuracy of judgment can be achieved. When the abnormality determination unit 18 detects an abnormality, the abnormality determination signal can be transmitted to, for example, a remote monitoring station.

The A / D converter 5 shown in FIG. 1 digitally converts two or more analog signals including, for example, an analog superimposed signal and an analog test signal, in parallel at the same sampling frequency and the same number of quantization bits. It has two or more processing routes. Or A / D converter 5,
Two or more sample and hold circuits for inputting analog signals, a multiplexer for inputting output signals of each sample and hold circuit, and selectively outputting any one of them, a quantizer for quantizing the output signal of the multiplexer, and a quantizer You may have an encoder which converts an output signal into a code sequence.

According to the present invention, the clock of the sampling signal of the A / D converter 5 and the clock of the digital test signal can be perfectly matched, so that the occurrence of an error due to the mismatch of both clocks can be avoided. it can. Further, by accurately setting the frequency of the sampling signal to M times the test frequency, it is possible to always calculate the ideal effective value of the test signal from the root mean square of M consecutive values in the effective value calculation units 14 and 17. Therefore, the accuracy of the input circuit monitoring can be further improved. Further, according to the present invention, even if the accuracy of the circuit for generating the clock of the CPU is deteriorated due to the environmental change or the deterioration of the parts, the continuous monitoring of the accurate input circuit can be continued without being affected.

Thus, the "input circuit monitoring type transducer capable of monitoring the input circuit with high accuracy" which is the object of the present invention.
Can be achieved.

[0030]

FIG. 2 shows a first effective value calculation unit 14 for the first multiplier 19 _{1 for} the digital superimposed signal and the digital sine wave sin (ω _t t) signal shown in FIG. shows an embodiment in which a second multiplier 19 _2, and the first multiplier 19 ₁ and the effective value computing unit 23 connected to the second multiplier 19 ₂ of the cosine wave cos (ω _{t t)} signal. In the present invention, the timing of the sampling operation of the A / D converter 5 is matched with the clock of the test signal, and the angular frequency ω of the test signal in the digital superposition signal V (t) is
_{Since t} and the angular frequency ω _{t of the} digital sine wave and cosine wave can always be made to coincide with each other, it is possible to obtain an accurate effective value of the test signal by the arithmetic unit 23 using the above equations (2) to (5). Is.

[0031] Figure 3 shows an embodiment of an input circuit monitoring transducer of the present invention having a plurality of input circuits 2 ₁ to 2 ₆ for converting a plurality of analog signals into digital signals. The transducer of the embodiment has a plurality of input circuits 2 ₁
Corresponding to 2 to ₂₆ , a plurality of pairs of test signal superimposing sections 3 _{1 to} 3 ₆ and first effective value calculating sections 14 _{1 to} 14 ₆ are provided. A / D in the figure
Converter 5, a plurality of sample-and-hold circuits 28 ₁ to 28 ₆ for sampling according to the output of a plurality of superposed portions 3 ₁ to 3 ₆ to the sampling signal of the sampling signal generator 13, the sample-and-hold circuits 28 ₁ to 28 An input selection unit (not shown) for selectively inputting the output of ₆ to the A / D converter 5 and a digital superposition signal after conversion by the A / D converter 5 are superposed in conjunction with the selection of the input selection unit. 1st RMS value calculation part corresponding to parts 3 _{1 to} 3 ₆
It has 14 output selector for outputting to _{1-14 6} (not shown). An example of the input selection unit is a multiplexer that selects and outputs one from a plurality of input signals according to a control signal, and an example of the output selection unit selects one from a plurality of outputs according to the control signal. A demultiplexer that outputs an input signal.

Most of the conventional transducers are an analog type of one unit / one measurement according to the measurement item, and as the number of analog input signals to be measured increases, the area of the measurement rack for accommodating the transducer increases and the cost increases. It was a factor. According to the embodiment shown in FIG. 3, since a plurality of analog input signals can be processed and transmitted by a single transducer, the accommodation area can be greatly reduced.
Further, since a plurality of input circuits 2 ₁ to 2 ₆ property degradation or the like can respectively continuously monitored to discover characteristics deterioration at an early stage, it is possible to avoid the operation while the error has occurred.

Further, the analog input signal of the transducer shown in FIG.
The input signal separation unit 6 which is, for example, a digital filter including the linear phase voltages V1, V2, V3 and the phase currents I1, I2, I3
The input signal component is separated from each digital superposed signal by (see FIG. 1), and various measurement data necessary for remote monitoring of the power system based on the digital input signal of the voltage amount and the power amount after separation in the arithmetic processing unit 7, For example, various electric quantities such as active power, reactive power, voltage, and current can be calculated, so that a so-called multi-transducer that obtains a plurality of measurement data from the minimum input electric quantity can be realized. In this case, it is possible to increase or select the types of measurement data as needed, and it is possible to efficiently use the transducer. The measurement data can be digitally transmitted from the output unit 8 to a remote monitoring station or the like, and the measurement accuracy can be maintained by omitting the A / D conversion process on the receiving side.

[0034]

As described in detail above, the input circuit monitoring type transducer of the present invention generates a test frequency different from the predetermined frequency by dividing the CPU clock signal and converts the analog test signal of the test frequency into an analog signal. It is continuously superimposed on the input signal and input to the analog input circuit with the A / D converter of the transducer, and the sampling signal for the A / D converter is generated at a frequency more than twice the test frequency by dividing the CPU clock signal. However, since the abnormality of the input circuit is determined based on the effective value of the test signal in the digital superposed signal converted by the sampling signal, the following remarkable effects are obtained.

(B) Since the deterioration of the performance of the input circuit of the transducer can be monitored continuously and with high accuracy, the reliability of the transducer can be improved. (B) Since the clock of the sampling signal of the A / D converter and the clock of the digital test signal are made to completely coincide with each other, the occurrence of a calculation error of the effective value due to the disagreement of both clocks is avoided, and the accuracy of the input circuit monitoring is improved. Can be realized. (C) Since the frequency of the sampling signal can be exactly M times the test frequency, it is possible to accurately calculate the effective value of the test signal by a simple calculation process. (D) Even if the accuracy of the CPU clock circuit deteriorates due to environmental changes or component deterioration, accurate input circuit monitoring can be continued without being affected.

(E) By making the frequency of the test signal different from N times the predetermined frequency of the input signal (N is a natural number), even if the input signal includes the Nth harmonic,
It is possible to perform high-precision continuous monitoring of the input circuit while avoiding the influence of the second harmonic. (F) Since a plurality of input circuits are provided and each input circuit can be continuously monitored, the accommodation area can be significantly reduced as compared with the conventional single / measuring type transducer. (G) A multi-transducer that obtains a large number of measurement data from a minimum input signal by including the voltage amount and current amount of each phase of the power system in the input signal and calculating various measurement data necessary for digital arithmetic processing. realizable. (H) Since the work of switching between the input signal and the test signal is not necessary, the labor and labor for the inspection operation of the analog input circuit can be significantly reduced. (I) No need for switching device between input signal and test signal,
The input circuit monitoring device may have no moving parts.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the present invention.

FIG. 3 is a block diagram of still another embodiment of the present invention.

FIG. 4 is a block diagram of an example of a conventional analog input circuit monitoring device.

FIG. 5 is a block diagram of a conventional switching type analog input circuit monitoring device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal 2 ... Input circuit 3 ... Test signal superposition circuit 4 ... Analog filter 5 ... A / D converter 6 ... Input signal separation part 7 ... Input signal calculation part 8 ... Output part 9 ... Test signal separation part 10 ... CPU Clock 11 ... Test signal generator 12 ... Sine wave shaping circuit 13 ... Sampling signal generator 14 ... First effective value calculator 15 ... Test signal separator 16 ... Effective value calculator 17 ... Second effective value calculator 18 ... Input Circuit abnormality determination unit 19 ... Multiplier 20 ... Cosine wave generator 21 ... Sine wave generator 22 ... Digital filter 23 ... Effective value calculator 24 ... Test frequency storage unit 25 ... Digital rectangular wave signal generation unit 26 ... Sine wave waveform shaping Circuit 27 ... Effective value calculator 28 ... Sampling hold circuit 30 ... Input / test signal switching device 31 ... Input signal switch 32 ... Test signal switch 33 ... Test signal source 34 ... Analog filter 35 ... A / D converter 36 ... Digital filter 37 ... Input signal calculator 38 Output unit 39 ... input circuit abnormality determining unit 40 ... input circuit monitoring transducer

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H02H 3/05 H02H 3/05 L H03M 1/10 C H03M 1/10 G01R 31/28 C (72) Invention Hiroshi Ishikawa 2-9-20 Shirako, Wako-shi, Saitama O-term Denki Co., Ltd. F-term (reference) 2F073 AA01 AA19 AB02 AB07 BC01 CC01 CD22 EE01 FG04 GG01 2G036 AA24 BA34 CA06 2G132 AA11 AB01 AD01 AE06 AE14 AG08 AL11 5A02 FF25 FF26 GG02 GG08 5J022 AA01 CA07 CA10 CC03 CD06 CE01 CF08 CF10

Claims (7)

[Claims] 1. A transducer with a CPU clock having an input circuit for converting an analog input signal of a predetermined frequency into a digital signal by an A / D converter, wherein the C
A test signal generator for generating a digital test signal having a test frequency different from the predetermined frequency by dividing the PU clock signal, a sine wave waveform shaping circuit for converting the digital test signal into an analog test signal, and the analog test signal A test signal superimposing section that continuously superimposes on an analog input signal, a sampling signal generating section that generates a sampling signal for the A / D converter having a frequency that is at least twice the test frequency by dividing the CPU clock signal, and the superimposing section. A first effective value calculation unit for obtaining an effective value of a test signal in the digital superposed signal after the conversion of the output of the section by the input circuit, an effective of the digital test signal after conversion of the analog test signal by the A / D converter. A second effective value calculation unit for obtaining a value, and a comparison of the outputs of the first and second effective value calculation units Input circuit monitoring transducer consisting includes a determination unit for determining normal. 2. The transducer according to claim 1, wherein the sampling signal generating section generates a sampling signal of M times the test frequency (M is a natural number of 2 or more), and the second effective value calculating section outputs the digital signal. An input circuit monitoring type transducer that calculates the effective value of the test signal from the root mean square of M consecutive test signals. 3. The transducer according to claim 2, wherein the first effective value calculating section includes a test signal separating section for separating a test signal component from the digital superimposed signal, and M consecutive squares of the separated test signal. An input circuit monitoring type transducer comprising an arithmetic unit for calculating an effective value of the test signal after separation from an average. 4. The transducer according to claim 1 or 2, wherein the first effective value computing unit obtains a product of the digital superimposed signal and a sine component of the digital test signal, and the digital multiplying unit. A second multiplication unit that obtains a product of a superimposed signal and a cosine (cos) component of the digital test signal, and an arithmetic unit that obtains an effective value of the test signal in the digital superimposed signal from outputs of the first and second multipliers. Input circuit monitoring type transducer. 5. The input circuit according to claim 1, wherein the test signal generator generates a digital signal having a test frequency different from N times the predetermined frequency (N is a natural number). Supervised transducer. 6. The transducer according to claim 1, wherein a plurality of input circuits for converting the plurality of analog signals into digital signals, respectively, and the test signal superposition provided corresponding to the plurality of input circuits. And a plurality of sample hold circuits for sampling the outputs of the plurality of superimposing sections in accordance with the sampling signals in the A / D converter, and a plurality of sample and hold circuits. And an input selection unit for selectively inputting the output of the above into the A / D converter, and a digital superimposition signal converted by the A / D converter in association with the selection of the input selection unit, corresponding to the superposition unit. An input circuit monitoring type transducer provided with an output selection section for outputting to a first effective value calculation section. 7. The transducer according to claim 6, wherein the input signal includes an analog measurement signal of a voltage amount and a power amount of an electric system and separates an input signal component from the digital superimposed signal, and a voltage after the separation. An input circuit monitoring type transducer provided with an arithmetic processing unit for calculating measurement data for remote monitoring of a power system based on a digital input signal of the amount of electricity and electric power, and an output unit for transmitting the calculated measurement data to a remote monitoring place.