JP2003110115A - Tft evaluation structure and tft evaluation method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT evaluation structure which readily enables the type discrimination of a channel region formed in an intrinsic semiconductor for TFT and enables the evaluation of an interfacial level density of the TFT. SOLUTION: The TFT evaluation structure for evaluating a thin film transistor is provided with a source electrode and a drain electrode which are disposed, respectively, on both sides of the intrinsic semiconductor formed on an insulating substrate, and a gate electrode which is disposed faced with the intrinsic semiconductor with a gate insulating film interposed therebetween. An N-type semiconductor and a P-type semiconductor are provided facing the thin film transistor so as to fix the substrate potential in the channel region which is formed in the intrinsic semiconductor at the time of applying a voltage on the gate electrode, while constituting a diode of the N-type semiconductor - intrinsic semiconductor - P-type semiconductor.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a TFT evaluation structure for evaluating a thin film transistor and an evaluation method used for the structure.

[0002]

2. Description of the Related Art As is well known, in semiconductor manufacturing technology, various elements such as circuit performance evaluation, structural design evaluation, manufacturing process evaluation, material evaluation, and electrical property evaluation are used to make elements, structures, or circuits that constitute a semiconductor device. By setting a TEG (Test Element Group) that is separated and independent at a single level and evaluating the quality of the configuration for each TEG, it is possible to facilitate evaluation of the entire device and response to defective TEGs. .

In FIGS. 7 and 8, for example, a conventional TEG composed of a thin film transistor (hereinafter referred to as TFT) unit used as a switching element for driving a liquid crystal cell, for example.
Represents the structure. FIG. 7 shows a TEG pattern structure, while FIG. 8 is a diagram schematically showing a cross-sectional structure in which contact portions of external terminals with respect to electrodes in the TFT are collectively shown on one plane.

The TFT which constitutes the TEG 50 is a TFT (so-called polysilicon TFT) which employs thin film polysilicon directly provided on a substrate as a semiconductor for forming a channel region. In the TFT, an intrinsic semiconductor layer 55 is provided on the glass substrate 54, and N + -type LDD layers 56A and 56B are provided on both sides of the intrinsic semiconductor layer 55 to provide N +.
Semiconductor layers 57A and 57B are provided. As external terminals, a gate terminal 51, an N-type source terminal 52, and an N-type drain terminal 53 are provided, and the gate terminal 51 is
Gate electrode 58 provided corresponding to the intrinsic semiconductor layer 55
The N-type source terminal 52 and the N-type drain terminal 53 are connected to the N + semiconductor layers 57A and 57B, respectively.

By the way, in recent years, as the miniaturization of polysilicon TFTs has advanced along with the higher definition of liquid crystal displays, it is important to evaluate each TEG with high precision in order to secure the yield and reliability of the products. In order to realize this, it is necessary to accurately grasp the characteristics and quality of the configuration included in the TEG.

[0006] In the structure of TEG50 shown in FIGS. 7 and 8, the quality evaluation of the TFT, for example, it is performed on the basis of electrical characteristics, such as _I D -V _G characteristics and _I D -V _D characteristic.
I _D is the current flowing through the N-type drain terminal 53, V _G is the voltage applied to the gate terminal 51, and V _D is the drain terminal 53.
Represents the voltage applied to. Further, the determination of the P-type or N-type of the channel region formed in the intrinsic semiconductor layer 55 when the gate voltage is applied is based on the fact that the temperature characteristics are evaluated, and FEC (Forward Error Correction:
Or using a forward error correction) method, performed by or calculated trap level from the sub-threshold swing evaluation in I _D -V _G characteristics evaluation.

[0007]

However, in the conventionally known structure of the TEG 50, the type of the channel region formed in the intrinsic semiconductor layer 55 is determined by the influence of extremely minute impurity contamination, fixed charges, etc., that is, There is a problem that it is difficult to discriminate between the N-type semiconductor and the P-type semiconductor. Further, when the intrinsic semiconductor layer 55 is thin-film polysilicon, there is a problem that it is difficult to accurately evaluate the interface state density between the glass substrate 54 and the intrinsic semiconductor layer 55. Furthermore, in this case, it is difficult to evaluate the interface state density and the bulk trap level, and
There is a problem that it is difficult to measure the minority carrier lifetime with good sensitivity.

The present invention has been made in view of the above technical problems, and facilitates the determination of the type of a channel region formed in an intrinsic semiconductor and the evaluation of the interface state density between the glass substrate and the intrinsic semiconductor. It is an object to provide a semiconductor device with a possible TEG structure.

[0009]

According to a first aspect of the present invention, a source electrode and a drain electrode provided on both sides of an intrinsic semiconductor formed on an insulating substrate, and a gate insulating film corresponding to the intrinsic semiconductor are provided. In a TFT evaluation structure for evaluating a thin film transistor having a gate electrode provided via a diode, a diode in which an N-type semiconductor and a P-type semiconductor are N-type semiconductor-intrinsic semiconductor-P-type semiconductor is added to the thin film transistor. It is characterized in that it is provided so that the substrate potential of the channel region formed in the intrinsic semiconductor can be fixed when a voltage is applied to the gate electrode.

The invention according to claim 2 of the present application is the substrate for a channel region formed in the intrinsic semiconductor when a voltage is applied to the gate electrode in the TFT evaluation method using the TFT evaluation structure according to claim 1. Potential
Fixing in each region of the P-type semiconductor and the N-type semiconductor, applying a bias voltage to the diode composed of the N-type semiconductor-intrinsic semiconductor-P-type semiconductor, and based on the band gap of the diode, the N-type of the channel region. Alternatively, it is characterized by discriminating the P-type.

Further, in the invention according to claim 3 of the present application, in the TFT evaluation method using the TFT evaluation structure according to claim 1, the terminals connected to the P-type semiconductor and the N-type semiconductor are respectively used as reverse bias terminals. Connect to the variable voltage source after short-circuiting the terminals connected to the source electrode and the drain electrode, and apply a predetermined pulse voltage to the gate electrode while monitoring the charge pumping current at the reverse bias terminal. Then, the interface state density of the TFT is evaluated based on the charge pumping current.

[0012]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following, as a TFT that constitutes the TEG to be evaluated, S
A case where a polysilicon TFT which is an OI (Silicon on Insulator) type transistor is adopted will be described.
However, the TFT is not limited to the type of polysilicon TFT, and any type may be adopted as appropriate.

FIG. 1 shows a TFT according to an embodiment of the present invention.
FIG. 2 shows a pattern structure of the TEG 10 constituted by a unit, and FIG. 2 schematically shows a cross-sectional structure in which the connecting portions of the three terminals with respect to the internal electrodes in the TFT are collectively shown on one plane. In the TFT that constitutes the TEG 10,
The intrinsic semiconductor layer 2 is directly formed on the glass substrate 1 which is an insulating substrate. The intrinsic semiconductor layer 2 forms a channel region when a gate voltage higher than a predetermined level is applied.

Further, on the glass substrate 1, along the pair of side surfaces of the intrinsic semiconductor layer 2 (the surface along the longitudinal direction of the intrinsic semiconductor layer 2 in FIG. 1), the N-type lightly doped drain layer (hereinafter , N-type LDD layers) 3A, 3B are provided, and N + semiconductor layers 4A, 4B are provided outside the N-type LDD layers 3A, 3B. N + semiconductor layer 4
In this TFT, A and 4B form a source electrode and a drain electrode, respectively. Furthermore, on the glass substrate 1, the intrinsic semiconductor layer 2, the N-type LDD layers 3A, 3B, and N.
A gate insulating film 5 is formed so as to cover + semiconductor layers 4A and 4B.

A gate electrode 6 is provided on the gate insulating film 5 at a portion corresponding to the intrinsic semiconductor layer 2 below the film. An interlayer insulating film 8 is formed on the gate insulating film 5 so as to cover the gate electrode 6.

As is clear from FIG. 2, in this polysilicon TFT, the gate terminal 11 is connected to the gate electrode 6 through the interlayer insulating film 8 by forming the contact hole 11a. The N-type source terminal 12 and the N-type drain terminal 13 are connected to the N + semiconductor layers 4A and 4B through the interlayer insulating film 8 and the gate insulating film 5 by forming the contact holes 12a and 13a, respectively. . The gate terminal 11, the N-type source terminal 12, and the N-type drain terminal 13 are exposed to the outside on the upper side of the interlayer insulating film 8.

As can be seen from FIG. 1, the TEG 10 according to this embodiment further has N along the pair of side surfaces of the intrinsic semiconductor layer 2 (in FIG. 1, the surface along the width direction of the intrinsic semiconductor layer 2). A mold substrate potential extracting layer 21 and a P type substrate potential extracting layer 22 are provided. An N-type substrate potential extracting terminal 23 and a P-type substrate potential extracting terminal 24 are provided corresponding to these layers 21 and 22, and the N-type substrate potential extracting terminal 23 and the P-type substrate potential extracting terminal 24 are provided in the contact hole 23a. And 24a are connected to the N-type semiconductor layer potential extracting layer 21 and the P-type semiconductor layer potential extracting layer 22, respectively, through the interlayer insulating film 8 and the gate insulating film 5. Although not shown in particular, the N-type substrate potential extracting terminal 23 and the P-type substrate potential extracting terminal 24 are
Both are exposed to the outside on the upper side of the interlayer insulating film 8.

As described above, in the TEG 10, the polysilicon TFT is formed by providing the N + semiconductor layers 4A and 4B forming the source region and the drain region on both sides of the intrinsic semiconductor layer 2 forming the channel region. At the same time, the N-type substrate potential extracting layer 21 and the P-type substrate potential extracting layer 22 are provided on both sides of the intrinsic semiconductor layer 2 in the direction orthogonal to the direction of the N + semiconductor layer 4A-intrinsic semiconductor layer 2-N + semiconductor layer 4B. As a result, a pin diode is formed. Then, the terminals (5) corresponding to each layer are provided so as to be exposed to the outside.

With such a structure of the TEG 10, it is possible to take out the substrate potential of the intrinsic semiconductor layer 2 regardless of whether it is of N type or P type. A method of evaluating the substrate potential of the intrinsic semiconductor layer 2 will be described with reference to FIG. First, the N-type substrate potential extracting terminal 23 is connected to the constant voltage source 25, and the P-type substrate potential extracting terminal 24 is grounded. In this state, from the constant voltage source 25 to the N-type substrate potential extraction terminal 23, a voltage of -15 V to +15
By sequentially applying a voltage of about V, the N-type substrate potential extraction layer 2
1, the electrical characteristics (IV characteristics) of the pin diode composed of the intrinsic semiconductor layer 2 and the P-type substrate potential extraction layer 22 are evaluated.

FIGS. 4 and 5 show the N-type substrate potential extracting layer 21, the intrinsic semiconductor layer 2 and the P-type substrate potential extracting layer 22, respectively, when the intrinsic semiconductor layer 2 is made of an N-type or P-type semiconductor. The band gap of the configured pin diode is shown. 4 and 5, Ec
And Ev represent the energy level at the bottom of the conduction band and the top of the full band, respectively, and Ef represents the Fermi level.

First, when the intrinsic semiconductor layer 2 is made of an N-type semiconductor, there is no potential barrier between the intrinsic semiconductor layer 2 (N-) and the N-type substrate potential extraction layer 21, as shown in FIG.
Between the N-type intrinsic semiconductor layer 2 and the P-type substrate potential extraction layer 22, breakdown of the P + / N- junction occurs.

On the other hand, when the intrinsic semiconductor layer 2 is made of a P-type semiconductor, as shown in FIG. 5, the P-type substrate potential extracting layer 22 is formed.
There is no potential barrier between the intrinsic semiconductor layer 2 and the intrinsic semiconductor layer 2, and the intrinsic semiconductor layer (P-) that is P-type and the P-type of the N-type semiconductor layer.
Breakdown occurs at the N + junction.

As can be seen by comparing the band gaps shown in FIGS. 4 and 5, the two junction breakdown voltages are very different. Therefore, the intrinsic semiconductor layer 2 is N-type or P-type by utilizing this difference in the junction breakdown voltage. It becomes possible to judge whether. In addition, when light emission analysis is performed using a photoelectron emission microscope, the potential barrier portion shown in FIGS. 4 and 5 becomes clear in the vicinity of the breakdown voltage, which can be confirmed by this method.

Next, with reference to FIG. 6, a method of evaluating the interface state density of the TFT will be described. In this evaluation method, first, the N-type substrate potential extracting terminal 23 and the P-type substrate potential extracting terminal 24 are short-circuited and connected to a reverse bias terminal (not shown) via the constant voltage source 25. Further, the source terminal 12 and the drain terminal 13 are short-circuited and connected to the variable voltage source 26. Further, the gate terminal 11 is connected to the pulse voltage source 27.

In the evaluation of the interface state density, a variable voltage is applied to the N + source terminal 12 and the N + drain terminal 13 and the gate terminal 11 is -6 [V] to 6 [V].
With the pulse voltage of about 1 [KHz] to 1 [MHz] applied, the charge pumping method is used to observe the charge pumping current at the reverse bias terminal. In this charge pumping method, by applying a pulse voltage to the gate electrode 6 of the polysilicon TFT, electrons and holes are alternately injected into the interface of the intrinsic semiconductor layer 2 and recombined via the interface level. Measure the current that sometimes occurs. Then, the interface state density is evaluated from this charge pumping current.

As described above, in the TEG 10, the N-type substrate potential extracting layer 21 and the P-type substrate potential extracting layer 22 are provided on both sides of the intrinsic semiconductor layer 2 which constitutes the polysilicon TFT, thereby forming a pin diode. It is possible to easily determine whether the channel region formed in the intrinsic semiconductor layer 2 is of P type or N type. In addition, the substrate potential of the intrinsic semiconductor layer 2 can be fixed by the N-type substrate potential extracting layer 21 and the P-type substrate potential extracting layer 22, and the interface state density can be evaluated by using the charge pumping method.

In this case, in addition to the evaluation of the interface state density using the charge pumping method, FEC, Levis
It is possible to evaluate the bulk trap level by the on method. Further, in the case of evaluating the pin diode, after fixing the source potential and the drain potential of the polysilicon TFT to the ground potential, light is applied to the point selected by the slit with respect to the channel region formed in the intrinsic semiconductor layer 2. Irradiation can be performed to measure minority carrier lifetime with high sensitivity.

Needless to say, the present invention is not limited to the illustrated embodiments, and various improvements and design changes can be made without departing from the gist of the present invention.

[0029]

As is apparent from the above description, according to the invention of claim 1 of the present application, the source electrode and the drain electrode provided on both sides of the intrinsic semiconductor formed on the insulating substrate, and the intrinsic semiconductor. In a TFT evaluation structure for evaluating a thin film transistor provided with a gate electrode provided via a gate insulating film corresponding to, an N-type semiconductor and a P-type semiconductor are added to the thin film transistor, and an N-type semiconductor-intrinsic semiconductor- Since a diode made of a P-type semiconductor is formed, the substrate potential of the channel region formed in the intrinsic semiconductor can be fixed when a voltage is applied to the gate electrode. The type of the channel region can be easily discriminated. Further, it is possible to evaluate the interface state density by fixing the substrate potential with N-type and P-type semiconductors and using the charge pumping method.

Further, according to the invention of claim 2 of the present application, the substrate potential of the channel region formed in the intrinsic semiconductor when the voltage is applied to the gate electrode is set to the respective regions of the P-type semiconductor and the N-type semiconductor. Then, a bias voltage is applied to the diode made of the N-type semiconductor-intrinsic semiconductor-P-type semiconductor, and the type of the channel region can be easily determined based on the band gap of the diode.

Further, according to the invention of claim 3 of the present application, the terminals connected to the P-type semiconductor and the N-type semiconductor are respectively connected to the reverse bias terminals, and the terminals connected to the source electrode and the drain electrode. Is connected to a variable voltage source after short-circuiting, the charge pumping current is monitored at the reverse bias terminal while applying a predetermined pulse voltage to the gate electrode, and the interface level of the TFT is based on the charge pumping current. The density can be easily evaluated.

[Brief description of drawings]

FIG. 1 is a polysilicon TF according to an embodiment of the present invention.
It is a top view which shows the pattern structure of T.

FIG. 2 is an explanatory diagram showing a cross-sectional structure of the polysilicon TFT.

FIG. 3 is an explanatory diagram showing a method of discriminating a type of a channel region formed in an intrinsic semiconductor layer of the polysilicon TFT.

FIG. 4 is an explanatory diagram showing a band gap when the type of a channel region formed in the intrinsic semiconductor layer of the polysilicon TFT is N type.

FIG. 5 is an explanatory diagram showing a band gap when the type of a channel region formed in the intrinsic semiconductor layer of the polysilicon TFT is P type.

FIG. 6 is an explanatory diagram showing a method of evaluating an interface state density of the polysilicon TFT.

FIG. 7 is a plan view showing a pattern structure of a conventional polysilicon TFT.

FIG. 8 is an explanatory diagram showing a cross-sectional structure of a conventional polysilicon TFT.

[Explanation of symbols]

1 ... Glass substrate 2 ... Intrinsic semiconductor layer 3A, 3B ... N-type LDD layer 4A, 4B ... N + semiconductor layer 5 ... Gate insulating film 6 ... Gate electrode 8 ... Interlayer insulating film 11 ... Gate terminal 12 ... Source terminal 13 ... Drain terminal 11a, 12a, 13a ... Contact holes 21 ... N-type substrate potential extraction layer 22 ... P-type substrate potential extraction layer 23 ... N-type substrate potential extraction terminal 24 ... P type substrate potential output terminal 23a, 24a ... Contact holes 25 ... Constant voltage source 26 ... Variable voltage source 27 ... Pulse voltage source

Claims (3)

[Claims] 1. A thin film transistor having a source electrode and a drain electrode provided on both sides of an intrinsic semiconductor formed on an insulating substrate, and a gate electrode provided corresponding to the intrinsic semiconductor via a gate insulating film is evaluated. TF for
In the T evaluation structure, an N-type semiconductor and a P-type semiconductor are formed in an intrinsic semiconductor when a voltage is applied to the gate electrode, while forming an N-type semiconductor-intrinsic semiconductor-P-type semiconductor diode with respect to the thin film transistor. A TFT evaluation structure, which is provided so as to fix the substrate potential of a channel region to be formed. 2. The TFT evaluation method using the TFT evaluation structure according to claim 1, wherein the substrate potential of a channel region formed in the intrinsic semiconductor when the voltage is applied to the gate electrode is the P
The semiconductor device is fixed in each region of the N-type semiconductor and the N-type semiconductor, a bias voltage is applied to the diode composed of the N-type semiconductor-intrinsic semiconductor-P-type semiconductor, and the N-type or P-type of the channel region is determined based on the band gap of the diode. A TFT evaluation method characterized by determining the type of mold. 3. The TFT evaluation method using the TFT evaluation structure according to claim 1, wherein the terminals connected to the P-type semiconductor and the N-type semiconductor are respectively connected to a reverse bias terminal, and the source electrode and the drain electrode are connected to each other. Connected to a variable voltage source after short-circuiting the connected terminals, while applying a predetermined pulse voltage to the gate electrode, monitor the charge pumping current at the reverse bias terminal, based on the charge pumping current, A TFT evaluation method characterized by evaluating the interface state density of a TFT.