JP2003108441A - Secret data processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an excellent secret data processing circuit having an extremely high security of secret data. SOLUTION: This secret data processing circuit comprises a data processing circuit block 2 for performing a specified data processing, a calculation circuit block 1 for transferring the secret data or non-secret data to the data processing circuit block 2, a non-secret data-dedicated bus line 8 installed between the calculation circuit block 1 and the data processing circuit block 2 for transferring the non-secret data to the data processing circuit block 2, and a single secret data-dedicated bus line 7 installed between the calculation circuit block 1 and the data processing circuit 2 for transferring the non-secret data-dedicated bus line 7 to the data processing circuit block 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a secret data processing circuit for processing confidential data, and more particularly to a secret data processing circuit for transferring this secret data via a bus line.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIG.

FIG. 3 is a block diagram of a conventional secret data processing circuit.

The secret data processing circuit includes a microcomputer 21 which is an arithmetic circuit block, a data processing LSI 20 which is a data processing circuit for processing data, and an EEPROM which functions as a work memory of the data processing LSI 20.
(Electrically Erasable Programmable Re
ad Only Memory) 22, data processing LSI 20 and E
A first bus 24 interposed between the EPROM 22 and a second bus 25 interposed between the data processing LSI 20 and the microcomputer 21.

An external device 23 is connected to the second bus. Microcomputer 21 or data processing LSI
20 and the external device 23 mutually transfer non-confidential data.

This secret data processing circuit is provided in the microcomputer 21.
The secret data from is transferred to the data processing LSI 20 via the second bus 25.

The data processing LSI buffers the transferred secret data in the EEPROM 22 via the first bus 24, and performs a predetermined process on the secret data while the secret data is being buffered in the EEPROM 22. .

Data processing LSI 20 and EEPROM 22
Since the first bus 24 interposed between the data processing LSI 20 and the EEPROM is not connected to the external device 23,
In the case of transferring data between 22 and 22, the security for the data is extremely high, and the possibility that the confidential data is leaked from the first bus is extremely low.

On the other hand, the second bus 25 interposed between the data processing LSI 20 and the microcomputer 21 is the external device 2
3 is connected, the security for data is extremely low when data is transferred between the data processing LSI 20 and the microcomputer 21, and there is a high possibility that confidential data will leak from the second bus.

In the conventional secret data processing circuit, since confidential data and non-confidential data are transferred by the common bus, the security of the secret data on this bus is extremely low.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a good secret data processing circuit having extremely high security for secret data as compared with the secret data processing circuit in the prior art.

[0012]

In order to solve the above-mentioned problems, a secret data processing circuit according to the present invention includes a data processing circuit block for performing a predetermined data processing, and a secret data or a secret data for the data processing circuit block. An arithmetic circuit block for transferring non-confidential data, and a non-secret data dedicated bus line for transferring the non-secret data to the data processing circuit block, interposed between the arithmetic circuit block and the data processing circuit block. And a single secret data dedicated bus line for transferring the secret data to the data processing circuit block, interposed between the arithmetic circuit block and the data processing circuit.

In order to solve the above-mentioned problems, the secret data processing circuit of the present invention transfers a secret data to the first data processing circuit block for processing predetermined data and the first data processing circuit block. A second data processing circuit block, and the first data processing circuit block and the second data processing circuit block are interposed between the first data processing circuit block and the first data processing circuit block.
A single secret data dedicated bus line for transferring the secret data to the data processing circuit block, a multi-layer substrate having a sandwich structure, and enclosing the secret data dedicated bus line in an intermediate layer of the multi-layer substrate. Characterize.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to FIGS.

FIG. 1 is a circuit block diagram of a secret data processing circuit of the present invention.

The secret data processing circuit shown in FIG. 1 functions as a work memory for the microcomputer 1, which is an arithmetic circuit block, the data processing LSI 2, which is a data processing circuit block, the data processing LSI 3, and the data processing LSI 2.
ROM (Electrically Erasable Program)
le Read Only Memory) 4 and EEPROM 5
, Microcomputer 1, data processing LSI 2 which is a data processing circuit block, EEPROM 4, and EEPROM
A secret data dedicated bus line 7 for transferring secret data that is interposed between the M5, the microcomputer 1, and the data processing LSI
2. The non-secret data dedicated bus line 8 is interposed between the data processing LSI 3 and the non-secret data other than the secret data.

An external device 6 is connected to the bus line 8 dedicated to non-secret data, and the microcomputer 1 and the data processing L are connected.
The non-secret data is mutually transferred between the SI2 and the data processing LSI 3 through the non-secret data dedicated bus line 8 and the non-secret data dedicated bus line.

On the other hand, the microcomputer 1 and the data processing LSI
2, data processing LSI3, EEPROM4, EEP
The ROM 5 mutually transfers secret data via a secret data dedicated bus line that is not connected to the external device 6.

Since the secret data dedicated bus line is not connected to the external device 6, the security of the secret data is extremely high.

Next, an embodiment in which the secret data processing circuit of the present invention is mounted on a substrate will be described with reference to FIG.

FIG. 2 is a sectional view of a substrate on which the secret data processing circuit is mounted.

In the figure, the substrate 19 employs a multilayer sandwich structure, and the surface layer 15 and the surface layer 16 are provided.
And a bus line 7 for exclusive use of secret data which is an intermediate layer inserted between them, a protective member 17 and a protective member 18 which are in contact with the end of the intermediate layer.

The surface layer 15 and the surface layer 16 of the substrate 19
Of these, the surface layer 15 is provided with holes 30, 31 and 32, and these holes 30 to 32 are filled with the signal lines of the bus lines and are exposed from the surface layer 15.

The microcomputer 1, the data processing LSI 2 and the data processing LSI 3 are mounted on the surface layer 15 of the substrate 19 as chip parts.

These chip parts include linear signal pins 1
2, linear signal pin 13 and linear signal pin 14, spherical signal pin 9, spherical signal pin 10 and spherical signal pin 11
And are provided respectively.

The linear signal pins 12 to 14 are electrically connected to the printed wiring pattern arranged on the surface layer 15.

Further, the spherical signal pins 9 to 11 have the surface layer 1
5 is electrically connected to the secret data dedicated bus line 7 exposed from the holes 30 to 32.

Further, the peripheral portion of the spherical pin connected to the secret data dedicated bus line 7 is covered with the resins 33, 34 and 35, which further enhances the security of the secret data dedicated bus line.

As described above, the microcomputer 1 and the data processing LS
I2 and the bus line 7 for exclusive use of secret data interposed between the data processing LSI 3 are the microcomputer 1 and the data processing LS.
Since the I2 and the chip parts of the data processing LSI 3 are sealed inside the mounted multilayer substrate 19, it is extremely unlikely that the secret data transferred through the secret data dedicated bus line is exposed outside the secret data processing circuit. .

As described above, in the secret data processing circuit of the present invention, since the secret data dedicated bus line used when mutually transferring the secret data between the circuit blocks is provided, the security of the secret data is extremely high. A secret data processing circuit can be realized.

[0031]

As described above, according to the present invention, the security of secret data is extremely high as compared with the secret data processing circuit in the prior art.
A good secret data processing circuit can be provided.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a secret data processing circuit according to the present invention.

FIG. 2 is a sectional view of a board on which a secret data processing circuit is mounted.

FIG. 3 is a block diagram of a conventional secret data processing circuit.

[Explanation of symbols]

1 ... Calculation circuit block 2 ... Data processing circuit block 7 ... Bus line dedicated to secret data 8 ... Bus line dedicated to non-secret data 19 ... substrate

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2C005 MA01 MA34 NA02 SA02                 5B017 AA03 BB00 CA00                 5B061 BA01 SS04

Claims (4)

[Claims] 1. A data processing circuit block for performing predetermined data processing, an arithmetic circuit block for transferring confidential data or non-concealment data to the data processing circuit block, the arithmetic circuit block and the data processing. A non-secret data dedicated bus line for transferring the non-secret data to the data processing circuit block, interposed between circuit blocks, and the data interposed between the arithmetic circuit block and the data processing circuit. A secret data processing circuit, comprising: a secret data dedicated bus line for transferring the secret data to a processing circuit block. 2. The secret data processing circuit according to claim 1, wherein the non-secret data dedicated bus line is connected to a signal line exposed from the secret data processing circuit. 3. The bus line dedicated to the secret data, which is connected to the data processing circuit and the arithmetic processing circuit, is enclosed in an intermediate layer of a multilayer substrate having a sandwich structure, and the bus line dedicated to the secret data. The secret data processing circuit according to claim 1, wherein the secret data is transferred between the data processing circuit and the arithmetic processing circuit without being exposed to the outside. 4. A first data processing circuit block for processing predetermined data, a second data processing circuit block for transferring secret data to the first data processing circuit block, and the first data processing. A single secret data dedicated bus line for transferring the secret data to the first data processing circuit block, interposed between a circuit block and the second processing circuit block; and a multilayer substrate having a sandwich structure. A secret data processing circuit, wherein the secret data dedicated bus line is enclosed in an intermediate layer of the multilayer substrate.