JP2003101217A - Circuit substrate and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit substrate which has a high joining strength of a wiring circuit layer to a sintered material and which does not bring about a fault even when a plating layer is formed, and to provide a method for inexpensively manufacturing the same. SOLUTION: The circuit substrate comprises an insulating substrate 1 containing a silicon nitride as a main crystal phase, a flat pattern layer 3 provided on the main surface 2 of an insulating substrate 1, and a wiring circuit layer 5 provided on an opposed main surface 4 disposed at an opposite side to the main surface 2, In the substrate, the surface roughness Rmax of the main surface 2 is 5 to 10 μm, and the main surface 4 has smaller surface roughness Rmax than that of the main surface 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in a method of manufacturing a circuit board that is low in cost and excellent in mass productivity, and various insulating substrate materials and semiconductor storage package materials manufactured using the method. The present invention relates to a circuit board and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, the heat generated from a semiconductor device has increased with the high integration of semiconductor elements, and in order to prevent malfunction of the semiconductor device, such heat is quickly released to the outside of the device. A substrate is needed.

However, since the thermal conductivity of alumina materials such as various insulating substrates and semiconductor housing packages that have been conventionally used is as low as about 20 W / mK, a thermal conductivity of 120 W / mK or more is an alternative. Have
Attention has been paid to silicon nitride, which has high strength and high reliability.

With respect to silicon nitride having such high thermal conductivity, the wiring circuit layer also contributes to heat dissipation, so that high thermal conductivity has been attempted. For example, a circuit board in which a metal plate such as Cu, Au, and Ag is bonded to the surface of silicon nitride in order to dissipate heat generated in a semiconductor element Si used in a high-power semiconductor device is proposed in Japanese Patent Laid-Open No. 2001-94016. Has been done.

However, since the difference in the coefficient of thermal expansion between the metal plate and the silicon nitride sintered body is large, the wiring circuit layer has a low adhesion to the silicon nitride sintered body and may peel off. As a result, the problem that the heat is not sufficiently dissipated and the semiconductor element malfunctions occurs.

Therefore, a ceramic circuit board in which the contribution of the anchor effect is increased by increasing the surface roughness to increase the bonding strength between the metal plate and the silicon nitride sintered body is disclosed in JP-A-11-268968. Proposed in the gazette.

Further, by interspersing an oxide layer of silicon oxide, aluminum oxide or the like on the surface of the silicon nitride substrate, a reaction layer is formed between the metal plate and the oxide layer, so that the bonding strength with the metal plate is high. 11-34317
No. 8 publication.

[0008]

However, since the circuit board described in JP-A No. 11-268968 has a large surface roughness, the plating component remains in the unevenness of the board surface between the wiring circuit layers in the plating step, There is a problem that defects such as poor appearance due to adhesion of plating between wirings and short-circuiting between wirings occur.

Further, according to the bonding method described in Japanese Patent Laid-Open No. 11-343178, an oxide layer must be formed on a substrate, and since the oxide layer is formed in an island shape, the oxide paste is used. There is a problem that the manufacturing and printing steps are added, the steps are complicated, and the cost is increased.

Therefore, an object of the present invention is to provide a circuit board which has a high bonding strength between a wiring circuit layer and a sintered body and which does not cause a problem even when a plating layer is formed, and a manufacturing method for manufacturing the circuit board at low cost. provide.

[0011]

According to the present invention, the bonding strength between a metal plate and a sintered body can be increased by controlling the surface roughness of the silicon nitride sintered body, and even after a plating step. This is based on the finding that a low-cost circuit board can be obtained without causing a defect.

That is, the circuit board of the present invention is mainly composed of silicon nitride.
An insulating substrate having a crystalline phase and a main surface of the insulating substrate
The flat pattern layer and the opposite side opposite to the main surface
In a circuit board having a wiring circuit layer provided on the main surface
And the surface roughness R of the main surface _maxIs 5-10 μm
And the surface roughness R is such that the facing main surface is smaller than the main surface._m
axIt is characterized by having.

Particularly, the surface roughness R _{max of the} facing main surface is 1
It is preferably ˜3 μm. As a result, sufficient bonding strength with the wiring circuit layer can be secured, and plating adhesion due to residual active liquid in the plating process after forming the wiring circuit layer can be prevented, and defects due to short circuits between wirings can be further reduced. it can.

The minimum thickness of the insulating substrate is 0.3 to
It is preferably 0.7 mm. As a result, it is possible to prevent the insulating substrate from cracking and obtain a circuit board having excellent heat dissipation capability.

Further, the room temperature strength of the insulating substrate is 800.
It is preferable that the pressure is at least MPa and the thermal conductivity is at least 60 W / mK. As a result, it is possible to prevent the insulating substrate from cracking and obtain a circuit board having excellent heat dissipation capability.

In the method for manufacturing a circuit board according to the present invention, silicon nitride is mainly used, and the main surface whose surface roughness R _max is controlled to 3 to 5 μm is located opposite to the main surface. A molded body having an opposing main surface having a surface roughness R _max smaller than that of the main surface, and firing the molded body so that the main surface has a surface roughness R _max of 5 to 10 μm. It is characterized in that a flat pattern layer is formed on the main surface of the sintered body obtained by firing, and a wiring circuit layer is formed on the opposing main surface.

As a result, the surface roughness R of the main surface of the circuit board is
It is possible to control _max to 5 to 10 μm, and it is possible to inexpensively manufacture a circuit board in which the facing main surface has a surface roughness smaller than that of the main surface.

In particular, a brazing material is placed on an insulating substrate, and a metal foil and / or a metal plate of at least one of Cu, Al and Ag is placed on the brazing material, and then bonded by heating. It is preferable to form the wiring circuit layer and / or the plane pattern layer by This allows
It is possible to obtain a circuit board having low specific resistance, excellent heat dissipation capability, and high bonding strength.

Further, it is preferable that a metal paste containing at least one of Cu, Al and Ag is coated on the insulating substrate and then heated to form the wiring circuit layer and / or the plane pattern layer. As a result, fine wiring can be formed, and a circuit board can be obtained at low cost.

[0020]

DETAILED DESCRIPTION OF THE INVENTION The circuit board of the present invention will be described with reference to FIG.

FIG. 1 is a schematic sectional view showing an example of the circuit board of the present invention. In the circuit board of the present invention, the plane pattern layer 3 is provided on the main surface 2 of the insulating substrate 1, and the wiring circuit layer 5 is provided on the opposing main surface 4 which is the surface opposite to the main surface 2.

According to the present invention, it is important that the surface roughness R _max of the main surface 2 of the insulating substrate 1 is 5 to 10 μm. If the surface roughness R _max is less than 5 μm, the unevenness of the surface of the main surface 2 is small, the anchor effect does not work sufficiently, the bonding strength between the insulating substrate 1 and the plane pattern layer 3 is not sufficient, and 10 μm is set. When it exceeds, the unevenness becomes large, so that a void is generated between the insulating substrate 1 and the plane pattern 3, and there arises a problem that the heat dissipation capability is lowered and the joint reliability is lowered.

Particularly, in terms of increasing the bonding strength between the insulating substrate 1 and the plane pattern layer 3 having a large area, the surface roughness R of the main surface is R.
It is preferable that _max is 7 to 9 μm.

Further, the surface roughness R _max of the opposing major surface 4 is also important that is smaller than the surface roughness R _max of the main surface 2.
This is to increase the bonding strength between the large-area flat pattern layer 3 and the insulating substrate 1 and reduce the adhesion of plating between the wirings of the wiring circuit layer 5. If the magnitude relation of the surface roughness is not established, the bonding strength of the large-area plane pattern layer 3 with the insulating substrate 1 becomes low and peeling easily occurs.
Further, there is a problem in that plating adheres between the wiring circuit layers 5 and short-circuits between the wirings.

The plane pattern layer 3 provided on the main surface
Since it is provided to improve heat dissipation as will be described later, since electricity does not flow, there is no possibility of short-circuiting even if plating adheres to a portion of the main surface where the planar pattern is not formed.

According to the present invention, the surface roughness R of the opposing main surface 4 is
It is preferable that _max is 1 to 3 μm, and particularly 1.5 to 2.5 μm. When the thickness is larger than 3 μm, the plating solution such as active Pd enters the convex and concave portions of the opposing main surface 4 and remains in the gap, and the metal plating such as Ni adheres, which easily causes poor appearance and short circuit between wirings. On the other hand, when the thickness is less than 1 μm, the adhesion between the insulating substrate 1 and the wiring circuit layer 5 tends to be small, peeling is likely to occur, and the heat dissipation tends to be deteriorated.

The insulating substrate 1 is a sintered body containing silicon nitride as a main crystal phase, and has a high thermal conductivity.
An insulating substrate having high strength can be realized. The thermal conductivity of such an insulating substrate 1 is 60 W / mK or more, especially 70 W.
/ MK or more, more preferably 80 W / mK or more. By increasing the thermal conductivity, the heat generated inside and / or on the insulating substrate 1 can be quickly dissipated.

As the grain boundary phase of the main crystal phase, for example, rare earth element (RE), Mg and Si can be used. In particular, the grain boundary phase of Si ₃ N ₄ —RE ₂ O ₃ —SiO ₂ type crystal phase can be used. It is preferable that it is present in order to have a high thermal conductivity of 60 W / mK or more and to enhance the heat dissipation of the circuit board.

In order to improve the adhesion between the insulating substrate 1 and the plane pattern layer 3 and between the insulating substrate 1 and the wiring circuit layer 5, at least the grain boundary phase in the main surface 2 and the opposing main surface 4 contains a melilite phase. Is preferred.

Further, the insulating substrate 1 preferably has a room temperature strength of 800 MPa or more, particularly 850 MPa or more, in order to make it difficult to crack even if the thickness is reduced. In addition, the measurement of room temperature strength is 45 m in length based on JISR1601.
The sample shape of m, width 4 mm, and thickness 3 mm was measured by three-point bending strength.

In order to prevent cracking due to handling in the manufacturing process such as mounting of semiconductor elements to suppress defects and further improve heat dissipation, the minimum thickness is 0.3 to 0.7 mm, especially 0 mm. It is preferably 0.35 to 0.635 mm.

The plane pattern layer 3 is made of Cu, Al and A.
It is preferably at least one of g. These metals have high thermal conductivity, and the insulating substrate 1 and the wiring circuit layer 5 are
Also, the heat dissipation of the semiconductor element mounted on the insulating substrate 1 can be improved, the temperature of the semiconductor element can be prevented from becoming excessively high, and malfunction can be easily prevented.

The wiring circuit layer 5 has a low resistance C.
At least one of u, Al and Ag is preferable. Among these, Cu is particularly preferable in terms of thermal conductivity, cost and ease of handling. When the wiring circuit layer 5 is made of a high resistance metal such as W or Mo, it is 1 A or more, especially 10
This is because when a large current of A or more is applied, the wiring circuit layer 5 itself may generate heat, which may cause disconnection or the like.

Further, the plane pattern layer 3 and a foil or plate made of the above metal are preferable. This can improve heat dissipation. The wiring circuit layer 5 is also preferably a foil or plate made of the above metal. As a result, the heat dissipation can be improved, and the resistance when a large current is applied can be reduced, and the amount of heat generation can be further reduced.

The plane pattern layer 3 is provided on the main surface 2 of the insulating substrate 1 to play the role of heat dissipation, and in order to enhance the heat dissipation capability, the flat pattern layer 3 is 80% of the total area of the main surface 1. %, Especially 90 to 99% is preferably occupied by the plane pattern layer 3.

The wiring circuit layer 5 has a desired pattern shape.
A wiring circuit through which electric signals and current flow is provided. Particularly, in order to suppress heat generation even when a large current flows, the thickness of the wiring circuit layer 5 is preferably 0.1 mm or more, and more preferably 0.2 mm or more.

In addition, a semiconductor element may be mounted on a part of the wiring circuit layer 5, and heat generated in the semiconductor element passes through the wiring circuit layer 5, the insulating substrate 1, the main surface 2 and / or the plane pattern. Since it is released from the layer 3, the thickness of the wiring circuit layer 5 is preferably 1 mm or less, particularly preferably 0.5 mm or less in order to reduce the thermal resistance in the wiring circuit layer 5.

The circuit board constructed in this way has the characteristics of high strength and high heat dissipation, and is suitable for IGBTs and MOS-Fs.
It can be suitably used for a power device mounting circuit board such as ET.

Next, a method of manufacturing the circuit board of the present invention will be described with reference to FIG.

First, the insulating substrate 11 is manufactured. Since this insulating substrate 11 is made of a silicon nitride sintered material, a silicon nitride powder and a sintering aid powder are prepared. A silicon nitride powder having an average particle diameter of 0.1 to 1.5 μm and an α ratio of 80% or more is prepared as the silicon nitride powder. Further, it is desirable that the amount of impurity oxygen in the silicon nitride powder is 0.5 to 3.0 mass%.

The sintering aid is a rare earth element compound, M
Known compounds such as g compounds, Si compounds, and Al compounds can be used. These compounds are preferably oxides, carbonates, acetates and the like that can form oxides by firing. If the addition amount of the sintering aid is too small, the sintering will be defective and the thermal conductivity and strength will decrease, and if it is too large, the liquid phase will ooze out during firing, and the formed bodies will be stuck together. Since it is easy, it is preferable to add an appropriate amount depending on the auxiliary agent to be added.

Specifically, in the case of a rare earth element compound, it is 3 to 20% by mass, particularly 10 to 15% by mass, in terms of oxide, M
If it is a g compound, it is 0.5 to 5 mass% in terms of oxide, especially 1 to 3 mass%, and if it is a Si compound, it is 0.1 in terms of oxide.
˜7% by mass, especially 0.1 to 4% by mass, and if it is an Al compound, it is 0.35 to 0.5% by mass in terms of oxide, especially 0.37.
˜0.47% by mass, more preferably 0.4 to 0.45% by mass.

The above-mentioned amount of the sintering aid is the amount when added alone, and when a plurality of the above compounds are used in combination, the addition amount of each may deviate from the above range. When combined, the optimum amount may be determined in consideration of characteristics such as strength and thermal conductivity.

Next, an organic binder and a solvent are added to the above powder to prepare a slurry, and a sheet-shaped compact (hereinafter referred to as a green sheet) is produced by a doctor blade method or the like. At that time, the surface roughness R _max of the main surface of the green sheet
(Main) is controlled so as to be 3 to 5 μm, and the surface roughness R _max (direction) of the facing main surface existing opposite to the main surface is present.
Is smaller than the surface roughness R _max (main) of the main surface.

In the control of the surface roughness of the green sheet, for example, in the case of molding by the doctor blade method, the slurry drying temperature, the molding speed and the surface roughness of the release paper have a great influence on the surface roughness of the green sheet. Therefore, the green sheet may be produced by adjusting these conditions.

By setting R _max (main) to 3 to 5 μm, there is an advantage that the green sheets are not fixed even when stacked in the firing process, and R _max (main)> R
By setting the magnitude relationship of _max (direction), it is possible to prevent plating from adhering between wirings and to prevent peeling from a large-area planar pattern insulating substrate.

Further, R _max (direction) is preferably smaller than 3 μm, and particularly 0.5 to 1.0 μm can reduce the surface roughness after firing, and as a result, reduce short-circuit defects due to adhesion of plating. It is preferable in terms. In addition, the measurement of the surface roughness R _max in the present invention is performed by measuring the maximum height at a reference length of 2.5 mm with a contact-type surface roughness measuring device based on JIS B0601-1982, and measuring the value of R _max . And

The obtained green sheet may be used as a single layer or a plurality of green sheets may be laminated. If desired, this green sheet is degreased at 900 ° C. in a weakly oxidizing atmosphere. Then, in a non-oxidizing atmosphere such as nitrogen, 1650 to 1800 ° C., especially 16
Baking at a temperature of 80 to 1750 ° C.

In the firing, it is important to control the firing conditions so that the main surface of the green sheet has a surface roughness R _max of 5 to 10 μm. In order to control the surface roughness, the firing conditions such as the firing temperature, the holding time, the atmosphere and the temperature lowering time may be adjusted.

Immediately after the firing, in order to crystallize the glass phase, the glass is gradually cooled to 1500 ° C. at a temperature lowering rate of 60 ° C./hour or less, then the heating of the heater is stopped, and the relative density is 95% or more. In particular, 98% or more, and even 99% or more can be achieved.

When the green sheet is put in the firing furnace,
The main surface of the green sheet and the other green sheet
Stack so that the main surface is in contact, in other words, all
Stack with the main surface of the green sheets facing down, or
Can be stacked and fired on top.
The surface roughness of the main surface of the green sheet used in the present invention is R.
_maxIs 5-10 μm, so it can be piled up without using bedding
Stacked green sheets adhere even if stacked and fired
Never. In this way, many greens can be fired once.
Sheets can be fired, which reduces manufacturing costs.
Can be reduced to

The sintered body thus obtained is cut into a desired shape to produce an insulating substrate 11, and a plane pattern layer 13 is formed on the main surface 12 of the insulating substrate 11 and a wiring circuit layer is formed on the opposing main surface 14. Form 15. Although a known forming method can be used for forming these, it is preferable to use a brazing material containing an active metal since it has a high bonding strength.

For example, Cu-Ag-Ti, Cu-Au-
A brazing material containing an active metal such as Ti and a paste containing a low resistance metal are applied and baked at 800 to 900 ° C. under pressure to form a metal layer 13 b on the adhesive layer 13 a. Further, the circuit board can be obtained by forming the plating layer 13c of Ni or the like on the metal layer 13b by the electroless plating method.

To bond the metal foil and / or the metal plate to the insulating substrate 11, Cu-Ag-Ti, Cu-Au-
After applying a paste of a brazing material containing an active metal such as Ti, a metal foil or metal plate having a thickness of 0.1 mm or more is placed and bonded under pressure at 800 to 900 ° C., and then a metal foil or metal plate. Then, the wiring circuit layer 15 having a predetermined circuit pattern is formed by a method such as resist coating, exposure, development, etching treatment, and resist stripping. For example, the metal layer 15 made of a metal foil or a metal plate via the bonding layer 15a.
b is formed. Then, a plating layer 15c of Ni or the like is formed by electroless plating to obtain a circuit board having the wiring circuit layer 15.

It is also possible to bond the metal foil or the metal plate to the insulating substrate 11 with a brazing material containing at least one active metal selected from the group consisting of Ti, Zr and Hf.
For example, the planar pattern layer 15 is formed on the main surface 12 of the insulating substrate 11.
The metal foil and / or the metal plate provided as are Cu, A
It is desirable that the metal plate is made of at least one kind of high thermal conductive metal selected from the group consisting of 1 and Ag. By bonding this metal plate to the insulating substrate 11 with the above brazing material, the insulating substrate 11 can be formed. The metal layer 15b can be bonded with high bonding strength via the bonding layer 15a.

Further, with respect to the circuit board shown in FIG.
It is also possible to mount a semiconductor element. That is, as shown in FIG. 3, after applying a solder paste on the wiring circuit layer 25, the wiring circuit layer 25 is mounted by an automatic mounting device or the like and heated at 300 to 400 ° C. to bond the semiconductor element 27.

Furthermore, when the circuit board of the present invention is mounted on a heat sink or the like, a solder paste such as Pb-Sn eutectic solder is applied on the plane pattern layer to form
It may be brazed at 400 ° C.

By manufacturing the circuit board in this way, it is possible to provide a circuit board having a high bonding strength between the wiring circuit layer and the sintered body and having no problem even if the plating layer is formed at a low cost. it can.

[0059]

EXAMPLE As raw material powder, particles having a particle size of 1 μm or less are accumulated in a particle size distribution of 40 to 60%, and an average particle diameter is 0.8 to 1.
Particle diameter at 2 μm and a cumulative mass ratio of 90% (D9
0) is 2 to 5 μm, the amount of oxygen is 1.0% by mass, and the α ratio is 87%.
A raw material powder of silicon nitride manufactured by the direct nitriding method was prepared.

Further, as a sintering aid, Er ₂ O _{3 having} a purity of 99% and an average particle size of 1 μm, a purity of 99% and an average particle size of 1 μm
m Y ₂ O ₃ , purity 99%, average particle size 1 μm Yb
₂ O ₃ , 99% purity, MgO having an average particle size of 3 μm, purity 9
9%, MgCO _{3 having} an average particle diameter of 1 μm, purity 99%, Al ₂ O _{3 having} an average particle diameter of 1 μm, purity 99%, average particle diameter 1
A μm AlN was prepared.

The above raw material powders were blended so as to have the composition shown in Table 1, acrylic resin binder and toluene were added as a solvent, and the mixture was kneaded.
Form a green sheet of 3 to 0.4 mm and stack it appropriately,
80 × 115mm and 0.8m thickness by cutting
A disk-shaped molded body having m, a diameter of 12 mm, and a thickness of 5 mm was produced.

In the production of the green sheet, the slurry drying temperature, the molding speed, and the surface roughness of the release paper were adjusted so that the surface roughness R _max shown in Table 1 was obtained.
In addition, the surface roughness is measured with a surface contact type surface roughness measuring device.
Standard length 2.5 according to IS B0601-1982
The maximum height in mm was measured and used as the value of R _max .

The green sheet thus obtained was degreased at 900 ° C. in a weakly oxidizing atmosphere, and then fired in a nitrogen atmosphere at atmospheric pressure under the firing conditions shown in Table 1. The obtained sintered body was cut to prepare a measurement sample having a length of 45 mm, a width of 4 mm, and a thickness of 3 mm, and an insulating substrate having a length of 60 mm, a width of 90 mm, and a thickness of 0.6 mm.

The specific gravity of this measurement substrate was measured by the Archimedes method, and the relative density was calculated from the theoretical density. Further, the value of R _max was calculated by the above-mentioned surface roughness measuring method.

Further, the thermal conductivity at room temperature was measured by the laser flash method. Furthermore, JISR1601
The three-point bending strength was measured at room temperature by a three-point bending test based on. The results are shown in Table 1.

[0066]

[Table 1]

Next, a plane pattern layer was formed on the main surface of the insulating substrate, and a wiring circuit layer was formed on the opposing main surface. The formation method is
(1) Plate bonding method and (2) Paste coating method.

In the plate joining method, when a plane pattern layer is formed, an active metal brazing material of Cu-Ag-Ti is printed and applied on the main surface of the insulating substrate, and a Cu plate having a thickness of 0.5 mm is attached.
The Cu plates were joined by heat treatment in a reducing atmosphere. When a wiring circuit layer is formed, a Cu-Ag-Ti active metal brazing material is printed and applied in a circuit pattern shape, and a solder resist is printed and applied in a circuit pattern shape thereon to a thickness of 0.5.
mm Cu plate is attached and heat treated in a reducing atmosphere to C
The u plates were joined.

Screen printing was used as the paste application method.

The board thickness of the obtained circuit board was measured with a micrometer, and the withstand voltage was applied between the insulating boards while increasing the voltage in increments of 1 kV, and the breakdown voltage was defined as the withstand voltage. Further, as shown in FIG. 3, a semiconductor element is actually mounted on the wiring circuit layer 23 formed on the opposing main surface of the circuit board, and the semiconductor element is heated to 100 ° C. The thermal resistance was measured by measuring the temperature of the pattern layer and measuring the temperature difference between the front and back of the circuit board, that is, the temperature difference between the main surface and the opposing main surface of the circuit board.

Further, in order to evaluate the bonding strength between the flat pattern layer and the insulating substrate, the end surface of a Cu plate having a length of 0.5 mm, a width of 1 cm and a length of 4 cm was bonded to the main surface by the same bonding method as for the flat pattern layer. The stress at the time of separating the Cu plate was measured by an autograph. Ten samples were measured for each sample number, and the lowest strength was determined as the bonding strength.

The adhesion of the plating was observed by observing the wiring circuit layer 25 with a microscope to confirm the adhesion of the plating between the wirings, and the presence or absence of an electrical short circuit was examined by a tester. The results are shown in Table 2.

[0073]

[Table 2]

Sample No. of the present invention. 2-4 and 8-22
No withstand voltage was 7 kV or more, thermal resistance was 11 ° C./W or more, bonding strength was 400 MPa or more, and no insulation failure was observed.

[0075] On the other hand, samples outside the main surface of the R _max is 4μm and less present invention No. 1 and the main surface of R _max is 12μm
And a large sample No. outside the range of the present invention. In No. 5, the bonding strength was 180 MPa or less. In addition, the sample No. In No. 5, the adhesion of plating was observed between the electrodes of the wiring circuit layer.

Further, sample No. outside the range of the present invention. In 6 and 7, the bonding strength was 200 MPa or less, and the insulation failure was observed.

[0077]

According to the present invention, since the surface roughness of the main surface and the opposing main surface is controlled, the plane pattern layer and the wiring circuit layer are firmly bonded to the insulating substrate, no trouble occurs, and the thinning is achieved. Even so, a highly reliable circuit board can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a structure of a circuit board of the present invention.

FIG. 2 is a schematic cross-sectional view showing a part of the circuit board of the present invention.

FIG. 3 is a cross-sectional view showing a part of the circuit board of the present invention after mounting a semiconductor element.

[Explanation of symbols]

1, 11, 21 ... Insulating substrate 2, 12, 22 ... Main surface 3, 13, 23 ... Plane pattern layer 4, 14, 24 ... Opposing main surface 5, 15, 25 ... Wiring circuit layer 13a, 15a, 23a, 25a ... Bonding layer 13b, 15b, 23b, 25b ... Metal layer 13c, 15c, 23c, 25c ... Plating layer 27 ... Semiconductor element

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H05K 1/03 610 H01L 23/12 J

Claims (7)

[Claims] 1. An insulating substrate having silicon nitride as a main crystal phase, a plane pattern layer provided on the main surface of the insulating substrate, and a wiring circuit provided on an opposite main surface opposite to the main surface. And a surface roughness R of the main surface in a circuit board including a layer.
A circuit board, wherein _max is 5 to 10 μm, and the facing main surface has a surface roughness R _max smaller than that of the main surface. 2. The surface roughness R _{max of the} facing main surface is 1 to 3 μm.
The circuit board according to claim 1, wherein the circuit board is m. 3. The minimum thickness of the insulating substrate is 0.3 to 0.7.
The circuit board according to claim 1 or 2, wherein the circuit board has a size of mm. 4. The circuit board according to claim 1, wherein the insulating substrate has a room temperature strength of 800 MPa or more and a thermal conductivity of 60 W / mK or more. 5. A silicon nitride-based material having a surface roughness R _max of 3
A controlled main surface 5 .mu.m, located opposite to the opposite side of the main surface, to prepare a molded body having a facing major surface having a small surface roughness R _{ma x} than the main surface, By firing, the molded body is fired so that the surface roughness R _{max of the} main surface becomes 5 to 10 μm, a flat pattern layer is formed on the main surface of the obtained sintered body, and the opposing main surface is formed. A method of manufacturing a circuit board, comprising forming a wiring circuit layer. 6. A brazing material is placed on an insulating substrate, and a metal foil and / or a metal plate of at least one of Cu, Al and Ag is placed on the brazing material, and then bonded by heating. 6. The method for manufacturing a circuit board according to claim 5, wherein the wiring circuit layer and / or the plane pattern layer is formed by. 7. An insulating substrate is coated with a metal paste containing at least one of Cu, Al and Ag, and then heated to form the wiring circuit layer and / or the plane pattern layer. 7. The method for manufacturing a circuit board according to claim 5 or 6.