JP2003100748A - Polycide wiring, method of forming the same, and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reinforce a predetermined region near the boundary between a P-type polysilicon film and an N-type polysilicon film by a minimum space to prevent breaking and high resistance of polycide wiring. SOLUTION: First N-type impurity of a first dosage is introduced on the entire surface of a silicon film deposited on a semiconductor substrate via an insulating film, and second N-type impurity of a second dosage is introduced on a first area of the silicon film while a second area is masked. Subsequently, in a connection region including the boundary between the first and second areas, patterning is performed on the silicon film so as to have a width wider than areas on the both sides. Then, P-type impurity of a third dosage larger than the first dosage is introduced only on the second area of the silicon film, high melting point metal film is deposited on the silicon film to form a silicide film, and thus the polycide wiring is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycide wiring used in a semiconductor device and a method for forming the same, and
The present invention relates to a method of manufacturing a semiconductor device configured using this polycide wiring.

[0002]

2. Description of the Related Art As semiconductor devices are miniaturized, for example, in a semiconductor device manufactured by a manufacturing process with a design rule of about 0.3 μm or less, in general, P which constitutes a CMOS (complementary metal oxide semiconductor) circuit is used. Channel MOS
A technique is used in which the gate electrode of the transistor is a P-type polysilicon film and the gate electrode of the same N-channel MOS transistor is a dual gate (heteropolar gate) structure formed of an N-type polysilicon film.

The polysilicon film forming the gate electrode is also used for forming a wiring for connecting the gate electrode to another element. In particular, it is often used as a wiring for connecting the gate electrode of a P-channel MOS transistor and the gate electrode of an N-channel MOS transistor that form a CMOS circuit as a set to each other.

Since the P-type polysilicon film and the N-type polysilicon film both have high resistance as wiring materials, generally, a device is formed to form a silicide on the wiring layer to reduce the resistance value. That is, in a CMOS circuit having a dual gate structure, a P-type polysilicon wiring and an N-type polysilicon wiring having different polarities are continuously formed of the same layer polysilicon film, and a polycide wiring having a silicide film formed thereon is formed. Used.

In the semiconductor device adopting this dual gate structure, a P / N junction is formed in the region of the boundary between the P-type polysilicon wiring and the N-type polysilicon wiring. The above silicide film short-circuits this P / N junction,
It is also useful for reducing the resistance between the P-type polysilicon wiring and the N-type polysilicon wiring.

However, there is a problem that the silicide film in the upper layer is broken in this boundary region and the resistance of the polycide wiring is increased. When the resistance of the polycide wiring becomes high, the frequency characteristic deteriorates. For example, as shown in an example in the graph of FIG. 10, it operates if the frequency is lowered to some extent, but it does not operate at a high frequency during actual operation, which has poor frequency dependence. So-called delay fault occurs.

The graph shown in FIG. 10 shows the yield of products to be operated at 14 MHz, the horizontal axis thereof is the operating frequency, and the vertical axis is the number of non-defective or defective products. The data on the right end shows that there are 412 good products out of 665 that have operated (passed) at a speed of 14 MHz. Also, the second data from the right does not work at 14 MHz (fail)
Indicates that there are 13 defective products that operate at 12 MHz. The same applies to the following, and the data on the left end indicates that there are 96 defective products that do not operate at all even if the operating frequency is lowered.

Here, as a conventional technique of a semiconductor device having a dual gate structure, for example, Japanese Patent Laid-Open No. 2001-77210 is used.
JP-A-2001-57391, JP-A-5-7504
There is No. 5, etc.

In Japanese Patent Laid-Open No. 2001-77210, the width of the electrode in the region including all the high resistance portions at the boundary between the first portion made of the P-type conductive layer and the second portion made of the N-type conductive layer is The area is made larger than the area not including the high resistance portion. As a result, according to the publication, it is possible to suppress the disconnection of the metal silicide layer formed on the surface of the silicon gate electrode without causing a large increase in the circuit area, and prevent the circuit failure due to this disconnection. .

In Japanese Patent Laid-Open No. 2001-57391, the impurity concentration of the connecting region between the region in which the N-type impurity is introduced and the region in which the P-type impurity is introduced is set to 1 × 10 ²⁰ cm ⁻³ or more, or the connection is made. The width of the region is made thicker than the width of the region in which the N-type impurity is introduced or the width of the region in which the P-type impurity is introduced. As a result, according to the publication, the resistivity of the conductive film in the connecting region can be reduced, and the probability that the titanium silicide film will be completely broken can be reduced.

Further, in Japanese Patent Laid-Open No. 75045/1993, after forming an N well and a P well on a silicon substrate, a gate oxide film and a polysilicon film are grown, phosphorus is ion-implanted, and a heat treatment is performed to form an N-type polysilicon. A film is formed, a gate electrode is formed, the P well is masked, and boron is ion-implanted to form a P-type polysilicon film. As a result, according to the publication, the leakage current of the CMOS integrated circuit is significantly reduced, and the highly reliable CMOS is provided.
It is said that an integrated circuit will be obtained.

[0012]

However, Japanese Patent Laid-Open No. 2001-2001
According to the study by the present inventors, it is impossible to sufficiently suppress the increase in the resistance of the polycide wiring when the miniaturization is further advanced only by the measures proposed in JP-57391 or JP 2001-77210. It was revealed.

Incidentally, JP-A-5-75045 discloses a CMO.
The purpose is to prevent the leakage current of the S integrated circuit, and naturally, it is not possible to obtain the effect of preventing the disconnection or the high resistance in the region near the boundary.

An object of the present invention is to eliminate the problems based on the above-mentioned prior art, to reinforce a predetermined region near the boundary between the P-type polysilicon wiring and the N-type polysilicon wiring with a minimum space, and to prevent disconnection or It is an object of the present invention to provide a polycide wiring capable of preventing an increase in resistance, a method for forming the same, and a method for manufacturing a semiconductor device.

[0015]

In order to achieve the above object, the present invention provides a polycide wiring for a semiconductor device,
A silicon film having a first part in the length direction and a second part connected to the first part via a boundary; and a silicide film laminated on the first and second parts of the silicon film. The first portion of the silicon film contains an N-type impurity, the second portion of the silicon film contains at least a P-type impurity, and the first portion of the silicon film and the second portion of the silicon film include Exists in the inter-diffusion region where the N-type impurity and the P-type impurity are mutually diffused, and the N-type impurity in a portion of the first portion of the silicon film excluding the inter-diffusion region is A second concentration of the silicon film having a first concentration
Of the P-type impurity having a second concentration in a portion of the silicon film excluding the inter-diffusion region, and the first and second portions of the second portion of the silicon film excluding the inter-diffusion region. The third aspect of the present invention is to provide a polycide wiring characterized in that it includes an N-type impurity having a third concentration lower than the concentration of, and has a larger width at both sides of the connection portion including the boundary.

Here, the third concentration is 5 × 10 ¹⁸ cm
^It is preferably ⁻³ or more.

Further, the present invention is a method for forming a polycide wiring of a semiconductor device, comprising a step of depositing a silicon film on a semiconductor substrate via an insulating film, and a step of applying a first dose amount over the entire surface of the silicon film. A step of introducing a first N-type impurity, a mask covering the second portion of the silicon film is formed, and a second portion is formed on the first portion on the opposite side so as to contact the boundary of the second portion. A step of introducing a dose of the second N-type impurity, and a step of forming the N-type impurity-introduced silicon film into a shape of a wiring connected to the second portion from the first portion across the boundary. Patterning; introducing a P-type impurity having a third dose amount larger than the first dose amount into only the second portion of the silicon film before or after the patterning; High melting rate on the formed silicon film A step of depositing a metal film and reacting the silicon film with the refractory metal film to form a silicide film, wherein the shape of the wiring is in a connecting region including the boundary, compared with regions on both sides thereof. And a method of forming a polycide wiring having a large width.

Here, it is preferable that the introduction of the P-type impurity is performed after the patterning and before the deposition of the refractory metal film. Also, the first dose amount is 1 × 1
It is preferably 0 ¹⁴ cm ^-2 or more.

Further, the present invention is a method for manufacturing a polycide wiring of a semiconductor device, comprising the steps of depositing a silicon film on a semiconductor substrate via an insulating film, and the second step of forming the silicon film.
And a mask that covers a predetermined region near the boundary between the first part connected to the second part and the second part, and the part of the first part that is not covered by the mask is formed. Introducing an N-type impurity, patterning the silicon film into which the N-type impurity is introduced into a shape of a wiring extending from the first portion to the second portion across the boundary, and patterning Before or after the step of introducing a P-type impurity into the second portion of the silicon film, and performing the patterning, depositing a refractory metal film on the silicon film into which the P-type impurity has been introduced, And a step of reacting a silicon film with a refractory metal film to form a silicide film, wherein the shape of the wiring has a larger width in a connection region including the boundary as compared with regions on both sides thereof. Special Method for forming a polycide interconnection to.

Here, it is preferable to introduce the P-type impurities after the patterning.

Further, the present invention is a method of manufacturing a semiconductor device having a polycide wiring, comprising a step of depositing a silicon film on a semiconductor substrate via an insulating film, and a first dose amount over the entire surface of the silicon film. The step of introducing the N-type impurity, and a mask for covering the second portion of the silicon film is formed, and a second dose amount is applied to the first portion on the opposite side of the second portion with the boundary in contact. Second step of introducing the N-type impurity, and patterning the N-type impurity-introduced silicon film into a shape of a wiring extending from the first portion to the second portion across the boundary. And a step of introducing a P-type impurity having a third dose amount larger than the first dose amount into only the second portion of the silicon film before or after the patterning, and the patterned silicon film. High melting on top A step of depositing a metal film, reacting the silicon film with the refractory metal film to form a silicide film, and after the manufacturing process of the semiconductor device is completed, P / N near the boundary in the silicon film. A semiconductor device having a polycide wiring in which a junction is formed and the shape of the wiring has a larger width in a connection region including a position where the P / N junction is formed as compared with regions on both sides thereof. A method for manufacturing the same is provided.

The present invention is also a method of manufacturing a semiconductor device having polycide wiring, comprising the steps of depositing a silicon film on a semiconductor substrate via an insulating film, the second portion of the silicon film, and A mask is formed to cover a predetermined region near the boundary of the first portion connected to the second portion with the second portion, and an N-type impurity is introduced into a portion of the first portion not covered by the mask. And a step of patterning the N-type impurity-introduced silicon film into a shape of a wiring extending from the first portion to the second portion across the boundary, and before or after the patterning. The step of introducing a P-type impurity into the second portion of the silicon film and the patterning, and depositing a refractory metal film on the silicon film into which the P-type impurity is introduced,
A step of reacting the silicon film with the refractory metal film to form a silicide film, and after the manufacturing process of the semiconductor device is completed, P / N is formed near the boundary in the silicon film.
A semiconductor device having a polycide wiring in which a junction is formed and the shape of the wiring has a larger width in a connection region including a position where the P / N junction is formed as compared with regions on both sides thereof. A method for manufacturing the same is provided.

Here, the lengthwise dimension of the polycide wiring in the predetermined region is set to 1 when the distance from the boundary to the position where the P / N junction is formed is zero.
It is preferable to set it to be / 2 or less.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION The polycide wiring, the method for forming the same, and the method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

1 to 4 are sectional views of an embodiment showing each step of the method for manufacturing a semiconductor device of the present invention. Figure 1 (a)
-(D), FIG. 2 (e)-(g), FIG. 3 (h)-(j), and FIG. 4 (k)-(m) are P which comprises a CMOS circuit.
FIG. 9 is a cross-sectional view showing a series of manufacturing steps for forming a channel MOS transistor and an N-channel MOS transistor on the same semiconductor substrate. The right part of the figure is the P channel M
The P channel region in which the OS transistor (Pch Tr) is formed, and the left portion is the N channel region in which the N channel MOS transistor (Nch Tr) is formed.

In manufacturing the semiconductor device 10 in which the CMOS circuit having the dual gate structure constituted by using the polycide wiring of the present invention is formed, first, by thermal oxidation,
Forming a silicon oxide film 14 on the surface of the semiconductor substrate 12;
The silicon oxide film 14 is formed by the CVD (chemical vapor deposition) method.
A silicon nitride film 16 is deposited on the upper layer. Then, by a photolithography technique, a photoresist 18 is formed on the silicon nitride film 16 by using an active region forming mask.
Is patterned (FIG. 1A).

Then, using the photoresist 18 as a mask, the silicon nitride film 16, the silicon oxide film 14 and the semiconductor substrate 12 are sequentially etched to form a groove for element isolation, and the entire surface of the semiconductor substrate 12 is formed by the CVD method. A silicon oxide film is deposited, and the surface of the silicon oxide film is polished and flattened by a CMP (chemical mechanical polishing) method. As a result, the silicon oxide film is embedded in the trench for element isolation, and the element isolation region 20 is formed (FIG. 1B).
The active region between the element isolation regions 20 is used to form a transistor.

Subsequently, the N-channel region is masked with a photoresist 22 and an N-type impurity such as phosphorus (P ⁺ ) is ion-implanted into an active region where a P-channel MOS transistor is formed to form an N well 24 ( FIG. 1 (c)).

Similarly, the P-channel region is masked by the photoresist 26, and P-type impurities such as boron (B ⁺ ) are implanted into the active region where the N-channel MOS transistor is formed to form the P well 28. (Fig. 1
(D)).

Subsequently, a gate insulating film 32 is formed on the surfaces of the P well 28 and the N well 24 by thermal oxidation.
After that, a silicon film is formed on the entire surface of the gate insulating film 32 by the CVD method, and in this embodiment, a polysilicon film 34 is formed.
Are deposited (FIG. 2E).

Here, N-type impurities such as phosphorus (P ⁺ ) are implanted (blanket ion implantation) on the entire surface of the polysilicon film 34 (FIG. 2F). As a result, N-type impurities are introduced into the entire surface of the polysilicon film 34, and the N-type polysilicon film having no non-doped region is formed.

The dose amount of the N-type impurity implantation is 1 × 10 ¹⁸ when the polysilicon film 34 is uniformly diffused in the thickness direction.
It is preferable to set it to be cm ⁻³ or more, preferably 5 × 10 ¹⁸ cm ⁻³ or more, and more preferably 1 × 10 ¹⁹ cm ⁻³ or more. For example, if the thickness of the polysilicon film 34 is 2
In the case of 00 to 300 nm, 20 to 40 KeV, 2 to 5 ×
Conditions in the range of 10 ¹⁴ cm ^-2 are suitable.

Further, in order to prevent depletion when the polysilicon film 34 is used as a gate electrode of an N-channel MOS transistor, the P-channel region is masked with a photoresist 36, for example, implantation energy = 20-40K.
Under the conditions of eV and dose = 3 to 5 × 10 ¹⁵ cm ⁻³ , the same N-type impurities as those introduced by the blanket ion implantation, that is, the present embodiment, are applied to the entire surface of the polysilicon film 34 in the N channel region. In the case of the example, phosphorus (P ⁺ ) is introduced (FIG. 2 (g)). Then, for example, 800 ℃, 30
Heat treatment is performed for a minute to activate the implanted N-type impurities and diffuse them in the thickness direction of the polysilicon film 34.

As described above, a manufacturing method including a step of introducing an N-type impurity into the entire surface of the polysilicon film 34 so that the non-doped region does not exist in the polysilicon film 34,
Hereinafter, this is called the blanket method. When a dual gate structure CMOS semiconductor device is manufactured by the blanket method, as will be described later, a dose amount larger than the dose amount of the N-type impurity introduced by the blanket is applied to the P channel region of the polysilicon film. A P-type impurity is introduced to invert to P-type. Therefore, the dose amount of the N-type impurity introduced by the blanket is within a range in which the polarity can be inverted by introducing the P-type impurity.

On the other hand, for example, the above-mentioned Japanese Unexamined Patent Publication 2001
No. 77210, N-type impurities are added to the N channel region of the polysilicon film and P is added to the P channel region.
C with a dual gate structure, in which each type impurity is implanted
A method of manufacturing a MOS semiconductor device is disclosed. The manufacturing method in which the N-type impurity is not introduced into the entire surface of the polysilicon film in this manner is hereinafter referred to as a normal method.

Subsequently, a photoresist (not shown) is patterned on the polysilicon film 34 by using a gate electrode mask, and the polysilicon film 34 is etched by using this photoresist as a mask to form the polysilicon wiring 3
8 is formed (patterned) (FIG. 3 (h)).

Here, the gate electrodes of the P-channel and N-channel MOS transistors that form a CMOS circuit as a set are formed by a polysilicon film 34 that is the same layer as the polysilicon film that forms this gate electrode. The silicon wires 38 are formed into a shape that is continuously connected. That is, in the center of FIG. 3H, the gate electrode of the N-channel MOS transistor on the left side and the gate of the P-channel transistor on the right side extend in the horizontal direction across the boundary between the N-channel region and the P-channel region. Polysilicon wiring 38 connecting to the electrodes is shown.

On the other hand, the left and right ends of FIG. 3 (h) respectively extend in the direction perpendicular to the plane of the drawing to form another N-channel MOS.
Polysilicon wiring 38 forming the gates of the transistor and P-channel MOS transistor is shown.

Subsequently, the P channel region is masked, and the N channel region is doped with N-type impurities. In the case of this embodiment, phosphorus (P
⁺ ) Is ion-implanted and LDD (Lightly-doped drain
) Region 40 is formed (FIG. 3 (i)). At this time, phosphorus is also ion-implanted into the polysilicon wiring 38 in the N-channel region at the same time. However, the dose amount of phosphorus introduced in this step is smaller than the dose amount of phosphorus introduced into the polysilicon film 34 before patterning, and the influence on the impurity concentration distribution in the polysilicon film is small.

Similarly, the N-channel region is masked and a P-type impurity such as boron (B ⁺ ) is ion-implanted into the P-channel region to form the LDD region 46 (FIG. 3 (j)). Similarly, at this time, boron is ion-implanted into the polysilicon wiring 38 in the P-channel region at the same time. The dose of boron introduced in this step is also the same as that of the polysilicon wiring 3 in the source / drain region forming step described later.
It is smaller than the dose amount of the P-type impurity introduced in FIG. Therefore, the introduction of boron in this process has a small effect on the impurity concentration distribution in the polysilicon film after the manufacturing process is completed.

Then, a silicon oxide film or a silicon nitride film is deposited on the entire surface by the CVD method, and this is etched back to form spacers 5 on the sidewalls of the polysilicon wiring 38.
Form 0. Then, the P-channel region is masked with the photoresist 52, N-type impurities such as arsenic (As ⁺ ) are ion-implanted into the N-channel region, and the N-channel MOS is formed.
The source and drain regions 54 of the transistor are formed (FIG. 4 (k)). At this time, arsenic is also ion-implanted into the polysilicon wiring 38 in the N-channel region at the same time.

However, arsenic is implanted only in the vicinity of the surface of the polysilicon film 34 forming the polysilicon wiring. Further, the diffusion in the thermal process performed thereafter is small and stays near the surface. This polysilicon film 34
The portion in the vicinity of the surface of is converted into a silicide film in a salicide process described later. Therefore, the influence of arsenic introduced into the polysilicon wiring in this process on the impurity concentration distribution in the polysilicon film after the manufacturing process is small.

Similarly, the N-channel region is masked with the photoresist 56, and P-type impurities such as boron (B ⁺ ) are ion-implanted into the P-channel region to form the source region and the drain region 58 of the P-channel region. (FIG. 4 (l)). At this time, at the same time, boron ions are also implanted into the polysilicon wiring 38 in the P channel region. The implantation conditions are, for example, 5 to ¹⁵ KeV and 3 to 4 × 10 ¹⁵ cm ^-2.
And Then, for example, heat treatment is performed at 1000 ° C. for 20 seconds to activate the implanted P-type impurities.

The dose amount of the P-type impurity with respect to the polysilicon wiring 38 is larger than the dose amount of the N-type impurity at the time of the blanket ion implantation step into the polysilicon film 34 shown in FIG. 2F, for example, 1 × 10 ¹⁵ It is preferably cm ⁻² or more. The ion implantation conditions of the P-type impurity for forming the source region and the drain region of the P channel MOS transistor described above satisfy this condition, and therefore, in the ion implantation process for forming the source and drain regions, the polysilicon is simultaneously formed. P-type impurities can be introduced into the wiring.

The P-type impurity introduced in this step is diffused almost uniformly in the film thickness direction of the polysilicon film by the heat treatment for activation and activated, whereby the P channel of the polysilicon film 34 is activated. The part of the region is from N type to P
Flip to mold.

On the other hand, the portion of the N channel region remains N type due to the N type impurities implanted before the patterning. A P / N junction is formed in the boundary region between the P-type portion and the N-type portion, and the introduced P
By mutually diffusing in the heat step (heat treatment step and step such as CVD step where the semiconductor substrate is heated to a high temperature) performed after the introduction of the n-type and n-type impurities,
A mutual diffusion region is formed.

When the blanket method described here is used, the concentration of the N-type impurity in the portion of the N-channel region other than the interdiffusion region of the polysilicon wiring is set to the first concentration, and the polysilicon wiring of the P-channel region is used. If the concentration of the P-type impurity in the portion excluding the mutual diffusion region of is the second concentration,
In a portion of the P channel region excluding the interdiffusion region of the polysilicon wiring, an N-type impurity having a third concentration lower than the first and second concentrations, that is, in the step shown in FIG. The entire surface of the polysilicon film 34 contains the ion-implanted N-type impurities.

Subsequently, the manufacturing process of the semiconductor device proceeds to a salicide process for forming a silicide film on the polysilicon wiring and on the source and drain regions in a self-aligned manner. First, in order to accelerate the silicidation reaction, for example, arsenic (As), silicon (Si), argon (A
r) or the like is ion-implanted to amorphize the surface of the polysilicon film 34.

This is a process that has been generally carried out conventionally, and its purpose is completely different from the blanket ion implantation of N-type impurities such as phosphorus into the polysilicon film 34 carried out in the present invention. That is, the polysilicon film 34
The purpose of the blanket ion implantation is to ensure that the whole is an N-type semiconductor. Therefore, ion implantation energy and thermal diffusion are required so that phosphorus, which is an N-type impurity, is diffused throughout the polysilicon film 34. It

On the other hand, in the ion implantation for amorphization, since only the surface of the polysilicon film 34 is amorphized, ions of a heavy element such as arsenic are deposited at low acceleration energy in the polysilicon film 34. Inject only near the surface. Therefore, the arsenic implanted in this process is absorbed in the silicide film by the silicidation reaction described later, and has almost no effect on the impurity concentration distribution in the polysilicon film at the end of the manufacturing process.

Then, a refractory metal film such as Ti (titanium) is deposited on the semiconductor substrate 12 by the sputtering method. Then, by heat treatment, the polysilicon film 34
The silicon substrate exposed in the source and drain regions and the refractory metal film are reacted with each other to form a silicide film 60 on the surfaces of the polysilicon wiring 38 and the source and drain regions 54 and 58 of the N-channel and P-channel MOS transistors. (FIG. 4 (m)). Then, the unreacted refractory metal film is removed. As a result, the polycide wiring of the present invention including the lower polysilicon film 34 and the upper silicide film 60 is formed.

Through the above steps, the P of the dual gate structure in which the gate, source and drain regions are silicided
A channel and an N-channel MOS transistor and a gate electrode of the MOS transistor are formed, and
Polycide wiring is formed to connect the two to each other.
After this, steps such as wiring formation are further performed to complete the semiconductor device. Since the manufacturing process is the same as the conventional one, the description thereof is omitted here. In addition, in each of the above steps, each step may be performed by using another means in order to obtain the same result.

As described above, in the method of manufacturing a semiconductor device according to the present invention, the thermal step of introducing impurities into the polysilicon film forming the polycide wiring by ion implantation and activating and diffusing the impurities. Is repeated. The impurity concentration distribution in the polysilicon film forming the polycide wiring of the completed semiconductor device is determined by such impurity introduction and heat treatment.

However, the impurity concentration distribution is mainly determined when the blanket method described above is used.
2F and 2G, a blanket N-type impurity is introduced into the entire polysilicon film 34, an N-type impurity is introduced into a portion of the N-channel region, and a heat treatment is performed thereafter for activation. In addition, in FIG. 4 (l), it is a heat treatment for introducing a P-type impurity, which is also performed to form the source and drain regions, and for subsequent activation.

The impurity distribution in the polysilicon film formed up to the step of FIG. 4 (l) is kept almost the same even after the salicide step of FIG. 4 (m) or after the completion of the semiconductor device. Be done.

Therefore, the impurity concentration distribution in the polysilicon film changes depending on the conditions of the above steps, for example, the ion implantation dose amount and the temperature and time of the heat treatment. Of course, when the normal method is used instead of the blanket method, the impurity distribution changes greatly.

The impurity distribution is also changed by changing the layout of the mask used for selectively introducing impurities into the N-channel region or P-channel region near the boundary. That is, for example, in FIG.
It is also possible to introduce at least one of the N-type impurity introduction in (1) and the P-type impurity introduction in FIG. 3 (j) into only a part of the entire surface of the N-channel region and the P-channel region, respectively. Particularly, in the boundary region between the N-channel region and the P-channel region, the impurity distribution changes depending on the position of the range where the N-type or P-type impurity is introduced. As will be described later, it has been clarified that by changing these process conditions and the mask layout to change the impurity concentration distribution, the state of occurrence of high resistance of the polycide wiring is different.

In the example described here, the introduction of the N-type impurity into the polysilicon film 34 is divided into the introduction of the blanket over the entire surface and the subsequent selective introduction into the N-channel region. It was Then, the total dose amount is introduced into the polysilicon film in the N channel region. It is also possible to introduce into the entire surface with a total dose amount without dividing into two introductions.

In that case, however, since the polysilicon film 34 in the P channel region is inverted to P type, it is necessary to increase the amount of P type impurities introduced later. This causes a problem that the load of the ion implanter increases.

When the P-type impurity is introduced into the P-channel region of the polysilicon film also as the P-type impurity for forming the source / drain regions as in the example described here, the P-type impurity is introduced. It is difficult to change the conditions for impurity implantation. Therefore, it is preferable to carry out the introduction in two steps.
When divided into two times, it is possible to carry out either the introduction of the blanket or the introduction into the N channel region first.

In the example described here, a heat treatment step for activation is provided after the introduction of the N-type impurity into the polysilicon film. However, this heat treatment can also be performed in another step. For example, it can be performed by appropriately setting the condition of the CVD process for forming the spacer 50 after the patterning. The same applies to the heat treatment for activation performed after introducing the P-type impurity.

Further, in the example shown here, the same impurity, that is, phosphorus is used for introducing the N-type impurity into the blanket and introducing the N-type impurity into the N-channel region. This is not essential to the manufacturing method of the present invention. But,
To simplify the manufacturing process, it is preferable to use the same impurities.

In the example described here, the P-channel MO is also introduced after introducing the P-type impurity into the polysilicon film in the P-channel region and patterning the polysilicon film.
P for forming the source and drain regions of the S transistor
It was performed in the step of introducing the type impurities. This is the preferred method for shortening the manufacturing process.

However, for example, the above-mentioned Japanese Patent Laid-Open No. 2001-77
It is also possible to introduce P-type impurities before patterning, as described in No. 210. It is also possible to perform the introduction separately before and after patterning. Furthermore, in the example described here, the P-type impurity is introduced into the polysilicon film before the high melting point metal film is deposited for the salicide process, but it is also possible to introduce it after the high melting point metal film is deposited. is there.

Next, the blanket method and the ordinary method described above are applied to explain a specific example of the semiconductor device having the polycide wiring of the present invention.

(Example 1) A TEG (test element group) 62 shown in FIG. 5, which was formed by a blanket method and a normal method and was formed by four types of mask layouts A, B, C and D shown later, was used. As one module,
Prototypes of dual gate semiconductor devices each having 660 of this module mounted were measured and their characteristics were measured.
The measurement result is shown in FIG.

In the case of production by the usual method, specifically,
Without introducing the N-type impurity into the polysilicon film in the blanket in the blanket method described above, the N-type impurity in the N-channel region is obtained by the total dose amount of the blanket introduction and the N-channel region introduction in the blanket method. Impurities were introduced. The other steps were performed in the same manner as in the blanket method described above.

The TEG 62 shown in FIG. 5 has an active region 6 of the P-channel region extending in the left-right direction in the central portion of the drawing.
The active regions 66 of the 4 and N channel regions are alternately arranged in the vertical direction, and the polycide wiring 68 of the dual gate structure extending in the vertical direction extends in the horizontal direction so as to pass through the upper layer of these active regions 64 and 66. Multiple lines are arranged. The plurality of polycide wirings 68 are one polycide wiring continuously formed by connecting the polycide wirings 68 adjacent to each other at the ends in the vertical direction. The line width of the polycide wiring was 0.24 μm.

The polycide wiring 68 has a dual gate structure as described above, and is composed of a lower polysilicon film and a silicide film formed above it, although not shown. In this polysilicon film, a portion passing over the active region 64 of the P channel region has P type polarity, and a portion passing over the active region 66 of the N channel region has N type polarity. These P-type polysilicon film and N-type polysilicon film are continuously formed by the same-layer polysilicon film.

In the length direction of the polycide wiring 68,
An extremely large number of P-type portions and N-type portions and boundary regions between them are formed in series. Therefore, by measuring the resistance value, the occurrence of resistance abnormality (resistance increase) in the boundary region can be detected with extremely high sensitivity. In fact, it was confirmed that anomalies occur in the boundary regions because resistance anomalies were observed with a detectable probability only in TEGs in which a very large number of boundary regions were connected in series.

However, in the observation by the inventor, it was not possible to observe a clear disconnection of the silicide film even in the polycide wiring exhibiting abnormal resistance. For example, due to the discontinuity of the impurity distribution in the polysilicon film in the boundary region, the silicidation reaction proceeds nonuniformly, and a finer shape abnormality that does not lead to a clear disconnection occurs, resulting in a resistance abnormality. May have occurred.

The four types A, B, C, and D described above are formed by using a mask having a layout as shown in FIG.

In FIG. 6, a mask pattern 66 for the active region of the N-channel region, a mask pattern 64 for the active region of the P-channel region (these are combined to form a mask for the active region), and an N-well mask. A pattern 70, a P ⁺ region mask pattern 72 used for forming P-type source and drain regions, and a gate mask pattern 68 used for patterning a polysilicon film are shown.

The P well mask is an N well mask pattern.
By reversing the transistor 70, P-type source and drain
N used for ion implantation for region formation⁺The area mask is
P⁺It by inverting the area mask pattern
Each is created. Therefore, N ⁺Area and P⁺Area is a figure
At P⁺Upper boundary of the area mask pattern 72
They are adjacent to each other at the boundaries. Here above this border
The side is the N channel region, and the lower side is the P channel region.

FIG. 6 shows only a portion within the range of one repeating unit constituting TEG62. Although omitted in the figure, in the actual mask, the P channel region and N
The channel regions and the channel regions are alternately and vertically arranged.
Further, in the lateral direction of the figure, N channel and P channel active regions 66, 64, P ⁺ region 72 and P well region 70 are formed extending long. Then, a plurality of gate patterns are repeatedly arranged at regular intervals.

In the manufacture of the semiconductor device in this example, a P well mask was used for implanting N type impurities into the N channel region of the polysilicon film. That is, N-type impurities are introduced into the polysilicon film outside the N-well mask pattern 70 shown in FIG.

As shown in FIG. 6, the gate pattern extends vertically with respect to the boundary between the P-channel region and the N-channel region. Therefore, the polycide wiring extending in the direction perpendicular to the boundary line is formed.

Type A is a standard pattern. In this case, the upper boundary of the P well mask pattern 70 is P
It coincides with the upper boundary line of the ⁺ region mask pattern 72. Therefore, the implantation of N-type impurities into the polysilicon film is
Performed on the entire N-channel region using a mask that covers only the P-channel region.

On the other hand, in the implantation for forming the P-type source / drain regions, P to the polysilicon film after patterning is performed.
The implantation of the type impurities is performed on the entire P channel region by using a mask covering only the N channel region. Therefore,
The region into which the N-type impurity is implanted and the region into which the P-type impurity is implanted are vertically adjacent to each other with a common boundary line in contact,
If there is no mask misalignment, no overlap or gap occurs between them.

In the type B, the upper boundary line of the P well mask pattern is based on the upper boundary line of the P ⁺ region (the boundary between the P channel region and the N channel region) and the upper side (N channel region). It is shifted by 0.3 μm from the side). In this case, the N-type impurity implantation into the polysilicon film is
Not only in the P channel region, but in P in the N channel region
Near the boundary between the channel region and the N channel region,
0 in the vertical direction, that is, in the length direction of the polycide wiring.
It is performed in a state of covering a 3 μm portion (predetermined region).
As a result, the N-type impurity introduction position is adjusted. That is, N-type impurities are not implanted into the polysilicon film in the 0.3 μm portion near the boundary. In the case of the blanket method, only N-type impurities are introduced into the predetermined region of 0.3 μm by blanket implantation.

Types C and D are of types A and B, respectively.
In the above, the width of the gate pattern 68 in the predetermined region near the boundary between the P channel region and the N channel region is increased. Such a widened portion is hereinafter referred to as a polypatch 74.

Incidentally, as shown in FIG.
Has a square shape, and its size is 0.4 μm × 0.
Two types were manufactured, one of 4 μm and one of 0.3 μm × 0.3 μm. Gate pattern 68 before adding polypatch
Has a width of 0.24 μm, and the width is evenly widened in the left-right direction. That is, the size of the polypatch is 0.4 μm × 0.4
In the case of μm, it is about 1.7 times that before addition, 0.3 μm ×
In the case of 0.3 μm, it was expanded about 1.3 times. In the vertical direction, the polypatch 74 is arranged so that the center thereof coincides with the boundary between the P-channel region and the N-channel region.

In the table of FIG. 7, A, B, C and D represent the types A, B, C and D shown in FIG. Further, the process condition 1 is manufactured by the normal method, and the process condition 2 is manufactured by the blanket method.

The following can be seen from the measurement results of FIG.

1. Improvement by manufacturing process First, compared to process 1 (normal method), process 2
(Blanket method) is excellent. For example, comparing types A with each other, the number of defects in the conventional method was 116, whereas the number in the blanket method was reduced to 77.

2. Improvement by mask layout Compared with standard A type, C with polypatch added
However, in addition to the addition of the polypatch, D in which the position for introducing the N-type impurity is adjusted is excellent. For example, when manufactured by the normal method, the number of defects was reduced to 72 in the type C and 66 in the type D.

3. The synergistic effect of improving the synergistic process and improving the mask layout further significantly reduces the number of defects. That is,
The number of defects was reduced to 23 by the combination of the blanket method (Process 2) and the polypatch (C), and further to 2 by the combination (D) with the adjustment of the N-type impurity introduction position.

It is considered that the reason why the improvement by the blanket method is obtained is that it is possible to surely prevent the non-doped region from remaining in the polysilicon film, and to suppress the progress of the non-uniform silicidation reaction near the boundary. Further, since the heat treatment for activation is performed after introducing the N-type impurity of a certain concentration or more or the same N-type impurity (specifically, phosphorus) over the entire surface of the polysilicon film, the crystal growth in this heat treatment is It can be considered that one of the causes is that the process proceeds uniformly and the crystal grain size distribution of the polysilicon film is made uniform.

The effect of adding a polypatch is as described in the above-mentioned JP-A-200
1-77210. The cause of the effect of the combination of the polypatch and the adjustment of the N-type impurity implantation range will be described later.

The size of the polypatch 74 is 0.4 μ.
No significant difference was observed in the improvement effect between the case of m × 0.4 μm and the case of 0.3 μm × 0.3 μm. However, considering the results of various experiments, the width of the polycide wiring in the boundary region is compared with the widths of other parts (the part used as the gate electrode of the MOS transistor),
At least 1.2 times or more, preferably 1.5 times or more,
Further, if possible, it is preferable to adopt a polypatch having a size which is doubled or more.

Needless to say, the shape of the polypatch is not limited to the square. The position and dimensions of the polycide in the length direction of the polycide wiring ensure that the high-resistivity region formed in the polysilicon film near the boundary will be in the polypatch part even if mask misalignment or manufacturing process variations occur. It is preferable to set it to be included. This point will also be described later.

Next, the impurity concentration distribution in the polysilicon film forming the polycide wiring, especially the positions of the P / N junction and the high resistance region formed near the boundary between the N channel region and the P channel region, and the position of the poly patch. Consider relationships.

FIG. 8 and FIG. 9 are graphs of an example showing the simulation result of the impurity concentration profile in the polysilicon film of the polycide wiring after the manufacturing process is completed. The horizontal axis represents the position in the length direction of the polycide wiring, and the vertical axis represents the impurity concentration. In addition, these graphs are examples in the case of manufacturing by a normal method.

The graph shows the net (net) doping amount and the total doping amount. The total doping amount is the total concentration of the introduced P-type impurities and the N-type impurities, and the net doping amount is the absolute value of the difference between the concentration of the introduced P-type impurities and the concentration of the N-type impurities.
The position of 1 μm on the horizontal axis in the figure is the boundary position between the P channel region and the N channel region on the mask, the left side in the figure is the N channel region, and the right side is the P channel region. Here, the valley of the doping amount of the net corresponds to the mutual diffusion region, and the position of the bottom of the valley corresponds to the position of the P / N junction. The amount of net doping is extremely high near the valley bottom (for example, 1 × 10 ¹⁸ cm ^−3).
The region that has decreased (to a certain extent) is the high resistance region.

First, the type C is shown in the graph of FIG.
It is a simulation result about the case of. In this case, the N-type impurity is introduced into the polysilicon film on the left side thereof and the P-type impurity is introduced into the polysilicon film after patterning on the right side thereof with a position of 1 μm on the horizontal axis as a boundary. The polypatch is formed in the range of 0.8 to 1.2 μm.

From the simulation result, the position of the P / N junction was found to be on the right side from the position of 1 μm which is the boundary on the mask,
That is, it can be seen that it is formed at a position displaced by about 0.16 μm on the P channel region side. As described above, in the normal method, first, the N-type impurity is introduced into the N-channel region of the polysilicon film, and the N-type impurity activation is performed before the P-type impurity is introduced into the P-channel region. Heat treatment is performed. During this heat treatment, the N-type impurity diffuses in the P channel region direction, that is, in the right direction in the figure, so that such P
It is considered that the shift of the / N junction position occurred.

In the illustrated case, the P / N junction position is still within the range of 0.8 to 1.2 μm where the polypatch is provided. However, there is no room in consideration of the fluctuation of process conditions and the possibility of mask misalignment.

On the other hand, the graph of FIG. 9 shows that type D
It is a simulation result about the case of. Also in this case, the same as in the case of FIG.
A shift to the channel region side) is seen. However, the shift distance is about 0.05 μm, which is suppressed to about 1/3 or less of the case of FIG. In this case, the high resistance region remains within the range of the polypatch even if the change in process conditions and the possibility of mask misalignment occur.

In the case of type D, the introduction of P-type impurities into the polysilicon film is performed on the right side of the position of 1 μm in the figure, as in the case of type C shown in FIG. However, the introduction of N-type impurities is 0.3 μm to the left from the 1 μm position in the figure.
Is not performed in the range of, but only on the left side from the position of 0.7 μm. Therefore, it is considered that the diffusion of the N-type impurities into the P channel region due to the heat treatment was suppressed, and as a result, the shift of the P / N junction position was suppressed.

As described above, by suppressing the P / N junction position shift, the high resistance region is surely retained in the poly patch. As shown in FIG. 7, addition of the poly patch and adjustment of the N-type impurity introduction position are performed. It can be interpreted that this is the reason why a particularly large effect is obtained in the type D in which

From these results, even if the polypatch is arranged at the boundary position of the mask for introducing the P-type and N-type impurities, the actual position of the P / N junction shifts from the boundary position on the mask. It can be seen that the high resistance region may not be completely covered with the polypatch. On the other hand, like the type D, by adjusting the position where impurities are introduced into the polysilicon film, it is possible to suppress the shift of the P / N junction position and keep the high resistance region within the polypatch. I found out.

Of course, if the dimension of the polycide in the length direction of the polycide wiring is increased, it is possible to keep the high resistance region within the polypatch even if the shift amount of the P / N junction position is large. However, enlargement of the dimension of the polypatch in the lengthwise direction is not preferable for miniaturization of the semiconductor device. Therefore, the size of the polypatch in the lengthwise direction is increased by suppressing the shift of the P / N position by devising the mask layout as in the type D, or adjusting the position of the polypatch according to the shift amount. Instead, it is preferable to keep the high resistance region within the polypatch.

In the example shown here, the P / N junction position was shifted due to the diffusion of the N-type impurity toward the P channel region. Therefore, the shift can be suppressed by using the type D mask layout and not introducing the N-type impurity into the predetermined region near the boundary. However, the generation direction and distance of the P / N junction position shift differ depending on the flow and conditions of the process used for manufacturing the semiconductor device. Therefore, it is preferable to select an appropriate shift suppression measure, specifically, a method of adjusting the impurity introduction position, and a layout of a mask used for introducing impurities according to the process flow and conditions to be used.

In the type D exemplified here, the P / N junction position is shifted in the case of the type C, that is, N by not introducing the N-type impurity into the predetermined region of 0.3 μm near the boundary. Approximately 1 / third compared with the case where the prescribed region where the impurity is not introduced is not provided and the impurity introduction position is not adjusted
Could be suppressed to 3. Generally, a remarkable effect can be obtained by setting the size of the predetermined region so that the shift of the P / N junction position can be suppressed to 1/2 or less as compared with the case where the impurity introduction position is not adjusted. be able to.

In the example of the above graph, the blanket ion implantation is not performed on the polysilicon film, but the same can be said when blanket ion implantation is performed.

Summarizing the above experimental results, first, a significant improvement effect can be obtained by introducing a blanket impurity into the polysilicon film. Also, P
A polypatch is added to the boundary position between the channel region and the N-channel region, and in addition to this, the shift of the P / N junction position is suppressed so that the high resistance region remains in the polypatch. It is preferable to adjust the impurity introduction position.

By combining the impurity introduction of the blanket with the polypatch, or the polypatch and the impurity introduction position adjustment, a more remarkable synergistic effect can be obtained.

The polycide wiring, the method for forming the same, and the method for manufacturing a semiconductor device according to the present invention are basically as described above. The polycide wiring, the method for forming the same, and the method for manufacturing a semiconductor device according to the present invention have been described above in detail. However, the present invention is not limited to the above-described embodiments, and various improvements and changes are made without departing from the spirit of the present invention. Of course you can

For example, the polycide wiring of the present invention is not limited to the application for mutually connecting the gate electrodes of the P-channel MOS transistor and the N-channel MOS transistor forming a CMOS circuit as a set, and is not limited to a semiconductor device. It can be used as various wirings used.

[0110]

As described above in detail, according to the present invention, it is possible to prevent the polycide wiring used in a semiconductor device from breaking or having a high resistance, and to configure a semiconductor device using this polycide wiring. In the above, the disconnection of the polycide wiring and the increase in resistance can be suppressed, and the product yield can be improved.

[Brief description of drawings]

1A to 1D are cross-sectional views of an embodiment showing each step of a method for manufacturing a semiconductor device of the present invention.

2 (e) to 2 (g) are cross-sectional views of an example showing each step of the method for manufacturing a semiconductor device of the present invention, following FIG. 1 (d).

3 (h) to 3 (j) are cross-sectional views of an example showing each step of the method for manufacturing a semiconductor device of the present invention, following FIG. 2 (g).

4 (k) to (m) are cross-sectional views of an example showing each step of the manufacturing method of the semiconductor device of the present invention, following FIG. 3 (j).

FIG. 5 is a layout diagram of an example of a TEG.

FIG. 6 is a layout diagram showing four types of mask layouts in a TEG.

FIG. 7 is a table of an example showing the measurement results of TEG.

FIG. 8 is a graph of an example showing an impurity profile in the vicinity of a P / N junction of a polysilicon wiring of a gate electrode.

FIG. 9 is a graph of another example showing the impurity profile in the vicinity of the P / N junction of the polysilicon wiring of the gate electrode.

FIG. 10 is an example graph showing a yield of a semiconductor device manufactured by a conventionally known manufacturing process.

[Explanation of symbols]

10 semiconductor device 12 semiconductor substrate 14 silicon oxide film 16 silicon nitride film 18, 22, 26, 36, 42, 48, 52, 56 photoresist 20 element isolation region 24, 70 N well 28 P well 32 gate insulating film 34 polysilicon Film 38 Polysilicon wiring 40, 46 LDD regions 54, 58 Source and drain regions 60 Silicide film 62 TEG 64 P channel region active region 66 N channel region active region 68 Polycide wiring 72 P ⁺ region

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshitaka Kimura             3-3 Nakase Nakase, Mihama-ku, Chiba-shi, Chiba             Saki Microelectronics Co., Ltd. Makuhari             Head office F-term (reference) 4M104 AA01 BB01 BB37 BB40 CC05                       DD04 DD26 DD37 DD43 DD78                       DD84 DD89 FF14 GG09 GG10                       GG14 HH14 HH16                 5F033 HH04 HH27 LL04 LL08 MM07                       PP06 PP15 QQ08 QQ09 QQ31                       QQ58 QQ59 QQ61 QQ65 QQ70                       QQ73 QQ79 RR04 RR06 SS11                       TT08 VV06 XX03 XX10 XX15                 5F048 AA07 AC03 BA01 BB06 BB07                       BB08 BB12 BC06 BD04 BE03                       BF03 BF06 BG14 DA25 DA27

Claims (10)

[Claims] 1. A polycide wiring of a semiconductor device, comprising a silicon film having a first portion in a length direction and a second portion connected to the first portion via a boundary, and a first portion of the silicon film. And a silicide film laminated on the second portion, the first portion of the silicon film contains N-type impurities, and the second portion of the silicon film contains at least P-type impurities. An interdiffusion region in which the N-type impurity and the P-type impurity are mutually diffused is present between the first portion and the second portion of the silicon film, and the first portion of the silicon film is included. Has a first concentration in the portion excluding the mutual diffusion region, and has a second concentration in the portion except the mutual diffusion region in the second portion of the silicon film having the second concentration. The interdiffusion region of the second portion of the silicon film In addition, the portion other than the portion further contains an N-type impurity having a third concentration lower than the first and second concentrations, and the connecting portion including the boundary has a larger width than both sides thereof. Characteristic polycide wiring. 2. The polycide wiring according to claim 1, wherein the third concentration is 5 × 10 ¹⁸ cm ⁻³ or more. 3. A method of forming a polycide wiring of a semiconductor device, which comprises depositing a silicon film on a semiconductor substrate via an insulating film, and a first dose of a first N film on the entire surface of the silicon film. A step of introducing a type impurity, a mask covering the second portion of the silicon film is formed, and a boundary of the second portion is in contact with the first portion on the opposite side to a second portion having a second dose amount. 2. Introducing an N-type impurity, and patterning the N-type impurity-introduced silicon film into a shape of a wiring that is connected to the second portion from the first portion across the boundary. A step of introducing a P-type impurity having a third dose amount larger than the first dose amount into only the second portion of the silicon film before or after the patterning, and on the patterned silicon film A high melting point metal film And, by reacting the silicon film and the refractory metal film and forming a silicide film, the shape of the wiring in the connection area including the boundary,
A method for forming polycide wiring, which has a larger width than the regions on both sides thereof. 4. The method for forming a polycide wiring according to claim 3, wherein the introduction of the P-type impurity is performed after the patterning and before the deposition of the refractory metal film. 5. The method for forming a polycide wiring according to claim 3, wherein the first dose amount is 1 × 10 ¹⁴ cm ⁻² or more. 6. A method of manufacturing a polycide wiring of a semiconductor device, which comprises depositing a silicon film on a semiconductor substrate with an insulating film interposed between the second part of the silicon film and the second part. Forming a mask covering a predetermined region in the vicinity of a boundary between the first portion and the second portion, and introducing an N-type impurity into a portion of the first portion which is not covered by the mask; Patterning a silicon film into which an N-type impurity has been introduced into a shape of a wiring extending from the first portion to the second portion across the boundary; and Introducing a P-type impurity into the second portion, performing the patterning, depositing a refractory metal film on the silicon film into which the P-type impurity is introduced, and reacting the silicon film with the refractory metal film. So has a step of forming a silicide film, the shape of the wiring in the connection area including the boundary,
A method for forming polycide wiring, which has a larger width than the regions on both sides thereof. 7. The method for forming a polycide wiring according to claim 6, wherein the P-type impurity is introduced after the patterning. 8. A method of manufacturing a semiconductor device having polycide wiring, comprising: depositing a silicon film on a semiconductor substrate with an insulating film interposed therebetween; and a first dose of N-type impurities on the entire surface of the silicon film. And a mask for covering the second portion of the silicon film is formed, and a second dose of a second dose is applied to the first portion on the opposite side with the boundary being in contact with the second portion. Introducing an N-type impurity; patterning the N-type impurity-introduced silicon film into a shape of a wiring extending from the first portion to the second portion across the boundary; Before or after the step of introducing a P-type impurity of a third dose amount larger than the first dose amount into only the second portion of the silicon film, and a high melting point on the patterned silicon film. Metal film stack And a step of reacting the silicon film with the refractory metal film to form a silicide film. After the manufacturing process of the semiconductor device is completed, a P / N junction is formed in the silicon film near the boundary. A method for manufacturing a semiconductor device having a polycide wiring, wherein the shape of the wiring has a larger width in a connection region including a position where the P / N junction is formed than in regions on both sides thereof. 9. A method of manufacturing a semiconductor device having polycide wiring, comprising: depositing a silicon film on a semiconductor substrate via an insulating film; a second portion of the silicon film; and the second portion. Forming a mask covering a predetermined region in the vicinity of a boundary between the first portion and the second portion connected to the first portion, and introducing an N-type impurity into a portion of the first portion not covered by the mask. Patterning the silicon film into which the N-type impurity has been introduced into a shape of a wiring extending from the first portion to the second portion across the boundary; and the silicon film before or after the patterning. A step of introducing a P-type impurity into the second portion of the above, and the patterning is performed to deposit a refractory metal film on the silicon film into which the P-type impurity has been introduced. To form a silicide film, and after the manufacturing process of the semiconductor device is completed, a P / N junction is formed near the boundary in the silicon film, and the shape of the wiring is the P / N. A method of manufacturing a semiconductor device having a polycide wiring, which has a larger width in a connection region including a position where a junction is formed than in regions on both sides of the connection region. 10. A lengthwise dimension of the polycide wiring in the predetermined region is set to be 1/2 or less of a distance from the boundary to a position where the P / N junction is formed when the dimension is zero. 10. The method for manufacturing a semiconductor device having polycide wiring according to claim 9, wherein the setting is made as follows.