JP2003099008A - Planar display device and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize cost reduction by reducing the number of output terminals of a controller. SOLUTION: Display data DATA, a start pulse YST, a clock YCK, etc., are inputted from a controller to a display panel DP, and a gate line driving circuit GD outputs a serial output signal from a built-in shift register. A polarity inversion driving circuit CTcom1 uses this signal as a polarity inversion instruction signal REF and generates a common voltage Vcom to be applied to a common electrode. Thus, the polarity inversion instruction signal REF does not need to be outputted from the controller CTL1, and this reduces the number of the output terminals and contributes to cost reduction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, flat panel display devices using liquid crystal panels, organic EL panels and the like have been widely used. FIG. 9 shows the configuration of a conventional flat display device, and the time chart of FIG. 10 shows the waveform of each drive signal.

A controller C is provided around the display panel DP.
TL11, power supply circuit DC / DC1, polarity inversion drive circuit C
Tcom11 is located. Controller CTL1
1, power supply circuit DC / DC1, polarity inversion drive circuit CTcom
11 may be provided on the same insulating substrate as the display panel DP or may be provided outside the substrate.

The display panel DP is provided with an active matrix substrate and a counter substrate which is arranged so as to face the active matrix substrate so as to sandwich liquid crystal, organic EL or the like in the gap.

A plurality of signal lines (not shown) and a plurality of gate lines (not shown) are arranged on the active matrix substrate, and a transistor is arranged as a switching element at each intersection. A common electrode is arranged on the counter substrate.

The signal line and the gate line are driven by a signal line drive circuit and a gate line drive circuit (not shown), respectively.

The power supply circuit DC / DC1 is supplied with a voltage of + 3V from the outside, for example, and generates 10V, -5V and + 5V and supplies them to the display panel DP.

The polarity reversal drive circuit CTcom11 supplies the common voltage Vcom to the common electrode provided on the counter substrate and the reference voltages Vref1 and Vref2 to the active matrix substrate.

The controller CTL11 has a built-in frame memory FM for storing video data, and the video data D is supplied to a signal line drive circuit on the active matrix substrate.
ATA and start pulse XS as a signal line control signal
T, clock XST is supplied to the gate line drive circuit as a gate line control signal, start pulse YST, clock Y
Supply ST. Further, the controller CTL11 supplies the power supply circuit DC / DC1 with a control signal SHUT so as not to output the power supply voltage from the power supply circuit DC / DC1 to the display panel DP when the power supply voltage is unstable immediately after the power is turned on. , And polarity reversal drive circuit CT
And a polarity inversion instruction signal REF and a control signal SHUT for instructing the timing of polarity inversion.

[0010]

However, the above-mentioned conventional flat display device has the following problems.

A signal line drive circuit, a gate line drive circuit, a power supply circuit DC / DC1, a polarity reversal drive circuit CTco arranged on the active matrix substrate in the display panel DP.
The display data DATA and each control signal to be supplied to m11 are all supplied by the controller CTL11. Therefore, the number of output terminals of the controller CTL11 is large, which hinders cost reduction.

In view of the above circumstances, it is an object of the present invention to provide a flat panel display device and a driving method thereof which can reduce the number of output terminals of a controller and realize cost reduction.

[0013]

According to another aspect of the present invention, there is provided a flat panel display device in which a first substrate having a signal line and a gate line arranged in a display region, a first substrate, and a common electrode. A second substrate, a display panel having a signal line drive circuit for driving the signal line, and a gate line drive circuit for driving the gate line; and outputting a gate line control signal to the gate line drive circuit, A controller for outputting display data and a signal line control signal to the signal line drive circuit, and a gate line drive signal generated by the gate line drive circuit given the gate line control signal as a signal for instructing the timing of polarity inversion. And a polarity inversion drive circuit for generating a common voltage by using the common voltage and supplying the common voltage to the common electrode.

The controller outputs a start pulse and a clock as the gate line control signal to the gate line drive circuit, and the gate line drive circuit includes a plurality of stages of flip-flops connected in series, each of the flip-flops. May sequentially shift and transfer the start pulse in accordance with the timing of the clock to generate the gate line drive signal.

In the flat panel display device of the present invention, the first substrate on which the signal line and the gate line are arranged in the display region and the second substrate on which the common electrode is arranged so as to face the first substrate. A display panel having a signal line drive circuit for driving the signal line and a gate line drive circuit for driving the gate line; and a gate line control signal for outputting to the gate line drive circuit, the signal line drive circuit A controller that outputs display data and a signal line control signal, and a first power supply voltage that is supplied, and that uses the first power supply voltage to generate at least one second power supply voltage that is supplied to the display panel, Further, a power supply circuit for generating substantially stationary first voltage and second voltage which the common voltage to be supplied to the common electrode has, and a gate generated by the gate line drive circuit given the gate line control signal. The drive signal is given as a polarity inversion instruction signal for instructing the timing of polarity inversion, and further the first and second voltages output from the power supply circuit are given, and the polarity inversion instruction signal is used as a switching control signal. And a switch circuit which alternately outputs the first and second voltages to generate the common voltage and supplies the common voltage to the common electrode.

Here, the power supply circuit, which is included in the second power supply voltage, should be supplied to the signal line drive circuit. The first reference voltage and the second reference voltage are in a mutually inverted polarity relationship. And a substantially constant third voltage and a fourth voltage that the voltage has, and the switch circuit uses the gate line driving signal as the switching control signal to generate the first voltage and the second voltage. It is also possible to alternately output the first reference voltage and the second reference voltage and supply them to the signal line drive circuit.

A method of driving a liquid crystal display device according to the present invention comprises: a first substrate having a signal line and a gate line arranged in a display area;
A display panel having a second substrate facing the first substrate and having a common electrode, a signal line driving circuit driving the signal lines, and a gate line driving circuit driving the gate lines. A method of driving a flat display device including the steps of: supplying a gate line control signal to the gate line drive circuit; supplying display data and a signal line control signal to the signal line drive circuit; A step of generating a gate line drive signal using the gate line control signal, and a step of generating a common voltage using the gate line drive signal as a signal instructing timing of polarity inversion and supplying the common voltage to the common electrode. It is characterized by having and.

In the step of supplying the gate line control signal, a start pulse and a clock are supplied to the gate line drive circuit, and in the step of generating the gate line drive signal by the gate line drive circuit, according to the timing of the clock. The gate line drive signal can be generated by sequentially shifting and transferring the start pulse.

The driving method of the flat panel display device of the present invention is
A first substrate on which a signal line and a gate line are arranged in a display region, a second substrate which is arranged opposite to the first substrate and on which a common electrode is arranged, and a signal line driving circuit which drives the signal line. And a gate line driving circuit for driving the gate line, which is a method of driving a device including a display panel, wherein a gate line control signal is supplied to the gate line driving circuit, and display data and display data are supplied to the signal line driving circuit. Supplying a signal line control signal, and using the first power supply voltage to generate at least one second power supply voltage to be supplied to the display panel,
Further, generating a substantially steady first voltage and a second voltage that the common voltage to be supplied to the common electrode has, and the gate line drive circuit using the gate line control signal by the gate line drive circuit. And the gate line drive signal is used as a polarity inversion instruction signal for instructing the timing of polarity inversion, and the polarity inversion instruction signal is used as a timing signal for switching control to alternate the first and second voltages. To generate the common voltage and supply the common voltage to the common electrode.

In the step of generating the second power supply voltage, the first reference voltage and the second reference voltage, which are in a relationship in which the polarities are inverted to each other, which should be supplied to the signal line drive circuit, are substantially stationary. Generating the third voltage and the fourth voltage, using the gate line drive signal as the switching control signal, and alternately outputting the first voltage and the second voltage to output the first reference voltage. The method may further include the step of generating a voltage and a second reference voltage and supplying the voltage and the second reference voltage to the signal line driving circuit.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a flat panel display device and a driving method thereof according to embodiments of the present invention will be described with reference to the drawings.

(1) First Embodiment The configuration of the flat panel display device according to the first embodiment is as shown in FIG.

Conventionally, as described with reference to FIG. 9, the polarity inversion instruction signal RE to be supplied to the polarity inversion drive circuit CT.
The controller CTL11 generated and output F.
The polarity inversion instruction signal REF generates a pulse once during one horizontal period 1H, as shown in FIG. Such a signal can be generated by combining the start pulse YST and the clock YCK, which are output from the same controller CTL11 to the gate line drive circuit as the gate line control signal. This makes it possible to eliminate the output of duplicated signals and reduce the number of output terminals of the controller CTL11.

Therefore, the display data DATA and the start pulse XS are displayed on the display panel DP from the controller CTL1.
T, clock XCK, start pulse YST, clock YCK are output, and control signal SH is output to power supply circuit DC / DC1.
The control signal SH is output without outputting the polarity inversion instruction signal REF to the polarity inversion circuit CTcom1.
Output only UT.

In a gate line drive circuit, which will be described later, provided on the display panel DP, a signal generated by receiving a start pulse YST and a clock YCK is output to the polarity inversion drive circuit CTcom1 as a polarity inversion instruction signal REF. The polarity reversal drive circuit CTcom1 uses the polarity reversal instruction signal REF and the control signal SHUT to, for example, a common voltage Vco for reversing the polarity between 4.7V and 0.3V.
m, for example, reference voltages Vref1 and Vref2 whose polarity is inverted between 4.5 V and 0.5 V are generated, common voltage Vcom is output to the counter substrate, and reference voltages Vref1 and Vref2 are provided on the display panel DP, which will be described later. Output to a digital / analog conversion circuit included in the signal line drive circuit. The same elements as those shown in FIG. 9 described above are designated by the same reference numerals, and description thereof will be omitted.

FIG. 2 shows the configuration of the circuit arranged on the display panel DP, and FIG. 4 shows the operation waveform of each signal in this circuit. Here, in the display panel DP, a drive circuit is formed on the same insulating substrate by using low-temperature polysilicon technology or the like in addition to the display area DA.

In the display area DA, a plurality of gate lines GL are arranged, and a plurality of signal lines SL are arranged so as to be orthogonal to the gate lines GL, and a thin film transistor (hereinafter, referred to as a switch element) as a switching element for each intersecting pixel. TFT
Tr (called Thin Film Transistor) is arranged. The gate of the TFT Tr is connected to the gate line GL, the source is connected to the signal line SL, and the drain is connected to a pixel electrode (not shown). The pixel electrode holds the liquid crystal LC and is arranged on the counter substrate. Common voltage Vcom
Is arranged so as to face a common electrode to which is applied.

The signal line SL is driven by the signal line drive circuit SD and supplied with the video data DATA. The signal line drive circuit SD includes a data latch circuit DL and a digital / digital
It has an analog (hereinafter referred to as D / A) conversion circuit DAC. The video data DATA stored in the frame memory FM is given to the data latch circuit DL, and the start pulse XST and the clock XST outputted from the controller CTL1 are given. This start pulse XS
According to the timing of T, the video data DATA is output to the D / A conversion circuit DAC.

The D / A conversion circuit DAC has video data DA.
In addition to TA, start pulse XST, clock XCK,
Reference voltage Vr output from the polarity inversion drive circuit CTcom1
ef1 and Vref2 are provided. The reference voltages Vref1 and Vref2 are video data DA as digital data.
The minimum voltage and the maximum voltage are shown when TA is converted into analog data of a plurality of gradations. When there are three or more reference voltages, any one of the intermediate voltages is indicated. Then, the D / A conversion circuit DAC sequentially outputs the display data DATA converted into analog data to the signal line SL in accordance with the timing of the start pulse XST.

Any one of the gate lines GL is sequentially driven by the gate line drive circuit GD. The start pulse YST and the clock YCK described above are input to the gate line drive circuit GD, and a serial out signal described later is generated as a gate line drive signal and output to the gate line GL. Here, FIG. 3 illustrates a configuration of a shift register as an example of a specific circuit of the gate line driver circuit GD. Flip-flops S / R0, S / R1, S / R2, ..., S / R
n-1 (n is an integer of 2 or more) are connected in series, and the clock YCK is input to each clock terminal CK. Then, the start pulse YST input to the data terminal D of the first-stage flip-flop S / R0 is shifted to the subsequent flip-flops S / R1, S / R2, ... According to the timing of the clock YCK.

In this way, each flip-flop S
, R0, S / R1, S / R2, ..., S / Rn−1, output terminals Q of serial output signals OUT0, OUT1, OU sequentially phase-shifted by the timing of clock YCK.
T2, ..., OUTn-1 are output. The serial out signals OUT0, OUT1, OUT2, ..., OUTn-1
Either of them is taken out as a polarity inversion instruction signal REF and output to the polarity inversion drive circuit CT. Here, one of the serial out signals OUT0, OUT1, OUT
When using 2, ..., OUTn−1, adjustment is performed as necessary so that a desired phase is obtained.

As described above, in the present embodiment, the controller CTL1 does not output the polarity inversion instruction signal REF to the polarity inversion drive circuit CT, but rather the controller CTL1.
Start pulse YST and clock YS output from
Serial out signals OUT0, OUT1, OUT2, ..., OUTn− from the gate line drive circuit GD to which T is given
Any one of 1 is used as the polarity inversion instruction signal REF.
As a result, the conventional controller CTL shown in FIG.
Unlike 1, the terminal that has output the polarity inversion instruction signal REF is not required, so that the number of output terminals can be reduced and the cost can be reduced.

(2) Second Embodiment The present embodiment has the configuration shown in FIG. 5, and the operation waveform of each signal is shown in the time chart of FIG.

In the first embodiment, the polarity reversal drive circuit CTcom1 is supplied with the polarity reversal instruction signal REF to generate the common voltage Vcom and the reference voltages Vref1 and Vref2. On the other hand, in the present embodiment, the polarity inversion drive circuit CT is omitted, and instead of this, the power supply circuit D
C / DC2 is a constant voltage VcomH (for example, 4.7V), Vc
omL (eg 0.3 V), voltage VrefH (eg 4.5 V
V) and VrefL (for example, 0.5 V) are generated and output to the analog switch circuit ASW. The analog switch circuit ASW has voltages VcomH, VcomL, VrefH, and VrefL.
And the polarity reversal instruction signal REF output from the gate line drive circuit GD, and the common voltage Vcom and the reference voltages Vref1 and Vref2 are generated and output.

FIG. 6 shows the power supply circuit D according to this embodiment.
The structure of C / DC2 is shown. This power circuit DC / DC2
Is the power supply circuit DC / DC in the first embodiment.
In addition to supplying the power supply voltages + 10V and -5V to the gate line drive circuit GD and supplying + 5V to the signal line drive circuit SD as in the case of 1, the constant voltages VcomH, VcomL, VrefH and Vref are also provided.
L is constantly output.

Here, the analog switch circuit ASW is provided on the same insulating substrate as the display panel DP,
It has six switch elements SW1 to SW6.

The switches SW1 to SW6 have voltages VrefH, VrefL, VrefH, VrefL, and
VcomH and VcomL are input, and both are turned on / off at the same timing by the polarity inversion instruction signal REF. The signal output from the switches SW1 and SW2 is 1
The signal outputted from the output terminal a1 of the book as the reference voltage Vref1 which switches between 0.5V and 4.5V for each frame and outputted from the switches SW3 and SW4 is 1
The output terminal b1 of the book is switched between 0.5 V and 4.5 V for each frame, and is output as a reference voltage Vref2 having a polarity opposite to that of the voltage Vref1. Further, the signals output from the switches SW5 and SW6 are output from one output terminal c1 as a common voltage Vcom which switches between 0.3V and 4.7V for each frame. The reference voltages Vref1 and Vref2 are supplied to the D / A conversion circuit DAC, and the common voltage Vcom is supplied to the common electrode of the counter substrate (not shown).

The switch elements SW1 to SW6 have the same structure, and among them, the switch element SW5.
7 is shown as an example. The P-channel transistor PT and the N-channel transistor NT are connected in parallel, the inverted polarity inversion instruction signal / REF is input to the gate of the P-channel transistor PT, and the polarity inversion instruction signal REF is input to the gate of the N-channel transistor, respectively. ON / OFF is controlled at the timing of, and the reference voltage Vref1 is input to the input terminal side and output from the output terminal a2. With such a configuration, the analog switch circuit ASW opens and closes for each frame and outputs the common voltage Vcom and the reference voltages Vref1 and Vref2.

Also in this embodiment, as in the first embodiment, instead of the controller CTL1 outputting the polarity inversion instruction signal REF, the controller CTL1 is also used.
Start pulse YST and clock YS output from
Serial out signals OUT0, OUT1, OUT2, ..., OUTn− from the gate line drive circuit GD to which T is given
Any one of 1 is used as the polarity inversion instruction signal REF.
Further, in the present embodiment, the polarity reversal drive circuit is eliminated and the constant voltage VcomH, VcomL,
Analog switch circuit A that outputs VrefH and VrefL
Output to SW. And the analog switch circuit ASW
, The common voltage Vcom and the reference voltage Vref1 are opened and closed for each frame based on the polarity inversion instruction signal REF.
And Vref2 are output.

As a result, unlike the conventional controller CTL1 shown in FIG. 9, a terminal for outputting the polarity inversion instruction signal REF is unnecessary, and it is possible to reduce the number of output terminals and reduce the cost. Furthermore, the polarity inversion drive circuit that is composed of an analog circuit and consumes a large amount of power is deleted, and the steady output from the power supply circuit DC / DC2 is switching-controlled to generate the voltages Vcom, Vref1, and Vref2, thereby reducing the power consumption. can do.

The above-described embodiments are merely examples and do not limit the present invention. For example, the configuration of the display panel DP shown in FIG. 2, the configuration of the gate line drive circuit GD shown in FIG. 3, or the configuration of the power supply circuit DC / DC2 and the analog switch circuit ASW shown in FIG. This is also an example, and various modifications can be made as necessary within the scope of the present invention.

[0042]

As described above, according to the flat panel display device and its driving method of the present invention, the controller outputs the gate line control signal to the gate line drive circuit, and the gate line control circuit generates the gate line control signal. By using the signal as the polarity inversion instruction signal to generate the common voltage, it is possible to reduce the number of output terminals of the controller and contribute to cost reduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a flat panel display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a display panel in the flat display device.

FIG. 3 is a block diagram showing a configuration of a gate line drive circuit in the flat panel display device.

FIG. 4 is a time chart showing operation waveforms of respective signals in the flat panel display device.

FIG. 5 is a block diagram showing the configuration of the flat panel display device according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an analog switch circuit in the flat panel display device.

FIG. 7 is a circuit diagram showing a configuration of the analog switch circuit.

FIG. 8 is a time chart showing operation waveforms of respective signals in the flat panel display device.

FIG. 9 is a block diagram showing a configuration of a conventional flat panel display device.

FIG. 10 is a time chart showing operation waveforms of respective signals in the flat panel display device.

[Explanation of symbols]

CTL1 controller DC / DC1, DC / DC2 power supply circuit CTcom1 polarity inversion drive circuit FM frame memory GD gate line drive circuit DA display area DL data latch circuit DAC D / A conversion circuit SD signal line drive circuit DP display panel S / R0 to S / Rn-1 shift register OUT0 to OUTn-1 serial out ASW analog switch circuit SW1 to SW4 switches PT P-channel transistor NT N-channel transistor

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2H093 NA33 NC18 NC22                 5C006 AA16 AC25 AC26 AF83 AF84                       BB16 BC03 BC12 BF03 BF43                       FA42                 5C080 AA06 AA10 BB05 DD03 DD23                       EE29 FF11 JJ02 JJ04

Claims (8)

[Claims] 1. A first substrate on which a signal line and a gate line are arranged in a display region, a second substrate on the opposite side of the first substrate and on which a common electrode is arranged, and the signal line is driven. A display panel having a signal line drive circuit for driving the gate line and a gate line drive circuit for driving the gate line, and outputting a gate line control signal to the gate line drive circuit to display data and signal line control on the signal line drive circuit. A controller that outputs a signal and a gate line drive circuit that receives the gate line control signal and uses the generated gate line drive signal as a signal that indicates the timing of polarity reversal to generate a common voltage and to the common electrode. A flat-panel display device comprising: a polarity reversal drive circuit for supplying. 2. The controller outputs a start pulse and a clock as the gate line control signal to the gate line drive circuit, and the gate line drive circuit includes a plurality of stages of flip-flops connected in series. 2. The flat panel display device according to claim 1, wherein the flip-flop sequentially shifts and transfers the start pulse in accordance with the timing of the clock to generate the gate line drive signal. 3. A first substrate on which a signal line and a gate line are arranged in a display area, a second substrate on the opposite side of the first substrate and on which a common electrode is arranged, and the signal line is driven. A display panel having a signal line drive circuit for driving the gate line and a gate line drive circuit for driving the gate line, and outputting a gate line control signal to the gate line drive circuit to display data and signal line control on the signal line drive circuit. A controller that outputs a signal and a first power supply voltage are supplied, and the first power supply voltage is used to generate at least one second power supply voltage to be supplied to the display panel, which is further supplied to the common electrode. Power supply circuit for generating substantially constant first voltage and second voltage which the common voltage should have, and polarity reversal of the gate line drive signal generated by the gate line drive circuit given the gate line control signal. Thailand The polarity inversion instruction signal for instructing the switching, and the first and second voltages output from the power supply circuit, and the first and second voltages using the polarity inversion instruction signal as a switching control signal. A switch circuit that alternately outputs the voltage of 1 to generate the common voltage and supplies the common voltage to the common electrode. 4. The power supply circuit, which is included in the second power supply voltage, is to be supplied to the signal line drive circuit, and has a first reference voltage and a second reference voltage which are in a mutually inverted polarity relationship. And a substantially constant third voltage and a fourth voltage that the voltage has, and the switch circuit uses the gate line drive signal as the switching control signal to generate the first voltage and the second voltage.
4. The flat panel display device according to claim 3, wherein the first reference voltage and the second reference voltage are generated by alternately outputting the voltages of 1 to 3, and are supplied to the signal line drive circuit. 5. A first substrate on which a signal line and a gate line are arranged in a display region, a second substrate on the opposite side of the first substrate and on which a common electrode is arranged, and the signal line is driven. In a method for driving a flat panel display device including a display panel having a signal line drive circuit for driving the gate line and a gate line drive circuit for driving the gate line, a gate line control signal is supplied to the gate line drive circuit to drive the signal line drive circuit. Supplying display data and a signal line control signal to the circuit; generating a gate line drive signal using the gate line control signal by the gate line drive circuit; and timing of inverting the polarity of the gate line drive signal. Generating a common voltage using the signal as an instruction signal and supplying the common voltage to the common electrode. 6. The step of supplying the gate line control signal, the step of supplying a start pulse and a clock to the gate line drive circuit, the step of generating the gate line drive signal by the gate line drive circuit, the clock of the clock 6. The gate line drive signal is generated by sequentially shifting and transferring the start pulse according to timing.
A method for driving the flat display device described. 7. A first substrate on which a signal line and a gate line are arranged in a display area, a second substrate on the opposite side of the first substrate and on which a common electrode is arranged, and the signal line is driven. In a method for driving a flat panel display device including a display panel having a signal line drive circuit for driving the gate line and a gate line drive circuit for driving the gate line, a gate line control signal is supplied to the gate line drive circuit to drive the signal line Supplying display data and a signal line control signal to the circuit, and generating at least one second power supply voltage to be supplied to the display panel using the first power supply voltage, and further supplying the second power supply voltage to the common electrode. Generating a substantially steady first voltage and a second voltage that the common voltage has; generating a gate line drive signal using the gate line control signal by the gate line drive circuit; The gate line drive signal is used as a polarity inversion instruction signal for instructing the timing of polarity inversion, and the polarity inversion instruction signal is used as a timing signal for switching control to alternately output the first and second voltages. A step of generating a common voltage and supplying the common voltage to the common electrode. 8. In the step of generating the second power supply voltage, the first reference voltage and the second reference voltage having a relationship in which the polarities are inverted to each other to be supplied to the signal line drive circuit A stationary third voltage and a fourth voltage are generated, the gate line drive signal is used as the switching control signal, and the first voltage and the second voltage are alternately output to output the first voltage. 8. The method for driving a flat panel display device according to claim 7, further comprising the step of generating the reference voltage and the second reference voltage and supplying the reference voltage to the signal line drive circuit.