JP2003086735A - Wiring board with location information and method of manufacturing the same, and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To feed back results of defective analysis rapidly to manufacturing processes and thereby to contribute to increase in efficiency of the defect analysis. SOLUTION: In a wiring board 10 with location information, an interconnection layer formed with a predetermined wiring pattern is formed at least on one face of a base substrate. In the periphery of each semiconductor element mounting region 11 of the interconnection layer to be mounted with a semiconductor chip, a specific pattern shape (plating leader line MP) is provided to each region 11 as location information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a wiring board on which a semiconductor chip is mounted, and more particularly, to a high degree of failure analysis performed when a failure occurs in a wiring board and a semiconductor device using the wiring board. The present invention relates to a wiring board with position information adapted to improve efficiency, a method for manufacturing the wiring board, and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, wiring boards have been required to be light and thin in order to mount a BGA (ball grid array) having a small size and a large number of pins. For this reason, recent wiring boards are often of the plastic type, which is formed by laminating glass-epoxy resin composite plates and the like. Such a plastic type wiring board is typically formed by forming a copper wiring pattern by resist coating or etching a copper-clad resin plate (glass-epoxy resin composite plate or the like) having a copper foil stuck on one side or both sides. Alternatively, it is manufactured by forming through holes in a resin plate and laminating copper plating on the inner wall surface with an epoxy adhesive. Then, a required number of semiconductor chips are mounted on the wiring board manufactured in this way, and a semiconductor device is manufactured.

In general, the manufacturing process of this semiconductor device is a process of mounting a semiconductor chip on a substrate (die attaching), and a process of electrically connecting an electrode of the semiconductor chip and a wiring pattern on the substrate by a wire ( Wire bonding), semiconductor chips, wires, etc. are sealed with a sealing resin (molding), external connection terminals such as solder balls are bonded to the substrate surface opposite to the chip mounting side (ball mounting), It includes processing (cutting) for dividing the substrate into units of each package (semiconductor device). In addition, as a mode of molding, there are an individual molding method in which molding is performed for each semiconductor chip and a collective molding method in which molding is performed for each of a plurality of semiconductor chips. As a recent trend of wiring boards, the collective molding method is becoming the mainstream from the viewpoint of improving the efficiency of package assembly.

Performance, price, and reliability are important in evaluating a semiconductor device manufactured by such a manufacturing process, but in recent years, due to high integration and sophistication of manufacturing devices, performance and price are extremely high. Has improved. When the performance and price become stable in this way, it becomes a very important task to quickly perform a thorough failure analysis in order to further improve reliability.

In the conventional technique, the failure analysis is performed as follows, for example. In other words, after performing electrical characteristic evaluation on each semiconductor device that has completed the diffusion process at the wafer level, it is selected whether each semiconductor device is a good product or a defective product, and a defect analysis is performed on the defective product. , The cause was clarified. On the other hand, for non-defective products, mounting is performed, pre-shipment inspection is performed to select good products or defective products, and if they are good products, they are shipped to the market. Had been clarified. Further, when a defective product (semiconductor device) shipped to the market subsequently has a defect, the defective semiconductor device is collected and the defect analysis is similarly performed to elucidate the cause.

[0006]

As described above, in the conventional semiconductor device failure analysis method, if any defect occurs in the pre-shipment inspection after product assembly (after being divided into package units), the package (semiconductor apparatus)
Has a disadvantage that it is not possible to clearly specify the position of the sheet in the sheet state (state of the wiring board before being divided into package units). Specifically, it is necessary to clearly determine whether the failure is caused by a specific place in the wiring board or a specific process in the manufacturing process. I couldn't.

When it is attempted to confirm which position each package was in when it was in the sheet state, marking by marking or the like is manually performed to identify the position of each package after the product is assembled, and a reproduction experiment or the like is performed. Had to do.

However, such a work is very troublesome and requires a considerable amount of time, so that it is not always preferable from the viewpoint of improving the efficiency of failure analysis. In addition, even if a reproduction experiment was performed, it was sometimes difficult to clearly confirm the position of each package.

As described above, according to the conventional technique, the position of each package (semiconductor device) in the sheet state cannot always be clearly specified when some trouble occurs in the pre-shipment inspection. However, there is a problem in that it is not possible to provide quick feedback to the system and it is not possible to improve the efficiency of failure analysis. Such a problem can similarly occur even when some trouble occurs in the semiconductor device once shipped to the market.

In order to eliminate such inconvenience, for example, it is conceivable to give specific unique information to each semiconductor chip during the manufacturing process. One example is JP-A-5-1.
No. 29384, a semiconductor element mounting region on a wafer (a region which is finally cut out from the wafer as individual semiconductor chips) is provided with a chip in a peripheral portion excluding a semiconductor circuit forming region. A technique is described in which a number or a symbol representing attribute information (information indicating which position in which wafer belongs in the manufacturing process) is written.

However, in the technique described in this publication,
Since the chip attribute information consists of a combination of numbers or symbols, a considerable area is required to write the chip attribute information on the wafer, and it may be difficult to write the chip attribute information spatially. It

In addition to the technique described in this publication, it is also conceivable to write similar chip attribute information on the surface of the ball bonding side opposite to the chip mounting area.

However, according to this method, there is a recent demand for miniaturization and increase in the number of pins, so that external terminals to be joined (solder balls)
It is assumed that the chip attribute information cannot be written in a space depending on the arrangement of and the arrangement interval (pitch).

The present invention was created in view of the above-mentioned problems in the prior art, and the result of failure analysis can be quickly fed back to the manufacturing process, which in turn can contribute to higher efficiency of failure analysis. An object of the present invention is to provide a wiring board with position information, a method for manufacturing the same, and a method for manufacturing a semiconductor device.

[0015]

In order to solve the above-mentioned problems of the prior art, according to one aspect of the present invention, a wiring layer having a required wiring pattern is formed on at least one surface of a base substrate. Provided is a wiring board with position information, wherein each semiconductor element mounting region of the wiring layer on which a semiconductor chip is mounted has a unique pattern shape as position information for each semiconductor element mounting region. .

According to the wiring board with position information according to this aspect, the portion of the wiring layer corresponding to each semiconductor element mounting area (area where semiconductor chips are finally mounted and cut out as individual semiconductor devices) is formed. A unique pattern shape is formed for each semiconductor element mounting area, and these unique patterns are used as position information for specifying the position of each semiconductor element mounting area on the wiring board.

As a result, if any defect occurs in the semiconductor device in the pre-shipment inspection after the product is assembled, or if any defect occurs after the product is shipped, it is given to the semiconductor device in the defect analysis. Since it is possible to obtain unique position information, it is possible to clearly specify the position of the semiconductor device in the sheet state. As a result, it is possible to clearly determine whether the failure has occurred depending on a specific place in the wiring board or a specific process in the manufacturing process. Then, the result of the failure analysis can be promptly fed back to the manufacturing process, and the efficiency of the failure analysis can be improved.

Further, since it is not necessary to perform the manual work of marking by scratching or the like, which is required in the prior art, and the experiment of reproduction, it is possible to perform the failure analysis more efficiently.

According to another aspect of the present invention, the method further includes the step of forming a wiring layer having a required wiring pattern on at least one surface of the base substrate, and when forming the wiring layer, the wiring layer is formed. A method for manufacturing a wiring board with position information, characterized by patterning a part of each semiconductor element mounting area on which a semiconductor chip is mounted into a unique shape as position information for each semiconductor element mounting area. To be done.

Furthermore, when patterning a part of each semiconductor element mounting region into a unique shape, the signal line and the plating power supply line may be disconnected by etchback.

According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device using the wiring board with position information manufactured by the manufacturing method of the wiring board with position information described above. This method comprises a step of mounting the semiconductor chip in a chip mounting region on one surface side of the wiring board with position information, with the surface opposite to the side where the electrodes of the semiconductor chip are formed facing down. A step of electrically connecting an electrode of the semiconductor chip and a wiring pattern of a corresponding wiring layer with a bonding wire, a step of sealing the semiconductor chip and the bonding wire with a resin, and the other of the wiring board with position information A step of electrically connecting the solder balls to the wiring pattern of the corresponding wiring layer on the surface side of, and a step of dividing the wiring board with position information obtained through the above steps into each semiconductor device unit It is characterized by including and.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 schematically shows the configuration of a wiring board with position information according to a first embodiment of the present invention in the form of a plan view.

The illustrated example shows the structure of the wiring board 10 with position information according to the present embodiment when viewed from the surface on the chip mounting side. Reference numeral 11 denotes a region in which a semiconductor chip is finally mounted and is cut out as an individual semiconductor device (package) (for convenience, referred to as a “semiconductor element mounting region”).
The respective semiconductor element mounting regions 11 are arranged in a 3 × 3 matrix, and four matrix-shaped region groups are further arranged. Reference numeral 12 denotes a slit that separates each matrix-shaped region group.

Further, 13 is a solder resist layer as a protective film (insulating layer) coated on the surface of the substrate 10, and 14 is an injection port for filling a sealing resin at the time of molding during assembly of the package. The mold gate part is shown. The mold gate portion 14 is formed by removing a predetermined portion of the solder resist layer 13 (that is, opening the predetermined portion when the substrate 10 is viewed in cross section), as will be described later. It is defined by a region where the solder resist layer 13 is not formed. The mold gate portion 14 is provided corresponding to each matrix (3 × 3) region group as shown in the figure,
When assembling the package, the molding gate portions 14 collectively mold the corresponding nine semiconductor chips.

MP indicates a lead line used as "positional information" which is a feature of the present invention, and is provided in the peripheral portion of each semiconductor element mounting region 11 with a unique shape as shown in the figure. Plated lead wire M
The P is used as a wiring for electrolytic plating as described later, and is formed at the same time when a required wiring pattern is formed on both surfaces of the substrate. Note that the wiring pattern is omitted in FIG. 1 for simplification of the drawing.

SL represents a power feed line, and each plating lead line MP in each matrix (3 × 3) region group.
Are electrically connected to each other. As a result, gold (A
Electroplating such as u) can be performed. The power supply line SL is formed together with the plated lead line MP, and is formed so as to be located at the substrate cutting portion when the cutting is finally performed in the assembly of the package. Therefore, when cut out as an individual semiconductor device, the power supply line SL is removed, and the plating lead line MP of the device is electrically isolated from the plating lead line of another device.

Hereinafter, a method for manufacturing the wiring board 10 with position information according to the present embodiment will be described with reference to FIGS. 2 to 4 show the cross-sectional structure taken along the line AA 'in FIG. 1, and have a two-layer wiring structure for simplification of the drawing.

First, in the first step (see FIG. 2A), a core substrate 21 serving as a base material of the wiring substrate 10 having copper (Cu) foils 22 attached to both surfaces thereof is prepared. For example, a plate in which a glass cloth is used as a base material and an organic resin such as BT resin, epoxy resin, or polyimide resin is impregnated to form the core substrate 21, and copper (Cu) foils 22 are laminated and adhered on both surfaces of the core board 21 (glass cloth A base material copper-clad laminate) is prepared.

Note that a tape (TAB) substrate made of polyimide resin or the like may be used instead of the substrate made of glass cloth as a base material.

In the next step (see FIG. 2 (b)), through holes 23 are formed in required portions of the copper clad laminate 21 (22) by using, for example, a mechanical drill. In this case, depending on the diameter of the through hole 23 to be formed, a required drilling process may be performed using a CO ₂ laser, an excimer laser or the like instead of using a mechanical drill.

In the next step (see FIG. 2C), the Cu conductor layer 24 is formed on the entire surface of the copper clad laminate 21 (22) including the inner walls of the through holes 23. This conductor layer 24 is
For example, a thin film of Cu is formed on the entire surface by electroless plating of Cu.
After the layer is formed, this thin film Cu layer is used as a power feeding layer and C
It can be formed by further laminating a Cu layer on the thin film Cu layer by electrolytic plating of u.

In the next step (see FIG. 2D), a photosensitive dry film 25 used as an etching resist is formed on both surfaces of the copper clad laminate 21 (22) on which the conductor layer (Cu layer) 24 is formed. Are attached by thermocompression bonding.

In the next step (see FIG. 3A), the mask 26 preliminarily patterned so as to follow the required wiring pattern and the shape of the plating lead line MP (including the power supply line SL) is used. Dry film on both sides 2
5 is exposed. That is, each mask 26 is aligned with each dry film 25, and ultraviolet rays (U) are applied from above and below each mask 26 as indicated by arrows.
V) is irradiated.

In the next step (see FIG. 3B), the dry films 25 on both sides are developed to pattern each dry film. This can be performed using a developing solution containing an organic solvent when the dry film 25 is a negative type resist, and using an alkaline developing solution when the dry film 25 is a positive type resist. The illustrated example shows the case of a negative type, and the UV-irradiated portion (exposed portion) of each dry film 25 remains.

In the next step (see FIG. 3 (c)), the patterned dry films 25 are used as masks and exposed by, for example, wet etching (in this case, using a solution soluble in Cu). The portion of the Cu layer 24 (not shown, including the Cu foil 22 therebelow) is removed.

In the next step (see FIG. 3D), the dry film 25 is peeled and removed. As a result, the required wiring pattern WP and the plating lead wire M each made of a part of the conductor layer (Cu layer) 24 are formed on both surfaces of the core substrate 21.
P (including the power supply line SL) is formed.

In the next step (see FIG. 4 (a)), the core substrate 21 on which the conductor layer 24 (wiring pattern WP, plated lead MP and feed line SL) is formed is exposed by, for example, screen printing. Of a conductive solder resist is applied (formation of the solder resist layer 13).

In the next step (see FIG. 4B), the solder resist layers 13 on both sides are exposed by using the masks 27 each having a predetermined pattern. That is, each mask 27 is aligned with each solder resist layer 13, and ultraviolet rays (UV) are irradiated from above and below each mask 27 as indicated by arrows.

Each of the masks 27 used in this step has the above-mentioned wiring pattern WP, the plating lead wire MP, and the power supply wire S.
Patterning is performed so as to conform to the shape of L and the shape of the required electrode pad. Further, regarding the mask 27 on the chip mounting side, the mold gate portion 14 (see FIG. 1)
The patterning is performed so as to follow the shape of.

In the next step (see FIG. 4C), each solder resist layer 13 is developed and patterned so as to follow the above-mentioned predetermined shape. This can be performed using a developing solution containing an organic solvent (in the case of a negative type) or an alkaline developing solution (in the case of a positive type) in the same manner as in the step of FIG. 3B. The example shown is for the negative type,
The UV-irradiated portion (exposed portion) of each solder resist layer 13 remains.

At this time, the portion where the solder resist layer 13 is removed and the conductor layer (Cu layer) 24 is exposed is the wiring pattern WP, the plating lead wire MP, and the power feed line SL.
And a pad for connecting a bonding wire connected to an electrode of the semiconductor chip and a pad for joining a solder ball (external connection terminal). Further, on the chip mounting side, the portion where the solder resist layer 13 is removed constitutes the mold gate portion 14.

In the final step (see FIG. 4D), the conductor layers (Cu layers) 24 exposed from the solder resist layers 13 on both sides are provided with nickel as the power feeding layers. (Ni) is subjected to electrolytic plating, and then gold (Au) is subjected to electrolytic plating to form a conductive layer (Ni).
/ Au layer) 28 is formed. The formation of this Ni / Au layer is performed in order to improve the adhesiveness when connecting a bonding wire and the adhesiveness when joining a solder ball in a later stage.

Through the above steps (FIGS. 2 to 4), the wiring board with position information 10 of this embodiment is manufactured.

Next, the wiring board with position information 1 of this embodiment
A semiconductor device using 0 will be described with reference to FIGS.

First, in the first step (see FIG. 5A), die attaching and wire bonding are performed.

That is, the adhesive 30 such as epoxy resin is applied to the chip (or die) mounting region on the solder resist layer 13 of the wiring board 10 and the semiconductor chip 3 to be mounted.
The semiconductor chip 31 is adhered to the chip mounting area by the adhesive 30 with the back surface of 1 (the surface opposite to the side where the electrodes are formed) facing down (die attaching).

Next, the pads exposed from the electrodes of the semiconductor chip 31 and the solder resist layer 13, that is, Ni.
The Cu layer 24 is electrically connected to the Cu layer 24 via the / Au layer 28, for example, by Au bonding wire 32 (wire bonding).

In the example of FIG. 5A, only one semiconductor chip 31 is mounted for simplification of description, but in reality, a plurality of semiconductor chips are mounted.

In the next step (see FIG. 5B), the semiconductor chip 31 and the bonding wires 32 are sealed with the sealing resin 33 by the collective molding method. This is performed by using a molding die (not shown) having a recess corresponding to the final shape of the sealing resin 33, and heating and pressurizing the sealing resin while injecting the sealing resin. In this step, the collective molding method is used, but it goes without saying that an individual molding method may be used instead.

In the final step (see FIG. 5C), ball mounting and cutting are performed.

That is, the pad exposed from the solder resist layer 13 on the side opposite to the chip mounting side, that is, Ni
Solder balls 34 on the Cu layer 24 through the / Au layer 28.
And reflow to place the solder ball 3 on the pad.
Join 4 (ball mounting). As a result, the solder ball 34 is electrically connected to the semiconductor chip 31 from the pad via the Cu layer formed on the inner wall of the through hole 23, the wiring pattern WP on the chip mounting side, and the bonding wire 32.

Then, the wiring board 10 with position information together with the sealing resin 33 is divided into package units along a dividing line DD 'by a dicer or the like to obtain the semiconductor device 40 (cutting). ). At this time, as described above, the power supply line SL (a part of the Cu layer 24) is removed,
The plating lead line MP (a part of the Cu layer 24) of each semiconductor device 40 is electrically separated from the plating lead line of another device.

FIG. 6 is a semiconductor device manufactured by the steps of FIGS. 2 to 5, that is, the wiring board with position information 10 of FIG.
1 is a schematic view showing an example of the configuration of a semiconductor device manufactured by using a plan view.

FIG. 6A shows a state seen from the chip mounting surface before resin sealing, and corresponds to the configuration seen from above the substrate in the step of FIG. 5A. Further, FIG. 6B shows a state as seen from the chip mounting surface after resin sealing, and FIG. 6C shows a state as seen from the ball bonding surface. In the process of FIG. It corresponds to the configuration seen from below. However, the number of solder balls 34 installed is not supported.

As shown in the figure, the plating lead line MP used as "positional information" which is a feature of the present invention is such that the bonding surface side of the solder ball 34 is exposed through an insulating film such as the solder resist layer 13 or the like. Although the "positional information" is exposed to the outside, the mounting surface side of the semiconductor chip 31 is not exposed to the outside because the entire surface is covered with the sealing resin 33.

As described above, according to the wiring board 10 with position information (including the semiconductor device 40 using the board) and the manufacturing method thereof according to the first embodiment, the wiring board 10 is provided.
In the peripheral portion of each semiconductor element mounting region 11 (region where the semiconductor chip 31 is finally mounted and cut out as individual semiconductor devices 40) in, the plating lead lines MP are formed in a unique shape for each region (see FIG. 1)), and these unique plating lead lines MP are used as position information for specifying the position of each semiconductor element mounting region 11 on the wiring board 10.

Therefore, if any defect occurs in the semiconductor device 40 in the pre-shipment inspection after the product is assembled, or if any defect occurs after the product is shipped, it is given to the semiconductor device 40 in the defect analysis. Since the specific position information (plating lead line MP) that is present can be visually obtained (from the ball bonding surface side in the example of FIG. 6), the semiconductor device 40 is in a sheet state (before being divided into package units). It is possible to clearly specify at which position the wiring board 10 was located.

With this, it is possible to clearly determine whether the defect is caused by a specific place in the wiring board or is caused by a specific process in the manufacturing process. You can Then, the result of the failure analysis can be promptly fed back to the manufacturing process, and the efficiency of the failure analysis can be improved.

Further, since it is not necessary to perform the manual work of marking due to scribing or the like, which is required in the prior art, and the re-experiment, it is possible to perform the defect analysis more efficiently.

In the above-described first embodiment, the mold gate portion 14 is arranged in a strip shape along the peripheral edge of the wiring board 10 with position information. However, the mold gate portion is arranged in this manner. Of course, it is not limited to. An example thereof is shown in FIG.

FIG. 7 schematically shows the configuration of a wiring board with position information according to the second embodiment of the present invention in the form of a plan view, similar to FIG. 1 according to the first embodiment. , Wiring board with position information 50 (FIG. 7A) and 60 (FIG. 7)
It shows a configuration when (b)) is viewed from the surface on the chip mounting side.

In the figure, 51 and 61 are semiconductor element mounting regions, 52 and 62 are slits, 53 and 63 are solder resist layers as protective films (insulating layers), and 54 and 64 are mold gate portions. In the wiring board with position information 50, the mold gate portions 54 are provided in a one-to-one correspondence with the respective semiconductor element mounting regions 51, and when assembling the package, the mold gate portions 54 are provided for one corresponding semiconductor chip. Molding is being done. On the other hand, in the wiring board with position information 60, the mold gate portion 64 is provided in a strip shape corresponding to each matrix (1 × 2) region group, and each mold gate portion 64 is provided when the package is assembled. From 64, molding is performed simultaneously and individually for two corresponding semiconductor chips. In addition, the dotted line part,
The cutting line of the substrate is shown.

MP indicates a lead line for plating used as "positional information" which is a feature of the present invention. As in the case of the first embodiment (FIG. 1), MP of each semiconductor element mounting region 51, 61 is shown. Each of the peripheral portions is formed with a unique shape.

Although the power supply line SL as shown in FIG. 1 is not shown in the example of FIG. 7, gold (A) is used for the bonding pad of the wiring pattern as in the first embodiment.
Up to the stage prior to electrolytic plating such as u), the feeder line is provided together with the plating lead line MP. In other words, in the second embodiment, after the bonding pad of the wiring pattern is electrolytically plated, the power supply line forming portion of the substrate is punched out to form the slits 52 and 62, and the individual plated lead lines MP are separated from each other. It is electrically independent.

FIG. 8 shows the wiring board with position information 50 of FIG.
6 is a cross-sectional view showing the structure of a semiconductor device using 60. The illustrated semiconductor device 40a is different from the semiconductor device 40 according to the first embodiment (FIG. 5C) in that the peripheral portion on the chip mounting surface side is not covered with the sealing resin 33. The other structure is the same as that of the first embodiment, and therefore its description is omitted.

FIG. 9 is a schematic plan view showing one structural example of a semiconductor device manufactured using the wiring boards with position information 50, 60 according to the second embodiment.

In FIG. 9, (a) is a state viewed from the chip mounting surface before resin sealing, (b) is a state viewed from the chip mounting surface after resin sealing, and (c) is a ball bonding surface. 6A and 6B, which correspond to the plan views of FIGS. 6A, 6B, and 6C, respectively. However, the number of solder balls 34 installed is not supported.

As shown in FIG. 9, a plating lead wire MP used as "positional information" which is a feature of the present invention.
For the joint surface side of the solder ball 34, see FIG.
Similar to FIG. 6C, the “positional information” is exposed to the outside through the insulating film such as the solder resist layer 13, and the mounting surface side of the semiconductor chip 31 is different from that of FIG. 6B. In contrast, since the peripheral portion of the substrate is not covered with the sealing resin 33, the "positional information" is exposed to the outside through the insulating film such as the solder resist layer 13 in the portion.

Also in this second embodiment, the plating lead lines MP are formed in the peripheral portions of the respective semiconductor element mounting regions 51, 61 with their respective unique shapes.
The same effect as that of the first embodiment described above can be obtained.

Regarding the wiring boards 10, 50, 60 with position information according to each of the above-mentioned embodiments, a two-layer wiring structure is taken as an example for simplification of description, and the plating lead line MP (position information) is visually recognized from the outside. Although the case where it is provided so as to be exposed has been described, it goes without saying that the present invention is not limited to the two-layer wiring structure, and the arrangement of the plated lead lines MP is not limited to this. .

For example, a well-known build-up method or the like may be used to form a multilayer wiring structure in which four or more layers are stacked,
Further, in the case of such a multilayer wiring structure, the plated lead line (position information) may be provided in an inner wiring layer which cannot be visually recognized from the outside. An example of such a wiring board with position information is shown in FIG.

In FIG. 10, (a) is the same type as the semiconductor device 40 (FIGS. 5 (c) and 6) according to the first embodiment (type in which the chip mounting surface side is entirely covered with the sealing resin 33). 4B shows a cross-sectional structure of the semiconductor device 40b in FIG. 4B, and FIG.
FIG. 10 shows a cross-sectional structure of a semiconductor device 40c of the same type as a (FIGS. 8 and 9) (the chip mounting surface side is covered with the sealing resin 33 except for the peripheral portion).

In the figure, reference numerals 70 and 80 respectively denote a wiring board with position information having a four-layer wiring structure.
At 0 and 80, plating lead lines MP (position information) are formed on the inner wiring layer (Cu layer) 24a.

In the third embodiment, since the plating lead line MP (position information) cannot be visually recognized from the outside, a method for identifying the shape of the plating lead line MP inside the substrate is, for example, X A method of observing the inside of the product with lines or the like, a method of crushing the product (opening the package) and observing the inside can be considered.

Also in the third embodiment, the plating lead-out line MP is formed in the peripheral portion of each semiconductor element mounting region with a unique shape, so that it is similar to the above-described first and second embodiments. It is possible to exert an effect.

Further, as in the conventional case, fine pitch B is used.
Even in the case where it is difficult or impossible to give positional information to the surface on the ball bonding side in the GA, the plating lead wire MP is provided in the inner wiring layer 24a in the present embodiment, and therefore such inconvenience is caused. Can be resolved.

In the example of FIG. 10, the plating lead-out line MP is provided in the inner wiring layer 24a. However, as in the case of the above-described first and second embodiments, the outer wiring visible from the outside can be seen. Of course, it may be provided in the layer 24b.

Further, in each of the above-mentioned embodiments, the shape of the plating lead line MP is changed so as to be individually distinguishable as "position information" for specifying the position of each semiconductor element mounting region (package) on the wiring board. Granted,
Of course, the form of the "positional information" is not limited to this. For example, it may be in the form of characters such as numbers and symbols. An example thereof is shown in FIG.

FIG. 11 schematically shows the configuration of a wiring board with position information according to the fourth embodiment of the present invention in the form of a plan view, similar to FIG. 1 according to the first embodiment. , Showing the configuration of the wiring board 90 with position information when viewed from the surface on the chip mounting side.

In the figure, 91 is a semiconductor element mounting region, 92 is a slit, 93 is a solder resist layer as a protective film (insulating layer), and 94 is a mold gate portion. The operation mode of the mold gate portion 94 is the same as that of the mold gate portion 14 in the first embodiment. In addition, the dotted line part,
The cutting line of the substrate is shown. In addition, MQ is a character (A1, A1) used as "positional information" which is a feature of the present invention.
A2, ..., D9), and these characters MQ
The (positional information) is given to the peripheral portion of each semiconductor element mounting region 91 in the example of FIG. 11A, and FIG.
In the example of (3), it is provided in the central portion of each semiconductor element mounting region 91. The letter MQ is the above-mentioned plated lead wire MP
In the same manner as the process for forming the wiring pattern, the wiring pattern is simultaneously formed when the wiring pattern is formed. Illustration of the power supply line is omitted.

Also in the fourth embodiment, the same effects as those of the above-mentioned first and second embodiments can be obtained, and further, like the above-mentioned third embodiment, the four-layer wiring structure is adopted. At this time, by adding the character MQ to the inner wiring layer which cannot be visually recognized from the outside, it is possible to eliminate the inconvenience as seen in the related art.

FIG. 12 is a plan view schematically showing the configuration of the wiring board with position information according to the fifth embodiment of the present invention, which is similar to FIG. 1 according to the first embodiment. , Showing the configuration of the wiring board with position information 10a when viewed from the surface on the chip mounting side.

The wiring board with position information 10a shown in FIG.
1 is different from the wiring board with position information 10 (FIG. 1) according to the embodiment in that the slits 12 are not provided and the mold gate portions 14 are arranged in a 3 × 14 matrix. That is, it is provided corresponding to all the semiconductor element mounting regions 11. Other configurations are the same as in the case of the first embodiment, so description thereof will be omitted.

FIG. 13 is a plan view schematically showing the configuration of the wiring board with position information according to the sixth embodiment of the present invention, which is similar to FIG. 11 according to the fourth embodiment. ,
The structure when the wiring board 90a with position information is viewed from the chip mounting side is shown.

Wiring board 90 with position information according to the present embodiment
a is a wiring board 90 with position information according to the fourth embodiment
Compared with (FIG. 11), the structure has no slit 92, and the mold gate portion 94 is provided corresponding to all the semiconductor element mounting regions 91 arranged in a 3 × 14 matrix. Differences in points. Since other configurations are basically the same as those in the fourth embodiment,
The description is omitted. Similarly in the case of the present embodiment, the character MQ (positional information) is given to the peripheral portion of each semiconductor element mounting region 91 (FIG. 13A) or the central portion of each semiconductor element mounting region 91. (Fig. 13
(B)).

FIG. 14 is a schematic plan view showing one structural example of a semiconductor device manufactured using the wiring board with position information according to the seventh embodiment of the present invention. Figure 6
14A is a state viewed from the chip mounting surface before resin sealing, FIG. 14B is a state viewed from the chip mounting surface after resin sealing, and FIG. 14C is a ball bonding surface. The respective states are shown.

In the semiconductor device 40d according to the present embodiment, the plating lead line MP used as "position information" is insulated from the signal line (wiring pattern WP) by a method such as etch back (FIG. 14 ( a)).

FIG. 15 is a schematic plan view showing one structural example of a semiconductor device manufactured by using the wiring board with position information according to the eighth embodiment of the present invention. Figure 9
15A is a state viewed from the chip mounting surface before resin sealing, FIG. 15B is a state viewed from the chip mounting surface after resin sealing, and FIG. 15C is a ball bonding surface. The respective states are shown.

Also in the semiconductor device 40e according to the present embodiment, as in the semiconductor device 40d shown in FIG. 14, the plating lead line MP (positional information) is processed by a signal line (wiring pattern WP) by a method such as etch back. It is insulated from (FIG. 15 (a)).

Although not shown in the drawing, a process for producing a wiring board with position information in which the plating lead-out line MP (position information) is insulated from the signal line (wiring pattern WP) by using the etch back method. Will be described below.

(1) In the case of a substrate to which a solder resist is applied After forming a required circuit pattern (wiring layer), applying the solder resist and hardening the solder resist, the plating lead line MP and the signal line WP are formed. A dry film is attached to the part to be insulated to close the opening of the solder resist. At this time, the solder resist is opened at the portion where the plating lead-out line MP and the signal line WP are desired to be insulated. Next, the Ni / Au conductive layer is plated, the Ni / Au plating is applied, and then the dry film is peeled off. Then N
The opening of the solder resist plated with i / Au is closed with a dry film. Then, etching is performed again. The portion where the plating lead line MP and the signal line WP are desired to be insulated has an opening in the solder resist, and the plating lead line MP and the signal line WP are insulated by the above etching. Finally, when the dry film is peeled off, the wiring board with position information in which the plating lead wire MP and the signal wire WP are insulated is completed.

(2) When the wiring layer is a substrate which is not covered with an insulating film such as a solder resist, after forming a required circuit pattern (wiring layer), Ni / A
u The portion not requiring plating is covered with a dry film. next,
The Ni / Au conductive layer is plated, the Ni / Au plating is applied, and then the dry film is peeled off. Next, Ni /
Plated lead wire MP including Au plated part
And the portion other than the portion where the signal line WP is desired to be insulated is covered with a dry film. Then, etching is performed again. The part where you want to insulate the plating lead wire MP and the signal wire WP is
Since it is not covered with the dry film, the plating lead line MP and the signal line WP are insulated by the above etching. Finally, when the dry film is peeled off, the wiring board with position information in which the plating lead wire MP and the signal wire WP are insulated is completed.

16 to 18 show a manufacturing process of a wiring board with position information according to the ninth embodiment of the present invention, which has a one-layer wiring structure and is electrically conductive in the state of the wiring board with position information. The case where the portion (wiring layer) is not covered with an insulating film is illustrated.

In the manufacturing process according to the present embodiment, the wiring with position information in which the plating lead-out line MP (position information) is insulated from the signal line (wiring pattern WP) by the method (2) described above (etch back method) is used. Steps for manufacturing a substrate)
It corresponds to. The manufacturing method of this embodiment is basically the same as the manufacturing method according to the two-layer wiring structure illustrated in FIGS. 2 to 4, and the reference numerals used in FIGS. The same reference numerals as those used in Fig. 2 denote the same components. Therefore, a detailed description of each step will be omitted, but a schematic description is as follows.

First, a core substrate 21 as a base material is prepared (FIG. 16A), through holes 23 are formed (FIG. 16B), and a conductor layer 24 is formed (FIG. 16).
(C)), the conductor layer 24 is exposed and developed (patterning of the conductor layer 24) using the mask 26 (FIG. 16).
(D)), a required wiring pattern WP formed of a part of the conductor layer 24 and a plating lead wire MP (including the power supply wire SL) are formed (FIG. 17A), and the dry film 25 is attached (FIG. 17A). 17 (b)), the conductor layer 28 is formed by Ni / Au plating (FIG. 17 (c)), the dry film 25 is peeled off (FIG. 17 (d)), and the Ni / Au plated portion is included. A dry film 25a is attached to the portion other than the portion where the plating lead wire MP and the signal wire WP are desired to be insulated (see
8 (a)) and etching (etchback) is performed (see FIG. 1).
8 (b)), the dry film 25a is peeled off (FIG. 18).
(C)).

FIG. 19 shows a manufacturing process of a semiconductor device using the wiring board with position information manufactured by the manufacturing process of FIGS. The manufacturing process of the semiconductor device 40f according to the present embodiment (FIGS. 19A to 19C) is the same as the manufacturing process of the semiconductor device 40 illustrated in FIG. 5, and thus the description of each process will be omitted.

FIG. 20 shows a sectional structure of a semiconductor device manufactured by using the wiring board with position information manufactured by the manufacturing steps of FIGS.

20A shows a sectional structure of a semiconductor device 40f of the same type as the semiconductor device 40b illustrated in FIG. 10A (a type in which the chip mounting surface side is entirely covered with the sealing resin 33). 10B shows a semiconductor device 40g of the same type as the semiconductor device 40c illustrated in FIG. 10B (type in which the chip mounting surface side is covered with the sealing resin 33 except the peripheral portion). The cross-sectional structure is shown.

In each of the above-described embodiments, the case where the position information (plating lead line MP, character MQ) is added to either side of the ball bonding surface and the chip mounting surface of the wiring board has been described. As is clear from the summary of the above, it is sufficient that such position information is provided to the wiring layer on at least one surface side.

[0100]

As described above, according to the present invention, the result of failure analysis can be promptly fed back to the manufacturing process, and the efficiency of failure analysis can be improved.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a configuration of a wiring board with position information according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the wiring board shown in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process that follows the manufacturing process in FIG.

FIG. 4 is a cross-sectional view showing a manufacturing process that follows the manufacturing process in FIG.

5 is a cross-sectional view showing a manufacturing process of a semiconductor device using the wiring board of FIG.

6 is a plan view schematically showing a configuration example of a semiconductor device manufactured by using the wiring board of FIG.

FIG. 7 is a plan view schematically showing a configuration of a wiring board with position information according to a second embodiment of the present invention.

8 is a sectional view showing the structure of a semiconductor device using the wiring board of FIG.

9 is a plan view schematically showing a configuration example of a semiconductor device manufactured by using the wiring board of FIG.

FIG. 10 is a sectional view showing a structure of a semiconductor device using a wiring board with position information according to a third embodiment of the present invention.

FIG. 11 is a plan view schematically showing a configuration of a wiring board with position information according to a fourth embodiment of the present invention.

FIG. 12 is a plan view schematically showing the configuration of a wiring board with position information according to a fifth embodiment of the present invention.

FIG. 13 is a plan view schematically showing the configuration of a wiring board with position information according to a sixth embodiment of the present invention.

FIG. 14 is a plan view schematically showing a configuration example of a semiconductor device manufactured using the wiring board with position information according to the seventh embodiment of the present invention.

FIG. 15 is a plan view schematically showing a configuration example of a semiconductor device manufactured using the wiring board with position information according to the eighth embodiment of the present invention.

FIG. 16 is a cross-sectional view showing the manufacturing process of the wiring board with position information according to the ninth embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a manufacturing process that follows the manufacturing process in FIG. 16.

FIG. 18 is a cross-sectional view showing a manufacturing process that follows the manufacturing process in FIG. 17.

FIG. 19 is a cross-sectional view showing a manufacturing process of a semiconductor device using a wiring board according to a ninth embodiment.

FIG. 20 is a cross-sectional view showing the structure of a semiconductor device manufactured using the wiring board according to the ninth embodiment.

[Explanation of symbols]

10, 10a, 50, 60, 70, 80, 90, 90a
... Wiring board with position information, 11, 51, 61, 91 ... Semiconductor element mounting area, 13, 53, 63, 93 ... Solder resist layer (protective film /
Insulation layer), 14, 54, 64, 94 ... Mold gate part, 21 ... Core substrate (base substrate), 23 ... Through hole, 24, 24a, 24b ... Cu layer (conductor layer, wiring layer), 28 ... Ni / Au layer (conductor layer), 31 ... Semiconductor chip (die), 32 ... Bonding wire, 33 ... Sealing resin, 34 ... Solder ball (external connection terminal), 40, 40a-40g ... Semiconductor device, MP ... Plating lead wire (Cu that indicates "location information"
Layer), MQ ... letters (Cu layer indicating "positional information"), SL ... feeder line (Cu layer), WP ... wiring pattern (Cu layer).

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masayoshi Aoki             711 Toshida, Kurita, Oita, Nagano City, Nagano Prefecture             Shinko Electric Industry Co., Ltd. F term (reference) 5E338 AA16 BB75 CC01 DD12 DD22                       DD32 EE43

Claims (11)

[Claims] 1. A base substrate having a wiring layer on which a required wiring pattern is formed on at least one surface, and each semiconductor element mounting region of the wiring layer on which a semiconductor chip is mounted is a semiconductor element mounting region. A wiring board with position information, wherein each wiring board has a unique pattern shape as position information. 2. The wiring board with position information according to claim 1, wherein a portion of the wiring layer having the unique pattern shape is exposed to the outside. 3. The wiring board with position information according to claim 1, wherein a portion of the wiring layer having the unique pattern shape is covered with a protective film. 4. A base substrate having, on at least one surface thereof, two or more wiring layers each having a required wiring pattern with an insulating layer interposed therebetween, and any wiring inside the wiring layers. A wiring board with position information, wherein each semiconductor element mounting area of the layer on which a semiconductor chip is mounted has a unique pattern shape as position information for each semiconductor element mounting area. 5. Instead of any of the inner wiring layers,
The wiring board with position information according to claim 4, wherein the outermost wiring layer has the unique pattern shape and is exposed to the outside. 6. The plating pattern lead used as a wiring for electrolytic plating, or a form in which characters are written, as the peculiar pattern shape.
The wiring board with position information according to any one of 1. 7. A step of forming a wiring layer having a required wiring pattern on at least one surface of a base substrate, wherein when forming the wiring layer, each semiconductor of the wiring layer on which a semiconductor chip is mounted, respectively. A method of manufacturing a wiring board with position information, comprising patterning a part of an element mounting area into a unique shape as position information for each semiconductor element mounting area. 8. A base substrate having a required wiring pattern on at least one surface thereof with an insulating layer interposed therebetween.
Including a step of forming a wiring layer of at least one layer, when forming any one wiring layer,
A method of manufacturing a wiring board with position information, comprising patterning a part of each semiconductor element mounting area on which a semiconductor chip is mounted, into a unique shape as position information for each semiconductor element mounting area. 9. A step of forming a wiring layer having a required wiring pattern on at least one surface of a base substrate, wherein when forming the wiring layer, each semiconductor of the wiring layer on which a semiconductor chip is mounted, respectively. Part of the element mounting area is patterned into a unique shape as position information for each semiconductor element mounting area, and the signal line and the plating power supply line are disconnected by etchback. Manufacturing method of wiring board with position information. 10. On at least one surface of the base substrate,
The method includes the step of forming two or more wiring layers each having a required wiring pattern with an insulating layer interposed therebetween. When forming any one wiring layer,
Part of each semiconductor element mounting area on which a semiconductor chip is mounted is patterned into a unique shape as position information for each semiconductor element mounting area, and the area between the signal line and the plating power supply line is etched back by etching back. A method of manufacturing a wiring board with position information, wherein the wiring board is broken. 11. A method of manufacturing a semiconductor device using a wiring board with position information manufactured by the method of manufacturing a wiring board with position information according to any one of claims 7 to 10, wherein: In a chip mounting region on one surface side of the attached wiring board, the step of mounting the semiconductor chip with the surface opposite to the side on which the electrodes of the semiconductor chip are formed facing down, and the electrode of the semiconductor chip A step of electrically connecting a wiring pattern of a corresponding wiring layer with a bonding wire; a step of sealing the semiconductor chip and the bonding wire with a resin; The step of electrically connecting to the wiring pattern of the wiring layer to join the solder balls, and the wiring board with position information obtained through the above steps is divided into each semiconductor device unit. The method of manufacturing a semiconductor device which comprises a degree.