JP2003086705A - Logic circuit and parameter setting method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a setting method of a β ratio for improving the noise margin of a CMOS logic circuit. SOLUTION: The parameter setting method of a logic circuit has a plurality of P-channel MOS transistors (TP1, TP2) that are connected in parallel between a supply terminal (Vdd) and an output terminal (Vout), a first N-channel MOS transistor (TN1) that is provided between Vout and a grounding terminal (gnd), and a second N-channel MOS transistor (TN2) that is connected in series with TN1 and is provided at the gnd side, and sets a β ratio between the gain coefficients in TP1 and TP2 and gain coefficients in TN1 and TN2. In the parameter setting method, a Vdd voltage, a threshold voltage (Vtp) in the TP1 and TP2, a threshold voltage (Vtn) at the TN1 and TN2, and middle potential (Vint) between the TN1 and TN2 are used, thus setting the β ratio so that the circuit threshold of the logic circuit becomes half the Vdd voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, particularly a CMOS transistor (Complementary Metal Oxide Semiconductor).
Onductor field effect transistor).

[0002]

2. Description of the Related Art Conventionally, in the design of a CMOS logic circuit, the rising (L level → H level) and the falling (H level → L level) speeds of the output potential are matched, that is, the driving capability and driving on the load side. It was common to determine the gain coefficient β of each transistor so that the drive capability on the side becomes equal. When the drive capability on the load side and the drive capability on the drive side are equal to each other in this way, the gate drive capability ratio is said to be 1. On the other hand, the gain coefficient β of each transistor is a value that defines Ids (drain-source current) of a MOS transistor,

[0003]

[Equation 1]

Is given by

Β is a value that depends on both process parameters and device dimensions, as seen from the above equation. Where μ
Is the effective surface mobility of electrons (or holes) in the channel, ε is the dielectric constant of the gate insulating film, Tox is the gate insulating film thickness, W is the channel width, and L is the channel length. Therefore, β consists of a process-determined element με / Tox and W / L that depends on the actual layout dimensions of the device.

Since Tox and L are generally equal in the NMOS transistor and the PMOS transistor, the factor μ determined by the process
Of ε / Tox, the difference in mobility between holes and electrons is related to β. The mobility of holes is about half that of electrons, so if the Tox and L of PMOS and NMOS are the same, the W of PMOS is NMOS.
The ratio of β becomes 1 at about twice W.

Therefore, for example, in an inverter
The W of the PMOS is generally set to a value about twice that of the NMOS.

A conventional CMOS logic circuit will be described below with reference to FIG.

FIG. 1A is a circuit diagram of a conventional CMOS inverter (inverting circuit). Where TP is a PMOS transistor, TN is an NMOS transistor, Wp and Wn are PMOS and NM, respectively.
Indicates the OS channel width. Considering setting the gain coefficient of each transistor so that the gate drive capacity ratio becomes 1, the inverter has only one load side transistor (PMOS) and one drive side transistor (NMOS). The capacity ratio is equal to the ratio of β between PMOS and NMOS. Therefore, W is set so that the β ratio is 1, that is, the gain counts β of the PMOS and the NMOS are equal. As a typical example of this,
Wp: Wn = 2: 1 as shown in FIG.

It is assumed that the channel length Lp of the PMOS and the channel length Ln of the NMOS are equal.

Further, as described above, when determining the gate width (W) of a transistor in which a plurality of NMOS transistors (or PMOS transistors) are connected in multiple stages, simply connect W in the case of one transistor in series. In general, the value is set to a value obtained by multiplying the number of stages of the manufactured transistor.

As an example, a conventional 2-input CMOS is shown in FIG.
A NAND circuit (a NAND circuit) is shown. Since two NMOS transistors TN1 and TN2 are connected in series, in order to obtain W equivalent to one NMOS of the inverter effectively, each NM
The W of OS (TN1, TN2) is set to twice the W of NMOS of the inverter.

Therefore, originally, in the inverter, Wp: Wn =
W, which was 2: 1 is set to Wp: Wn = 2: (1 × 2) = 1: 1 in order to set the gate driving capability ratio to 1 in the 2-input NAND. At this time, the β ratio becomes 2 as a result.

Similarly, in the 3-input CMOS NAND circuit, the NMOS
Since 3 are connected in series, conventional Wp: Wn = 2: (1 × 3) =
W was set like 2: 3. The β ratio at this time is 3.

Further, in the conventional 2-input CMOS NOR circuit (negative OR circuit), two PMOS transistors TP1 and TP2 are connected in series as shown in (C) of FIG. In order to obtain W equivalent to one PMOS of, the W of each PMOS is set to twice the W of the PMOS of the inverter.

Therefore, originally, in the inverter, Wp: Wn =
W that was 2: 1 is Wp: Wn = (2
X2): 1 = 4: 1 will be set. The β ratio at this time is
It is 0.5. Similarly, in the 3-input CMOS NOR circuit, the PMOS is 3
Since they are connected in series, conventional Wp: Wn = (2 × 3): 1 = 6: 1
W was set like. The β ratio at this time is 1/3.
However, in such a method of simply multiplying the number of stages, when considering the circuit threshold value of the logic circuit, it does not necessarily become 1/2 Vdd with the largest margin, and it shifts to either a higher value or a lower value. There's a problem. Here, the circuit threshold means a potential at which the input voltage (Vin) = the output voltage (Vout).

For example, if only one input changes at the same time,
In the CMOS NAND circuit, the circuit threshold shifts to the smaller side of the inverter, and in the CMOS NOR circuit, it shifts to the larger side. This shift of course varies depending on the transistor model, but a shift of several hundred mV can be seen. This corresponds to about several percent if the power supply voltage is 5V.

As the circuit threshold deviates from 1/2 Vdd, the resistance to noise on the input, power supply voltage, and fluctuation of gnd is lower.

When the power supply voltage is sufficiently large with respect to the deviation of the circuit threshold from 1/2 Vdd as in the conventional case, this deviation is not a problem, but the power supply voltage is becoming lower and lower in recent years. Deviation and variation have come to have a great influence on the noise margin of the entire circuit. Here, the noise margin of the logic circuit is
It refers to the fluctuation range of the noise voltage that does not cause fluctuations in the output level when applied to the input voltage.

[0020]

SUMMARY OF THE INVENTION It is an object of the present invention to provide CMOS
It is to increase the noise margin of a semiconductor integrated circuit including the logic circuit by increasing the noise margin of the logic circuit.

[0021]

A first invention is a plurality of P-channel MOS transistors (TP1, TP2) connected in parallel between a power supply terminal (Vdd) and an output terminal (Vout), and the output terminal. And a ground terminal (gnd) between a first N-channel MOS transistor (TN1) and a second N-channel transistor connected in series with the first N-channel MOS transistor and provided on the ground terminal side. Parameter setting of a logic circuit including a channel MOS transistor (TN2) and setting a β ratio which is a ratio between the gain coefficients of the plurality of P channel MOS transistors and the gain coefficients of the first and second N channel MOS transistors A voltage of the power supply terminal, threshold voltages (Vtp) of the plurality of P-channel MOS transistors, threshold voltages (Vtn) of the first and second N-channel MOS transistors, and the first method. N-channel MOS transistor Intermediate potential between said second N-channel MOS transistor (Vin
t) is used to set the β ratio so that the circuit threshold of the logic circuit becomes half the voltage of the power supply terminal.

A second aspect of the invention is to set the β ratio,
Furthermore, the first embodiment is characterized in that channel length modulation elements (λp) of the plurality of P channel MOS transistors and channel length modulation elements (λn) of the first and second N channel MOS transistors are used. It is a parameter setting method of a logic circuit according to the invention.

A third invention is a plurality of N-channel MOS transistors connected in parallel between a ground terminal (gnd) and an output terminal (Vout).
Transistors (TN1, TN2), a first P-channel MOS transistor (TP1) provided between a power supply terminal (Vdd) and the output terminal, and the first P-channel MOS transistor connected in series, The second P provided on the output terminal side
Parameter setting of a logic circuit including a channel MOS transistor (TP2) and setting a β ratio which is a ratio between the gain coefficients of the first and second P-channel MOS transistors and the gain coefficients of the plurality of N-channel MOS transistors A voltage of the power supply terminal, threshold voltages (Vtp) of the first and second P-channel MOS transistors, and a plurality of N
The threshold voltage (Vtn) of the channel MOS transistor and the first
P-channel MOS transistor and the second P-channel MOS
A parameter setting method for a logic circuit, characterized in that the β ratio is set so that a circuit threshold value of the logic circuit becomes half of a voltage of the power supply terminal by using an intermediate potential (Vint) of a transistor.

A fourth invention is to set the β ratio,
Furthermore, the channel length modulation elements (λp) of the first and second P-channel MOS transistors and the plurality of N-channels
A parameter setting method for a logic circuit according to the third invention is characterized by using a channel length modulation element (λn) of a MOS transistor.

A fifth invention is a plurality of P-channel MOS transistors connected in parallel between a power supply terminal (Vdd) and an output terminal (Vout).
Transistors (TP1, TP2), a first N-channel MOS transistor (TN1) provided between the output terminal and a ground terminal (gnd), and the first N-channel MOS transistor connected in series, The second provided on the ground terminal side
A logic circuit including an N-channel MOS transistor (TN2), wherein a β ratio, which is a ratio between the gain coefficients of the plurality of P-channel MOS transistors and the gain coefficients of the first and second N-channel MOS transistors, The voltage of the power supply terminal,
Threshold voltage (Vtp) of the plurality of P-channel MOS transistors
And a threshold voltage (Vtn) of the first and second N-channel MOS transistors and an intermediate potential (Vint) between the first N-channel MOS transistor and the second N-channel MOS transistor. A logic circuit is characterized in that the circuit threshold of the logic circuit is set to be half the voltage of the power supply terminal.

A sixth invention is a plurality of N-channel MOS transistors connected in parallel between a ground terminal (gnd) and an output terminal (Vout).
Transistors (TN1, TN2), a first P-channel MOS transistor (TP1) provided between a power supply terminal (Vdd) and the output terminal, and the first P-channel MOS transistor connected in series, The second P provided on the output terminal side
A logic circuit including a channel MOS transistor (TP2), wherein a β ratio, which is a ratio between the gain coefficients of the first and second P-channel MOS transistors and the gain coefficients of the plurality of N-channel MOS transistors, Power supply terminal voltage and threshold voltage of the first and second P-channel MOS transistors
(Vtp), a threshold voltage (Vtn) of the plurality of N-channel MOS transistors, and an intermediate potential (Vin of the first P-channel MOS transistor and the second P-channel MOS transistor).
t) is used to set the circuit threshold of the logic circuit to half the voltage of the power supply terminal.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION The embodiments of the present invention are described below.
The CMOS logic circuit will be described with reference to the drawings.

(First Embodiment) In the first embodiment,
A method of setting the β ratio for increasing the noise margin in the case of a 2-input CMOS NAND circuit (negative AND circuit) will be described. In the following, the equation expressing the β ratio such that the circuit threshold becomes 1/2 Vdd is given by
In one case, that is, (the 1-1st embodiment) the output terminal Vo
When the input to the NMOS transistor TN1 close to ut changes (Example 1-2-A), the NMOS close to the ground terminal gnd
When the input to the transistor TN2 changes and the transistor operates in saturation, and (Example 1-2B) when the input to the NMOS transistor TN2 near the ground terminal gnd changes and the transistor operates linearly. I will explain separately.

(Embodiment 1-1) FIG. 1 is a circuit diagram of a 2-input CMOS NAND circuit according to the embodiment 1-1. TP
1, TP2 is a PMOS transistor, TN1 and TN2 are NMOS transistors, and βp and βn are gain coefficients of the respective MOS transistors, which are values proportional to the gate widths Wp and Wn.

Now, of the two inputs, the signal Vin entering TP1 and TN1 changes from L to H (Vdd), and the output Vout is changed to H accordingly.
→ Consider the case of L. The input to TP2 and TN2 is H (Vdd)
It is fixed.

Vin where Vin = Vout, that is, the circuit threshold is 1/2
Since Vdd has the largest noise margin and is desirable, consider the operation around Vin = 1 / 2Vdd.

The PMOS transistor TP2 whose input to the gate is fixed to Vdd is cut off, and the NMOS transistor TN2 is linearly operated (0 <Vds <Vgs-Vt). On the other hand, the PMOS transistor TP1 and the NMOS transistor TN1 whose gate inputs change are
It operates in the saturation region (0 <Vgs-Vt <Vds) near Vgs = 1 / 2Vdd. This is represented by an equivalent circuit in FIG.

The saturated PMOS transistor (TP1) is equivalent to one current source connected in parallel, and the similarly saturated NMOS transistor (TN1) linearly operates as one current source. The NMOS transistor (TN2) is given as a resistance and is connected in series with the current source.

The source / drain current Ids5 in the saturation region (pentode region; 0 <Vgs-Vt <Vds) is approximated below in consideration of channel length modulation.

[0035]

[Equation 2]

(Λ is a channel length modulation element, about 0.01 / V)
On the other hand, the source / drain current Ids3 in the linear region (triode region; 0 <Vds <Vgs−Vt) is

[0037]

[Equation 3]

[0038]

The total current Idsp of the PMOS transistors connected in parallel is the transistor TP2 to which Vdd is input to the gate.
The transistor whose input signal changes because is off
Only one TP1 (saturation operation) need be considered. If the gate input potential Vin is Vdd / 2 which is the circuit threshold,

[0040]

[Equation 4]

From

[0042]

[Equation 5]

It is

On the other hand, in the NMOS transistors connected in series, the gate input of TN1 is 1/2 Vdd and the gate input of TN2 is Vdd.
It is fixed. The intermediate potential between TN1 and TN2 in Fig. 2 is Vint (however
Vint <1/2 ・ Vdd), Ids3 = Ids5 = Idsn from Ids of TN1 = Ids of TN2

[0045]

[Equation 6]

Vint is given as the solution of equation (1). That is, equation (1) is the output Vo in the 2-input CMOS NAND circuit.
6 is an expression representing an intermediate potential Vint between TN1 and TN2 when the input to the NMOS transistor TN1 near ut changes.

Next, from Idsp = Idsn

[0048]

[Equation 7]

However, Vtp <0

[0050]

[Equation 8]

However, Vint is given by the equation (1).

Β ratio (= βn / βp) that satisfies the condition of equation (2)
The 2-input NAND circuit in which is set is the 1-1st embodiment. That is, equation (2) is the output Vo in the 2-input CMOS NAND circuit.
It is an expression representing a β ratio such that the circuit threshold becomes 1/2 Vdd when the input to the NMOS transistor TN1 near ut changes. The circuit threshold of the NAND configured by this β ratio is Vdd / 2, and a high noise margin can be secured when configuring the integrated circuit.

Where βn is the gain coefficient of the NMOS transistor,
βp is the gain coefficient of the PMOS transistor, Vdd is the power supply voltage, Vt
n is the threshold voltage of the NMOS transistor, Vtp is the threshold voltage of the PMOS transistor, Vint is the intermediate potential between TN1 and TN2 in FIG. 2, λp
Is the channel length modulation element of the PMOS transistor, λn is the NMOS
It is a channel length modulation element of a transistor.

Assuming that Vtp = -Vtn and Vtn = | Vt |

[0055]

[Equation 9]

It becomes

This is, for example, λp = λn = 0.01, Vdd = 1.0
If V, Vtn = 0.2V,

[0058]

[Equation 10]

It becomes

As for the gate width W, as described in the conventional example (FIG. 10 (B)), a two-stage NAND 2-stage series NM is used.
The W of the OS transistor was often designed to be twice as large as the W of the inverter with one stage connected in series. Further, because of the process parameter relationship (that is, the relationship between hole and electron mobilities and the driving capability ratio was generally set to 1), Wp was normally set to twice Wn.
In the case of NAND, Wp: Wn = 2: (1 × 2) = 1: 1. In this embodiment, for example, the β ratio may be 1.35, so that the W ratio is Wp: Wn =
2: (1 × 1.35) = 1: 0.675, which means that a smaller NMOS transistor is required for the same PMOS transistor, which has the advantage of reducing the layout pattern area.

(Embodiment 1-2) Next, as Embodiment 1-2, as shown in FIG. 3, the signal input to TP2 and TN2 of the two inputs changes from L to H (Vdd). And output Vout accordingly
Consider the case where H → L. Input to TP1, TN1 is H (Vdd)
And

Vin where Vin = Vout, that is, the circuit threshold is 1/2
Since Vdd has the largest noise margin and is desirable, consider the operation around Vin = 1 / 2Vdd.

The PMOS transistor TP1 whose gate input is fixed to Vdd is cut off, and the gate input is changed.
Transistor TP2 is in the saturation region (0 <Vgs
Operates with −Vt <Vds). In addition, the NMOS transistor TN1 whose gate input is fixed at Vdd operates linearly (0 <Vds <Vgs−Vt).
To do. On the other hand, an NMOS transistor TN whose gate input changes
2 is the voltage drop due to TN1 (α = 1 near Vin = 1 / 2Vdd
If / 2Vdd−Vint) is smaller than the threshold value Vtn2 of TN2, then saturated operation is performed, and if larger, linear operation is performed.

The equivalent circuit of this is shown in FIG.
(B).

1/2 ・ Vdd−Vtn2 <Vint Vtn2> α → Saturation operation (FIG. 4 (A)) 1/2 · Vdd−Vtn2> Vint Vtn2 <α → Linear operation (FIG. 4 (B)) Saturation operation TP2 is equivalent to having one current source connected in parallel. Regarding the NMOS transistor, TN1 can be described as a resistance because TN1 is a linear operation, and TN2 is shown in the same figure (A).
As shown in the figure, one current source is used for saturation operation.
When it operates linearly like (B), it can be described as a resistance.

The total current Idsp of the PMOS transistors connected in parallel is the transistor TP1 to which Vdd is input to the gate.
Is off, it is only necessary to consider one transistor (saturation operation) in which the input signal changes. Let Vgs be the circuit threshold Vdd / 2,

[0067]

[Equation 11]

It is

(Embodiment 1-2-A) First, considering the case where TN2 is in a saturated operation as shown in FIG. 4 (A), the gate input of TN1 is Vdd and the gate input of TN2 is 1 /. It is 2 Vdd.
Assuming that the intermediate potential of FIG. 4A is Vint and Vtn1 = Vtn2, Ids3 = Ids5 = Idsn from Ids of TN1 = Ids of TN2.

[0070]

[Equation 12]

Vint is given as the solution of equation (3). That is, Equation (3) is the intermediate potential Vint between TN1 and TN2 when the input to the NMOS transistor TN2 near gnd changes in the 2-input CMOS NAND circuit and the transistor operates in saturation.
Is an expression representing. If λn = 0,

[0072]

[Equation 13]

It becomes Next from Idsp = Idsn

[0074]

[Equation 14]

However, Vtp <0

[0076]

[Equation 15]

However, Vint is a 2-input NAND circuit in which the β ratio that satisfies the condition of the formula (4) given by the formula (3) is set.
It is an example of A. That is, equation (4) is a 2-input CMOS NA.
In the ND circuit, when the input to the NMOS transistor TN2 near gnd changes and the transistor operates in saturation, it is a formula that represents a β ratio such that the circuit threshold becomes 1/2 Vdd. This β
The NAND circuit threshold composed of the ratio is Vdd / 2, and a high noise margin can be secured when configuring an integrated circuit. Here, assuming that Vtp = −Vtn and Vtn = | Vt |, the equation (4) can be expressed as follows.

[0078]

[Equation 16]

Further, TN2 is saturated (1 / 2Vdd−Vint <Vtn2)
If you look at the condition of Vtn2 from the assumption that
It operates in the saturation range of 0.146Vdd <Vtn2. Therefore, when the thresholds of TN1 and TN2 are equal (Vtn1 = Vtn2), equations (3) and (4) are established when the threshold is 0.146 · Vdd or more (and actually less than 1/2 Vdd). This is, for example, λ
If p = λn = 0.01, Vdd = 1.0V, | Vt | = 0.2V,

[0080]

[Equation 17]

It becomes

(Embodiment 1-2-B) Next, considering the case where TN2 is linearly operating as shown in FIG. 4B, the gate input of TN1 is Vdd and the gate input of TN2 is 1 It is / 2Vdd. If the intermediate potential of FIG. 4 (B) is Vint,

[0083]

[Equation 18]

Because these are equal

[0085]

[Formula 19]

Vint is given as the solution of equation (5). That is, the equation (5) is obtained when the input to the NMOS transistor TN2 near gnd changes and the transistor operates linearly.
It is an expression representing an intermediate potential Vint between TN1 and TN2. here

[0087]

[Equation 20]

From IdsP = IdsN,

[0089]

[Equation 21]

However, Vtp <0

[0091]

[Equation 22]

However, Vint is given by the equation (5).

The 2-input NAND circuit in which the β ratio is set to satisfy the condition of the expression (6) is the embodiment 1-2-B. That is,
Equation (6) is an NMOS that is close to gnd in a 2-input CMOS NAND circuit.
When the input to the transistor TN2 changes and the transistor operates linearly, the circuit threshold becomes 1/2 Vdd.
It is an expression showing a ratio. The circuit threshold of the NAND configured by this β ratio is Vdd / 2, and a high noise margin can be secured when configuring the integrated circuit. Where λp = λn = 0.01, Vtp = −V
Assuming tn, Vtn = | Vt |

[0094]

[Equation 23]

It becomes

Further, TN2 is linearly operated (1 / 2Vdd-Vint> Vtn2)
If you look at the condition of Vtn2 from the assumption that
TN2 operates linearly in the range of Vtn <0.146Vdd. That is, Eqs. (5) and (6) hold when Vtn <0.146Vdd.

This is, for example, λp = λn = 0.01, Vdd = 1.0
If V, | Vt | = 0.1V,

[0098]

[Equation 24]

If Vtp = -Vtn,

[0100]

[Equation 25]

It becomes

Therefore, when Vtn1 = Vtn2, Vtn <
For devices with thresholds such as 0.146 Vdd, β in equation (6)
If the ratio is set, and the threshold device is 0.146Vdd <Vtn <0.5Vdd, the 2-input NAND that sets the β ratio in equation (4) is the 1-2nd.
It is an example of. The circuit threshold of NAND configured with this β ratio is
It becomes Vdd / 2, and a high noise margin can be secured when configuring an integrated circuit.

As for the gate width W, as described in the conventional example (FIG. 10 (B)), the two-stage NAND of the 2-input NAND is connected in series.
The W of a MOS transistor was often designed to be twice as large as the W of an inverter with one stage connected in series. Because of the process parameters, Wp is usually twice Wn, so in the case of the conventional 2-input NAND, Wp: Wn = 2: (1 × 2) = 1:
It was 1.

In this embodiment, for example, the β ratio may be 1 to 1.025, so that the W ratio is Wp: Wn = 2: (1 × 1.025) = 1: 0.5125, and a small NMOS transistor is sufficient for the same PMOS transistor. There is also the advantage of reducing the area of the pattern.

According to the present embodiment, the noise margin is increased by setting the β ratio of the 2-input CMOS NAND circuit within the range surrounded by the equations (2), (4) and (6). You can

Therefore, depending on how the input signal of the target NAND changes, for example, which of the inputs of TN1 and TN2 has a higher probability of changing stochastically, the β ratio is set to the 1-1. Either the embodiment or the 1-2nd embodiment can be selected and determined most appropriately.

Further, in the case of the 1-2nd embodiment, the optimum β ratio can be determined by the threshold value of the NMOS transistor TN2. Alternatively, it is possible to optimize the input pattern according to the critical path.

Further, although the optimum β ratio in the 2-input NAND is shown in the 1-1 and 1-2 embodiments, the optimum β ratio and the optimization method in the NAND are not limited to 2-input. Even in NAND with m inputs (m> 2), the optimum β ratio can be set by the same method.

(Second Embodiment) In the second embodiment,
A method of setting the β ratio that enhances the noise margin in the case of a 2-input CMOS NOR circuit (negative OR circuit) will be described. In the following, the equation expressing the β ratio such that the circuit threshold becomes 1/2 Vdd is given by
In one case, that is, (the 2-1st embodiment) the output terminal Vo
When the input to the PMOS transistor TP2 close to ut changes (Example 2-2-A), the PMOS close to the power supply voltage Vdd
When the input to the transistor TP1 changes and the transistor operates in saturation, and (Example 2-2-B) when the input to the PMOS transistor TP1 near the power supply voltage Vdd changes and the transistor operates linearly. I will explain separately.

(Second Example) FIG. 5 is a circuit diagram of a 2-input CMOS NOR circuit according to the second embodiment. TP1, TP
2 is a PMOS transistor, TN1 and TN2 are NMOS transistors, β
p and βn are the gain coefficient of each MOS transistor and the gate width
It is a value proportional to Wp and Wn.

Now, of the two inputs, the signal entering TP2 and TN2 changes from H (Vdd) to L (gnd), and the output Vout accordingly.
Consider the case of L → H. The input to TP1 and TN1 is L (gnd).

Vin where Vin = Vout, that is, the circuit threshold is 1/2
Since Vdd has the largest noise margin and is desirable, consider the operation around Vin = 1 / 2Vdd.

The NMOS transistor TN1 whose gate input is fixed to gnd is cut off, and the PMOS transistor TP1 is linearly operated (0 <Vds <Vgs-Vt). On the other hand, the PMOS transistor TP2 and the NMOS transistor TN2 whose gate inputs change are
It operates in the saturation region (0 <Vgs-Vt <Vds) near Vgs = 1 / 2Vdd. FIG. 6 shows this by an equivalent circuit.

The NMOS transistor TN2 which operates in saturation is equivalent to one current source connected in parallel, and the PMOS transistor TP2 which operates in saturation similarly operates as a single current source, the PMOS transistor TP1 which operates linearly. Is given as a resistance and is connected in series with the current source.

The total current Idsn of the NMOS transistors connected in parallel is calculated by the transistor TN1 whose gate is input by gnd.
The transistor whose input signal changes because is off
Only one TN2 (saturation operation) need be considered. Assuming that Vgs is Vdd / 2 which is a circuit threshold value, considering channel length modulation,

[0116]

[Equation 26]

It becomes:

On the other hand, in the PMOS transistors connected in series, the gate input of TP1 is gnd and the gate input of TP2 is 1/2 Vd.
d. The intermediate potential of Fig. 6 is Vint (however, Vint> 1/2 ・ Vd
d), (Ids of TP1) = (Ids of TP2), Ids3 =
Since Ids5 = Idsp,

[0119]

[Equation 27]

From now on

[0121]

[Equation 28]

However, Vtp <0Vint is given as the solution of equation (7). That is, the expression (7) is an expression representing the intermediate potential Vint between TP1 and TP2 when the input to the PMOS transistor TP2 near the output changes in the 2-input CMOS NOR circuit. If channel length modulation is not taken into consideration, λ = 0 is set as shown below.

[0123]

[Equation 29]

However, Vtp <0 and then Idsp = Idsn

[0125]

[Equation 30]

However, Vint is given by the equation (7).

The 2-input NOR circuit in which the β ratio which satisfies the condition of the expression (8) is set is the 2-1st embodiment.

That is, the expression (8) is an expression representing the β ratio such that the circuit threshold becomes 1/2 Vdd when the input to the PMOS transistor TP2 near the output changes in the 2-input CMOS NOR circuit.

The circuit threshold of NOR constructed by this β ratio is Vdd / 2
Therefore, a high noise margin can be secured when configuring the integrated circuit. Here, assuming that Vtp = −Vtn and Vtn = | Vt |

[0130]

[Equation 31]

It becomes: This means, for example, λp = λn = 0.01,
If Vdd = 1.0V, | Vt | = 0.2V,

[0132]

[Equation 32]

It becomes:

As for the gate width W, as described in the conventional example (FIG. 10 (C)), the 2-stage NOR 2-stage serial PMO is used.
The W of the S-transistor was often designed twice as much as the W of the inverter with one stage connected in series. Since Wp is normally twice Wn because of the process parameters, Wp: Wn = (2 × 2): 1 = 4: 1 in the case of the conventional 2-input NAND.
Met. In this embodiment, for example, the β ratio may be 1.37,
The W ratio is Wp: Wn == (2 × 1.37): 1 = 2.74: 1, and the same N
The size of the layout pattern is also reduced, because it requires a smaller PMOS transistor than the MOS transistor.

(Second to Second Embodiment) Next, as a second to second embodiment, as shown in FIG. 7, the signal input to TP1 and TN1 of the two inputs changes from H to L (gnd). And output Vout accordingly
Consider the case where L → H. Input to TP2, TN2 is L (gnd)
And

Vin where Vin = Vout, that is, the circuit threshold is 1/2
Since Vdd has the largest noise margin and is desirable, consider the operation around Vin = 1 / 2Vdd.

The NMOS transistor TN2 whose gate input is fixed to gnd is cut off, and whose gate input changes
Transistor TN1 is in the saturation region (0 <Vgs near Vgs = 1 / 2Vdd.
Operates with −Vt <Vds).

Also, the PMOS whose gate input is fixed to gnd
The transistor TP2 operates linearly (0 <Vds <Vgs−Vt).

On the other hand, in the PMOS transistor TP1 whose gate input changes, α = Vint−1 / 2 · Vdd near Vin = 1 / 2Vdd
If it is smaller than the threshold value Vtp1 of TP1, saturation operation is performed, and if it is larger, linear operation is performed.

This is represented by an equivalent circuit in FIGS. 8 (A) and 8 (B).

1/2 · Vdd− | Vtp1 | <Vdd−Vint | Vtp1 |> α → Saturation operation (Fig. 8 (A)) 1/2 ・ Vdd− | Vtp1 |> Vdd−Vint | Vtp1 | <α → Linear operation (Fig. 8 (B)) TN1 operating in saturation is equivalent to one current source connected in parallel. Regarding the PMOS transistor, TP2 can be described as a resistance because TP2 is a linear operation, and TP1 is shown in Fig. 8 (A).
As shown in FIG.
It is given as a resistance when it operates linearly like (B).

Regarding the total current Idsn of the NMOS transistors connected in parallel, since the transistor whose gate is input by gnd is off, only one transistor (saturation operation) in which the input signal changes may be considered. Let Vgs be the circuit threshold Vdd / 2,

[0143]

[Expression 33]

It is

(Embodiment 2-2-A) First, considering the case where TP1 is in a saturated operation as shown in FIG. 8A, the gate input of TP1 is 1/2 Vdd and the gate input of TP2 is It's gnd. Assuming that the intermediate potential in FIG. 8A is Vint and Vtp1 = Vtp2,
From Ids of TP1 = Ids of TP2, Ids5 = Ids3 = Idsn, so

[0146]

[Equation 34]

Vint is given as the solution of equation (9). That is, the expression (9) is close to Vdd in the 2-input CMOS NOR circuit.
6 is an expression representing an intermediate potential Vint between TP1 and TP2 when the input to the PMOS transistor TP1 changes and the transistor operates in saturation.

If λ = 0,

[0149]

[Equation 35]

Next, from Idsp = Idsn

[0151]

[Equation 36]

However, Vtp <0 and Vint are given by equation (9).

The 2-input NOR circuit in which the β ratio is set to satisfy the condition of the expression (10) is the 2-2-A embodiment.

That is, the equation (10) shows that in the 2-input CMOS NOR circuit, when the input to the PMOS transistor TP1 close to Vdd changes and the transistor operates in saturation, the circuit threshold is
It is an expression representing a β ratio such that 1/2 Vdd is obtained.

The circuit threshold value of the NOR configured with this β ratio is Vdd / 2.
Therefore, a high noise margin can be secured when configuring the integrated circuit. Here, assuming that Vtp = −Vtn and Vtn = | Vt |, the equation (10) can be expressed as follows.

[0156]

[Equation 37]

Since it is assumed that TP1 is a saturated operation (Vint <1 / 2Vdd−Vtp1),

[0158]

[Equation 38]

It is understood that the expressions (9) and (10) are satisfied within the range of. This is, for example, λp = λn = 0.01, Vdd = 1.0V, | V
If t | = 0.2V,

[0160]

[Formula 39]

It becomes Therefore, when the threshold value of the PMOS transistor is within the above range, designing the β ratio according to the equation (10) enables circuit design with a large margin.

(Example 2-2-B) Next, considering the case where TP1 is linearly operating as shown in FIG. 8B, the gate input of TP2 is gnd and the gate input of TP1 is 1 It is / 2Vdd.
If the intermediate potential of FIG. 8 (B) is Vint,

[0163]

[Formula 40]

Because these are equal

[0165]

[Formula 41]

Vint is given as the solution of equation (11). That is, equation (11) is the intermediate potential Vint between TP1 and TP2 when the input to the PMOS transistor TP1 near Vdd changes and the transistor operates linearly in the 2-input CMOS NOR circuit.
Is an expression representing. here

[0167]

[Equation 42]

From IdsP = IdsN,

[0169]

[Equation 43]

However, Vtp <0 and Vint are given by the equation (11).

The 2-input NOR circuit in which the β ratio is set to satisfy the condition of the expression (12) is the 2-2-B embodiment.

That is, in the equation (12), in the 2-input CMOS NOR circuit, when the input to the PMOS transistor TP1 near Vdd changes and the transistor operates linearly, the circuit threshold is
It is an expression representing a β ratio such that 1/2 Vdd is obtained.

The circuit threshold of NOR constructed by this β ratio is Vdd / 2
Therefore, a high noise margin can be secured when configuring the integrated circuit. Here, assuming that Vtp = −Vtn and Vtn = | Vt |

[0174]

[Equation 44]

It becomes: Also, the linear operation of TP1 (Vint> 1 / 2Vd
From the assumption of (d−Vtp1),

[0176]

[Equation 45]

Expressions (11) and (12) are satisfied in the range of. this is,
For example, if λp = λn = 0.01, Vdd = 1.0V, | Vt | = 0.1V,

[0178]

[Equation 46]

It becomes:

Therefore, when Vtp1 = Vtp2, the formula (1
The 2-input NOR setting the β ratio of (0) or (12) is the second
2 is an example. The NOR circuit threshold configured with this β ratio is Vdd / 2, and a high noise margin can be secured when configuring an integrated circuit.

As for the gate width W, as described in the conventional example (FIG. 10C), the two-stage NOR 2-stage series P
The W of a MOS transistor was often designed to be twice as large as the W of an inverter with one stage connected in series. Because of the process parameters, Wp is usually twice Wn, so in the case of the conventional 2-input NOR, Wp: Wn = (2 × 2): 1 = 4: 1.

In the present embodiment, for example, the β ratio may be 1 to 1.025, so the W ratio is Wp: Wn = (2 × 1.025): 1 = 2.05: 1, which means that a small PMOS transistor can be used for the same NMOS transistor. There is also the advantage of reducing the area of the pattern.

According to the present embodiment, the β ratio of the 2-input CMOS NOR circuit is set within the range surrounded by the equations (8), (10), and (12) to enhance the noise margin. You can

Therefore, depending on how the input signal of the target NOR changes, for example, which one of the inputs of TP1 and TP2 has a higher probability of changing stochastically, the β ratio is set to the 2-1st ratio. Either the embodiment or the 2-2nd embodiment can be selected and determined most appropriately. Further, in the case of the 2-2nd embodiment, the PMOS transistor TP1
The optimum β ratio can be determined by the threshold value of. Alternatively, it is possible to optimize the input pattern according to the critical path.

Furthermore, although the optimum β ratio in the 2-input NOR is shown in the 2-1 and 2-2 embodiments, the optimum β ratio in the NOR and the optimization method are not limited to 2-input. Even in NOR with m inputs (m> 2), the optimum β ratio can be set by the same method.

Further, in addition to NAND and NOR, in a logic circuit in which NMOS or PMOS has a multistage series structure such as an Exclusive NOR circuit (non-exclusive OR circuit) as shown in FIG. It is clear that the β ratio can be calculated. In the case of FIG. 9, two types of potentials, namely, a potential between TP1 and TP2 and a potential between TN3 and TN1 (or TN2) are required as Vint.

[0187]

As described above, according to the present invention, CM
The noise margin of the semiconductor integrated circuit is increased by increasing the noise margin of the OS logic circuit. Especially, the effect is great in a circuit with a low power supply voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a 2-input CMOS NAND circuit according to Example 1-1 according to the first exemplary embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the circuit of FIG.

FIG. 3 is a circuit diagram of a 2-input CMOS NAND circuit according to Example 1-2 according to the first embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of FIG.

FIG. 5 is a circuit diagram of a 2-input CMOS NOR circuit according to a 2-1st example according to the second exemplary embodiment of the present invention.

6 is an equivalent circuit diagram of FIG.

FIG. 7 is a circuit diagram of a 2-input CMOS NOR circuit according to Example 2-2 according to the second embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of FIG. 7.

FIG. 9 is a circuit diagram of a 2-input Exclusive NOR circuit.

FIG. 10 A conventional CMOS logic circuit ((A) inverter,
FIG. 6 is a circuit diagram illustrating a channel width W of (B) 2-input NAND, (C) 2-input NOR).

[Explanation of symbols]

TP1, TP2, TP3 PMOS transistor TN1, TN2, TP3 NMOS transistor Vdd power supply voltage gnd ground terminal Vout output terminal

Continued front page    (72) Inventor Tsuneaki Fuse             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center F term (reference) 5F048 AB03 AB04 AC03 BA01 BB03                       BB15                 5J056 AA03 BB32 DD16 DD29 DD45                       EE06 EE12 EE13 FF09 GG09                       HH02

Claims (6)

[Claims] 1. A plurality of P-channel MOS transistors connected in parallel between a power supply terminal and an output terminal; a first N-channel MOS transistor provided between the output terminal and a ground terminal; Connected in series with one N-channel MOS transistor,
A second N-channel MOS transistor provided on the side of the ground terminal, and is a ratio of gain coefficients of the plurality of P-channel MOS transistors to gain coefficients of the first and second N-channel MOS transistors β A parameter setting method of a logic circuit for setting a ratio, comprising: the voltage of the power supply terminal, the threshold voltages of the plurality of P-channel MOS transistors, the threshold voltages of the first and second N-channel MOS transistors, The first N channel
A logic characterized by using the intermediate potential between the MOS transistor and the second N-channel MOS transistor to set the β ratio so that the circuit threshold of the logic circuit becomes half the voltage of the power supply terminal. Circuit parameter setting method. 2. The channel length modulation elements of the plurality of P-channel MOS transistors and the channel length modulation elements of the first and second N-channel MOS transistors are further used to set the β ratio. 2. The parameter setting method for a logic circuit according to claim 1, wherein: 3. A plurality of N-channel MOS transistors connected in parallel between a ground terminal and an output terminal, a first P-channel MOS transistor provided between a power supply terminal and the output terminal, Connected in series with 1 P-channel MOS transistor,
A second P-channel MOS transistor provided on the output terminal side, and a ratio β of gain coefficients of the first and second P-channel MOS transistors and a plurality of N-channel MOS transistors. A method for setting a parameter of a logic circuit for setting a ratio, comprising: the voltage of the power supply terminal; and the first and second P-channel M
The threshold voltage of the OS transistor and the N-channel MOS
The threshold voltage of the transistor and the intermediate potential between the first P-channel MOS transistor and the second P-channel MOS transistor are used so that the circuit threshold of the logic circuit is half the voltage of the power supply terminal. A parameter setting method for a logic circuit, characterized by setting a β ratio. 4. The channel length modulation elements of the first and second P-channel MOS transistors and the channel length modulation elements of the plurality of N-channel MOS transistors are further used to set the β ratio. 4. The method according to claim 3,
Parameter setting method for the described logic circuit. 5. A plurality of P-channel MOS transistors connected in parallel between a power supply terminal and an output terminal; a first N-channel MOS transistor provided between the output terminal and a ground terminal; Connected in series with one N-channel MOS transistor,
A logic circuit comprising a second N-channel MOS transistor provided on the ground terminal side, wherein the gain coefficients of the plurality of P-channel MOS transistors and the gain coefficients of the first and second N-channel MOS transistors are included. The β ratio, which is the ratio of the
Using a threshold voltage of a P-channel MOS transistor, threshold voltages of the first and second N-channel MOS transistors, and an intermediate potential between the first N-channel MOS transistor and the second N-channel MOS transistor And a circuit threshold of the logic circuit is set to be half the voltage of the power supply terminal. 6. A plurality of N-channel MOS transistors connected in parallel between a ground terminal and an output terminal; a first P-channel MOS transistor provided between a power supply terminal and the output terminal; Connected in series with 1 P-channel MOS transistor,
A logic circuit including a second P-channel MOS transistor provided on the output terminal side, wherein the gain coefficients of the first and second P-channel MOS transistors and the gain coefficients of the plurality of N-channel MOS transistors are provided. The ratio β of the power supply terminal, the threshold voltage of the first and second P-channel MOS transistors, the threshold voltage of the plurality of N-channel MOS transistors, and the first P-channel MOS Transistor and the second P channel M
A logic circuit characterized in that the circuit threshold of the logic circuit is set to be half the voltage of the power supply terminal by using the intermediate potential of the OS transistor.