JP2003086674A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device which is made small-sized by high integration. SOLUTION: The manufacturing method has a process of forming a 1st insulating layer 8 on a substrate where at least three adjacent contacts 5, 6, and 7 are formed, a process of forming an opening part at a specific position of the 1st insulating layer, a process of forming an Si-based conductive layer 10 on the 1st insulating layer and opening part, a process of forming a 2nd insulating layer 11 on the Si-based conductive layer, a process of etching only the Si-based conductive layer by anisotropic etching, a process of forming a silicide layer 15 on the etched Si-based conductive layer and forming Bit wires on the contacts respectively, a process of burying the 1st insulating layer and silicide layer in the 2nd insulating layer and 3rd insulating layer 16, and a process of forming a contact hole 19 by etching the 3rd insulating layer between adjacent Bit wires.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of forming a contact hole in a narrow space.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been required to be more cost-effective and higher in quality due to their improved characteristics and yields. There is an increasing demand for the provision of semiconductor devices.

For example, in manufacturing a DRAM (Dynamic Random Access Memory) or the like, a contact hole is formed in a very narrow space between Bit wirings, but miniaturization progresses for miniaturization of a semiconductor device. Accordingly, it is necessary to form a contact hole in a narrower space.

This can be dealt with by reducing the diameter of the contact hole, but in practice, there is a limit to the mask patterning technique for forming the contact hole, so the diameter of the contact hole should be reduced. It is difficult. Therefore, currently, PSC (Poly Shrun
The contact holes are formed using a ken contact) method, a SAC (Self Align Contact) method, a SWP (side wall protection) method, or the like.

[0005]

However, in the above-mentioned PSC method, the contact hole formation position exceeds the predetermined allowable range due to the displacement of the mask position during the contact hole formation process, and as a result, There is a problem that a short circuit will occur.

Further, in the case of the SAC method described above, since a film having a high dielectric constant such as SiN is used between the wirings, there is a problem that the capacitance between the wirings becomes large.

Therefore, at present, a method of manufacturing a semiconductor device in which a contact hole is formed in a narrower space to achieve miniaturization due to high integration of the semiconductor device has not yet been established.

Therefore, the present invention has been conceived in view of the above-mentioned conventional circumstances, and an object thereof is to provide a method of manufacturing a semiconductor device which achieves miniaturization by high integration.

[0009]

A method of manufacturing a semiconductor device according to the present invention, which achieves the above object, comprises a step of forming a first insulating layer on the entire surface of a substrate on which at least three adjacent contacts are formed. , A step of forming an opening on each of the two contacts located at both ends of the three contacts of the first insulating layer, and a step other than on the contact located in the center of the three contacts on the first insulating layer. A step of forming a Si-based conductive layer on the region and the opening, a step of forming a second insulating layer on the Si-based conductive layer, and a step of etching only the Si-based conductive layer by isotropic etching, A metal layer is formed on the etched Si-based conductive layer, and heat treatment is performed to form a silicide layer.
A step of forming bit wirings adjacent to each other on two contacts located at both ends of one contact, and a step of filling a first insulating layer, a silicide layer and a second insulating layer with a third insulating layer And between adjacent Bit wirings in the third insulating layer, a contact hole is formed by etching so that only the central contact of the three contacts, the first insulating layer and the second insulating layer are exposed. It has a process of forming.

In the method of manufacturing a semiconductor device according to the present invention as described above, the Si-based conductive layer formed below the insulating layer having etching selectivity with respect to Si is finely processed by isotropic etching. The region where the contact hole is formed between the wirings is effectively used. Further, a silicide formed by forming a metal layer on the Si-based conductive layer finely processed by the isotropic etching by electroless plating and further performing heat treatment is used for the Bit wiring. As a result, in this semiconductor device manufacturing method, low-resistance, self-aligned contact holes are formed in a very narrow region between the bit wirings. In addition, the contact hole formed by the method of manufacturing a semiconductor device is surely ensured of electrical insulation.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to COB (Capacitor Over Bit Li).
A case of manufacturing a ne) DRAM will be described as an example. A detailed description will be given with reference to the drawings.

First, as shown in FIG. 1, BPSG (Boro-Phospho-Silicate-Glass) is formed on a Si substrate 1 by a known process.
s) deposit the film 2 to a thickness of eg 300 nm and then
As shown in FIG. 3, a resist 3 is formed to have a thickness of 320 nm and patterned into a predetermined shape. Next, as shown in FIG. 3, the resist 3 is used as a mask to form the BPSG film 2
A part of is etched to form a groove 4 for a contact hole. Next, as shown in FIG. 4, the resist 3 is removed, and as shown in FIG. 5, Poly-Si doped with impurities for lowering the electric resistance is embedded in the groove, and contacts 5, 6 with the Si substrate 1 are formed. Form 7. Here, the contacts 5 and 7 are for connecting to the bit wiring of the DRAM, and the contact 6 is for connecting to the capacitor. Moreover, as impurities added to Poly-Si, phosphorus, boron, etc. are suitable.

Next, as shown in FIG. 6, an oxide film 8 is formed as an insulating film on the BPSG film 2 and the contacts 5, 6 and 7 to a thickness of 100 nm, for example. Then, as shown in FIG. 7, an opening of, for example, about 100 nm is formed only above the contacts 5 and 7 connected to the Bit wiring.

Next, as shown in FIG.
As the Si-based conductive film on the oxide film 8, Poly-Si doped with impurities for reducing the electric resistance is used, for example, 3
The poly-Si 10 layer is deposited to a thickness of 00 nm, and SiN is deposited to a thickness of 100 nm on the poly-Si layer 10 as an insulating film having etching selectivity with respect to Si as shown in FIG. Then, the SiN layer 11 is formed. Here, phosphorus, boron, etc. are suitable as impurities added to the Poly-Si. Also, S
As the material for forming the insulating film having etching selectivity with respect to i, SiON, S
A composite film of iC, SiN, SiON, and SiC is suitable.

Then, as shown in FIG. 10, the SiN layer 11 is formed.
A resist 12 is formed thereon with a thickness of, for example, 350 nm,
Poly-S having a predetermined shape, that is, a Bit wiring
The i layer 10 and the SiN layer 11 are patterned into a shape so as to be separated for each Bit wiring. Next, FIG.
As shown in FIG. 1, using this resist 12 as a mask, SiN
A part of the layer 11 and the Poly-Si layer 11 is etched to form a Bit wiring 13 made of Poly-Si and SiN.

Next, the resist is removed as shown in FIG. 12, and the Poly-Si layer 10 and Si are removed as shown in FIG.
The Bit wiring 13 made of the N layer 11 is finely processed by isotropic etching to process the Bit wiring 13 to a predetermined size. At this time, the isotropic etching is performed by the bit wiring 13
The poly-Si layer 10 of the above is etched, but the SiN layer 11 of the bit wiring 13 and the oxide film 8 are formed.
Selectively etches under conditions that are not etched. In addition, the Poly-S of the oxide film 8 and the Bit wiring 13
Etching is performed so as to have a portion that overlaps with the i layer 10.

Next, as shown in FIG. 14, Ni is formed by electroless plating so as to cover the oxide film 8 and the bit wiring 13.
To have a thickness of 35 nm, for example, to form a Ni layer 14. Next, heat treatment is performed at a predetermined temperature, for example, a temperature of about 550 ° C. in a state where Ni is deposited, thereby
The layer 14 and the portion of the Poly-Si layer 10 of the Bit wiring 13 are reacted to form a silicide layer 15 as shown in FIG. At this time, the Poly-Si of the Bit wiring 13 is
The line width of the portion composed of the layer 10 and the silicide layer 15 is S
The Ni layer 14 is formed so as to be thinner than the line width of the iN layer 11. That is, when viewed from the direction of arrow A in FIG. 15, the Ni layer 14 is formed so that the SiN layer 11 protrudes from the silicide layer 15. By forming the Ni layer 14 in this way, it is possible to secure a space for forming the oxide film 16 as an insulating layer below the portion where the SiN layer 11 protrudes from the silicide layer 15 in a later step. Then, specifically, the Poly- of the Bit wiring 13 after the silicide layer 15 is formed is formed.
The Ni layer 14 is formed so that the line width of the portion composed of the Si layer 10 and the silicide layer 15 is smaller than the line width of the SiN layer 11 by 30 nm or more on one side. With such a size, the oxide film 16 as an insulating layer can be formed with a sufficient thickness, so that sufficient insulating properties can be obtained. Further, the Ni layer 14 is formed so that the line width of the Bit wiring 13 after forming the silicide layer 15 is thicker than the line width of the contacts 5 and 7.

Then, as shown in FIG. 16, the Ni layer 14 remaining unreacted with respect to the portion of the Poly-Si layer 10 of the Ni layer 14 is washed and removed.

Next, as shown in FIG. 17, an oxide film 16 serving as an interlayer insulating layer is formed on the oxide film 8 so as to cover the Poly-Si layer 10 and the silicide layer 15. At this time,
It is important to form the oxide film 16 also under the portion where the SiN layer 11 protrudes from the silicide layer 15. Si
By forming the oxide film 16 also under the portion of the N layer 14 protruding from the silicide layer 15, the bit wiring 13 is formed.
The contact hole 19 to be formed later can be surely electrically insulated.

Next, as shown in FIG. 18, a resist 17 having a thickness of, for example, 450 nm is formed on the oxide film 16 to have a predetermined shape, that is, a contact hole 19 to the capacitor.
The patterning is performed so as to have the opening 18 only in the portion where the pattern is formed. Next, as shown in FIG. 19, a part of the oxide film 16 is processed by anisotropic etching using the resist 17 as a mask to form a contact hole 19 to the capacitor.
To form. At this time, anisotropic etching is performed on the oxide film 8
The oxide film 16 is etched, but the SiN layer 1
1 is selectively performed in the vertical direction without etching. Then, the resist 17 is removed, and the formation of the contact hole 19 is completed.

In the semiconductor device manufacturing method as described above, the Poly-Si layer 1 which is a Si-based conductive layer formed below the insulating layer having etching selectivity with respect to Si.
Since 0 is finely processed by isotropic etching, Bit
It is possible to more effectively utilize the region where the contact hole 19 is formed between the wirings 13. As a result, B
The degree of freedom in designing the dimensions and arrangement of the it wiring 13 and the contact holes 19 is increased, and high integration of the semiconductor device is possible.

Further, a Ni layer 14 which is a metal layer is formed on the Poly-Si layer 10 finely processed by the isotropic etching by electroless plating, and a silicide layer 15 formed by further heat treatment is formed on the bit wiring 13. Used as a constituent material of. Specifically, since the Ni layer 14 and the silicide layer 15 of Poly-Si 10 are used as the constituent material of the Bit wiring 13, the Bit wiring 13 having a wiring resistance lower than that of the conventional Bit wiring can be realized. is there. Instead of forming the silicide of Ni and the Poly-Si layer as described above, the Co layer may be formed by electroless plating to form the silicide of Co and Poly-Si. Even in this case, Ni and Po
Similar to the case of forming a silicide with ly-Si, it is possible to realize a Bit wiring having a wiring resistance lower than that of the conventional Bit wiring.

That is, according to this method of manufacturing a semiconductor device, a low resistance self-aligned contact hole 19 can be formed in a very narrow region between the bit wirings 13.
It is also possible to reduce the cost of the PR process.

In this semiconductor device manufacturing method, the semiconductor device has a structure in which the Poly-Si layer 10 formed below the SiN layer 11 is microfabricated and silicide is formed in the microfabricated portion. Since the electrical insulation of the contact hole 19 can be reliably ensured, it is possible to manufacture a semiconductor device in which electrical defects such as a short circuit are prevented.

In the method of manufacturing the semiconductor device, B
Since a material having a high dielectric constant such as SiN is not used between the it wirings 13, it is possible to suppress the capacitance between the Bit wirings to be low.

Therefore, according to the method for manufacturing the semiconductor device, the bit wirings 13 are reliably insulated from each other in the narrower area with the minimum space between the bit wirings as compared with the conventional method for manufacturing the semiconductor device. The contact hole 19 can be formed in this state. This allows
The design dimensions of various members in the semiconductor device can be reduced, and the semiconductor device can be miniaturized by high integration.

It should be noted that the present invention is not limited to the above, and can be appropriately modified without departing from the gist of the present invention.

[0028]

According to the method of manufacturing a semiconductor device of the present invention,
A step of forming a first insulating layer on the entire surface of a substrate on which at least three adjacent contacts are formed; and a step of arranging the first insulating layer at both ends of the three contacts 2
Forming an opening on each of the two contacts,
Of the three contacts on the first insulating layer, a step of forming a Si-based conductive layer on a region other than the centrally located contact and on the opening, and a second insulation on the Si-based conductive layer. A step of forming a layer, a step of etching only the Si-based conductive layer by isotropic etching,
A metal layer is formed on the etched Si-based conductive layer, and a heat treatment is performed to form a silicide layer, and bit wirings are adjacent to each other on the two contacts located at both ends of the three contacts. The step of forming, the step of embedding the first insulating layer, the silicide layer, and the second insulating layer with a third insulating layer, and the step between the adjacent Bit wirings in the third insulating layer, The method includes a step of forming a contact hole by performing etching processing so that only the contact located at the center of the three contacts, the first insulating layer, and the second insulating layer are exposed.

In the semiconductor device manufacturing method according to the present invention as described above, as compared with the conventional semiconductor device manufacturing method, a self-aligned contact hole having a low resistance is formed in a very narrow region between adjacent bit wirings. Can be formed, and the design dimensions of various members of the semiconductor device can be reduced.

Therefore, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device which achieves miniaturization by high integration.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating one step of a method of manufacturing a semiconductor device to which the present invention is applied, in which a BPSG film 2 is formed on a Si substrate 1.
It is sectional drawing which shows the state which accumulated.

FIG. 2 is a cross-sectional view illustrating one step of the method of manufacturing a semiconductor device to which the present invention is applied, showing a state in which the resist 3 is patterned into a predetermined shape.

FIG. 3 is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device to which the present invention is applied, showing a state in which a trench 3 for a contact hole is formed by etching using a resist 3 as a mask. .

FIG. 4 is a cross-sectional view illustrating one step of the method of manufacturing a semiconductor device to which the present invention is applied, showing a state in which the resist 3 is removed.

FIG. 5 is a cross-sectional view illustrating one step of the method of manufacturing a semiconductor device to which the present invention is applied, showing a state in which contacts 5, 6, and 7 with the Si substrate 1 are formed.

FIG. 6 is a cross-sectional view illustrating one step of a method of manufacturing a semiconductor device to which the present invention is applied, showing a state in which an oxide film 8 is formed.

FIG. 7 is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device to which the present invention is applied, showing a state in which openings are formed only above contacts 5 and 7 connected to Bit wiring. .

FIG. 8 is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device to which the present invention is applied, showing a state in which a Poly-Si10 layer is formed.

FIG. 9 is a cross-sectional view illustrating one step of the method of manufacturing a semiconductor device to which the present invention is applied, showing the state in which the SiN layer 11 is formed.

FIG. 10 is a cross-sectional view illustrating one step of the method of manufacturing a semiconductor device to which the present invention is applied, showing a state in which the resist 12 is patterned into a predetermined shape.

FIG. 11 is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device to which the present invention is applied, showing a state in which a Bit wiring 13 made of Poly-Si and SiN is formed by etching using a resist 12 as a mask. FIG.

FIG. 12 is a cross-sectional view illustrating one step of the method of manufacturing a semiconductor device to which the present invention is applied, showing a state in which the resist has been removed.

FIG. 13 is a cross-sectional view for explaining one step of the method for manufacturing a semiconductor device to which the present invention is applied, and is a cross-sectional view showing a state where the Bit wiring 13 is finely processed by isotropic etching.

FIG. 14 is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device to which the present invention is applied, showing a state in which a Ni layer 14 is formed.

FIG. 15 is a cross-sectional view illustrating one step of the method of manufacturing a semiconductor device to which the present invention is applied, showing a state in which a silicide layer 15 is formed.

FIG. 16 is a cross-sectional view illustrating one step of the method of manufacturing a semiconductor device to which the present invention is applied, showing a state in which the Ni layer 14 is removed.

FIG. 17 is a cross-sectional view illustrating one step of the method of manufacturing a semiconductor device to which the present invention is applied, showing a state in which an oxide film 16 is formed.

FIG. 18 is a cross-sectional view illustrating one step of the method for manufacturing a semiconductor device to which the present invention is applied, showing a state in which the resist 17 is patterned into a predetermined shape.

FIG. 19 is a cross-sectional view illustrating one step of the method for manufacturing a semiconductor device to which the present invention is applied, showing a state in which contact holes 19 are formed by etching using resist 17 as a mask.

[Explanation of symbols]

1 Si substrate, 2 BPSG film, 3 resist, 4
Groove, 5 contacts, 6 contacts, 7 contacts,
8 oxide film, 9 openings, 10 Poly-Si layer, 1
1 SiN layer, 12 resist, 13 Bit wiring, 1
4 Ni layer, 15 Silicide layer, 16 Oxide film, 17
Resist, 18 openings, 19 contact holes

Continued front page    F-term (reference) 5F033 HH04 HH07 HH15 HH25 JJ04                       KK01 LL01 LL04 MM10 PP28                       QQ08 QQ09 QQ18 QQ28 QQ35                       QQ37 QQ70 QQ73 RR01 RR02                       RR06 RR08 RR15 TT02 VV10                       VV16 XX03 XX24                 5F083 AD21 AD48 AD49 JA35 JA39                       MA02 MA06 MA17 MA20 PR06                       PR07 PR29

Claims (12)

[Claims] 1. A step of forming a first insulating layer on the entire surface of a substrate on which at least three adjacent contacts are formed, and two contacts located at both ends of the three contacts of the first insulating layer. Forming openings on the first insulating layer, forming a Si-based conductive layer on the opening other than the central contact among the three contacts on the first insulating layer, and the opening. A step of forming a second insulating layer on the Si-based conductive layer; a step of etching only the Si-based conductive layer by isotropic etching; and a metal layer formed on the etched Si-based conductive layer. Then, a heat treatment is performed to form a silicide layer, and bit wirings are formed adjacent to each other on the two contacts located at both ends of the above three contacts. And a step of filling the first insulating layer, the silicide layer, and the second insulating layer with a third insulating layer, and the three contacts between the adjacent Bit wirings in the third insulating layer. A method of manufacturing a semiconductor device, which comprises a step of forming a contact hole by etching so as to expose only the contact located in the center, the first insulating layer, and the second insulating layer. . 2. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating layer has etching selectivity with respect to the Si-based conductive layer. 3. The size of each of the openings is 3 or more.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the size of the two contacts located at both ends of the one contact is smaller than the size of the two contacts. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the Si-based conductive layer contains phosphorus. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the Si-based conductive layer contains boron. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the Si-based conductive layer is made of SiN. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the Si-based conductive layer is made of SiON. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the Si-based conductive layer is made of SiC. 9. The semiconductor device according to claim 1, wherein the adjacent bit wiring line widths are larger than the line widths of two contacts located at both ends of the three contacts. Production method. 10. The method of manufacturing a semiconductor device according to claim 1, wherein the metal layer is formed by electroless plating. 11. The method of manufacturing a semiconductor device according to claim 1, wherein the metal layer is made of Ni. 12. The method of manufacturing a semiconductor device according to claim 1, wherein the metal layer is made of Co.