JP2003077932A - Bidirectional type two terminal thyristor - Google Patents
Bidirectional type two terminal thyristorInfo
- Publication number
- JP2003077932A JP2003077932A JP2001265787A JP2001265787A JP2003077932A JP 2003077932 A JP2003077932 A JP 2003077932A JP 2001265787 A JP2001265787 A JP 2001265787A JP 2001265787 A JP2001265787 A JP 2001265787A JP 2003077932 A JP2003077932 A JP 2003077932A
- Authority
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- Japan
- Prior art keywords
- conductive region
- type conductive
- region
- type
- bidirectional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Thyristors (AREA)
- Thyristor Switches And Gates (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する分野】本発明は、サイリスタ、特に異常
電圧または異常電流から電子回路系を保護するサージ防
護素子等に用いる双方向型二端子サイリスタに関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thyristor, and more particularly to a bidirectional two-terminal thyristor used as a surge protection element for protecting an electronic circuit system from abnormal voltage or current.
【０００２】[0002]
【従来の技術】双方向型二端子サイリスタは、電話回線
などの通信回線に発生した異常電圧や異常電流から電子
回路を保護するサージ防護素子として、通信業界等で幅
広く用いられている。2. Description of the Related Art Bidirectional two-terminal thyristors are widely used in the telecommunications industry and the like as surge protection elements for protecting electronic circuits from abnormal voltages and currents generated in communication lines such as telephone lines.
【０００３】図２は、従来技術に係る双方向型二端子サ
イリスタを示す断面図である。図２において、１は基板
導電領域、２は第１Ｎ型導電領域、３は第２Ｎ型導電領
域、４は第１Ｐ型導電領域、７は第２Ｐ型導電領域、１
０は第１電極、１１は第２電極、５１はＰＮＰＮ構造、
１００は半導体基板である。また、図４は、従来技術に
係る双方向型二端子サイリスタの等価回路図である。FIG. 2 is a sectional view showing a bidirectional two-terminal thyristor according to the prior art. In FIG. 2, 1 is a substrate conductive region, 2 is a first N-type conductive region, 3 is a second N-type conductive region, 4 is a first P-type conductive region, 7 is a second P-type conductive region, 1
0 is the first electrode, 11 is the second electrode, 51 is the PNPN structure,
100 is a semiconductor substrate. Further, FIG. 4 is an equivalent circuit diagram of a bidirectional two-terminal thyristor according to a conventional technique.
【０００４】基板導電領域１は、Ｐ型の導電型を有する
ものである。第１Ｎ型導電領域２と第２Ｎ型導電領域３
は、基板導電領域１内部に不純物拡散によって形成され
たＮ型の導電型を有するものである。第１Ｐ型導電領域
４と第２Ｐ型導電領域７は、基板導電領域１内部に不純
物拡散によって形成されたＰ型の導電型を有するもので
ある。第１電極１０と第２電極１１は、半導体基板１０
０の両主面に形成された電極である。ここで、電極１０
は、第１Ｎ型導電領域２と第１Ｐ型導電領域４の双方と
電気的に接続される。また、第２電極１１は、第２Ｎ型
導電領域３と第２Ｐ型導電領域７の双方と電気的に接続
されるが、電極１０及び電極１１からみた電気的特性が
同一になるように、全体の構造を点対称とするのが一般
的である。なお、図２に示した双方向型二端子サイリス
タの等価回路図は、図４に示すものとなる。The substrate conductive region 1 has a P type conductivity type. First N-type conductive region 2 and second N-type conductive region 3
Has an N-type conductivity type formed by impurity diffusion inside the substrate conductive region 1. The first P-type conductive region 4 and the second P-type conductive region 7 have a P-type conductivity type formed by impurity diffusion inside the substrate conductive region 1. The first electrode 10 and the second electrode 11 are the semiconductor substrate 10
0 is an electrode formed on both main surfaces. Here, the electrode 10
Are electrically connected to both the first N-type conductive region 2 and the first P-type conductive region 4. In addition, the second electrode 11 is electrically connected to both the second N-type conductive region 3 and the second P-type conductive region 7, but the second electrode 11 has the same electrical characteristics as seen from the electrode 10 and the electrode 11. It is common to make the structure of point symmetry. The equivalent circuit diagram of the bidirectional two-terminal thyristor shown in FIG. 2 is shown in FIG.
【０００５】前記した双方向型二端子サイリスタにおい
て、第１Ｎ型導電領域２が設けられた上面側を第２Ｎ型
導電領域３が設けられた下面側に対して正の電位とする
電圧の印加方向を順方向、上面側を下面側に対して負の
電位とする電圧の印加方向を逆方向とする。図３は、従
来技術に係る双方向型二端子サイリスタの順方向の電気
的特性を示すグラフである。図３に示すように、順方向
においては、第１Ｐ型導電領域４をエミッタ、第１Ｎ型
導電領域２をベース、基板導電領域１をコレクタとする
ＰＮＰトランジスタと、第２Ｎ型導電領域３をエミッ
タ、基板導電領域１をベース、第１Ｎ型導電領域２をコ
レクタとするＮＰＮトランジスタの間で電子と正孔の交
換が行なわれて、オフ状態からオン状態へ移行する点弧
動作が行なわれる。In the above-described bidirectional two-terminal thyristor, the voltage application direction in which the upper surface side where the first N-type conductive area 2 is provided has a positive potential with respect to the lower surface side where the second N-type conductive area 3 is provided. Is the forward direction, and the application direction of the voltage that makes the upper surface side a negative potential with respect to the lower surface side is the reverse direction. FIG. 3 is a graph showing a forward electrical characteristic of a bidirectional two-terminal thyristor according to the related art. As shown in FIG. 3, in the forward direction, a PNP transistor having the first P-type conductive region 4 as an emitter, the first N-type conductive region 2 as a base, and the substrate conductive region 1 as a collector, and the second N-type conductive region 3 as an emitter. Electrons and holes are exchanged between NPN transistors having the substrate conductive region 1 as a base and the first N-type conductive region 2 as a collector, and an ignition operation for transitioning from an off state to an on state is performed.
【０００６】すなわち、最初オフ状態にあった図２のＰ
ＮＰＮ構造５１において、当該二端子電極領域に印加さ
れる電圧が、ブレークオ−バー電圧Ｖｂに達すると雪崩
降伏あるいはパンチスルーにより、逆バイアス状態にあ
る第１Ｎ型導電領域２と基板導電領域１の境界及び当該
境界近傍において、電子と正孔の交換が活発に行なわれ
るようになる。そして、前記のＰＮＰトランジスタのベ
ースと前記のＮＰＮトランジスタのコレクタが共通の第
１Ｎ型導電領域２であるため、当該ＰＮＰＮ構造からな
るサイリスタが点弧してオン状態へ遷移する。なお、構
造が上下で対称であることから逆方向においても全く同
様な動作が行なわれる。That is, P in FIG.
In the NPN structure 51, when the voltage applied to the two-terminal electrode region reaches the breakover voltage Vb, the boundary between the first N-type conductive region 2 and the substrate conductive region 1 in the reverse bias state due to avalanche breakdown or punch through. And, the exchange of electrons and holes is actively performed near the boundary. Since the base of the PNP transistor and the collector of the NPN transistor are the common first N-type conductive region 2, the thyristor having the PNPN structure is fired and transits to the ON state. Since the structure is vertically symmetrical, exactly the same operation is performed in the opposite direction.
【０００７】なお、ＰＮＰＮ構造からなるサイリスタが
点弧動作してオフ状態からオン状態へ移行するときに、
前記ＰＮＰトランジスタのベース接地電流増幅率α１と
前記ＮＰＮトランジスタのベース接地電流増幅率α２の
間には、α１+α2＝1の関係があることは周知の事実で
あり、ここでは内部動作のより詳細な説明については省
略する。When the thyristor having the PNPN structure is ignited to shift from the off state to the on state,
It is a well-known fact that there is a relationship of α 1 + α 2 = 1 between the grounded base current amplification factor α 1 of the PNP transistor and the grounded base current amplification factor α 2 of the NPN transistor. A more detailed description of the operation is omitted.
【０００８】以上のような点弧動作を行うサイリスタ
は、前記したように、ブレークオーバー電圧Ｖｂでサー
ジ電圧を抑圧するが、雷誘導サージのようにかなり速い
電気的サージに対してもその応答が他のサージ防護素
子、例えば避雷管や金属酸化物バリスタなどと比較して
非常に速いために、高い信頼性を要求される通信ネット
ワーク系の電子機器のように雷誘導サージを拾いやすい
ところでは殆ど利用されている状況にある。As described above, the thyristor which performs the ignition operation as described above suppresses the surge voltage by the breakover voltage Vb, but it also has a response to a considerably fast electric surge such as lightning induced surge. It is very fast compared to other surge protection devices such as lightning arresters and metal oxide varistors, so it is almost impossible to pick up lightning-induced surges, such as electronic devices of communication networks that require high reliability. It is being used.
【０００９】また、半導体基板で出来ているため、サー
ジ電流によって消耗するところがなく長期間に亘って信
頼性を維持することが可能であるという保守上の大きな
利点を有している。Further, since it is made of a semiconductor substrate, it has a great advantage in maintenance that it can be maintained for a long period of time without being consumed by a surge current.
【００１０】ところが、このような利点を有する双方向
型二端子サイリスタにおいても、どのような電気的サー
ジに対してもサージ電圧を抑圧出来るわけではなく、雷
誘導サージのような非常に時間変化の大きいサージに対
してはおのずと限界があり、そのサージに十分速く応答
出来ず、素子内で電流の集中が生じて局所的に高温とな
り、素子が溶解して破壊する場合がある。However, even in the bidirectional two-terminal thyristor having such advantages, the surge voltage cannot be suppressed against any electrical surge, and a very time-dependent change such as lightning-induced surge occurs. There is a limit to a large surge, and it is not possible to respond to the surge sufficiently quickly, and current may be concentrated in the element to locally raise the temperature, and the element may be melted and destroyed.
【００１１】そこで、時間変化の大きいサージに対する
対策の１つとして、本件の発明者らによるサイリスタが
ある。図５は、本件の発明者らによる双方向型二端子サ
イリスタの概略を示す断面図である。図５において、１
は基板導電領域、２は第１Ｎ型導電領域、３は第２Ｎ型
導電領域、４，５，６は第１Ｐ型導電領域、７，８，９
は第２Ｐ型導電領域、１０は第１電極、１１は第２電
極、１８，１９，２０，２１は絶縁体、５２はＰＮＰＮ
構造、１００は半導体基板である。また、図６は、図５
に示した双方向型二端子サイリスタにおける単位サイリ
スタ構造の等価回路図である。Therefore, as one of the countermeasures against the surge that greatly changes with time, there is a thyristor by the inventors of the present invention. FIG. 5 is a sectional view showing an outline of a bidirectional two-terminal thyristor by the inventors of the present invention. In FIG. 5, 1
Is a substrate conductive region, 2 is a first N type conductive region, 3 is a second N type conductive region, 4, 5 and 6 are first P type conductive regions, 7, 8 and 9
Is a second P-type conductive region, 10 is a first electrode, 11 is a second electrode, 18, 19, 20, 21 are insulators, and 52 is PNPN.
Structure 100 is a semiconductor substrate. In addition, FIG.
3 is an equivalent circuit diagram of a unit thyristor structure in the bidirectional two-terminal thyristor shown in FIG.
【００１２】図５に示されるように、上面側と下面側の
Ｐ型導電領域は、それぞれ分割して形成されており、さ
らに平面的に見て上面側と下面側のエミッタを重ねてい
る。この構成によって、図６の回路モデルで示される単
位サイリスタを並列に形成し、各単位サイリスタにサー
ジ電流の分流を図り、内部温度の上昇を抑制したもので
ある。実験によると、４個の単位サイリスタで、サージ
耐量が図２に示したような従来構造のサイリスタよりも
３０％以上向上することなどが確認されている。As shown in FIG. 5, the P-type conductive regions on the upper surface side and the lower surface side are formed separately, and the emitters on the upper surface side and the lower surface side are overlapped with each other in plan view. With this configuration, the unit thyristors shown in the circuit model of FIG. 6 are formed in parallel, the surge current is shunted to each unit thyristor, and the rise of the internal temperature is suppressed. According to experiments, it has been confirmed that the surge withstand capability of four unit thyristors is improved by 30% or more as compared with the thyristor having the conventional structure as shown in FIG.
【００１３】しかしながら、前記の構造では、図２に示
される従来構造のものより各単位サイリスタが点弧しや
すい構造になっているとはいえ、サージ電流が分流され
ることによって、点弧動作に必要な電流が大きくなり、
オフ状態からオン状態への遷移時間が長くなり、サージ
耐量が必ずしも期待したほど十分には大きくならないこ
とがあるという問題が残る。However, in the above-mentioned structure, although each unit thyristor is more easily ignited than the conventional structure shown in FIG. 2, the surge current is shunted to the ignition operation. The required current increases,
The problem remains that the transition time from the off state to the on state becomes long and the surge withstand capability may not always be sufficiently large as expected.
【００１４】[0014]
【発明が解決しようとする課題】本発明は、図５に示さ
れる従来構造をさらに改良して、当該構造で複数形成さ
れている単位サイリスタの全てを出来るだけ短時間に点
弧させてサージ耐量を大きくすることを目的としてい
る。The present invention further improves the conventional structure shown in FIG. 5 so that all of the unit thyristors formed in plural in the structure are ignited in the shortest time possible. The purpose is to increase.
【００１５】[0015]
【課題を解決するための手段】上記課題を解決するため
の手段として、本発明は、第1導電型の半導体基板に、
前記半導体基板の一方の面に露出させて形成してなる前
記半導体基板とは反対型の第２導電型の第１の導電領域
と、前記一方の面に露出させて形成すると共に前記第１
の導電領域内に配列してなるＮ個（Ｎ≧２）の第１導電
型の第２の導電領域と、前記第１の導電領域に隣接して
形成してなる第１導電型の第３の導電領域と、前記半導
体基板の前記一方の面に背向する他方の面に露出させて
形成してなる第２導電型の第４の導電領域と、前記他方
の面に露出させて形成すると共に前記第４の導電領域内
に配列してなるＮ個の第１導電型の第５の導電領域と、
前記第４の導電領域に隣接して形成してなる第１導電型
の第６の導電領域とを設け、１番目の前記第２の導電領
域は、平面的に見て２番目の前記第２の導電領域に近い
側の端部及びその近傍部分が１番目の前記第５の導電領
域と重なり合うように配置され、Ｎ番目の前記第５の導
電領域は、平面的に見てＮ−１番目の前記第５の導電領
域に近い側の端部及びその近傍部分がＮ番目の前記第２
の導電領域と重なり合うように配置され、１番目以外の
前記第２の導電領域は、平面的に見てそれらの両端部及
びそれらの近傍部分がＮ個の前記第５の導電領域と重な
り合うように配置され、Ｎ番目以外の前記第５の導電領
域は、平面的に見てそれらの両端部及びそれらの近傍部
分がＮ個の前記第２の導電領域と重なり合うように配置
されてなることを特徴とするものとした。前記した構成
においては、前記第３の導電領域及び前記第６の導電領
域を設けたことにより、前記第１の導電領域をコレク
タ、前記第３の導電領域、前記第６の導電領域、前記半
導体基板の第３及び第６の導電領域を設けていない残余
の領域からなるベース、前記第４の導電領域をエミッタ
とする第１のトランジスタのベース接地電流増幅率α1
を増大させた。As a means for solving the above problems, the present invention provides a semiconductor substrate of the first conductivity type,
A first conductive region of a second conductivity type opposite to that of the semiconductor substrate, which is formed by being exposed on one surface of the semiconductor substrate; and a first conductive region which is exposed on the one surface.
Second conductive regions of the first conductivity type (N ≧ 2) arranged in the conductive region of the first conductivity type, and third conductive regions of the first conductivity type formed adjacent to the first conductive region. Conductive region, a fourth conductive region of the second conductivity type formed by being exposed on the other surface of the semiconductor substrate facing the one surface, and a second conductive type fourth conductive region formed by being exposed on the other surface. Together with N fifth conductive regions of the first conductivity type arranged in the fourth conductive region,
A sixth conductive region of the first conductivity type formed adjacent to the fourth conductive region is provided, and the first second conductive region is the second second conductive region in plan view. Is arranged so that the end portion on the side close to the conductive region and the vicinity thereof overlap with the first fifth conductive region, and the Nth fifth conductive region is the (N-1) th in plan view. Of the N-th second end of the end portion near the fifth conductive region and the vicinity thereof.
Of the second conductive regions other than the first conductive region are overlapped with the N fifth conductive regions at both end portions thereof and in the vicinity thereof. The fifth conductive regions other than the Nth conductive region are arranged such that both end portions of the fifth conductive region and their neighboring portions in a plan view overlap with the N second conductive regions. And decided to. In the above-described configuration, by providing the third conductive region and the sixth conductive region, the first conductive region is a collector, the third conductive region, the sixth conductive region, and the semiconductor. Base ground current amplification factor α 1 of the first transistor having the base formed of the remaining region of the substrate not provided with the third and sixth conductive regions and the emitter of the fourth conductive region
Increased.
【００１６】従って、このベース接地電流増幅率α
1が、高抵抗率の半導体基板を用いることで大きくなっ
て、サージ電流が分流されることによって点弧動作に必
要な電流が大きくなり、オフ状態からオン状態への遷移
時間が長くなることに起因するサージ耐量の低下を改善
することが出来る。Therefore, this base ground current amplification factor α
1 increases with the use of a high-resistivity semiconductor substrate, and the surge current is shunted to increase the current required for ignition operation, resulting in a longer transition time from the off state to the on state. It is possible to improve the decrease in the surge withstand amount caused by the surge.
【００１７】また、前記の構成において、前記第３の導
電領域及び前記第６の導電領域は、それぞれ前記半導体
基板内に埋め込んで設けられるように出来る。Further, in the above structure, the third conductive region and the sixth conductive region may be embedded in the semiconductor substrate.
【００１８】また、前記第３の導電領域は、前記第１の
導電領域とその周辺との境界面のうち少なくとも前記第
４の導電領域に相対向する部分に接して設けられ、前記
第６の導電領域は、前記第４の導電領域とその周辺との
境界面のうち少なくとも前記第１の導電領域に相対向す
る部分に接して設けられるように出来る。Further, the third conductive region is provided in contact with at least a portion of the boundary surface between the first conductive region and the periphery thereof facing the fourth conductive region, and the sixth conductive region is provided. The conductive region may be provided in contact with at least a portion of the boundary surface between the fourth conductive region and the periphery thereof facing the first conductive region.
【００１９】さらに、前記第３の導電領域及び前記第６
の導電領域は、Ｎ個ずつ設けられると共に、それぞれ平
面的に見て前記第２の導電領域及び前記第５の導電領域
に重なり合う範囲内に設けられるように出来る。Further, the third conductive region and the sixth conductive region
N conductive regions may be provided, and each may be provided in a range overlapping with the second conductive region and the fifth conductive region when seen in a plan view.
【００２０】前記第３の導電領域及び前記第６の導電領
域は、Ｎ個ずつ設けられると共に、それぞれ平面的に見
て前記第２の導電領域及び前記第５の導電領域に重なり
合う範囲内に設けられるように出来る。Each of the third conductive region and the sixth conductive region is provided in N number, and is provided within a range overlapping with the second conductive region and the fifth conductive region in plan view. I can do it.
【００２１】くわえて、Ｎ個の前記第３の導電領域と前
記第６の導電領域とは、平面的に見て交互に且つ互いに
接した状態に配列されるように出来る。In addition, the N third conductive regions and the sixth conductive regions can be arranged alternately and in contact with each other in plan view.
【００２２】[0022]
【発明の実施の形態】以下に、本発明の第１の実施の形
態に係る双方向型二端子サイリスタを図面に基づいて詳
細に説明する。図１は、本発明の第１の実施の形態に係
る双方向型二端子サイリスタを示す断面図である。図１
において、１は基板導電領域、２は第１Ｎ型導電領域、
３は第２Ｎ型導電領域、４，５，６は第１Ｐ型導電領
域、７，８，９は第２Ｐ型導電領域、１０は第１電極、
１１は第２電極、１２は第３Ｐ型導電領域，１３は第４
Ｐ型導電領域、１８，１９，２０，２１は絶縁体、５３
はＰＮＰＮ構造、１００は半導体基板である。BEST MODE FOR CARRYING OUT THE INVENTION A bidirectional two-terminal thyristor according to a first embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a bidirectional two-terminal thyristor according to a first embodiment of the present invention. Figure 1
, 1 is a substrate conductive region, 2 is a first N-type conductive region,
3 is a second N-type conductive region, 4, 5, 6 are first P-type conductive regions, 7, 8 and 9 are second P-type conductive regions, 10 is a first electrode,
11 is the second electrode, 12 is the third P-type conductive region, and 13 is the fourth
P-type conductive region, 18, 19, 20, 21 are insulators, 53
Is a PNPN structure, and 100 is a semiconductor substrate.
【００２３】図１に示されるように、本発明の第１の実
施の形態に係る双方向型二端子サイリスタは、双方向で
電気的特性が対称となるように形成している。すなわ
ち、Ｐ型の半導体基板１００に第１Ｎ型導電領域２、第
２Ｎ型導電領域３を形成する。また、第１Ｎ型導電領域
２内に３つの第１Ｐ型導電領域４，５，６、第２Ｎ型導
電領域３内に３つの第２Ｐ型導電領域７，８，９を相対
向するＰ型導電領域と点対称になるように且つ等間隔に
形成する。また、第１Ｎ型導電領域２に隣接して第３Ｐ
型導電領域１２、第２Ｎ型導電領域３に隣接して第４Ｐ
型導電領域１３を配置する。また、第１Ｐ型導電領域４
を、平面的に見て第１Ｐ型導電領域５に近い側の端部及
びその近傍部分が第２Ｐ型導電領域７に重なり合うよう
に配置する。さらに、第２Ｐ型導電領域９を、平面的に
見て第２Ｐ型導電領域８に近い側の端部及びその近傍部
分が第１Ｐ型導電領域６に重なり合うように配置する。
くわえて、第１Ｐ型導電領域５，６と第２Ｐ型導電領域
７，８とを、平面的に見てそれらの両端部及びそれらの
近傍部分が相対向するＰ型導電領域とそれぞれ重なり合
うように配置する。電極は、半導体基板１００の上面側
の第１電極１０を第１Ｐ型導電領域４，５，６及び第１
Ｎ型導電領域２に接するように形成し、半導体基板１０
０の下面側の第２電極１１を第２Ｐ型導電領域７及び第
２Ｎ型導電領域１３に接するように形成して構成する。
なお、半導体基板１００の上記各領域を設けていない領
域は、Ｐ型の基板導電領域１となる。As shown in FIG. 1, the bidirectional two-terminal thyristor according to the first embodiment of the present invention is formed so that the electrical characteristics are bidirectional. That is, the first N-type conductive region 2 and the second N-type conductive region 3 are formed on the P-type semiconductor substrate 100. In addition, three first P-type conductive regions 4, 5, 6 in the first N-type conductive region 2 and three second P-type conductive regions 7, 8, 9 in the second N-type conductive region 3 face each other. It is formed so as to be point-symmetric with respect to the region and at equal intervals. In addition, the third P is adjacent to the first N-type conductive region 2.
Adjacent to the second conductive type region 12 and the second N-type conductive region 3
A type conductive region 13 is arranged. In addition, the first P-type conductive region 4
Is arranged so that the end portion on the side closer to the first P-type conductive region 5 and the vicinity thereof in plan view overlap the second P-type conductive region 7. Further, the second P-type conductive region 9 is arranged so that the end portion on the side closer to the second P-type conductive region 8 and the vicinity thereof are overlapped with the first P-type conductive region 6 in plan view.
In addition, the two ends of the first P-type conductive regions 5 and 6 and the second P-type conductive regions 7 and 8 and their neighboring portions are overlapped with the opposing P-type conductive regions. Deploy. The electrodes are formed by connecting the first electrode 10 on the upper surface side of the semiconductor substrate 100 to the first P-type conductive regions 4, 5, 6 and the first P-type conductive regions.
The semiconductor substrate 10 is formed so as to be in contact with the N-type conductive region 2.
The second electrode 11 on the lower surface side of 0 is formed so as to be in contact with the second P-type conductive region 7 and the second N-type conductive region 13.
The region of the semiconductor substrate 100 where the above regions are not provided becomes the P-type substrate conductive region 1.
【００２４】なお、第１Ｐ型導電領域４，５，６、及び
第２Ｐ型導電領域７，８，９は、上述した単位サイリス
タの特性を均一にするために、全て同一形状で同一面積
に形成することが好ましい。同様に、第３Ｐ型導電領域
１２及び第４Ｐ型導電領域１３も、全て同一形状で同一
面積に形成することが好ましい。また、第１Ｐ型導電領
域４，５，６と第２Ｐ型導電領域７，８，９との重ね幅
は、例えば２．６ｍｍチップの場合、マスク幅２５０μ
ｍに対して、２５μｍ重なるようにすればよく、サージ
耐量が向上することなどが確認されている。重なりが大
きくなるとオン電流が流れる領域が狭くなるため、重な
りはマスク幅の５０％未満とする必要がある。従って、
これらの重ね幅はあまり大きく出来ないが、サージの種
類に応じて適当な重ね幅に変更することが可能である。
第３Ｐ型導電領域１２と第４Ｐ型導電領域１３は、それ
ぞれ第１Ｎ型導電領域２を形成するための写真マスクの
パターンと第２Ｎ型導電領域３を形成するための写真マ
スクと兼用でもよいが、その場合余計な写真マスクは不
要であるという製造上の利点がある。図１に示される構
造においては、半導体基板１００の不純物濃度が小さい
が、サージ防護素子で重要となる順方向のブレークオー
バー電圧は、第１Ｎ型導電領域２と第３Ｐ型導電領域１
２で主に決定され、逆方向のブレークオーバー電圧は、
第２Ｎ型導電領域３と第４Ｐ型導電領域１３で主に決定
され、半導体基板１００の不純物濃度のばらつきに対し
て設計余裕度があるという製造上の利点がある。また、
半導体基板１００の不純物濃度のばらつきが大きいほ
ど、半導体基板の価格は安くなるので製造コストを低減
出来るという利点もある。第１Ｐ型導電領域４，５，
６、第３Ｐ型導電領域１２、第４Ｐ型導電領域１３、第
１Ｎ型導電領域２、第３Ｎ型導電領域３はエピタキシャ
ル成長で形成することも出来る。The first P-type conductive regions 4, 5, 6 and the second P-type conductive regions 7, 8, 9 are all formed in the same shape and in the same area in order to make the characteristics of the above-mentioned unit thyristor uniform. Preferably. Similarly, it is preferable that the third P-type conductive region 12 and the fourth P-type conductive region 13 are also formed in the same shape and in the same area. The overlapping width of the first P-type conductive regions 4, 5, 6 and the second P-type conductive regions 7, 8, 9 is, for example, a 2.6 mm chip, the mask width is 250 μm.
It has been confirmed that the surge withstand capability is improved, for example, by making 25 μm overlap with m. Since the region where the on-current flows becomes narrower as the overlap becomes larger, the overlap needs to be less than 50% of the mask width. Therefore,
Although the overlap width cannot be made very large, it is possible to change it to an appropriate overlap width according to the type of surge.
The third P-type conductive region 12 and the fourth P-type conductive region 13 may also serve as a photomask pattern for forming the first N-type conductive region 2 and a photomask for forming the second N-type conductive region 3, respectively. In that case, there is a manufacturing advantage that an extra photomask is unnecessary. In the structure shown in FIG. 1, although the impurity concentration of the semiconductor substrate 100 is low, the forward breakover voltage, which is important in the surge protection element, has a first N-type conductive region 2 and a third P-type conductive region 1.
2 is mainly determined, and the reverse breakover voltage is
It is mainly determined by the second N-type conductive region 3 and the fourth P-type conductive region 13, and has a manufacturing advantage that there is a design margin with respect to variations in the impurity concentration of the semiconductor substrate 100. Also,
The larger the variation in the impurity concentration of the semiconductor substrate 100, the lower the price of the semiconductor substrate, which is an advantage that the manufacturing cost can be reduced. First P-type conductive regions 4, 5,
6, the third P-type conductive region 12, the fourth P-type conductive region 13, the first N-type conductive region 2 and the third N-type conductive region 3 can also be formed by epitaxial growth.
【００２５】従って、本発明の第１の実施の形態におけ
る構造では、前記各単位サイリスタを構成するトランジ
スタのベース接地電流増幅率が大きくなって、各単位サ
イリスタが短時間に点弧し易くなって、素子破壊に繋が
る発熱を抑制出来、サージ耐量を向上させることが出来
るようになる。Therefore, in the structure according to the first embodiment of the present invention, the base ground current amplification factor of the transistor forming each unit thyristor is increased, and each unit thyristor is easily ignited in a short time. Therefore, it is possible to suppress heat generation that leads to element destruction and improve surge withstand capability.
【００２６】図１に示した構造の等価回路モデルは、図
７に示すものとなる。図７は、図１に示した双方向型二
端子サイリスタの等価回路図である。本発明の第１の実
施の形態に係る双方向型二端子サイリスタにおいては、
前記ベース接地電流増幅率α 0 １、α0 ２、α0 ３の値が
従来構造と比較して大きく、短時間に点弧しやすくなる
ため、サージ耐量を向上させることが出来る。The equivalent circuit model of the structure shown in FIG.
7 is shown. FIG. 7 shows the bidirectional type shown in FIG.
It is an equivalent circuit diagram of a terminal thyristor. First fruit of the present invention
In the bidirectional two-terminal thyristor according to the embodiment,
The base ground current amplification factor α 0 1, Α0 Two, Α0 ThreeThe value of
Larger than conventional structure and easier to fire in a short time
Therefore, the surge resistance can be improved.
【００２７】また、図１に示した構造では、製造上のば
らつきがあっても、第１Ｐ型導電領域４，５，６と第２
Ｐ型導電領域７，８，９が平面的に見て必ず重なるよう
に余裕をもってマスクパターンを設計することで、製造
上のばらつきがあっても、一部のサイリスタ領域におい
て、第１Ｐ型導電領域４，５，６と第２Ｐ型導電領域
７，８，９が平面的に見て必ず重なるようにしている。Further, in the structure shown in FIG. 1, the first P-type conductive regions 4, 5, 6 and the second P-type conductive regions are formed even if there are variations in manufacturing.
By designing the mask pattern with a margin so that the P-type conductive regions 7, 8 and 9 are always overlapped in plan view, even if there is a manufacturing variation, in some thyristor regions, the first P-type conductive region is formed. 4, 5, 6 and the second P-type conductive regions 7, 8, 9 are made to overlap each other when seen in a plan view.
【００２８】さらに、本発明の第２の実施の形態に係る
双方向型二端子サイリスタを図面に基づいて詳細に説明
する。図８は、本発明の第２の実施の形態に係る双方向
型二端子サイリスタを示す断面図である。図８におい
て、１は基板導電領域、２は第１Ｎ型導電領域、３は第
２Ｎ型導電領域、４，５，６は第１Ｐ型導電領域、７，
８，９は第２Ｐ型導電領域、１０は第１電極、１１は第
２電極、１８，１９，２０，２１は絶縁体、１２は第３
Ｐ型導電領域、１３は第４Ｐ型導電領域、５４はＰＮＰ
Ｎ構造、１００は半導体基板である。Further, a bidirectional two-terminal thyristor according to a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 8 is a sectional view showing a bidirectional two-terminal thyristor according to the second embodiment of the present invention. In FIG. 8, 1 is a substrate conductive region, 2 is a first N-type conductive region, 3 is a second N-type conductive region, 4, 5 and 6 are first P-type conductive regions, 7,
Reference numerals 8 and 9 are second P-type conductive regions, 10 is a first electrode, 11 is a second electrode, 18, 19, 20, and 21 are insulators, and 12 is a third electrode.
P-type conductive region, 13 is fourth P-type conductive region, and 54 is PNP
N structure, 100 is a semiconductor substrate.
【００２９】本発明の第２の実施の形態に係る双方向型
二端子サイリスタの構成は、前記した第１の実施の形態
に係る双方向型二端子サイリスタの構成と殆ど同じであ
るが、第３Ｐ型導電領域１２を、第１Ｎ型導電領域２の
第２Ｎ型導電領域３に相対向する面にのみ隣接するよう
に設け、第４Ｐ型導電領域１３を、第２Ｎ型導電領域３
の第１Ｎ型導電領域２に相対向する面にのみ隣接するよ
うに設ける。したがって、第３Ｐ型導電領域１２及び第
４Ｐ型導電領域１３は、第１Ｎ型導電領域２と第２Ｎ型
導電領域３との平面的に見て重なりあう領域内に設けら
れている。The structure of the bidirectional two-terminal thyristor according to the second embodiment of the present invention is almost the same as the structure of the bidirectional two-terminal thyristor according to the first embodiment described above. The 3P-type conductive region 12 is provided so as to be adjacent to only the surface of the first N-type conductive region 2 facing the second N-type conductive region 3, and the fourth P-type conductive region 13 is provided to the second N-type conductive region 3.
Is provided so as to be adjacent to only the surface facing the first N-type conductive region 2. Therefore, the third P-type conductive region 12 and the fourth P-type conductive region 13 are provided in a region where the first N-type conductive region 2 and the second N-type conductive region 3 overlap with each other in plan view.
【００３０】前記の双方向型二端子サイリスタでは、第
１Ｎ型導電領域２と第２Ｎ型導電領域３を不純物拡散で
形成したときに、ブレークオーバー電圧が、第１Ｎ型導
電領域２と第２Ｎ型導電領域３の端部の曲率半径の小さ
な領域で決定されず、曲率半径の大きい領域で決定され
ることになるため、前記第１の実施の形態と比較してブ
レークオ−バー電圧を大きくすることが容易に出来る。In the above-described bidirectional two-terminal thyristor, when the first N-type conductive region 2 and the second N-type conductive region 3 are formed by impurity diffusion, the breakover voltage is the first N-type conductive region 2 and the second N-type. The breakover voltage is set to be larger than that in the first embodiment because it is determined not in the region having a small radius of curvature at the end of the conductive region 3 but in the region having a large radius of curvature. Can be done easily.
【００３１】さらに、本発明の第３の実施の形態に係る
双方向型二端子サイリスタを図面に基づいて詳細に説明
する。図９は、本発明の第３の実施の形態に係る双方向
型二端子サイリスタを示す断面図である。図９におい
て、１は基板導電領域、２は第１Ｎ型導電領域、３は第
２Ｎ型導電領域、４，５，６は第１Ｐ型導電領域、７，
８，９は第２Ｐ型導電領域、１０は第１電極、１１は第
２電極、１２，１４，１６は第３Ｐ型導電領域、、１
３，１５，１７第４Ｐ型導電領域、５５はＰＮＰＮ構
造、１００は半導体基板である。Further, a bidirectional two-terminal thyristor according to a third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 9 is a sectional view showing a bidirectional two-terminal thyristor according to the third embodiment of the present invention. In FIG. 9, 1 is a substrate conductive region, 2 is a first N-type conductive region, 3 is a second N-type conductive region, 4, 5 and 6 are first P-type conductive regions, 7,
8 and 9 are second P-type conductive regions, 10 is a first electrode, 11 is a second electrode, 12, 14 and 16 are third P-type conductive regions, 1
3, 15 and 17 are fourth P-type conductive regions, 55 is a PNPN structure, and 100 is a semiconductor substrate.
【００３２】本発明の第３の実施の形態に係る双方向型
二端子サイリスタにおいては、前記第２の実施の形態に
係る双方向型二端子サイリスタにおける第３Ｐ型導電領
域１２を単位サイリスタ毎に分割して設けている。分割
して設けた第３Ｐ型導電領域１２，１４，１６は、第１
Ｐ型導電領域４，５，６との平面的に見て重なり合う領
域内に設ける。また、前記第２の実施の形態に係る双方
向型二端子サイリスタにおける第４Ｐ型導電領域１３も
単位サイリスタ毎に分割して設けている。分割して設け
た第４Ｐ型導電領域１３，１５，１７もまた、第２Ｐ型
導電領域７との平面的に見て重なり合う領域内に設け
る。In the bidirectional two-terminal thyristor according to the third embodiment of the present invention, the third P-type conductive region 12 in the bidirectional two-terminal thyristor according to the second embodiment is provided for each unit thyristor. It is provided separately. The third P-type conductive regions 12, 14, 16 provided separately are the first
It is provided in a region overlapping with the P-type conductive regions 4, 5 and 6 in plan view. Further, the fourth P-type conductive region 13 in the bidirectional two-terminal thyristor according to the second embodiment is also provided separately for each unit thyristor. The divided fourth P-type conductive regions 13, 15, 17 are also provided in a region overlapping with the second P-type conductive region 7 in plan view.
【００３３】前記の双方向型二端子サイリスタでは、前
記第１の実施の形態及び前記第２の実施の形態と比較し
て、第１Ｎ型導電領域２と第２Ｎ型導電領域３の間に形
成されるベースの抵抗率を高くすることと同じ効果が得
られるため、係るベース接地電流増幅率をより大きくす
ることが出来る。従って、本発明の第３の実施の形態に
おける構造では、各単位サイリスタがより短時間に点弧
し易くなって、素子破壊に繋がる発熱を抑制出来、サー
ジ耐量を向上させることが出来るようになる。なお、第
３Ｐ型導電領域１２，１４，１６、及び第４Ｐ型導電領
域１３，１５，１７は、上述した単位サイリスタの特性
を均一にするために、全て同一形状で同一面積に形成す
ることが好ましい。The bidirectional two-terminal thyristor is formed between the first N-type conductive region 2 and the second N-type conductive region 3 as compared with the first and second embodiments. Since the same effect as increasing the resistivity of the base to be obtained can be obtained, the base ground current amplification factor can be further increased. Therefore, in the structure according to the third embodiment of the present invention, each unit thyristor is more easily ignited in a shorter time, heat generation leading to element destruction can be suppressed, and surge withstand capability can be improved. . The third P-type conductive regions 12, 14, 16 and the fourth P-type conductive regions 13, 15, 17 may all be formed in the same shape and in the same area in order to make the characteristics of the unit thyristor uniform. preferable.
【００３４】くわえて、本発明の第４の実施の形態に係
る双方向型二端子サイリスタを図面に基づいて詳細に説
明する。図１０は、本発明の第４の実施の形態に係る双
方向型二端子サイリスタを示す断面図である。図１０に
おいて、１は基板導電領域、２は第１Ｎ型導電領域、３
は第２Ｎ型導電領域、４，５，６は第１Ｐ型導電領域、
７，８，９は第２Ｐ型導電領域、１０は第１電極、１１
は第２電極、１２，１４，１６は第３Ｐ型導電領域、１
３、１５，１７は第４Ｐ型導電領域、１８，１９，２
０，２１は絶縁体、２２，２３，２４、２５，２６は第
１孔状導電領域、２７，２８，２９，３０，３１は第２
孔状導電領域、３２，３３，３４は第１抵抗体、３５，
３６，３７は第２抵抗体、３８，３９，４０は第３Ｎ型
導電領域、４１，４２，４３は第４Ｎ型導電領域、５６
はＰＮＰＮ構造、１００は半導体基板である。In addition, a bidirectional two-terminal thyristor according to a fourth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 10 is a sectional view showing a bidirectional two-terminal thyristor according to the fourth embodiment of the present invention. In FIG. 10, 1 is a substrate conductive region, 2 is a first N-type conductive region, 3
Is a second N-type conductive region, 4, 5 and 6 are first P-type conductive regions,
7, 8 and 9 are second P-type conductive regions, 10 is a first electrode, 11
Is a second electrode, 12, 14, 16 are third P-type conductive regions, 1
3, 15, 17 are fourth P-type conductive regions, 18, 19, 2
0, 21 are insulators, 22, 23, 24, 25, 26 are first hole-shaped conductive regions, 27, 28, 29, 30, 31 are second
The hole-shaped conductive region, 32, 33, 34 are first resistors, 35,
36 and 37 are second resistors, 38, 39 and 40 are third N-type conductive regions, 41, 42 and 43 are fourth N-type conductive regions, and 56.
Is a PNPN structure, and 100 is a semiconductor substrate.
【００３５】前記の双方向型二端子サイリスタでは、半
導体基板１００と第１電極１０との間、及び半導体基板
１００と第２電極１１との間の接触抵抗がそれぞれ第３
Ｎ型導電領域３８，３９，４０及び第４Ｎ型導電領域４
１，４２，４３が存在することによって低減する。従っ
て、点弧動作に必要な電流が流れやすくなると共に、一
部の単位サイリスタに電流が集中することを防止しなが
ら点弧後のオン電圧を小さく出来る。ひいては、電気的
損失すなわち破壊に繋がる熱の発生を低減出来、サージ
耐量をより向上させることが出来る。In the bidirectional two-terminal thyristor, the contact resistance between the semiconductor substrate 100 and the first electrode 10 and between the semiconductor substrate 100 and the second electrode 11 is the third, respectively.
N-type conductive regions 38, 39, 40 and fourth N-type conductive region 4
It is reduced by the presence of 1, 42, 43. Therefore, the current required for the ignition operation can easily flow, and the ON voltage after ignition can be reduced while preventing the current from concentrating on a part of the unit thyristors. As a result, it is possible to reduce electrical loss, that is, generation of heat that leads to destruction, and it is possible to further improve surge withstand capability.
【００３６】また、前記の双方向型二端子サイリスタで
は、半導体基板１００と第１電極１０との間、及び半導
体基板１００と第２電極１１との間に追加された第１抵
抗体３２，３３，３４及び第２抵抗体３５，３６，３７
は、各々エミッタに直列に挿入されている。従って、本
発明の第１の実施の形態における構造では、一部の単位
サイリスタに電流が集中しても当該単位サイリスタのベ
ース電位が上昇して他の単位サイリスタが点弧し易くな
って一部の単位サイリスタに電流が集中しにくくなる。
これは、電流の分流を理想状態に近づけられることを意
味し、素子破壊に繋がる発熱を抑制出来、サージ耐量を
向上させることが出来るようになる。In the bidirectional two-terminal thyristor, the first resistors 32 and 33 added between the semiconductor substrate 100 and the first electrode 10 and between the semiconductor substrate 100 and the second electrode 11 are also included. , 34 and second resistors 35, 36, 37
Are inserted in series with the respective emitters. Therefore, in the structure according to the first embodiment of the present invention, even if the current is concentrated in a part of the unit thyristors, the base potential of the unit thyristor rises and other unit thyristors are easily ignited. It becomes difficult for current to concentrate on the unit thyristor.
This means that the shunt of the current can be brought close to the ideal state, the heat generation leading to the element destruction can be suppressed, and the surge withstand amount can be improved.
【００３７】また、前記の双方向型二端子サイリスタで
は、第２の導電領域及び第５の導電領域からなるエミッ
タを深く形成し、第１Ｐ型導電領域４，５，６及び第２
Ｐ型導電領域７，８，９内にそれぞれ第１孔状導電領域
２２，２３，２４、２５，２６及び第２孔状導電領域２
７，２８，２９，３０，３１を形成することにより、複
数形成されている各単位サイリスタの特性のばらつきを
小さくして、一部の単位サイリスタへの電流集中を防止
し易いようにしたので、各単位サイリスタの並列動作の
安定化を図り易い。第１孔状導電領域２２，２３，２
４、２５，２６と第２孔状導電領域２７，２８，２９，
３０，３１の配置や形状については、本件の発明者によ
る別の出願の明細書の記載に準ずる。In the bidirectional two-terminal thyristor, the emitter including the second conductive region and the fifth conductive region is deeply formed, and the first P-type conductive regions 4, 5, 6 and the second P-type conductive regions are formed.
In the P-type conductive regions 7, 8 and 9, the first hole-shaped conductive regions 22, 23, 24, 25 and 26 and the second hole-shaped conductive regions 2 are respectively formed.
By forming 7, 28, 29, 30, and 31, it is possible to reduce the variation in the characteristics of each of the plurality of unit thyristors and to easily prevent the concentration of current in some of the unit thyristors. It is easy to stabilize the parallel operation of each unit thyristor. First hole-shaped conductive regions 22, 23, 2
4, 25, 26 and the second hole-shaped conductive regions 27, 28, 29,
The arrangement and shape of 30, 31 are based on the description in the specification of another application by the inventor of the present application.
【００３８】第４の実施の形態に係る双方向型二端子サ
イリスタは、製造工程が複雑になって製造コストが上昇
することから、第１抵抗体３２，３３，３４及び第２抵
抗体３５，３６，３７を形成しない双方向型二端子サイ
リスタや、第３Ｎ型導電領域３８，３９，４０及び第４
Ｎ型導電領域４１，４２，４３を形成しない双方向型二
端子サイリスタを実施してもよい。また、第１の実施の
形態に係る双方向型二端子サイリスタや第２の実施の形
態に係る双方向型二端子サイリスタにおいて、第３の実
施の形態に係る二端子サイリスタにあるように第１抵抗
体３２，３３，３４及び第２抵抗体３５，３６，３７、
または、第３Ｎ型導電領域３８，３９，４０及び第４Ｎ
型導電領域４１，４２，４３を形成してもよい。また、
第１の実施の形態に係る双方向型二端子サイリスタや第
２の実施の形態に係る双方向型二端子サイリスタにおい
て、第１Ｐ型導電領域４，５，６及び第２Ｐ型導電領域
７，８，９からなるエミッタを深く形成し、第１Ｐ型導
電領域４，５，６及び第２Ｐ型導電領域７，８，９内に
それぞれ第１孔状導電領域２２，２３，２４、２５，２
６及び第２孔状導電領域２７，２８，２９，３０，３１
を形成してもよい。In the bidirectional two-terminal thyristor according to the fourth embodiment, since the manufacturing process is complicated and the manufacturing cost is increased, the first resistor 32, 33, 34 and the second resistor 35, Bidirectional two-terminal thyristor not forming 36, 37, third N-type conductive regions 38, 39, 40 and fourth
A bidirectional two-terminal thyristor which does not form the N-type conductive regions 41, 42 and 43 may be implemented. Further, in the bidirectional two-terminal thyristor according to the first embodiment and the bidirectional two-terminal thyristor according to the second embodiment, the first two-terminal thyristor according to the third embodiment Resistors 32, 33, 34 and second resistors 35, 36, 37,
Alternatively, the third N-type conductive regions 38, 39, 40 and the fourth N-type
The type conductive regions 41, 42, 43 may be formed. Also,
In the bidirectional two-terminal thyristor according to the first embodiment and the bidirectional two-terminal thyristor according to the second embodiment, first P-type conductive regions 4, 5, 6 and second P-type conductive regions 7, 8 are provided. , 9 are deeply formed, and the first hole-shaped conductive regions 22, 23, 24, 25, 2 are respectively formed in the first P-type conductive regions 4, 5, 6 and the second P-type conductive regions 7, 8, 9.
6 and second hole-shaped conductive regions 27, 28, 29, 30, 31
May be formed.
【００３９】[0039]
【発明の効果】このように本発明によれば、ブレークオ
ーバー電圧を変更せずに各単位サイリスタを構成するト
ランジスタのベース抵抗を大きくすることが出来、その
ためベース接地電流増幅率が高くなって、短時間に点弧
動作し易いようにしたので、サージ電流の分流による点
弧動作の遅れ改善出来、素子破壊に繋がる発熱を抑制
し、従来技術に係るサイリスタよりもサージ耐量を向上
させることが出来る。As described above, according to the present invention, it is possible to increase the base resistance of the transistor forming each unit thyristor without changing the breakover voltage, and thus the base ground current amplification factor becomes high. Since the ignition operation is made easier in a short time, the delay of the ignition operation due to the shunting of the surge current can be improved, the heat generation that leads to element destruction can be suppressed, and the surge withstand capability can be improved compared to the conventional thyristor. .
【図１】 本発明の第１の実施の形態に係る双方向型二
端子サイリスタを示す断面図である。FIG. 1 is a sectional view showing a bidirectional two-terminal thyristor according to a first embodiment of the present invention.
【図２】 従来技術に係る双方向型二端子サイリスタを
示す断面図である。FIG. 2 is a sectional view showing a bidirectional two-terminal thyristor according to a conventional technique.
【図３】 従来技術に係る双方向型二端子サイリスタの
順方向の電気的特性を示すグラフである。FIG. 3 is a graph showing forward electrical characteristics of a bidirectional two-terminal thyristor according to a conventional technique.
【図４】 従来技術に係る双方向型二端子サイリスタの
等価回路図である。FIG. 4 is an equivalent circuit diagram of a bidirectional two-terminal thyristor according to a conventional technique.
【図５】 本件の発明者らによる双方向型二端子サイリ
スタの概略を示す断面図である。FIG. 5 is a cross-sectional view showing an outline of a bidirectional two-terminal thyristor by the present inventors.
【図６】 図５に示した双方向型二端子サイリスタにお
ける単位サイリスタ構造の等価回路図である。6 is an equivalent circuit diagram of a unit thyristor structure in the bidirectional two-terminal thyristor shown in FIG.
【図７】 図１に示した双方向型二端子サイリスタの等
価回路図である。7 is an equivalent circuit diagram of the bidirectional two-terminal thyristor shown in FIG.
【図８】 本発明の第２の実施の形態に係る双方向型二
端子サイリスタを示す断面図である。FIG. 8 is a sectional view showing a bidirectional two-terminal thyristor according to a second embodiment of the present invention.
【図９】 本発明の第３の実施の形態に係る双方向型二
端子サイリスタを示す断面図である。FIG. 9 is a sectional view showing a bidirectional two-terminal thyristor according to a third embodiment of the present invention.
【図１０】 本発明の第４の実施の形態に係る双方向型
二端子サイリスタを示す断面図である。FIG. 10 is a sectional view showing a bidirectional two-terminal thyristor according to a fourth embodiment of the present invention.
１ 基板導電領域 ２ 第１Ｎ型導電領域 ３ 第２Ｎ型導電領域 ４ 第１Ｐ型導電領域 ５ 第１Ｐ型導電領域 ６ 第１Ｐ型導電領域 ７ 第２Ｐ型導電領域 ８ 第２Ｐ型導電領域 ９ 第２Ｐ型導電領域 １０ 第１電極 １１ 第２電極 １２ 第３Ｐ型導電領域 １３ 第４Ｐ型導電領域 １４ 第３Ｐ型導電領域 １５ 第４Ｐ型導電領域 １６ 第３Ｐ型導電領域 １７ 第４Ｐ型導電領域 １８ 絶縁体 １９ 絶縁体 ２０ 絶縁体 ２１ 絶縁体 ２２ 第１孔状導電領域 ２３ 第１孔状導電領域 ２４ 第１孔状導電領域 ２５ 第１孔状導電領域 ２６ 第１孔状導電領域 ２７ 第２孔状導電領域 ２８ 第２孔状導電領域 ２９ 第２孔状導電領域 ３０ 第２孔状導電領域 ３１ 第２孔状導電領域 ３２ 第１抵抗体 ３３ 第１抵抗体 ３４ 第１抵抗体 ３５ 第２抵抗体 ３６ 第２抵抗体 ３７ 第２抵抗体 ３８ 第３Ｎ型導電領域 ３９ 第３Ｎ型導電領域 ４０ 第３Ｎ型導電領域 ４１ 第４Ｎ型導電領域 ４２ 第４Ｎ型導電領域 ４３ 第４Ｎ型導電領域 ５１ ＰＮＰＮ構造 ５２ ＰＮＰＮ構造 ５３ ＰＮＰＮ構造 ５４ ＰＮＰＮ構造 ５５ ＰＮＰＮ構造 ５６ ＰＮＰＮ構造 １００ 半導体基板 1 Substrate conductive area 2 First N-type conductive region 3 Second N-type conductive region 4 First P-type conductive area 5 First P-type conductive region 6 First P-type conductive region 7 Second P-type conductive region 8 Second P-type conductive region 9 Second P-type conductive region 10 First electrode 11 Second electrode 12 Third P-type conductive region 13 Fourth P-type conductive region 14 Third P-type conductive region 15 Fourth P-type conductive region 16 Third P-type conductive region 17 Fourth P-type conductive region 18 Insulator 19 insulator 20 insulator 21 Insulator 22 First hole-shaped conductive region 23 First hole-shaped conductive region 24 First hole-shaped conductive region 25 First hole-shaped conductive region 26 First hole-shaped conductive region 27 Second hole-shaped conductive region 28 Second hole-shaped conductive region 29 Second hole-shaped conductive region 30 Second hole-shaped conductive region 31 second hole-shaped conductive region 32 1st resistor 33 First resistor 34 First resistor 35 Second resistor 36 Second resistor 37 Second resistor 38 Third N-type conductive region 39 Third N-type conductive region 40 Third N-type conductive region 41 Fourth N-type conductive region 42 Fourth N-type conductive region 43 Fourth N-type Conductive Region 51 PNPN structure 52 PNPN structure 53 PNPN structure 54 PNPN structure 55 PNPN structure 56 PNPN structure 100 semiconductor substrate
Claims (5)
記半導体基板とは反対型の第２導電型の第１の導電領域
と、 前記一方の面に露出させて形成すると共に前記第１の導
電領域内に配列してなるＮ個（Ｎ≧２）の第１導電型の
第２の導電領域と、 前記第１の導電領域に隣接して形成してなる第１導電型
の第３の導電領域と、 前記半導体基板の前記一方の面に背向する他方の面に露
出させて形成してなる第２導電型の第４の導電領域と、 前記他方の面に露出させて形成すると共に前記第４の導
電領域内に配列してなるＮ個の第１導電型の第５の導電
領域と、 前記第４の導電領域に隣接して形成してなる第１導電型
の第６の導電領域とを設け、 １番目の前記第２の導電領域は、平面的に見て２番目の
前記第２の導電領域に近い側の端部及びその近傍部分が
１番目の前記第５の導電領域と重なり合うように配置さ
れ、 Ｎ番目の前記第５の導電領域は、平面的に見てＮ−１番
目の前記第５の導電領域に近い側の端部及びその近傍部
分がＮ番目の前記第２の導電領域と重なり合うように配
置され、 １番目以外の前記第２の導電領域は、平面的に見てそれ
らの両端部及びそれらの近傍部分がＮ個の前記第５の導
電領域と重なり合うように配置され、Ｎ番目以外の前記
第５の導電領域は、平面的に見てそれらの両端部及びそ
れらの近傍部分がＮ個の前記第２の導電領域と重なり合
うように配置されてなることを特徴とする双方向型二端
子サイリスタ。1. A first-conductivity-type semiconductor substrate, a first-conductivity region of a second-conductivity-type opposite to the semiconductor substrate, the first-conductivity region being formed by being exposed on one surface of the semiconductor substrate. Adjacent to the first conductive region, N (N ≧ 2) second conductive regions of the first conductivity type, which are formed so as to be exposed on one surface and arranged in the first conductive region. A third conductive region of the first conductivity type formed by the above, and a fourth conductivity of the second conductivity type formed by being exposed on the other surface of the semiconductor substrate, which is opposite to the one surface. A region, N fifth conductive regions of the first conductivity type, which are formed so as to be exposed on the other surface and arranged in the fourth conductive region, and are adjacent to the fourth conductive region. And a sixth conductive region of the first conductivity type formed by: forming the first conductive region of the second conductive region; The end on the side closer to the second conductive region and the vicinity thereof are arranged so as to overlap the first fifth conductive region, and the Nth fifth conductive region is N in plan view. -1 is arranged so that the end portion on the side close to the fifth conductive region and the vicinity thereof overlap the N-th second conductive region, and the second conductive region other than the first is a flat surface. Are arranged so that their both end portions and their vicinity are overlapped with the N fifth conductive regions, and the fifth conductive regions other than the Nth are both ends of the fifth conductive region when viewed two-dimensionally. A bidirectional two-terminal thyristor, wherein the parts and their vicinity are arranged so as to overlap the N second conductive regions.
領域は、それぞれ前記半導体基板内に埋め込んで設けら
れることを特徴とする請求項１に記載の双方向型二端子
サイリスタ。2. The bidirectional two-terminal thyristor according to claim 1, wherein the third conductive region and the sixth conductive region are provided by being embedded in the semiconductor substrate, respectively.
領域とその周辺との境界面のうち少なくとも前記第４の
導電領域に相対向する部分に接して設けられ、 前記第６の導電領域は、前記第４の導電領域とその周辺
との境界面のうち少なくとも前記第１の導電領域に相対
向する部分に接して設けられることを特徴とする請求項
１または請求項２に記載の双方向型二端子サイリスタ。3. The third conductive region is provided in contact with at least a portion of the boundary surface between the first conductive region and the periphery thereof facing the fourth conductive region, and the sixth conductive region is provided. The conductive region is provided in contact with at least a portion of the boundary surface between the fourth conductive region and the periphery thereof facing the first conductive region. Bidirectional two-terminal thyristor.
領域は、Ｎ個ずつ設けられると共に、それぞれ平面的に
見て前記第２の導電領域及び前記第５の導電領域に重な
り合う範囲内に設けられることを特徴とする請求項２ま
たは請求項３に記載の双方向型二端子サイリスタ。4. The third conductive region and the sixth conductive region are provided in N number each and within a range overlapping with the second conductive region and the fifth conductive region when seen in a plan view, respectively. The bidirectional two-terminal thyristor according to claim 2 or 3, wherein the bidirectional two-terminal thyristor is provided.
導電領域とは、平面的に見て交互に且つ互いに接した状
態に配列されることを特徴とする請求項４に記載の双方
向型二端子サイリスタ。5. The N-th third conductive region and the sixth conductive region are arranged alternately and in contact with each other when seen in a plan view. Bidirectional two-terminal thyristor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001265787A JP5371165B2 (en) | 2001-09-03 | 2001-09-03 | Bidirectional two-terminal thyristor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001265787A JP5371165B2 (en) | 2001-09-03 | 2001-09-03 | Bidirectional two-terminal thyristor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003077932A true JP2003077932A (en) | 2003-03-14 |
| JP5371165B2 JP5371165B2 (en) | 2013-12-18 |
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ID=19092200
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|---|---|---|---|
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|---|---|---|---|---|
| JPS6471163A (en) * | 1987-06-09 | 1989-03-16 | Texas Instruments Inc | Semiconductor device for protecting electrical excessive stress |
| JPH07307459A (en) * | 1994-03-14 | 1995-11-21 | Fuji Electric Co Ltd | Double-sided semiconductor device |
| JPH088420A (en) * | 1994-06-20 | 1996-01-12 | Nippon Telegr & Teleph Corp <Ntt> | Surge protective element |
| JPH0945892A (en) * | 1995-07-26 | 1997-02-14 | Nippon Telegr & Teleph Corp <Ntt> | Surge-preventing device |
| JP2655575B2 (en) * | 1991-07-29 | 1997-09-24 | 日本電信電話株式会社 | Surge protection element |
-
2001
- 2001-09-03 JP JP2001265787A patent/JP5371165B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6471163A (en) * | 1987-06-09 | 1989-03-16 | Texas Instruments Inc | Semiconductor device for protecting electrical excessive stress |
| JP2655575B2 (en) * | 1991-07-29 | 1997-09-24 | 日本電信電話株式会社 | Surge protection element |
| JPH07307459A (en) * | 1994-03-14 | 1995-11-21 | Fuji Electric Co Ltd | Double-sided semiconductor device |
| JPH088420A (en) * | 1994-06-20 | 1996-01-12 | Nippon Telegr & Teleph Corp <Ntt> | Surge protective element |
| JPH0945892A (en) * | 1995-07-26 | 1997-02-14 | Nippon Telegr & Teleph Corp <Ntt> | Surge-preventing device |
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|---|---|
| JP5371165B2 (en) | 2013-12-18 |
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