JP2003070083A - Keyless entry system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a keyless entry system which can reduce the mean current consumption of an intermittent reception system. SOLUTION: This system has a transmitter 20, which modulates and transmits a binarized pulse signal including a start bit and a unique identification code as a user operates, a reception part (receiver) 12 which demodulates and receives the binarized pulse signal from the transmitter 20, and a control part 11 which decides the identification code received by the reception part 12 and a registered code stored in a storage part 14 and outputs an output signal for performing specific operation, that the user intends when both the codes match each other; the control part 11 places the reception part 12 in a power supply state where the binarized pulse signal can be received at specific time intervals. In this power supply state, the start bit is decided a plurality or number of times at specific time intervals, and when the start bit is decided, specific bit errors are allowed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a keyless entry system mounted on, for example, a four-wheel vehicle (hereinafter referred to as vehicle).

[0002]

2. Description of the Related Art For example, Japanese Unexamined Patent Publication No. 8-289372 discloses a wireless keyless entry system for vehicles that uses weak radio waves.

This is the case when a signal provided by a transmitter provided as a portable electronic key including an identification code by a user such as a driver is received by a receiver provided in a vehicle and judged to be normal. In the above, a desired part intended by the user is controlled by a controlled part such as an opening / closing operation of a vehicle door lock.

In such a keyless entry system, the power source of the receiver is a battery mounted on the vehicle. Therefore, in order to suppress the consumption of the battery when the vehicle is stopped, it is desirable to reduce the current consumption of the receiver. It is rare.

For example, in order to reduce the current consumption of the receiver while the vehicle is stopped, the power of the receiver is turned on for a predetermined short time t1, the presence or absence of a signal from the transmitter is confirmed, and the signal is received. The power is turned on for the time t2 (> t1) necessary for the operation to enter the reception mode, and after the time t1, the power is turned off for a predetermined time t3.
(> T1) is a standby mode in which no power is supplied, and after the time t3 has elapsed, the power is turned on again for the time t1 to check the presence / absence of a signal from the transmitter.

In the keyless entry system adopting the intermittent reception method, since the power is supplied to the receiver by repeating the power-on time t1 and the off-time t3 of the receiver, the average current consumption of the receiver is suppressed. Although there is an advantage, in order to further reduce the average current consumption, it is necessary to shorten the time t1 or extend the time t3. However, there is a certain amount of time required to reliably receive the so-called start bit, which represents the start portion of the signal included in the signal from the transmitter, and there is a limit to shortening it. However, ambient noise is picked up and it is determined that this is a start bit, the power-on time of the receiver is extended to t1 + t2, and eventually the average current consumption may increase. Further, if the time t3 is lengthened, the time until the signal including the start bit is detected becomes longer, and the responsiveness is impaired.

[0007]

Focusing on such a problem, it is intended to suppress the extension of the power-on time due to an erroneous determination as a start bit due to noise while determining the presence or absence of a start bit in a short time. For example, in Japanese Unexamined Patent Publication No. 10-155187, the receiver is in a receiving state in which it receives a start bit at every predetermined time, and if it is determined that the start bit in this receiving state is received, the entire signal can be received. A configuration that extends the reception state up to time is disclosed, and according to this, it is possible to determine the presence or absence of a start bit in a short time, minimize the extension of the reception time due to noise, and reduce the average current consumption of the receiver. It is shown that it can be reduced.

However, even with such a configuration, a minimum time for receiving the start bit (10 milliseconds is set to receive 4 bits as the start bit in the above embodiment) is required. The present invention has been made in view of this point, and an object of the present invention is to provide a keyless entry system having a receiver capable of reducing the average current consumption by further shortening the time.

[0009]

In order to solve the above-mentioned problems, the keyless entry system of the present invention comprises:
And a transmitter for modulating and transmitting a binarized pulse signal containing at least a start bit and a unique identification code by a user operation, and demodulating and receiving the binarized pulse signal from the transmitter. Output for determining the receiver to be operated and the identification code received by the receiver and the registration code stored in the storage unit, and performing the desired operation intended by the user when the two codes match. A control unit that outputs a signal, the control unit sets the receiver to a power supply state capable of receiving the binarized pulse signal at predetermined time intervals, and in this power supply state, the determination of the start bit is performed. Is divided into a plurality of times for each predetermined time, and a predetermined bit error is allowed at the time of this determination.

Further, according to a second aspect of the present invention, the control unit performs the determination of the start bit at predetermined time intervals for all the start bits received during that time.

Further, as described in claim 3, the controller is characterized in that the determination of the start bit is performed for a newly received start bit at every predetermined time.

Further, as described in claim 4, the control unit predetermines a total number of regular bits to be received at each of the predetermined times as a set value, and the allowable rate of error of the bit is set by the set value. It is characterized by being decided.

Further, according to a fifth aspect of the present invention, the control unit predetermines, as a set value, the number of consecutive regular bits to be received at each of the predetermined times, and based on the set value, the bit error tolerance rate is set. It is characterized by deciding.

Further, according to a sixth aspect of the present invention, the control unit predetermines a total number of regular bits to be received and the number of consecutive regular bits to be received at each predetermined time as preset values, and the error of the bits is determined by the preset values. It is characterized by deciding the allowable rate of.

Further, as described in claim 7, the set value is set in advance as a value that is changed every predetermined time.

Further, as described in claim 8, the set value is automatically variable according to the previous reception state.

Further, as described in claim 9, the control unit performs the retry process from a predetermined number of determinations among a plurality of determinations.

Further, as described in claim 10, the receiver is provided in a meter unit for performing various displays.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 relates to an embodiment of the present invention, and 10 is a meter unit which incorporates various electrical components and also serves as a receiver for receiving a signal including an identification code from a transmitter which will be described later. , 11 is a control unit including a microcomputer or the like for both meter processing and keyless processing, 12 is a receiving unit (receiver) for receiving a signal D from a portable transmitter 20 through an antenna 13, and 14 is the identification A storage unit composed of a storage element such as an EEPROM for storing codes and the like, 15
Is a drive unit that drives a drive unit 30 such as a door lock motor based on an instruction from the control unit 11, for example, an output signal for performing a predetermined operation, and 16 is a analog drive unit that displays traveling information such as traveling speed and engine speed. A first instrument (electrical unit) displayed by the pointer instruction, 17 is a second instrument (electrical unit) displayed by a multi-digit digital number or a design similar to this, for example, a 6-digit An odometer or section distance meter (trip meter) consisting of a day-shaped segment similar to a digital number is used.

Further, the meter unit 10 converts the voltage from the vehicle-mounted battery 40 into a predetermined level and controls the control unit 1.
1 or a power supply unit 18 for supplying to the receiving unit 12 is built-in or attached externally (in FIG. 1, the built-in type is shown),
An on / off switching unit 19 is provided for controlling the power supply from the power supply unit 18 between an on state (power supply state) and an off state (power cutoff state) by a predetermined method described later, and this on / off switching is performed. The switching control of the unit 19 is performed by a program preset in the control unit 11. The ON / OFF switching unit 19 controls the power supply to the receiving unit 12, and in the case of the ON state, the power is supplied. When the power is supplied from the unit 18, the reception unit 12 is set to a reception mode in which the signal can be received. In the off state, the power is cut off from the power supply unit 18 to receive the signal from the reception unit 12. By setting the impossible standby mode, the "intermittent reception system" in the receiving unit 12 is realized.

Each bit constituting the signal D which is the code information transmitted from the transmitter 20 is usually constituted by a binarized pulse signal, and is disclosed in, for example, the above-mentioned prior art Japanese Patent Laid-Open No. 10-155187. A pulse signal as shown in FIG. 4 (see paragraph number 0023 of the publication) is used. The data structure of the signal D includes a synchronization frame including a plurality of start bits as shown in FIG. 5 of the publication (see paragraph number 0024 of the publication) and an identification code stored in the receiver 10. It has an identification code having the same content as the collation code, and is composed of a data frame including various codes such as a vehicle type code and a manufacturer code. In the present embodiment, in order to facilitate comparison with the prior art, the same binarized pulse signal and data structure as in the above publication are used as the signal D in the following description.

In FIG. 2, a period T10 is a waiting time required for the receiving unit 12 to stabilize after the ON / OFF switching unit 19 supplies the receiving unit 12 with power from the power supply unit 18. During the period T20 to T22, the receiving unit 1 is operated after T10 has elapsed.
It is the time to start acceptance of the signal D in 2 and determine the presence / absence of a start bit in a plurality of times, and configure the reception mode time together with the period T10. The period T20 is a time required to surely receive a part of the start bit, for example, 2 bits, without receiving the entire start bit. Actually, since the signal D from the transmitter 20 is asynchronous, time for 3 bits is required. Similarly, the period T21 is the time required to reliably receive, for example, 4 bits. The period T22 is a time required to receive, for example, 8 bits. During the period T40, the on / off switching unit 1
9 is the time in which the power supply from the power supply unit 18 to the receiving unit 12 is cut off by 9, and is the time in the standby mode. In the periods T31 to T33, the start bit is continuously determined in the period T22, and the time for performing the retry process is variable. The number of ◯ × in FIG. 2 indicates the number of bits.

As described above, the power supply to the receiving unit 12 is performed in the ON state consisting of the period T10 + T2X + T3X and the period T4.
The off state of 0 is alternately repeated, and the synchronization frame including the start bit of the signal D is set to be longer than the total time of the period T10 + T2X + T3X + T40. The period T50 is the time for receiving the data frame.

Next, a permissible example of the total number of normal bits received (bit error) in the periods T20 to T22 will be described. In addition, ◯ indicates a received bit, and × indicates a non-received bit.

In the period T20, the judgment condition is that one or more regular bits are received.
For the bit or more and the period T22, the reception condition is to receive 7 bits or more.

As the judgment condition, it is possible to judge by a bit error tolerance rate. The allowable rate is
As shown by the following formula, when the number of bits received within a predetermined time T is n, this is the rate of bit errors in this number of bits n. Bit error tolerance = (n−m) / n n: Number of bits received within predetermined time T m: Number of regular bits received within predetermined time T

Therefore, the acceptable rate is 50% (((2-1) / 2) * 100) in the case where one or more regular bits are received as the determination condition in the period T20. The allowable rate when receiving at least 3 bits at T21 as a determination condition is 25% (((4-3) / 4)
* 100), and the acceptable rate is 12.5% when the condition for receiving is 7 bits or more in the period T22.
(((8-7) / 8) * 100).

In FIG. 2A, at the point A, the period T2
Since one regular bit could not be received at 0, period T
After shifting to 40, it is in the standby mode. At point B, one regular bit was received during period T20, so T
It has moved to 21. However, the regular bit is set to 3 in T21.
Since the bit could not be received, the process shifts to T40 and is in the standby mode. Similarly, at point C, since 7 normal bits could not be received at T22, the process proceeds to T40 and is in the standby mode.

Summarizing the judgment conditions of T20 to T30,
It looks like Figure 3.

In FIG. 2B, the regular bit is set to 7 in T22.
Since it was possible to receive bits, the process has moved to T31. As an example of the determination condition of T31, it is assumed that the regular bit is received eight times in succession. However, the retry is performed twice as an example of the allowable bit error. In this example, the regular bit is continuously received eight times without retrying at T31. At this point, the reception of the start bit is completed (judged to be a normal start), and the process proceeds to the reception of the data frame of T50.

In FIG. 2C, a retry is performed twice at T32, regular bits are received eight times in succession, and the process proceeds to T50.

In FIG. 2D, the retry is performed twice at T33, but the regular bit cannot be received eight times in succession, and T4 is used.
It has shifted to 0.

Next, another embodiment of the present invention will be described with reference to FIG.

In FIG. 4, periods T60, T60 ', T
60 ″ is the time during which four start bits can be received. However, the judgment conditions are different (permissible examples of bit errors). In FIG. 4A, T60 is the normal bit for two consecutive times. It must be received.D
At this point, this condition is not satisfied and the process moves to T40. T6
0'is a condition that the regular bit is continuous twice and the total number is 3 bits or more. At point E, this condition is not satisfied, and the process moves to T40. The condition for T60 ″ is that the total number of normal bits is 4 bits or more. This condition is not satisfied at point F, and T40 ″
Is moving to.

FIG. 4B shows that these conditions are satisfied and T5 is satisfied.
This is an example of shifting to 0.

FIG. 4C shows an example in which the judgment condition is relaxed based on the previous judgment result. Although the condition could not be satisfied at the judgment of the G point, the conditions of T60 and T60 'before that were satisfied. Therefore, at the point H, the determination condition is relaxed from T60 ″ to T60 ′. As a result, the process moves to T50.

Similarly, FIG. 4D is an example in which the determination condition is relaxed based on the previous determination result in the series of start bit determination processing. T60, T60 'before that at point J
Since there was no 1-bit error at T60 ″, it was relaxed from T60 ″ to T60 ′. As a result, the transition to T50 was made.

The keyless entry system having the above-mentioned structure includes a transmitter 20 that modulates and transmits a binarized pulse signal including at least a start bit and a unique identification code by a user operation, and the binary value from the transmitter 20. The receiving unit (receiver) 12 that demodulates and receives the pulsed pulse signal and the identification code received by the receiving unit 12 and the registration code stored in the storage unit 14 are determined. The control unit 11 outputs an output signal for performing a desired operation intended by the user, and the control unit 11 supplies power to the receiving unit 12 so that the binarized pulse signal can be received at predetermined time intervals. In this power supply state, the determination of the start bit is divided into a plurality of times at predetermined time intervals, and a predetermined bit error is allowed at the time of this determination. Et al., In which can be improved reduction and hit rate of the average current consumption.

The hit rate mentioned here is the rate at which the normal transmission signal D (start bit) is correctly received without being judged as random noise in the actual environment.

Further, the control unit 11 determines the start bit at predetermined time intervals for all the start bits received during that time. Therefore, for example, it is possible to gradually tighten the allowable rate of bit errors without changing the allowable number of bit errors for the entire start bit. As a result, it is possible to reliably remove the random noise while preventing the regular transmission signal D (start bit) from being mistakenly determined to be random noise.

Further, the control unit 11 determines the start bit with respect to a newly received start bit at every predetermined time. Therefore, it is possible to reliably remove the random noise while preventing the regular transmission signal D (start bit) from being mistakenly determined as the random noise.

Further, the control unit 11 can preset the total number of regular bits to be received at the predetermined time as a set value, and determine the allowable error rate of the bit by this set value. Therefore, the allowable number of bit errors can be easily set.

Further, the control unit 11 can previously set the number of consecutive regular bits to be received at each of the predetermined times as a set value, and can determine the permissible rate of error of the bit by this set value. Therefore, it is possible to easily set the bit error tolerance rate in consideration of the continuity of the regular bits.

Further, the control unit 11 can previously set the total number of regular bits to be received and the number of consecutive bits to be received at each predetermined time as preset values, and can determine the allowable rate of error of the bits by this preset value. . Therefore, it is possible to select a combination of the allowable number of bit errors and the allowable rate of bit errors in consideration of the continuity of regular bits, and more flexible setting can be performed.

Further, the set value may be set in advance as a value that is changed every predetermined time. Therefore, for example, it is possible to gradually tighten the determination criterion of the start bit. This makes it possible to reliably remove the random noise while preventing the regular transmission signal D (start bit) from being mistakenly determined to be random noise.

Further, the set value can be automatically changed according to the previous reception state. Therefore, in a bad environment such as under a strong electric field, it becomes possible to relax the bit error tolerance according to the previous reception state, and the normal transmission signal D
It is possible to prevent erroneous determination of (start bit) as random noise. Therefore, the hit rate can be improved.

Further, the control section 11 carries out the retry process from a predetermined number of times of the plurality of times of judgments. Therefore, it is possible to prevent erroneous determination as random noise when the possibility of the regular transmission signal D (start bit) is high. Therefore, the hit rate can be improved.

Further, the receiving section 12 is provided in a meter unit for performing various displays. Therefore, cost reduction can be achieved by sharing various parts (circuit, exterior, bracket, harness, etc.). In addition, the performance can be improved by arranging the keyless entry system in a place where the reception environment of radio waves is good.

[0049]

According to the present invention, the determination of the start bit is divided into a plurality of times, and the bit error is allowed at the time of the determination, so that the average current consumption is reduced and the hit rate (especially external noise such as under a strong electric field). Toughness and reliable reception under the limit of distance performance) can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a keyless entry system according to an embodiment of the present invention.

FIG. 2 is a time series diagram for explaining a reception state in the intermittent reception system of the above embodiment.

FIG. 3 is a diagram showing an example of determination of a reception state according to the same embodiment.

FIG. 4 is a time-series diagram illustrating a reception state in the intermittent reception system according to another embodiment of the present invention.

[Explanation of symbols]

10 meter unit 11 Control unit 12 Receiver (receiver) 13 antennas 14 Memory 15 Drive 16 First instruments 17 Second instruments 18 power supply 19 ON / OFF switching section 20 transmitter 30 drive unit 40 battery D signal

Claims (10)

[Claims] 1. A transmitter for modulating and transmitting a binarized pulse signal containing at least a start bit and a unique identification code by a user's operation, and a demodulator for receiving the binarized pulse signal from the transmitter. An output signal for determining the receiver and the identification code received by the receiver and the registration code stored in the storage unit, and performing the desired operation intended by the user when the two codes match. And a control unit for outputting the binarized pulse signal at predetermined time intervals, and the control unit determines the start bit in this power supply state. A keyless entry system characterized in that it is divided into a plurality of times at predetermined time intervals and a predetermined bit error is allowed at the time of this judgment. 2. The keyless entry system according to claim 1, wherein the control unit determines the start bit at predetermined time intervals for all the start bits received during the predetermined time. 3. The keyless entry system according to claim 1, wherein the control unit determines the start bit with respect to a newly received start bit at predetermined time intervals. 4. The control unit predetermines a total number of regular bits to be received at each predetermined time as a set value, and determines the error rate of the bit by the set value. The keyless entry system according to item 1. 5. The control unit determines in advance the number of consecutive regular bits to be received at each of the predetermined times as a set value, and determines the error rate of the bit by the set value. The keyless entry system according to claim 1. 6. The control unit predetermines the total number of regular bits to be received and the number of consecutive bits to be received at each of the predetermined times as preset values, and the allowable error rate of the bits is determined by the preset values. The keyless entry system according to claim 1, wherein the keyless entry system is a keyless entry system. 7. The keyless entry system according to claim 4, wherein the set value is set in advance as a value that is changed every predetermined time. 8. The keyless entry system according to claim 4, wherein the set value is automatically changed according to a previous reception state. 9. The keyless entry system according to claim 1, wherein the control unit performs the retry process from a predetermined number of determinations of a plurality of determinations. 10. The keyless entry system according to claim 1, wherein the receiver is provided in a meter unit that performs various displays.