JP3170407B2 - Method and apparatus for controlling energization of an amplitude modulation receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a device for controlling the energization of an amplitude modulation receiver suitably used for a so-called wireless door lock device of an automobile.

[0002]

2. Description of the Related Art The wireless door lock device has been widely used because of its high convenience and low cost. This device responds to a button operation of a transmitter carried by an operator without inserting a key into a key hole of a door or a trunk, and a receiver mounted on a vehicle responds to the button operation of the transmitter. This is a device that receives the transmitted signal and controls an actuator for locking / unlocking a door or a trunk.

Therefore, the characteristic of the receiver in such an apparatus is that the standby time for the signal from the transmitter is very long, and it is necessary to reliably receive the signal transmitted in response to a short button operation. That's what it means.

For this reason, a transmitter / receiver using a frequency-modulated wave is conventionally used in such an apparatus. This is because, by using the frequency modulated wave, the carrier can be detected by the squelch circuit on the receiver side during the period when the transmitter is transmitting the signal, so whether or not this carrier is transmitted Is intermittently received at a time period that does not give an uncomfortable feeling to the operator, and by switching to continuous reception when the carrier is detected,
This is because the burden on the battery can be reduced.

However, a transceiver using the frequency-modulated wave is expensive. Therefore, it is desired to use an amplitude-modulated wave that can realize the transceiver at a low cost for further spread.

Japanese Patent Application Laid-Open (JP-A) No. 61-33027 is an example of a prior art that can meet such a demand. In this prior art, intermittent reception is performed every predetermined period, and when a specific bit pattern such as bit synchronization or frame synchronization transmitted in the same pattern is detected from the signals transmitted from the transmitter each time, It is configured to switch to continuous reception.

[0007]

In the above-mentioned prior art,
Even in the standby state in which the intermittent reception is performed, it is necessary to energize the receiver for a period during which the specific bit pattern can be detected. Therefore, the period needs to be at least longer than the entire data period. If one transmission period of all data is, for example, 128 msec, the intermittent reception reduces the power consumption by 1/10. The receiving cycle requires about 1.3 sec. Therefore, the responsiveness is reduced, and even if the operator performs the button operation, the actuator does not operate for a while, which may give a sense of discomfort.

An object of the present invention is to provide a method and an apparatus for controlling power supply to an amplitude modulation receiver capable of reducing power consumption during standby without lowering responsiveness.

[0009]

According to the present invention, there is provided an amplitude modulation apparatus for receiving data transmitted from a transmitter and representing a unit data by sequentially modulating a plurality of levels and amplitude modulating a carrier. In the energization control method for the receiver, the power is intermittently energized to the receiver by a predetermined time for each predetermined cycle, and from a reception output of the receiver, a change in the modulation degree in at least the unit data is detected,
An energization control method for an amplitude modulation receiver characterized by continuously energizing a receiver during a period in which the switching of the modulation factor is detected.

According to another aspect of the present invention, there is provided a power supply to an amplitude modulation receiver which receives data transmitted from a transmitter, the plurality of levels being sequentially switched, and a carrier wave being amplitude-modulated, and receiving data representing unit data. In the control device, a switching element interposed between a power supply and the receiver for energizing / de-energizing the receiver, and the switching element intermittently transmitted to the receiver by a predetermined time at predetermined intervals. Control means for energizing the power, and detection means for detecting a change in the degree of modulation in at least the unit data from the reception output of the receiver, the control means,
An energization control device for an amplitude modulation receiver characterized by continuously energizing a switching element to a receiver during a period in which a change of a modulation degree is detected by a detection unit.

Further, the data of the present invention has a value of "0".
Alternatively, it is characterized in that the 1-bit unit data of “1” is split phase data represented by 2 bits of either “10” or “01” and either of the other.

Further, the predetermined time of the present invention is selected as a sum of a first time from the start of energization of the receiver to a rise of the power supply voltage of the receiver and a second time for at least 6-bit data. It is characterized by the following.

Still further, the detecting means of the present invention detects the presence or absence of the switching of the modulation degree a plurality of times within a 1-bit data period, and only when a predetermined number of detection results match in the 1-bit data period. The data is read, and when they do not match, the data immediately before the data is used as the data.

[0014]

According to the present invention, the data to be transmitted is, for example, 1-bit unit data of "0" or "1", for example, 2 bits of "10" or "01" and one of the other. The signal is converted into a plurality of levels such as split phase data each represented by a bit, a signal representing the level is mixed with a carrier as a modulation wave, and an amplitude-modulated signal is transmitted from the transmitter. That is, for example, when the data is the split phase data,
The data “010” is represented as “100110”, and the carrier is modulated with a modulation wave corresponding to this data. Therefore, even if the same data is continuous with the data to be transmitted, the modulation degree of the carrier of the signal to be actually transmitted changes at least in the third bit.

In the receiver for receiving the signal from the transmitter, the power from the power supply is controlled to be turned on / off by the control means via the switching element. The control means includes:
During standby reception of the receiver, power is supplied to the switching element intermittently for a predetermined period of time, for example, 1/10 of the period.

The reception output of the receiver is inputted to the detection means. The detection means detects at least the change of the modulation factor in the unit data from the reception output, and outputs the detection result to the control means. . The control unit determines that a signal is being transmitted from the transmitter during a period in which the switching of the modulation factor is detected by the detection unit,
The receiver is continuously energized by the switching element to perform continuous reception.

Therefore, the predetermined time for energization is independent of the type of data being received, that is, whether it is bit synchronization, frame synchronization, or the data itself, and the same data continues. However, since the modulation degree is switched in a very short time, even if the amplitude modulation wave is not a frequency modulation wave that can always detect the carrier,
Detection can be performed on the receiving side with good responsiveness, and the ratio of the energization time in the above cycle can be reduced to reduce power consumption.

As described above, even if there is no configuration for detecting a transmission signal such as a squelch circuit when a frequency modulation wave is used, intermittent reception is performed using a low-cost amplitude modulation wave receiver. be able to.

Preferably, the predetermined time is a first time from the start of energization of the receiver to a rise of the power supply voltage of the receiver, and a first time corresponding to at least 6-bit data when the data is the split phase data. Choose the sum of 2 hours. Therefore, even if the same data is continuously present in the split phase data and a detection omission occurs in a period of 3 bits in which the same data can be detected, the modulation degree is always switched within the remaining time of the second time. As a result, the switching can be reliably detected.

Preferably, the detecting means detects the presence / absence of the change of the modulation degree a plurality of times within one bit data period, and performs the predetermined number of times, for example, two times, in the one bit data period. The data is read only when the results match, and when the results do not match, it is determined that the data has not changed, and the data immediately before the data is used as data. Thereby, erroneous detection due to noise can be prevented.

[0021]

FIG. 1 is a block diagram showing an electrical configuration of a door lock control device 1 using an energization control method according to one embodiment of the present invention. The door lock control device 1 is generally realized by a transmitter 2 carried by a driver or a passenger, a receiver 3 mounted on a vehicle, an electromagnetic solenoid, a motor, and the like. An actuator 4 for locking / unlocking is provided.

The transmitter 2 includes a processing circuit 11 realized by a microcomputer or the like, a memory 12 realized by a read-only memory or the like, a signal conversion circuit 13 for performing a signal conversion operation described later, and a transmission circuit 14. , Antenna 1
5, a push button 16, and a battery 17. When the push button 16 is operated, the power from the battery 17 is supplied to the processing circuit 11, the signal conversion circuit 13, and the transmission circuit 14.
Supplied to

As a result, the processing circuit 11
The data corresponding to the identification code of the own vehicle is read out from the device, and the data is used as a data body D4 as shown in FIG. 2 by using an idle bit D1, a bit synchronization D2, a frame synchronization D3, and a check bit D5. The data D is created and given to the signal conversion circuit 13.

The signal conversion circuit 13 converts 1-bit data “1” or “0”, which is a unit bit of the data D, into 2 bits.
The bit data is converted into split phase format data represented by “01” or “10”, for example, 1
The data is input to the transmission circuit 14 so that the transmission speed is 1 msec per bit. The transmission circuit 14 receives the input data D
Is used as a modulation wave, a carrier having a predetermined frequency is amplitude-modulated, and transmitted from the antenna 15.

The receiver 3 comprises a receiving circuit 21 and a control circuit 22. The control circuit 22 includes a signal conversion circuit 25, a processing circuit 26 implemented by a microcomputer or the like, a memory 27 implemented by the read-only memory or the like, a drive circuit 28, and a switching element 29. ing.

As will be described later, the control circuit 22 intermittently or continuously supplies power from the battery 23 to the receiving circuit 21, and receives a signal from the transmitter 2 via the antenna 24. The received signal is provided to a signal conversion circuit 25, which performs a signal conversion reverse to that of the signal conversion circuit 13, and converts the input data in the split phase format into the data shown in FIG. The data is converted into normal data and output to a processing circuit 26 realized by a microcomputer or the like.

The processing circuit 26 includes an identification code represented by the data body D4 of the received data D and the memory 27.
It is determined whether or not the identification code of the own vehicle stored in the driver 4 matches with the identification code of the own vehicle.
To perform a locking or unlocking operation.

The switching element 2 is connected between the signal conversion circuit 25 and the reception circuit 21 and the battery 23.
9 are interposed. The switching element 29 has an emitter connected to the battery 23 and a collector connected to the reception circuit 21 and the signal conversion circuit 25. The base is connected to the battery 23 via a pull-up resistor 30 and to the processing circuit 26 via a resistor 31. When the processing circuit 26 should supply power to the reception circuit 21 and the signal conversion circuit 25,
The low-level output is conducted to the switching element 29, thereby conducting the switching element 29. When the current is not supplied, a high-level output is derived to the switching element 29, thereby turning off the switching element 29.

FIG. 3 is a timing chart for explaining the intermittent reception operation by the processing circuit 26. The processing circuit 26 controls the actuator 4 and the like in FIG.
As shown in (1), the control is performed at a predetermined control cycle T1, for example, every 25 msec, and the intermittent reception operation is also performed based on this control cycle T1.

Each time the control cycle T1 is reached, the control cycle shown in FIG.
As shown by, the counter sequentially performs a counting operation from "0" to "5". As shown by time t1, t3, t5,..., At the timing when the count value C1 becomes “5”, the intermittent reception flag FON is set to “1” as shown in FIG. As described above, the intermittent reception flag FON is reset to "0" at the timings indicated by the times t2, t4,... After the energization period T4 has elapsed.

Therefore, during the period when data D from the transmitter 3 is not received, the intermittent period T3, that is, 25 × 6
= 150 msec, the intermittent reception flag FON is set to "1" only during the energizing period T4 within the control cycle T1, for example, a period of 18 msec, and the flag FON is reset to "0" during the remaining period T2, that is, 132 msec. Is done. As a result, the power consumption per the intermittent cycle T3 is reduced to about 1/8.

During the control cycle T1, the time t
6, the data D from the transmitter 2 is received by the receiving circuit 21.
Is received, the count value C1 is reset to "0", whereby the intermittent reception flag FON is reset to "0", and the reception flag FRX is set to "1" as shown in FIG. Is set to During the period in which the reception of the data D is detected, the intermittent reception flag F
RX remains set to "1", and is reset to "0" when a predetermined time T5 elapses after the reception is stopped, as described later, and the counter restarts the count operation of the count value C1.

The processing circuit 26 controls the intermittent reception flag FO
During the period in which N or the reception flag FRX is set to “1”, as shown in FIG. 3 (5), the switching element 29 is turned on and the power from the battery 23 is supplied to the signal conversion circuit 25 and the reception circuit 21. Supply. Thus, during the period in which the data D is not received, about 1 / intermittent period T3
The receiving operation is performed for a time period of 8 and when the data D is received, the continuous receiving operation is performed.

FIGS. 4 and 5 are timing charts for explaining an operation for determining whether or not data D has been received. FIG. 4 shows an operation when data D is not received, and FIG. Indicates the operation when received. As shown in FIGS. 4 (2) and 5 (2), while the intermittent reception flag FON is set to “1”, FIG.
As shown in (1) and FIG. 5 (1), reception determination is performed as follows by a timer interruption every predetermined calculation period T10, for example, 384 μsec.

When the intermittent reception flag FON is set to "1" and energization of the reception circuit 21 and the signal conversion circuit 25 is started, as shown in FIGS. 4 (3) and 5 (3). Output once falls to a low level at time t11. This is due to circuit elements such as capacitors in the receiving circuit 21, and thereafter,
After a predetermined time T11, for example, about 12 msec, its output rises to a high level as shown at time t12. The power supply of the signal conversion circuit 25 is turned on sufficiently before the time t12.

As a result, FIGS. 4 (4) and 5
As shown in (4), at the next operation timing t13 after the time t12, the flag F indicating that the power has been turned on is displayed.
PW is set to "1". At this time, the count value C20 of the counter for preventing erroneous determination as described later
Is reset to "0" as shown in FIGS. 4 (5) and 5 (5), and is counted as shown in FIGS. 4 (6) and 5 (6) for a determination time T12 described later. The operation starts, and the count value C12 increases.

When the data D is not received as shown in FIG. 4, the count value C12 increases as shown in FIG. 4 (6), and the count value C12 is determined as shown at time t14. At time T12, the count value C12 is reset, and the flag FPW is also reset to "0" as shown in FIG. 4 (4), thus ending the determination operation.

On the other hand, as shown in FIG. 5, at time t12, the output of the receiving circuit 21 once rises to a high level as shown in FIG. 5 (3), and then data is received at time t15. When the signal level falls to the low level, the count operation of the count value C20 is started at time t16 of the operation timing immediately after that, and during the period when the low level output is derived from the receiving circuit 21, the count value C20 is calculated by the operation value It is added every cycle T10. When the count value C20 reaches a predetermined value, for example, 2 in this way, it is determined that the data D has been received at the time t17, and the count operation of the count value C12 is stopped as shown in FIG.
The flag FPW shown in FIG. 5D is reset to “0”. At this time, the intermittent reception flag FON is reset to "0" as shown in FIG. 5B, but the reception flag FRX is set to "1" instead of the reception operation as described above. Is continued, the interrupt calculation operation for each cycle T10 is continued.

Here, the transmission period T15 per bit of the data D is 1 msec. Therefore, after the output of the receiving circuit 21 falls at time t15, the output rises again at time t18 at least 2 msec later. In addition, the judgment time T1 is set in a period of at least 3 bits from the previous judgment timing in the calculation cycle T10.
Even if 2 is set, such data D can be received. Therefore, in one embodiment of the present invention, the determination time T12 is set to 6 msec in consideration of occurrence of a reception error.

The count value C20 is used for performing a plurality of determinations at each operation cycle T10 after the falling of the output of the receiving circuit 21 is detected in the unit bit transmission period T15. Time t17 when the operation cycle T10 has elapsed from time t16 when the fall was detected
It is determined that the data D has been received only when the result of the determination matches the determination result performed again. Thus, erroneous determination due to noise or the like can be prevented.

FIG. 6 is a flowchart for explaining the intermittent reception operation shown in FIG. In step s1, it is determined whether or not the data D has been received. If not, in step s20, after the permission flag FOK for permitting the driving of the actuator as described above is reset to "0", Move to step s2 for reception. In step s2, it is determined whether or not the control timing has come for each predetermined control cycle T1 shown in FIG. 3A. If not, the process returns to step s1. If the control timing comes, the process goes to step s3. In step s3, it is again determined whether or not data D has been received. If not, the process proceeds to step s4 for an intermittent reception operation.

In step s4, the count value C1 is added and updated as shown in FIG. 3 (2). In step s5, it is determined whether or not the count value C1 has reached the value 5, that is, whether or not the reception timing indicated by the times t1, t3, and t5 has been reached. After the intermittent reception flag FON shown in 3) is set to "1" and the count value C12 is reset to "0" in step s7, the process returns to step s1.

In step s5, the count value C
If 1 is not 5, the process proceeds to step s9, where it is determined whether or not the count value C1 has reached 6. If not, it is determined that the period T2 has the count value C1 of "0" to "4". The process returns to step s1, and if so, that is, if it is the control end timing indicated by the times t2 and t4, the process proceeds to step s10. In step s10, the count value C1 is reset to "0". Further, in step s11, the intermittent reception flag FON is reset to "0". Then, in step s12, the switching element 29 is shut off and the power supply to the receiving circuit 21 is stopped. Stopped.

In this manner, the power can be supplied to the receiving circuit 21 for the power supply period T4 within the control period T1 per predetermined intermittent period T3.

When the data D is received during the control period T1, the process proceeds from the step s1 to s21, where the bit synchronization D2 is searched from the data D, and the bit synchronization D2
If is not detected, the process proceeds to step s20. If detected, the process proceeds to step s22. In step s22, the count value C30 of the timer for determining that the transmission of the data D has been stopped is “0” as described later.
Is reset to In step s23, the frame synchronization D3 following the bit synchronization D2 is searched. If the frame synchronization D3 is not detected, the process proceeds to step s20. If the frame synchronization D3 is detected, the process proceeds to step s24.

In step s24, the data body D4 is searched. When the data body D4 is detected, the process proceeds to step s25, where the data body D4 is further collated with the identification code of the own vehicle. When the data body D4 matches, the permission flag FOK is set in step s26. After being set to "1", the process proceeds to step s2. When the data body D4 is not detected in step s24, and when the identification code in the data body does not match the identification code of the own vehicle in step s25, the process directly proceeds to step s20.

When the process proceeds from step s20 or s26 to step s2, the process further proceeds from step s3 to step s31. In step s31, the count value C30 is added and updated. In step s32, it is determined whether or not the count value C30 is equal to or longer than the predetermined time T5, for example, a value T30 corresponding to 250 msec. The process returns to s1, and if so, that is, at the timing of the time t7, the process proceeds to step s33. Since the data length of the data D is 128 msec, the time T5 is selected to be, for example, 250 msec, which is almost twice as long.

In step s33, the count value C1 is reset to "0". In step s34, the reception flag FRX is reset to "0".
After the switching element 29 is cut off at 5 and the power supply to the receiving circuit 21 is stopped, the process returns to step s1. After the transmission of the data D is stopped, the predetermined time T5
When the time elapses, the continuous reception operation is stopped.

FIG. 7 is a flowchart for explaining the operation of determining whether or not the data D shown in FIGS. 4 and 5 has been received. At step q1, it is determined whether or not it is within the energizing period T4 in which the intermittent reception flag FON is "1". If not, the process proceeds to step q2. In step q2, it is determined whether or not the data D has been received. If the data D is being received, data input processing such as identification of the data D received in step q3 is performed, and then the process proceeds to step q4. Move directly to step q4. In step q4, after other processing such as the control operation of the actuator 4 is performed, the process returns to the main routine shown in FIG.

In the step q1, the energizing period T
When it is within 4, the process proceeds to step q11, where the switching element 29 is turned on, the receiving circuit 21 is turned on, and the reception of the data D is determined. That is, it is determined in step q12 whether or not the output from the receiving circuit 21 has risen to a high level. If not, the process proceeds to step q13 to determine whether or not the flag FPW is set to "1". Otherwise, that is, during the time t11 to t13, the process directly proceeds to step q4.

At step q12, the receiving circuit 21
When the output is at a high level, the process proceeds to step q14, where the flag FPW is set to "1". After the count value C20 is reset to "0" in step q15, the process proceeds to step q16. In step q16, the count operation of the count value C12 is performed, and in step q17, the count value C12 is set to the energization time T12.
It is determined whether or not a time corresponding to step q has been reached.
4 and the energization is continued, and if it has elapsed, it is determined that the data D has not been detected within the energization time T12, and the process proceeds to step q18 at the time t14 as shown in FIG. . At step q18, the power supply to the receiving circuit 21 is stopped. At step q19, the flag FON is reset to "0". At step q20, the flag FPW is reset to "0". Then, the process proceeds to step q4.

On the other hand, when the output from the receiving circuit 21 once rises as shown at the time t13 and falls again as shown at the time t15, the steps q12 to q13 are performed at the timing of the time t16. Thereafter, the flow shifts to step q21. In step q21, the count value C2
0 is added and updated. At step q22, it is determined whether or not the count value C20 has become 2 or more as shown in FIG. 5 (5). It is determined that there is suspicion, and the process proceeds to step q16 to continue the determination operation. If so, that is, it is determined that the data D has been received at the timing of the time t17, and the process proceeds to step q23.

At step q23, the reception flag FRX is set to "1" as shown at the time t6. Instead, at step q24, the intermittent reception flag FON is reset to "0". Further, at step q25, the flag FPW is reset to "0", and at step q26, the count value C1 is reset to 0, and then the process proceeds to step q4.

As described above, in the door lock control device 1 according to the present invention, since the data D to be transmitted is transmitted from the transmitter 2 as split phase data, the output level from the receiving circuit 21 changes at least every two bits. Even if a low-cost amplitude modulation receiver 3 that does not require a special configuration for detecting a transmission signal such as a squelch circuit when using a frequency-modulated wave is used, the intermittent period can be maintained without impairing the response. Power consumption can be reduced by shortening the energization period T4 in T3.

The energization time T12 is a time period during which the same data can be detected continuously within the remaining time even if the detection omission occurs in a period of 3 bits in which the same data can be detected. , The switching of the modulation factor can be reliably detected. Furthermore, the level is determined every period T10 within the transmission period T15 of 1-bit data, and the presence or absence of the modulation degree switching is detected a plurality of times within the 1-bit data period T15. Since it is determined that only data has been received, the determination accuracy can be improved.

In the above-described embodiment, the data D is transmitted in the form of split phase data. However, as another embodiment of the present invention, even if the same data is continuously transmitted, the data D is transmitted every predetermined number of data. Other data formats with inverted levels may be used.

The present invention is not limited to the door lock control device, but can be suitably applied to other applications in which the standby time until the data D is transmitted is long and responsiveness is required.

[0058]

As described above, according to the present invention, the data transmitted from the transmitter is represented by sequentially switching a plurality of levels in the unit data. No matter what part of the data, such as the data itself, and even if the same data is continuous, the modulation degree of the signal to be transmitted changes at least every two bits of the data to be transmitted. Even if the receiver is energized only for a very short time, it is possible to detect such a signal from the transmitter and switch to continuous reception.

Therefore, even if a low-cost receiver for an amplitude-modulated wave that does not require a configuration for detecting a transmission signal such as a squelch circuit when a frequency-modulated wave is used is used, good responsiveness can be obtained. In addition, the power consumption can be reduced by reducing the ratio of the energizing time in the intermittent cycle.

Preferably, the predetermined time is a first time from the start of energization of the receiver to the rise of the power supply voltage of the receiver, and a second time corresponding to at least 6-bit data of the split phase data. Since the same data is selected as the sum of two hours, even if the same data continues in the split phase data and a detection omission occurs in a period of three bits in which the same data can be detected, the same data remains within the remaining time of the second time. Since the switching of the modulation degree always occurs, the switching can be reliably detected.

Preferably, the detecting means detects the presence / absence of the modulation degree switching a plurality of times within a 1-bit data period, and outputs the data only when a predetermined number of detection results match. Since reading is performed, erroneous detection due to noise can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a door lock control device 1 using an energization control method according to one embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of data D transmitted from a transmitter 2.

FIG. 3 is a timing chart for explaining an intermittent reception operation according to an embodiment of the present invention.

FIG. 4 is a timing chart for explaining an operation of determining whether or not the data D has been received;

FIG. 5 is a timing chart for explaining an operation of determining whether or not the data D has been received;

FIG. 6 is a flowchart of the intermittent reception operation shown in FIG. 3;

FIG. 7 is a flowchart for explaining the judgment operation shown in FIGS. 4 and 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Door lock control device 2 Transmitter 3 Receiver 4 Actuator 11, 26 Processing circuit 12, 27 Memory 13, 25 Signal conversion circuit 14 Transmission circuit 21 Receiving circuit 22 Control circuit 23 Battery 29 Switching element

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04B 1/16 B60R 25/00 E05B 49/00 H04Q 9/00 301

Claims (8)

(57) [Claims] 1. A method for controlling power supply to an amplitude-modulated receiver that receives data transmitted from a transmitter, the plurality of levels being sequentially switched, and a carrier wave being amplitude-modulated to represent unit data. Energizing the receiver intermittently for a predetermined period of time at a predetermined cycle, detecting a change in the modulation factor in at least the unit data from the reception output of the receiver, and detecting the change in the modulation factor. A power supply control method for the amplitude modulation receiver, wherein the power supply is continuously supplied to the receiver during the period. 2. The data is one of “0” or “1”.
2. The power supply to the amplitude modulation receiver according to claim 1, wherein the bit unit data is split phase data represented by two bits of either "10" or "01" and the other. Control method. 3. The method according to claim 1, wherein the predetermined time is selected to be a sum of a first time from when power is supplied to the receiver to when a power supply voltage of the receiver rises and a second time for at least 6-bit data. 3. The method for controlling power distribution to an amplitude modulation receiver according to claim 2, wherein 4. A method for detecting whether the modulation degree has been switched a plurality of times within a one-bit data period, reading the data only when a predetermined number of detection results match in the one-bit data period, and 3. The method according to claim 2, wherein data immediately before the data is used as data. 5. An energization control device for an amplitude modulation receiver, which receives data transmitted from a transmitter, a plurality of levels being sequentially switched, and a carrier wave being amplitude-modulated to represent unit data. A switching element interposed between a power supply and the receiver, for energizing / de-energizing the receiver; and intermittently supplying power to the switching element for a predetermined period of time at a predetermined period. Control means for energizing; and detecting means for detecting at least a change in the modulation factor in the unit data from a reception output of the receiver, wherein the control means detects the change in the modulation factor by the detection means. An energization control device for an amplitude modulation receiver, wherein the energization device continuously energizes a switching element during a period. 6. The data is one of “0” or “1”.
6. The power supply to the amplitude modulation receiver according to claim 5, wherein the bit unit data is split phase data represented by two bits of either "10" or "01" and the other. Control device. 7. The predetermined time may be selected as a sum of a first time from the start of power supply to the receiver to a rise of a power supply voltage of the receiver and a second time for at least 6-bit data. 7. The control apparatus according to claim 6, wherein the power supply to the amplitude modulation receiver is controlled. 8. The detecting means detects whether or not the modulation factor has been switched a plurality of times within one bit data period.
7. The power supply to the amplitude modulation receiver according to claim 6, wherein the data is read only when a predetermined number of detection results match in the bit data period, and when the detection results do not match, the data immediately before the data is used as data. Control device.