JP2003069344A - Frequency multiplication circuit and high frequency communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency multiplication circuit with a simple configuration that can enhance a higher order (particularly the third or the higher harmonic) frequency conversion efficiency and to provide a high frequency communication device employing the frequency multiplication circuit. SOLUTION: The frequency multiplication circuit, where a semiconductor element 3 with nonlinear characteristics receiving an input signal with a frequency f1, outputs signals with a frequency f3 three times the frequency f1, is provided with a feedback circuit 9 that positively feeds back a signal with a frequency f2 twice the frequency f1 of the input signal among harmonic components outputted from the nonlinear element 3 to the input terminal of the nonlinear element 3. A feedback circuit 9 is provided with a band pass filter circuit 10 that makes only the signal with the frequency f2 pass through so as to positively feed back only signals with the frequency f2 being a second harmonic due to secondary distortion of the semiconductor element 3 so that a third harmonic is generated via the semiconductor element 3 by the fundamental wave with the frequency f1 and the second harmonic. Thus, the frequency is converted by the secondary distortion component with a high conversion efficiency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplying circuit and a high frequency communication device, and more particularly to a frequency multiplying circuit and a high frequency communication device which can obtain high frequency conversion efficiency even in a high order multiplying operation of 3 times or more.

[0002]

2. Description of the Related Art A frequency multiplier is a frequency fn (= f) that is an integer n times the frequency f1 of an input electric signal.
A circuit that outputs a 1 × n) signal. However,
The integer n is n ≧ 2, and when n = 2, a doubler, n
When = 3, it is called a tripler. The frequency multiplier circuit is
Frequency conversion is performed using a semiconductor element having a non-linear characteristic, and as a semiconductor element having a non-linear characteristic, a three-terminal element having a gain has a higher frequency conversion efficiency than a two-terminal element such as a diode. Three-terminal devices such as transistors and FETs are often used. Here, the frequency conversion efficiency is the ratio of the power of the output signal of the frequency fn to the power of the input signal of the frequency f1,
It is an important index for judging the quality of the performance of the frequency multiplication circuit.

FIG. 10 shows a conventional frequency multiplier circuit 2
The block diagram of the multiplier is shown, which doubles the frequency conversion. The technology of such a doubler is disclosed in Japanese Patent Application Laid-Open No. 10-93349 and "Monolithic Microwave Integrated Circuit (MMIC)" (p125-p.25).
p127).

In FIG. 10, 1 is an input signal (frequency f
1) is input terminal, 2 is an output signal (frequency f2 =
f1 × 2) is output terminal, 3 is a semiconductor element which is a 3-terminal active element such as FET, 4 is a matching circuit for the input signal (frequency f1), 32 is a matching circuit for the output signal (frequency f2) Is. 31 is an input signal arranged between the semiconductor element 3 and the matching circuit 32.
It is a trap circuit for (frequency f1), and is designed to selectively totally reflect a signal of frequency f1 by an open stub or an LC resonance circuit. The specific design method of the trap circuit 31 is described in the above-mentioned document (Japanese Patent Laid-Open No. 10-9).
3349 gazette and the Institute of Electronics, Information and Communication Engineers "Monolithic Microwave Integrated Circuit (MMIC)"). Although the transmission line for phase adjustment is omitted in FIG. 10, it is disclosed in JP-A-2000-15 immediately before the trap circuit 31.
As discussed in Japanese Patent No. 6611, a transmission line for phase adjustment is usually provided.

The doubler shown in FIG. 10 has a circuit configuration close to that of a linear amplifier, but the harmonics are strongly generated by strengthening the non-linear characteristic by using some of the following. Non-linear distortion is generated by adjusting the bias point and operating a class C amplifier, for example. By increasing the power of the input signal, the output is deliberately saturated to cause non-linear distortion. By confining the fundamental wave component (frequency f1) between the trap circuit 31 and the semiconductor element 3 that is an active element, saturation occurs at the output end of the semiconductor element 3 and thus nonlinear distortion is generated.

As described above, various harmonics are generated due to the non-linear distortion in the doubler, but unnecessary harmonic components are suppressed by the trap circuit 31 on the output side, the matching circuit 32, etc. Efficiently extracting only the higher harmonic component, and this doubler extracts the second harmonic.

In the circuit configuration shown in FIG. 10, a tripler is obtained by taking out not the second harmonic but the third harmonic. However, in a high-order multiplier of 3 times or more,
In order to suppress unnecessary harmonic components and extract only necessary harmonic components, it is usual to use a structure more complicated than that shown in FIG.

Further, as another conventional frequency multiplying circuit, there has been disclosed 3 in Japanese Patent Laid-Open No. 2000-156611.
There is a multiplier. FIG. 11 shows a block diagram of the tripler, which has the same configuration as the doubler of FIG. 10 except for the trap circuit and the matching circuit on the output side. In FIG. 11, 8 is a matching circuit for the output signal (frequency f3), and 33 is a trap circuit for the fundamental wave (frequency f1) and the second harmonic (frequency f2). The basic operating principle of such a tripler is exactly the same as that of the doubler of FIG.

Further, the operation principle is the same even in the case of a higher-order multiplier of 4 or more, and the number and complexity of traps for suppressing unnecessary or higher harmonic components increases, and the necessary higher harmonic components are obtained. Are efficiently extracted through the matching circuit. FIG. 12 shows a block diagram of the quadrupler, and in FIG.
14 is a matching circuit for the output signal (frequency f4), 34 is a fundamental wave (frequency f1), a second harmonic (frequency f2) and a third harmonic
It is a trap circuit for (frequency f3).

[0010]

However, in the above frequency multiplier circuit, there is a problem in that the conversion efficiency of the frequency becomes worse as the multiplier has a higher order. It is empirically known that the conversion efficiency becomes less than 0 dB and becomes negative and the conversion loss abruptly increases when the frequency is tripled or more. Therefore, the multiplier actually used is
Limited to 2-4 multipliers at best.

First, in a millimeter-wave band wireless communication device,
We will explain how the constraint that a high-efficiency high-order multiplier cannot be made affects system design.

FIG. 13 is a block diagram of a radio communication device on the transmission side using the frequency multiplier circuit. Here, a simple up-converter circuit is taken for simplification of description. As shown in FIG. 13, the low frequency signal input from the input terminal 1 to which the IF (intermediate frequency) signal is input is converted into a high frequency signal as a result of being multiplied by the output signal of the local oscillator 39 in the mixer 35, Filter 36
The signal is transmitted from the antenna 38 after passing through an amplifier (hereinafter referred to as an amplifier) 37. By the way, in the case of a millimeter-wave band wireless communication device, the low-frequency signal input from the input terminal 1 has a frequency of about 1 to 3 GHz, while the frequency of the transmission signal radiated from the antenna 38 is 60 to 80GH
It often becomes as high as z. Therefore, the local oscillation frequency also requires an ultra high frequency of 60 to 80 GHz. In this case, it is difficult to directly obtain such a super-high frequency stable oscillation signal only by the local oscillator 39, and therefore it is used in combination with a frequency multiplication circuit. That is, the local oscillator 39 outputs a stable oscillation signal in a relatively low frequency band of several GHz.
The frequency of the signal is converted into a high frequency of several times to several tens of times by the frequency multiplication circuit.

In the radio communication apparatus shown in FIG. 13, the frequency of the output signal of the local oscillator 39 is multiplied by 12. In FIG. 13, 43 is an oscillating block, 44 is a 3 multiplication block that multiplies the frequency of the output signal from the transmission block 43 by 3, and 45 is a frequency that is further multiplied by 4 from the 3 multiplied signal from the 3 multiplication block 44. This is a 4 × block. Hereinafter, the oscillation block 43, the 3 multiplication block 44, and the 4 multiplication block 45 will be described in this order.

First, the oscillating block 43 includes the oscillator 3
9 and an amplifier 40 for amplifying the output signal of the oscillator 39
have. The reason is that the next stage tripler 41 is shown in FIG.
This is because, in the case of the triple multiplier shown in 1, the input power as high as 5 to 10 dBm is required to compensate for the low frequency conversion efficiency.

Next, the triple multiplier block 44 has a triple multiplier 41 and an amplifier 40 for amplifying the output signal of the triple multiplier 41. This is because the frequency conversion efficiency of the tripler 41 is low, so that sufficient power cannot be supplied to the quadrupling block 45 of the next stage as it is.

Finally, the quadruple multiplication block 45 has two doubling multipliers 42 connected in series and an amplifier 40 for amplifying the signal multiplied by four by the doubling multiplier 42. In the 4 × block 45, the frequency conversion efficiency of the 4 × multiplier shown in FIG. 12 is too low, so that sufficient power cannot be obtained with one 4 × multiplier, so that the 2 × multiplier 42 is not connected. A quadrupler is used instead.

As described above, in the above wireless communication device, 12
In order to realize the multiplication operation, a complicated configuration as shown in FIG. 13 has to be adopted, so that there are problems that the circuit scale increases, the size of the entire device increases, the cost increases, and the power consumption increases.

Next, in the conventional frequency multiplication circuit, 3
The reason why conversion loss occurs at the time of frequency conversion of higher than twice is explained.

To investigate the non-linear response of an active device,
Strictly speaking, nonlinear circuit simulation such as harmonic balance is required. However, it is known that a simplified model using the following polynomial is sufficient to intuitively grasp the phenomenon.

The characteristic of the non-linear response of the active element is that the output power exhibits a saturation characteristic with respect to the input power. FIG. 14 is a schematic graph showing the state of saturation of the active element. In FIG. 14, the horizontal axis x of the graph represents the input voltage amplitude, and the vertical axis y of the graph represents the output voltage amplitude. The straight line in the graph of FIG. 14 has a linear response (y = a ₁
The input / output characteristic in the case of x) is shown, and the curve shows the input / output characteristic in the case of a non-linear response. The curve of the graph of FIG. 14 can be approximated by, for example, the following polynomial. y = a ₁ x + a ₂ x ² + a ₃ x ³ + a ₄ x ⁴ (Equation 1) In the above (Equation 1), the coefficients a ₁ , a ₂ , a ₃ , a ₄ are real numbers. . Although the above (formula 1) is a polynomial of degree 4, the degree of the polynomial may be set to any degree if necessary. Generally, the higher the degree of polynomial, the higher the accuracy of approximation. From this fact, it is empirically known that there is a magnitude relation of a ₁ > a ₂ > a ₃ > a ₄ among the _four coefficients a _{1 to} a ₄ . Particularly in the case of a semiconductor device having good linearity, it is not uncommon for the relationship of a ₁ >> a ₂ >> a ₃ >> a ₄ to be extremely large or small.

In the above (formula 1), the input voltage amplitude x is a sine wave represented by x = cos (ωt). Here, t is time, ω is an angular frequency, and the angular frequency ω and the frequency f have a relationship of ω = 2πf. Here, the maximum amplitude of the input voltage amplitude x is set to 1 in order to simplify the description. Then, by substituting x = cos (ωt) into (Equation 1) and rearranging it using the trigonometric formula, the following (Equation 2) is obtained. _{y = ((a 2/2} ) + (3 · a 4/8)) + (a 1 + (3 · a 3/4)) · cos (ωt) + ((a 2/2) + (a 4 / 2)) · cos (2ωt ) + (a 3/4) · cos (3ωt) + (a 4/8) · cos (4ωt) ..................... in (equation 2) above (equation 2) , Cos (ωt) represents the fundamental wave output without frequency conversion, and is an important component in the linear amplifier. On the other hand, the cos (2ωt) term represents the second harmonic output, the cos (3ωt) term represents the third harmonic output, and the cos (4ωt) term represents the fourth harmonic output. It is an important component in the frequency multiplication circuit.

On the basis of such understanding, the second most important thing is the amplitude coefficient of each of the 2nd to 4th harmonic output. To summarize briefly, the amplitude of the second harmonic is 2
It can be seen that the amplitude of the third-order harmonic is a ₂ , which is the third-order coefficient, and the third-order coefficient of the polynomial is a ₃ , and the amplitude of the fourth-order harmonic is the fourth-order coefficient of the polynomial, a ₄ .

By the way, as described above, the four coefficients a ₁
Between ~a _4, the magnitude relationship of _{a 1> a 2> a 3} > a 4. That is, what is meant by (Equation 2) is that there is a magnitude relationship of 2nd order> 3rd order> 4th order also between the output amplitudes of the 2nd to 4th order harmonics. That is, in the inside of the semiconductor element used for the multiplier, originally, the higher the frequency component, the smaller the generated power, and there is a limit to how efficiently it can be extracted by the matching circuit. This is the fundamental cause of the large conversion loss in the high-order multiplier of 3 times or more.

Even in the conventional frequency multiplication circuit, there has been an attempt to improve the conversion efficiency of higher order of 3 times or more by further devising the circuit.

A first attempt to increase the conversion efficiency of higher order of 3 times or more is the high order multiplier described in Japanese Patent Laid-Open No. 63-149908. This high-order multiplier is shown in FIG.
As shown in the block diagram of 5, the matching circuit (frequency f1) 4 having one end connected to the input terminal 1 and the semiconductor element 3 having the input side connected to the other end of the matching circuit (frequency f1) 4
A matching circuit (frequency fn) 48 having one end connected to the output side of the semiconductor element 3, and the matching circuit (frequency fn) 4
It has a trap (frequency f1) 31 whose one end is connected to the other end of 8 and whose other end is connected to the output terminal 2, and a feedback circuit 49 which is connected between the input and output of the semiconductor element 3.

In the high-order multiplier, the feedback circuit 49 is provided to increase the gain in the higher-order frequency band of 3 times or more. The high-order multiplier has a frequency fn (= f1) in which the frequency of the output signal is n times the frequency f1 of the input signal.
Xn), and a signal having the same frequency fn as this output signal flows through the feedback circuit 49. As a result, the feedback circuit 49 has the same effect as the amplifier at the frequency fn, and therefore the circuit of FIG.
Can be represented by the circuit. That is, the high-order multiplier shown in FIG. 16 is a matching circuit whose one end is connected to the input terminal 1.
(Frequency f1) 4, an n multiplier 50 having an input terminal connected to the other end of the matching circuit (frequency f1) 4, an amplifier 51 having an input terminal connected to the output terminal of the n multiplier 50,
Matching circuit having one end connected to the output terminal of the amplifier 51
(Frequency fn) 48.

However, the drawback of this high-order multiplier is that FIG.
As is apparent from the above, nothing has been improved on the mechanism of the distortion that originally occurs in the n-multiplier 50. If the nth harmonic component itself generated in the n multiplier 50 is originally small, then the amplifier 51
There is a limit even when trying to amplify with. The reason is that a large gain that can sufficiently compensate the conversion loss in the high-order harmonic cannot be expected with the amplifier effect produced by the effect of the feedback circuit 49. Further, as another problem, in this high-order multiplier, the feedback circuit 49 easily causes oscillation at an arbitrary frequency, but there is also a problem that a concrete circuit measure for preventing the oscillation has not been clarified. is there.

A second attempt to increase the conversion efficiency of three times or more is the injection locked oscillator disclosed in Japanese Patent Laid-Open No. 55-110434. Although this is not described in detail because it deviates from the multiplier technology, the circuit configuration is almost the same as that of the high-order multiplier of FIG.
It can be understood that the feedback circuit in is extremely designed to be an oscillation condition. Further, it can be understood that the gain of the amplifier 51 in FIG. 16 is raised to the limit by causing oscillation. However, even if there is no input, the output is output due to self-oscillation. In such an oscillator, there is a risk that oscillation will occur simultaneously even at a frequency unrelated to the output frequency of the multiplier, but such a problem has been solved by a technique called injection locking. However, the multiplier and the injection-locked oscillator are usually used properly according to the conditions such as required stability and required bandwidth. Therefore, in this specification, a direct comparison between the present invention and the injection-locked oscillator is avoided.

An object of the present invention is to provide a frequency multiplication circuit which can improve the frequency conversion efficiency of the third or higher order with a simple structure, and at the same time, the frequency multiplication circuit can be used to greatly simplify the circuit. An object of the present invention is to provide a high-frequency communication device that can reduce the number of parts, downsize the device, reduce power consumption, and reduce price.

[0030]

In order to achieve the above object, the frequency multiplication circuit of the present invention comprises a semiconductor element having a non-linear characteristic to which an input signal of frequency f1 is inputted,
In a frequency multiplication circuit that outputs an output signal having a frequency fn that is n times (n is a natural number) the frequency f1 of the input signal from the output side of the semiconductor element having the non-linear characteristic, the semiconductor device having the non-linear characteristic outputs the signal. A feedback circuit for positively feeding back a signal having a frequency fm, which is m times (m is a natural number) of the frequency f1 of the input signal among the harmonic components, is provided to the input side of the semiconductor element having the nonlinear characteristic. The signal of frequency fm and the frequencies f1, fn, fm of the output signal satisfy the condition of f1 <fm <fn.

In the conventional frequency multiplication circuit, for example, in order to generate the third harmonic, a ₃ which is the _third coefficient in the above (Equation 1) is used, and in order to generate the fourth harmonic, due to the use of a ₄ is a fourth order coefficients in equation 1), due to the coefficient a ₃ and a ₄ itself is originally small value, the power of harmonic obtained wave was small.

On the other hand, according to the frequency multiplication circuit having the above-mentioned configuration, for example, in order to generate the third harmonic as the output signal of the frequency fn, the second coefficient a in the equation (1) is used.
₂ is used, and in order to generate a fourth harmonic as an output signal of frequency fn, the second-order coefficient a in (Equation 1) is a
_{Use 2} . Between these factors, there is a relationship of a _2> a _3> a ₄ or a ₂ »a ₃ »a _4, the conversion efficiency than the prior art increases.

That is, the frequency multiplication circuit of the present invention is
It is characterized in that distortion components of the highest possible order are created by using the distortion components of the lowest possible order among the harmonic components output from semiconductor devices having nonlinear characteristics. The distortion component of is returned to the input side of the semiconductor element having the non-linear characteristic through the feedback circuit, and is distorted again through the semiconductor element having the non-linear characteristic to obtain a higher-order distortion component through a multi-step step. There is. Therefore, it is possible to improve the frequency conversion efficiency of the third or higher order, especially with a simple configuration.

Further, the frequency multiplying circuit of one embodiment is characterized in that, in the frequency multiplying circuit according to claim 1, the feedback circuit is provided with a circuit having a bandpass filter function for passing only a signal of the frequency fm. I am trying.

According to the frequency multiplier circuit of the above embodiment,
By providing the feedback circuit with a circuit having a bandpass filter function for passing only the signal of the frequency fm, the signal passing through the feedback circuit is easily selected, and the circuit operates stably without causing oscillation. it can.

The frequency multiplier circuit according to one embodiment is the frequency multiplier circuit according to claim 1 or 2, wherein the signal of the frequency fm is twice the frequency f1 of the input signal and the frequency fn of the output signal. Is 3 or 4 times the frequency f1 of the input signal.

According to the frequency multiplier circuit of the above embodiment,
When the signal of the frequency fm is doubled the frequency f1 of the input signal and the frequency fn of the output signal is tripled the frequency f1 of the input signal, a distortion component with a large low-order (second-order) coefficient is obtained. By using, it is possible to realize a tripler with high conversion efficiency with a simple configuration. Further, when the frequency fm signal is twice the frequency f1 of the input signal and the frequency fn of the output signal is four times the frequency f1 of the input signal, a low-order (second-order) coefficient is large. It is possible to realize a quadrupler having high conversion efficiency by using a distortion component with a simple configuration.

Further, the frequency multiplying circuit of one embodiment is the frequency multiplying circuit according to any one of claims 1 to 3, wherein the output from the semiconductor element having the nonlinear characteristic is output to the output side of the semiconductor element having the nonlinear characteristic. It is characterized in that a fundamental wave component removing circuit for eliminating the generated fundamental wave component is provided.

According to the frequency multiplier circuit of the above embodiment,
By the fundamental wave component removal circuit provided on the output side of the semiconductor element having the non-linear characteristic, since the fundamental wave component output from the semiconductor element having the non-linear characteristic is removed, unnecessary fundamental wave components (frequency Since f1) does not perform positive feedback, circuit oscillation can be reliably prevented.

Further, the high frequency communication device of the present invention is characterized by including a local oscillating unit using the frequency multiplying circuit according to any one of claims 1 to 4.

According to the high frequency communication device having the above-mentioned configuration, by using the frequency multiplying circuit in the local oscillating section, the circuit is greatly simplified, the number of parts is reduced, the device is downsized, the power consumption is reduced, and the price is reduced. Can be reduced.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION The frequency multiplying circuit and the high frequency communication device of the present invention will be described below in detail with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 is a block diagram showing the principle of a tripler as a frequency multiplier circuit according to the first embodiment of the present invention. As shown in FIG. 1, this tripler has a matching circuit (frequency f
1) 4, a trap circuit (frequency f2) 5 whose one end is connected to the other end of the matching circuit (frequency f1) 4, and a semiconductor device whose input side is connected to the other end of the trap circuit (frequency f2) 5. 3, a trap circuit (frequency f1) 6 having one end connected to the output side of the semiconductor element 3, and the trap circuit
Trap circuit with one end connected to the other end of (frequency f1) 6
The (frequency f2) 7 and the matching circuit (frequency f3) 8 having one end connected to the other end of the trap circuit (frequency f2) 7 and the other end connected to the output terminal 2 are provided. Further, the other end of the trap circuit (frequency f1) 6 and the input side of the semiconductor element 3 are connected by a feedback circuit 9, and the feedback circuit 9 has a BPF circuit (frequency f2) 1 having a bandpass filter function.
0 is set.

In the triple multiplier having the above structure, the input terminal 1
Signal input from the matching circuit (frequency f1) 4
As a result of the frequency conversion of (frequency f1) by the second-order distortion coefficient a ₂ inside the semiconductor element 3, the frequency f2 (= f1) is obtained.
X2) signal. The component of the frequency f2 is returned to the input side of the semiconductor element 3 through the feedback circuit 9. This frequency f2 signal and the originally existing frequency f1 signal are frequency-converted by the second-order distortion coefficient a _{2 in the} semiconductor element 3, and as a result, a frequency f3 (= f1 + f2) component is produced. Further, trap circuits 5, 6 and 7 are provided to control such a signal flow. Although the trap circuit 6 is placed in front of the trap circuit 7 and the feedback circuit 9 in FIG. 1, the position of the trap circuit 6 is not limited as long as the position of the trap circuit 6 does not interfere with the signal flow which is the gist of the present invention.
Some degree of freedom is allowed. The positions of the matching circuit 4 and the trap circuit 5 also have some degree of freedom. Moreover, the matching circuits 4 and 8 efficiently input and output signals. Moreover, since the whole circuit is apt to oscillate remarkably due to the provision of the feedback circuit 9, the BPF circuit 10 inserted in the feedback circuit 9 allows only the signal of the minimum frequency f2 for stabilization to pass. . The BPF circuit 10 is not always necessary when the fear that the circuit will oscillate is eliminated for some other reason.

The frequency conversion up to the final frequency f3 is described mathematically as follows. In the above (formula 1), the input signal amplitude x composed of two frequencies is set as x = cos (ωt) + cos (2ωt). For simplicity, the formula is simplified to have an amplitude of 1 and a phase difference of zero, but this does not affect the principle of frequency conversion to be described here. The formula of this input signal amplitude x is (Formula 1)
Substituting into and rearranging using the trigonometric formula,
(Equation 3) is obtained. _{y = (a 2 + (3} · a 3/4)) + (a 1 + a 2 + (9 · a 3/4)) · cos (ωt) + (a 1 + (a 2/2) + (9 _{· a 3/4)) ·} cos (2ωt) + (a 2 + a 3) · cos (3ωt) + ((a 2/2) + (3 · a 3/4)) · cos (4ωt) + (3 _{· a 3/4) · cos} (5ωt) + (a 3/4) · cos (6ωt) ..................... ( equation 3) described above (equation 3) point results in important there are two. First, as a result of frequency conversion, cos (3ωt), which is a tripled component,
Is a new occurrence. Two signals like this
When the (fundamental wave and the doubled component) is frequency-converted using the second-order distortion a ₂ , it can be considered that the semiconductor element 3 operates as a mixer. Second, its tripled component cos
This means that, as the amplitude coefficient of (3ωt), not only the conventional small coefficient a ₃ but also a new large coefficient a ₂ is added.

Focusing on the principle described above, the circuit of the tripler of FIG. 1 can be represented by the equivalent circuit of FIG.
The triple multiplier shown in FIG. 2 includes a matching circuit (frequency f1) 4 having one end connected to the input terminal 1, and a doubler 11 having one end connected to the other end of the matching circuit (frequency f1) 4. , A BPF circuit having one end connected to the other end of the doubler 11
(Frequency f2) 10 and the BPF circuit (frequency f2) 10
One input terminal is connected to the other end of the mixer 1 and the other input terminal is connected to the other end of the matching circuit (frequency f1) 4
2 and a matching circuit (frequency f3) 8 having one end connected to the output terminal of the mixer 12 and the other end connected to the output terminal 2.

In the triple multiplier shown in FIG. 2, a part of the input signal of the frequency f1 is fed by the double multiplier 11 to the frequency f.
2 signal is converted. This doubler 11 is realized by the second-order distortion a ₂ component of the semiconductor element 3 in FIG. Then, the two signals of the frequency f1 and the frequency f2 are converted into a signal of the frequency f3 by the mixer 12. The mixer 12 is the same as the mixer 12 shown in FIG.
It is realized by the _second distortion a ₂ component. If the circuit of FIG. 2 is produced as it is, it becomes a large-scale circuit using two semiconductor elements, and power consumption becomes large. Therefore, the circuit of FIG. 1 is obtained by folding the circuit of FIG. 2 using a technique called a “feedback circuit” and using a single semiconductor element.

FIG. 3 is a circuit diagram in which the block diagram of the tripler shown in FIG. 1 is embodied by an actual electronic circuit. Figure 3
As shown in FIG. 3, the triple multiplier includes a matching circuit 18 for the frequency (f1) of the signal input from the input terminal 1 and a second-order harmonic wave whose one end is connected to the output side of the matching circuit 18.
Trap circuit 19 for (frequency f2), non-linear block 17 whose input side is connected to the other end of trap circuit 19, and trap circuit for fundamental wave (frequency f1) whose one end is connected to the output terminal of non-linear block 17 20
And one end connected to the other end of the trap circuit 20.
A trap circuit 21 for the second harmonic (frequency f2), one end of which is connected to the other end of the trap circuit 21 and the other end of which is connected to an output terminal, a matching circuit 22 for the frequency (f3) of the output signal, and the trap A feedback circuit 23 connected between the other end of the circuit 20 and the input terminal of the non-linear block 17.
It has and.

The matching circuit 18 has a coil L1 having one end connected to the input terminal 1 and a capacitor C1 connected between the other end of the coil L1 and the ground GND.

The trap circuit 19 has a coil L2 whose one end is connected to the other end of the coil L1 of the matching circuit 18.
And a capacitor C2 connected in parallel to the coil L2, and the coil L2 and the capacitor C2 are designed to cause parallel resonance at the frequency f2.

The non-linear block 17 is a DC circuit whose one end is connected to the other end of the coil L2 of the trap circuit 19.
Cut capacitor C20 and its DC cut capacitor C
A resistor R1 connected between the other end of 20 and the bias terminal
And the other end of the DC cut capacitor C20 and the ground G
A resistor R2 connected between ND, a transistor Q as a semiconductor element having a non-linear characteristic in which a base terminal is connected to the other end of the DC cut capacitor C20, and an emitter terminal is connected to the ground GND; A coil L3 whose one end is connected to the collector terminal of Q,
It has a capacitor C3 whose one end is connected to the collector terminal of the transistor Q, and the resistors R1 and R2 form a bias circuit.

In the trap circuit 20, the transmission line TL1 for phase adjustment, one end of which is connected to the other end of the capacitor C3 of the nonlinear block 17, and the transmission line TL1.
A coil L4 having one end connected to the other end of the
Has a capacitor C4 connected between the other end and the ground GND, and is designed so that the coil L4 and the capacitor C4 cause series resonance at the frequency f1. In addition,
The function of the transmission line TL1 provided for phase adjustment is described in, for example, Japanese Patent Laid-Open No. 2000-156611.

The trap circuit 21 has one end connected to the other end of the transmission line TL2 and a transmission line TL2 for phase adjustment, one end of which is connected to the other end of the transmission line TL1 of the trap circuit 20. It has a coil L5 and a capacitor C5 connected in parallel to the coil L5.

The matching circuit 22 has a capacitor C6 connected between the other end of the coil L5 of the trap circuit 21 and the ground GND, one end of which is connected to one end of the capacitor C6, and the other end of which is an output terminal. Coil L connected to 2
It has 6 and.

Further, the feedback circuit 23 has one end connected to the other end of the transmission line TL3 and the transmission line TL3 for phase adjustment, one end of which is connected to the other end of the transmission line TL1 of the trap circuit 20. Matching circuit 25 at frequency f2
And a bandpass filter 24 for the second harmonic (frequency f2), one end of which is connected to the other end of the matching circuit 25,
A transmission line TL4, one end of which is connected to the other end of the bandpass filter 24 for phase adjustment, and the transmission line TL4.
One end of the DC cut capacitor C20 of the non-linear block 17 is connected to the other end thereof, and the other end thereof is connected to the resistor R3 for adjusting the amount of feedback. The matching circuit 25 has a capacitor C7 connected between the other end of the transmission line TL3 and the ground GND, and a coil L7 having one end connected to one end of the capacitor C7. The bandpass filter 24 has a capacitor C8 having one end connected to the other end of the coil L7 of the matching circuit 25, one end connected to the other end of the capacitor C8, and the other end connected to one end of the transmission line TL4. Between the coil L8, the capacitor C9 connected between one end of the capacitor C8 and the ground GND, the coil L9 connected in parallel with the capacitor C9, and the other end of the coil L8 and the ground GND. Connected capacitor C10 and its capacitor C10
And a coil L10 connected in parallel with.

FIG. 4 shows a graph of input / output characteristics of the tripler shown in FIG. In FIG. 4, the horizontal axis represents the input power P
represents the in and the vertical axis represents the output power Pout. In the triple multiplier shown in FIG. 3, matching circuits 18, 22, 25 are provided so as to frequency-convert an input signal of 1 GHz into an output signal of 3 GHz.
And trap circuits 19, 20, 21 and band pass filter 2
4 and the phase constants of the phase lines 26 and 27 are tuned. In the non-linear block 17, as a semiconductor element having non-linear characteristics, H of about fmax = 160 GHz is used.
A BT (Heterojunction Bipolar Transistor) is used. In this HBT with the emitter grounded, when the power supply voltage supplied to the collector terminal is set to 3 V, under this power supply condition, H
The saturated output power of BT in the 1 to 4 GHz band is approximately 13 dB.
It was about m. As shown in the input / output characteristics of FIG. 4, in this tripler, the output power Pout = more than 10 dBm is obtained with respect to the input power Pin = 0 dBm, and in terms of frequency conversion efficiency, a result of more than +10 dB is obtained. Was given. In the conventional tripler, the frequency conversion efficiency becomes negative,
That is, conversion loss is generally generated, whereas the triple multiplier of the first embodiment can significantly improve the conversion efficiency.

(Second Embodiment) FIG. 5 is a block diagram showing the principle of a quadrupler as a frequency multiplier circuit according to a second embodiment of the present invention. As shown in FIG. 5, this quadruple multiplier is the same as the third embodiment, except for the matching circuit (frequency f4) 14.
It has the same configuration as the multiplier, and the same components are assigned the same reference numerals and their explanations are omitted.

In the quadrupler configured as described above, the frequency of the input signal (frequency f1) is converted by the quadratic distortion coefficient a ₂ inside the semiconductor element 3, resulting in frequency f2 (=
The signal becomes f1 × 2). The component of the frequency f2 is returned to the input side of the semiconductor element 3 through the feedback circuit 9. The signal of the frequency f2 is again frequency-converted by the second-order distortion coefficient a ₂ inside the semiconductor element 3, and as a result, a component of the frequency f4 (= f2 + f2) is generated. Further, trap circuits 5, 7, and 13 are provided to control such a signal flow. Although the trap circuit 13 is placed in front of the trap circuit 7 and the feedback circuit 9 in FIG. 5, such a position has a certain degree of freedom as long as it does not disturb the signal flow, which is the gist of the present invention. forgiven. The positions of the matching circuit 4 and the trap circuit 5 also have some degree of freedom. Further, the matching circuits 4 and 14 efficiently input and output signals. Further, in order to prevent oscillation by the feedback circuit 9, a BPF circuit 10 having a bandpass filter function is inserted. The BPF circuit 10 is not always necessary when the fear that the circuit will oscillate is eliminated for some other reason.

Focusing on the principle described above, the circuit of FIG. 5 can be equivalently represented by the circuit of FIG. The quadruple multiplier shown in FIG. 6 includes a matching circuit (frequency f1) 4 whose one end is connected to the input terminal 1 and the matching circuit (frequency f1) 4 described above.
A doubler 15 having one end connected to the other end, and a BPF circuit (frequency f having one end connected to the other end of the doubler 11).
2) 10, a doubler 16 having one end connected to the other end of the BPF circuit (frequency f2) 10, one end connected to the other end of the doubler 16 and the other end connected to the output terminal 2. The matching circuit (frequency f4) 14 is provided.

In the quadruple multiplier shown in FIG. 6, a part of the input signal of the frequency f1 is fed to the doubling multiplier 15 to generate the frequency f.
2 signal is converted. This doubler 15 is realized by the second-order distortion a ₂ component of the semiconductor element 3 in FIG. The signal of the frequency f2 is again fed to the doubler 16
Is converted into a signal of frequency f4. The doubler 16 is realized by the second-order distortion a ₂ component of the semiconductor element 3 in FIG. If the circuit of FIG. 6 is produced as it is, it becomes a large-scale circuit using two semiconductor elements, and power consumption becomes large. Therefore, the circuit of FIG. 5 is obtained by folding the circuit of FIG. 6 using a technique called “feedback circuit” and realizing it with one semiconductor element.

FIG. 7 is a circuit diagram in which the block diagram of the quadruple multiplier shown in FIG. 5 is embodied by an actual electronic circuit. The 4 × multiplier shown in FIG. 7 has the same configuration as the 3 × multiplier shown in FIG. 3 of the first embodiment except for the trap circuit 29 and the matching circuit 30, and the same components are designated by the same reference numerals. And the description is omitted.

As shown in FIG. 7, the trap circuit 29 is
A transmission line TL1 for phase adjustment, one end of which is connected to the other end of the capacitor C3 of the nonlinear block 17, a coil L4 whose one end is connected to the other end of the transmission line TL1, and one end of which is the other end of the coil L4. Is connected and the other end is ground G
The capacitor C4 connected to ND and the transmission line TL1
The coil L11 having one end connected to the other end of the
It has a capacitor C11 having one end connected to the other end of 11 and the other end connected to the ground GND. In the trap circuit 29, the coil L4 and the capacitor C4 are designed to cause series resonance at the frequency f1, and the coil L11 and the capacitor C11 are designed to cause series resonance at the frequency f3.

The matching circuit 30 includes the trap circuit 21.
Of the capacitor C12 connected between the other end of the coil L5 and the ground GND, and the coil L12 having one end connected to one end of the capacitor C12 and the other end connected to the output terminal 2.
And have.

FIG. 8 is a graph of input / output characteristics of the quadruple multiplier of FIG. In FIG. 8, the horizontal axis represents the input power Pin and the vertical axis represents the output power Pout. Here, the circuit of FIG. 7 is tuned so as to frequency-convert the input signal of 1 GHz into the output signal of 4 GHz. The conditions such as the semiconductor element and the power supply voltage are the same as the conditions described in FIG. As shown in the input / output characteristics of FIG. 8, in this quadrupler, the output power Pout was a little over 9 dBm when the input power Pin was 0 dBm, and the result was +9 dB in terms of frequency conversion efficiency. In the quadrupler of the prior art, the frequency conversion efficiency becomes negative,
That is, while conversion loss is generally generated, the quadrupler according to the second embodiment can significantly improve the conversion efficiency.

(Third Embodiment) FIG. 9 is a block diagram of a transmitting side of a millimeter wave band wireless communication apparatus using a tripler according to a third embodiment of the present invention. This millimeter-wave band wireless communication device is obtained by applying the frequency multiplication circuit of the present invention to the conventional wireless communication device shown in FIG. 13. The local communication unit is different from the wireless communication device shown in FIG. Three
8 and the oscillator 39 have the same configuration. In FIG. 9, 46 is a tripler that multiplies the frequency of the output signal of the oscillator 39 by 3, and 47 is a 4-multiplier that further multiplies the frequency of the signal tripled by the tripler 46 by 4.

The radio communication apparatus of FIG. 9 will be described below in comparison with the radio communication apparatus of FIG.

First, in contrast to the oscillation block 43 having the amplifier 40 of FIG. 13, this radio communication apparatus requires only the oscillator 39 without the amplifier. This is because, as can be seen from FIG. 4 and FIG. 8, the frequency multiplication circuit according to the present invention has a very high frequency conversion efficiency, and therefore, for example, 0 dB.
This is because a sufficiently low input power of about m is sufficient for operation.

Next, with respect to the tripler block 44 having the amplifier 40 of FIG. 13, this radio communication apparatus requires only the tripler 46 without the amplifier. because,
As can be seen from FIG. 4, the tripler 46 according to the invention
This is because, even by itself, it has a high frequency conversion efficiency of, for example, about 10 dB.

Finally, with respect to the quadrupler block 45 having the amplifier 40 of FIG. 13, in this radio communication device, the amplifier is omitted, and the number of the multipliers which are two is reduced to make one quadrupler. Only 47 will improve. This is because, as can be seen from FIG. 8, the quadrupler 47 according to the present invention has a high frequency conversion efficiency of about 9 dB by itself.

As is apparent from the comparison between FIG. 9 and FIG. 13, the triple multiplier according to the present invention is used in the local oscillating unit of the high-frequency communication device, so that the radio communication device in the millimeter-wave band or the like can be greatly improved. It is possible to simplify the circuit, reduce the number of parts, downsize the device, reduce power consumption, and reduce cost.

In the first and second embodiments described above, the 3 × multiplier and the 4 × multiplier as the frequency multiplying circuit have been described.
The present invention may be applied to a frequency doubler or a frequency multiplier circuit that performs higher-order frequency conversion of 5 times or more.

Further, although the high frequency communication device using the frequency multiplication circuit of the present invention has been described in the third embodiment, the frequency multiplication circuit of the present invention is applied to other devices as well as the high frequency communication device. Good.

[0073]

As is apparent from the above, according to the frequency multiplication circuit of the present invention, the frequency conversion efficiency can be greatly increased, especially in the multiplier for performing high-order frequency conversion of 3 times or more. For example, even in a tripler or a quadrupler, there is no conversion loss and a high conversion gain can be obtained. Further, although the feedback circuit is used, stable circuit operation can be realized with less oscillation.

Further, according to the high frequency communication device of the present invention of the present invention, by using the frequency multiplier circuit in the local oscillating section, the circuit is greatly simplified, the number of parts is reduced, the device is miniaturized, and the power consumption is reduced. Can be reduced and the price can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a tripler as a frequency multiplier circuit according to a first embodiment of the present invention.

FIG. 2 is an equivalent block diagram of the tripler.

FIG. 3 is a circuit diagram of the tripler.

FIG. 4 is a diagram showing input / output characteristics of the tripler.

FIG. 5 is a block diagram of a 4 × multiplier as a frequency multiplying circuit according to a second embodiment of the present invention.

FIG. 6 is an equivalent block diagram of the quadrupler.

FIG. 7 is a circuit diagram of the quadruple multiplier.

FIG. 8 is a diagram showing input / output characteristics of the quadruple multiplier.

FIG. 9 is a block diagram of a transmitting side of a millimeter-wave band wireless communication device using a tripler as a frequency multiplying circuit of a third embodiment of the present invention.

FIG. 10 is a block diagram of a conventional doubler.

FIG. 11 is a block diagram of a conventional tripler.

FIG. 12 is a block diagram of a conventional quadruple multiplier.

FIG. 13 is a block diagram of a conventional wireless communication device.

FIG. 14 is a graph showing a model of a nonlinear response of an active device.

FIG. 15 is a block diagram of a conventional high-order multiplier.

FIG. 16 is an equivalent block diagram of the high-order multiplier.

[Explanation of symbols]

1 ... input terminal, 2 ... Output terminal, 3 ... Semiconductor element, 4 ... Matching circuit (frequency f1), 5 ... Trap circuit (frequency f2), 6 ... Trap circuit (frequency f1), 7 ... Trap circuit (frequency f2), 8 ... Matching circuit (frequency f3), 9 ... Feedback circuit, 10 ... bandpass filter circuit (frequency f2), 11 ... doubler, 12 ... mixer, 13 ... Trap circuit (frequency f1, f3), 14 ... Matching circuit (frequency f4), 15 ... doubler, 16 ... 2 multiplier, 17 ... Non-linear block, 18 ... Matching circuit (frequency f1), 19 ... Trap circuit (frequency f2), 20 ... Trap circuit (frequency f1), 21 ... Trap circuit (frequency f2), 22 ... Matching circuit (frequency f3), 23 ... Feedback circuit, 24 ... bandpass filter (frequency f2), 25 ... Matching circuit, 29 ... Trap circuit (frequency f1, f3), 30 ... Matching circuit (frequency f4), 31 ... Trap circuit (frequency f1), 32 ... Matching circuit (frequency f2), 33 ... Trap circuit (frequency f1, f2), 34 ... Trap circuit (frequency f1, f2, f3), 35 ... mixer, 36 ... BPF circuit, 37 ... amplifier, 38 ... antenna, 39 ... Oscillator, 40 ... amplifier, 41 ... tripler, 42 ... a doubler, 43 ... Oscillation block, 44 ... 3 multiplication block, 45 ... 4 multiplication block, 46 ... 3 multiplier, 47 ... Quadrupler, 48 ... Matching circuit (frequency fn), 49 ... Feedback circuit (frequency fn), 50 ... n multiplier, 51 ... amplifier, C1 to C12 ... capacitors, C20 ... DC cut capacitor, L1 to L12 ... coil, Q: Transistor, TL1 to TL4 ... Phase line, R1 to R3 ... Resistance.

Claims (5)

[Claims] 1. A semiconductor device having a non-linear characteristic to which an input signal having a frequency f1 is inputted, wherein the frequency f1 of the input signal is output from the output side of the semiconductor device having the non-linear characteristic.
In a frequency multiplication circuit that outputs an output signal with a frequency fn that is n times (n is a natural number), the frequency component is multiplied by m (m) of the frequency f1 of the input signal among the harmonic components output from the semiconductor element having the above-mentioned nonlinear characteristic. A feedback circuit that positively feeds back a signal of frequency fm (a natural number) to the input side of the semiconductor element having the above-mentioned non-linear characteristic, and the frequencies f1, fn, fm of the input signal, the signal of the frequency fm, and the output signal are , F1 <fm <fn, which is a frequency multiplication circuit. 2. The frequency multiplying circuit according to claim 1, wherein the feedback circuit is provided with a circuit having a bandpass filter function for passing only a signal of the frequency fm. 3. The frequency multiplication circuit according to claim 1, wherein the signal of the frequency fm is 2 times the frequency f1 of the input signal.
And the frequency fn of the output signal is equal to the frequency f1 of the input signal.
Frequency multiplication circuit characterized by being 3 times or 4 times. 4. The frequency multiplier circuit according to claim 1, wherein a fundamental wave component output from the semiconductor element having the non-linear characteristic is output to the output side of the semiconductor element having the non-linear characteristic. A frequency multiplication circuit comprising a fundamental wave component removal circuit for removal. 5. A high-frequency communication device comprising a local oscillating unit using the frequency multiplication circuit according to any one of claims 1 to 4.