JP2003067440A5 - - Google Patents

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Publication number
JP2003067440A5
JP2003067440A5 JP2002126588A JP2002126588A JP2003067440A5 JP 2003067440 A5 JP2003067440 A5 JP 2003067440A5 JP 2002126588 A JP2002126588 A JP 2002126588A JP 2002126588 A JP2002126588 A JP 2002126588A JP 2003067440 A5 JP2003067440 A5 JP 2003067440A5
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JP
Japan
Prior art keywords
type
width
identifying
output node
determining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002126588A
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English (en)
Japanese (ja)
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JP2003067440A (ja
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Publication date
Priority claimed from US09/845,437 external-priority patent/US6502223B1/en
Application filed filed Critical
Publication of JP2003067440A publication Critical patent/JP2003067440A/ja
Publication of JP2003067440A5 publication Critical patent/JP2003067440A5/ja
Pending legal-status Critical Current

Links

JP2002126588A 2001-04-30 2002-04-26 スタティックゲートの入力におけるノイズをシミュレートして出力におけるノイズを求めるための方法 Pending JP2003067440A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/845,437 US6502223B1 (en) 2001-04-30 2001-04-30 Method for simulating noise on the input of a static gate and determining noise on the output
US09/845437 2001-04-30

Publications (2)

Publication Number Publication Date
JP2003067440A JP2003067440A (ja) 2003-03-07
JP2003067440A5 true JP2003067440A5 (cg-RX-API-DMAC10.html) 2005-04-07

Family

ID=25295234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002126588A Pending JP2003067440A (ja) 2001-04-30 2002-04-26 スタティックゲートの入力におけるノイズをシミュレートして出力におけるノイズを求めるための方法

Country Status (2)

Country Link
US (1) US6502223B1 (cg-RX-API-DMAC10.html)
JP (1) JP2003067440A (cg-RX-API-DMAC10.html)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7552040B2 (en) * 2003-02-13 2009-06-23 International Business Machines Corporation Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects
US7107552B2 (en) * 2003-06-10 2006-09-12 Intel Corporation Method and apparatus to analyze noise in a pulse logic digital circuit design
EP1577801A1 (en) * 2004-03-15 2005-09-21 Infineon Technologies AG Device characterization concept
US7400167B2 (en) * 2005-08-16 2008-07-15 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices
US7269809B2 (en) * 2004-06-23 2007-09-11 Sioptical, Inc. Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6253351B1 (en) * 1998-03-24 2001-06-26 Matsushita Electric Industrial Co., Ltd. Circuit optimization system
JP3068065B2 (ja) * 1998-09-25 2000-07-24 日本電気株式会社 回路設計方法
US6405347B1 (en) * 1999-06-30 2002-06-11 Hewlett-Packard Company Method and apparatus for determining the maximum permitted and minimum required width of a feedback FET on a precharge node

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