JP2003066122A - Ic tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a IC tester in which failure analysis can be carried out readily in a short time. SOLUTION: An IC tester for testing an object to be tested is improved by pattern data being outputted from a pattern memory based on an address. The IC tester is characterized in that it has one or more index counter for counting the number of times of looping an instruction, more than one pattern generating sequencer providing an address exclusively to the pattern memory based on the instruction, a section for selecting the index counter of a pattern generating sequencer providing an address among these pattern generators, and a section for storing the count of an index counter thus selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus for testing an object to be tested by pattern data output from a pattern memory based on an address, and more particularly to an IC test apparatus capable of easily performing failure analysis in a short time. is there.

[0002]

2. Description of the Related Art An IC test apparatus is an object to be tested, for example,
The test pattern is given to an IC, an LSI, etc., and the output of the test object is compared with the expected value pattern to judge the pass / fail of the test object. The test pattern, expected value pattern, etc. are stored in the pattern memory as pattern data, and an address is given to the pattern memory to output the pattern data. The structure of the main part of such an apparatus will be described with reference to FIG.

In FIG. 3, the address generator 1 has pattern generation sequencers 11 and 12, and supplies an address to a pattern memory (not shown). The pattern generation sequencers 11 and 12 have one or more index counters 11
0 and 120 are provided, and an address is exclusively given to the pattern memory based on an instruction stored in a memory (not shown). The pattern generation sequencer 11 is suitable for continuous addresses, receives an active signal, becomes valid, and outputs an active signal. The pattern generation sequencer 12 is suitable for generating random addresses,
Upon receiving the active signal of the pattern generation sequencer 11, the pattern generation sequencer 11 becomes valid and outputs the active signal to the pattern generation sequencer 11. Index counter 110,12
0 counts the number of loops of the instruction.

The failure analysis data storage unit 2 is connected to a data bus and has a path / path for each pin (not shown) to be tested.
A plurality of index storage units 21, 22 are stored while storing a fail (comparison result of the output of the device under test and the expected value pattern) and an address generated by the address generation unit 1.
Have. The index storage units 21 and 22 are provided for the index counters 110 and 120, respectively,
A data bus is connected to the index counter 110,
The count value of 120 is stored as index data. Here, in addition to the address given to the pattern memory, the address generated by the address generation unit 1 is added with information indicating which of the pattern generation sequencers 11 and 12 has generated the address.

The operation of such a device will be described below.
The pattern generation sequencer 11 generates an address based on an instruction and the index counter 1 indicates the number of loops of the instruction.
Count at 10. At this time, the pattern generation sequencer 12 has not generated an address. The pattern data is output from the pattern memory by the address of the pattern generation sequencer 11, the test of the test target is performed, and the pass / fail of each pin of the test target is determined. Then, the pass / fail defect analysis data storage unit 2 stores the pass / fail and the address of the pattern generation sequencer 11, and the index storage units 21 and 22 of the defect analysis data storage unit 2 store the index counter 110,
The count value of 120 is stored.

By repeating such an operation, the pattern generation sequencer 11 outputs an active signal to the pattern generation sequencer 12 in response to an instruction to stop the address generation. As a result, the pattern generation sequencer 12 becomes valid, generates an address based on the instruction, and the index counter 120 counts the number of loops of the instruction. With this address, the pattern data is output from the pattern memory, the test of the test target is performed, and the pass / fail of each pin of the test target is determined. The pass / fail data storage unit for failure analysis 2 stores the pass / fail and the address of the pattern generation sequencer 12, and the index storage unit 2 of the data storage unit for failure analysis 2
Reference numerals 1 and 22 store the count values of the index counters 110 and 120. Such operation is repeated.

Then, the pattern generation sequencer 12 sends an active signal to the pattern generation sequencer 11 according to an instruction.
To address and stop address generation. Again, the pattern generation sequencer 11 starts address generation.

When the operation is repeated and the test is completed, the failure analysis is performed by reading the data from the failure analysis data storage unit 2 via the data bus. At this time, from the count values stored in the index storage units 21 and 22, the valid pattern generation sequencers 11 and 12 are picked up, and only the valid count values are arranged, and then the failure analysis is performed.

[0009]

As described above, when the index data is read via the data bus during the failure analysis, it takes a long time to read the data because there are many index storage units. Further, data corresponding to the pattern generation sequencers 11 and 12 that are effective for each pattern data is extracted from the read index data,
There is a problem that it takes a long time to process data such as combination in time series.

Therefore, an object of the present invention is to realize an IC test apparatus which enables easy failure analysis in a short time.

[0011]

According to a first aspect of the present invention, in an IC test apparatus for testing an object to be tested by pattern data output from a pattern memory based on an address, at least one or more of counting the number of loops of instructions Of at least two pattern generation sequencers that exclusively give addresses to the pattern memory based on an instruction, and an index counter of the pattern generation sequencer that gives an address among these pattern generation sequencers. The present invention is characterized by having a selecting unit for selecting and an index storing unit for storing the count value of the index counter selected by the selecting unit.

A second aspect of the present invention is characterized in that an index controller for selecting a selecting section is provided based on a pattern generation sequencer giving an address.
Of the invention.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same parts as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 1, an index controller 3 is provided in the address generator 1 and receives active signals from the pattern generation sequencers 11 and 12 and outputs selection signals. The multiplexer 4 is a selection unit, and selects the count value of the index counters 110 and 120 according to the selection signal of the index controller 3. The plurality of index storage units 23 are index storage units 21 and 2.
Instead of 2, it is provided in the failure analysis data storage unit 2,
Index counter 11 selected by multiplexer 4
The count value of 0, 120 is stored as index data, and the data bus is connected.

The operation of such a device will be described below.
The pattern generation sequencer 11 generates an address based on an instruction and the index counter 1 indicates the number of loops of the instruction.
Count at 10. At this time, the pattern generation sequencer 12 has not generated an address. Further, the index controller 3 causes the multiplexer 4 to select the index counter 110 at the time of starting.

At the address of the pattern generation sequencer 11, pattern data is output from the pattern memory,
The device under test is tested and the pass / fail of each pin under test is determined. Then, the pass / fail defect analysis data storage unit 2 stores the pass / fail and the address of the pattern generation sequencer 11. At the same time, the index storage unit 23 of the failure analysis data storage unit 2 stores the count value of the index counter 110 from the multiplexer 4.

By repeating such operations, the pattern generation sequencer 11 outputs an active signal to the pattern generation sequencer 12 in response to an instruction to stop the address generation. As a result, the pattern generation sequencer 12 becomes valid, generates an address based on the instruction, and the index counter 120 counts the number of loops of the instruction. Further, the index controller 3 inputs the active signal output from the pattern generation sequencer 11, and causes the multiplexer 4 to select the index counter 120.

At the address of the pattern generation sequencer 12, pattern data is output from the pattern memory,
The device under test is tested and the pass / fail of each pin under test is determined. Then, the pass / fail defect analysis data storage unit 2 stores the pass / fail and the address of the pattern generation sequencer 12. At the same time, the index storage unit 23 of the failure analysis data storage unit 2 stores the count value of the index counter 120. Such operation is repeated.

Then, the pattern generation sequencer 12 sends an active signal to the pattern generation sequencer 11 according to an instruction.
To address and stop address generation. Again, the pattern generation sequencer 11 starts address generation. Also, the index controller 3 is the pattern generation sequencer 1
2 inputs the active signal output from the multiplexer 2, and causes the multiplexer 4 to select the index counter 110.

When the test is repeated by repeating the above operation, the failure analysis is performed by reading the data from the failure analysis data storage unit 2 via the data bus.

In this way, the index controller 3
As a result, the multiplexer 4 selects the index counters 110 and 120 based on the pattern generation sequencers 11 and 12 that give addresses, so that only valid count values are stored in the index storage unit 23 in the order of execution, reducing the data processing time. can do. Further, since only one index storage unit 23 is required, the circuit scale can be reduced.

Next, a second embodiment will be described with reference to FIG. Here, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The apparatus shown in FIG. 2 is different from the apparatus shown in FIG. 1 in that two pattern generation sequencers 11 and 12 are provided with n pattern generation sequencers 11 to 1n. Along with this, the index controller 3 outputs a selection signal based on the pattern generation by the pattern generation sequencers 11 to 1n, and the multiplexer 4 causes the index counters 110 to 1n0 of the pattern generation sequencers 11 to 1n by the selection signal. select. Since other operations are the same as those of the apparatus shown in FIG. 1, description thereof will be omitted.

The present invention is not limited to this, and the configuration in which the multiplexer 4 is selected by using the index controller 3 has been shown. However, the pattern generation sequencer 11 without the index controller 3 is provided.
The configuration may be such that switching is performed by an active signal from 0, 120. Further, instead of the index controller 3 receiving the active signal, the pattern generation sequencers 110 and 120 may be monitored and the multiplexer 4 may be switched.

Further, although the index storage unit 23 is shown as an example including a plurality of memories, it may have a structure in which one memory area is divided.

Although the failure analysis data storage unit 2 has shown an example in which all data is stored, it may be configured to store data only when a failure occurs.

[0026]

According to the present invention, since the selection section selects the index counter based on the pattern generation sequencer which gives the address, only the effective count value is stored in the index storage section in the order of execution, and the data processing time is reduced. Can be shortened. Moreover, since only one index storage unit is required, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing another embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional IC test apparatus.

[Explanation of symbols]

3 Index controller 4 multiplexer 11-1n pattern generation sequencer 23 Index Storage

Claims (2)

[Claims] 1. An IC for testing an object to be tested by pattern data output from a pattern memory based on an address.
In the test apparatus, at least one or more index counters for counting the number of loops of instructions are provided, and at least two or more pattern generation sequencers for exclusively giving an address to the pattern memory based on the instructions, and these pattern generation sequencer Among them, an IC test apparatus having a selecting section for selecting an index counter of a pattern generation sequencer giving an address and an index storing section for storing a count value of the index counter selected by the selecting section. 2. The IC according to claim 1, further comprising an index controller for selecting a selection unit based on a pattern generation sequencer giving an address.
Test equipment.