JP2003060226A - Laminated structure and light-emitting element, lamp, and light source using the same - Google Patents

Laminated structure and light-emitting element, lamp, and light source using the same

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Publication number
JP2003060226A
JP2003060226A JP2001248587A JP2001248587A JP2003060226A JP 2003060226 A JP2003060226 A JP 2003060226A JP 2001248587 A JP2001248587 A JP 2001248587A JP 2001248587 A JP2001248587 A JP 2001248587A JP 2003060226 A JP2003060226 A JP 2003060226A
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Japan
Prior art keywords
substrate
buffer layer
layer
temperature buffer
laminated structure
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JP3649170B2 (en
Inventor
Takashi Udagawa
隆 宇田川
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Resonac Holdings Corp
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Showa Denko KK
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Abstract

PROBLEM TO BE SOLVED: To solve the problem, when an impurity-added low-temperature buffer layer composed of a boron phosphide-based semiconductor layer is joined to the upper surface of a conductive single-crystal substrate, particularly, a single- crystal silicon substrate, the crystallinity of the substrate near the junction interface between the buffer layer and substrate deteriorating due to the impurity contained in the buffer layer when the impurity infiltrates into the substrate. SOLUTION: An element having a larger atomic radius than phosphorus has is used as the impurity added to the low-temperature buffer layer 102. When the buffer layer 102 is provided on a silicon substrate 101, particularly, an element having atomic radius larger than that of silicon is used as the impurity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、導電性の単結晶基
板上に積層されたリン化硼素系半導体からなる低温緩衝
層を備えた積層構造体と、それを利用して構成された発
光素子、ランプ、及び光源に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated structure provided with a low temperature buffer layer made of a boron phosphide-based semiconductor laminated on a conductive single crystal substrate, and a light emitting device constructed by using the laminated structure. , Lamps, and light sources.

【0002】[0002]

【従来の技術】III−V族化合物半導体の一種とし
て、硼素(B)とリン(P)とを構成元素として含むリ
ン化硼素(BP)系III−V族化合物半導体(リン化
硼素系半導体)が知られている(寺本 巌著、「半導体
デバイス概論」(1995年3月30日、(株)培風館
発行初版、26〜28頁参照)。従来において、リン化
硼素或いはその混晶を利用して青色帯或いは緑色帯の発
光素子を構成する技術が開示されている(日本国特許
第2809690号、第2809691号、第28
09692号各公報、及び米国特許6,069,02
1号参照)。例えば、リン化硼素(BP)とその多元混
晶であるAlGaInBNとの超格子構造体から緑色帯
光を出射する発光層を構成する技術が知られている(上
記の特許第2809691号公報参照)。
2. Description of the Related Art Boron phosphide (BP) group III-V group compound semiconductors (boron phosphide group semiconductors) containing boron (B) and phosphorus (P) as constituent elements are one type of III-V group compound semiconductors. Iwa Teramoto, "Introduction to Semiconductor Devices" (March 30, 1995, first edition issued by Baifukan Co., Ltd., pp. 26-28). Conventionally, boron phosphide or its mixed crystal was used. A technique for forming a blue band or green band light emitting device has been disclosed (Japanese Patent Nos. 2809690, 2809691, 28).
No. 09692 and US Pat. No. 6,069,02
(See No. 1). For example, there is known a technique of forming a light emitting layer that emits green band light from a superlattice structure of boron phosphide (BP) and its multi-element mixed crystal, AlGaInBN (see Japanese Patent No. 2809691). .

【0003】リン化硼素系半導体層、特にリン化硼素
(BP)層は上記の発光素子を構成するための積層構造
体にあって、発光層に加えて緩衝層として利用されてい
る(米国特許5,042,043号参照)。また、電流
狭窄型のレーザダイオード(LD)をなすための電流狭
窄層を構成するに利用されている(日本国特許第315
2900号公報参照)。リン化硼素(格子定数≒4.5
38Å)層を備えた積層構造体は、珪素(Si:格子定
数≒5.431Å)、リン化ガリウム(GaP:格子定
数≒5.450Å)、或いは六方晶ウルツ鉱型炭化珪素
(SiC:a軸格子定数≒3.086Å)等の導電性単
結晶を基板として構成されるのがもっぱらである(上記
の米国特許6,069,021号参照)。
A boron phosphide-based semiconductor layer, particularly a boron phosphide (BP) layer, is a laminated structure for constructing the above light emitting device and is used as a buffer layer in addition to the light emitting layer (US Pat. 5,042,043). It is also used to form a current confinement layer for forming a current confinement type laser diode (LD) (Japanese Patent No. 315).
2900). Boron phosphide (lattice constant ≈4.5
The laminated structure including the 38 Å) layer is made of silicon (Si: lattice constant ≈ 5.431 Å), gallium phosphide (GaP: lattice constant ≈ 5.450 Å), or hexagonal wurtzite silicon carbide (SiC: a-axis). The substrate is mainly composed of a conductive single crystal having a lattice constant of approximately 3.086Å) (see the above-mentioned US Pat. No. 6,069,021).

【0004】[0004]

【発明が解決しようとする課題】発光素子用途の積層構
造体をなすリン化硼素系半導体層は、従来では、格子不
整合の関係にある基板上に積層されている。加えて、リ
ン化硼素系半導体と基板材料との熱膨張率の相違に起因
して、基板上にリン化硼素系半導体層を積層する際に、
基板表面からリン化硼素系半導体層が剥離する問題を発
生させている。最近では、例えば、珪素(シリコン)単
結晶からなる基板上に、比較的低温で形成した非晶質或
いは多結晶のリン化硼素系半導体からなる低温緩衝層を
配置して上記の剥離に関する問題点を解決できる技術手
段が開示されている(上記の米国特許6,069,02
1号参照)。
Conventionally, a boron phosphide-based semiconductor layer forming a laminated structure for use in a light emitting device is laminated on a substrate having a lattice mismatching relationship. In addition, due to the difference in the coefficient of thermal expansion between the boron phosphide-based semiconductor and the substrate material, when laminating the boron phosphide-based semiconductor layer on the substrate,
This causes a problem that the boron phosphide-based semiconductor layer peels off from the substrate surface. Recently, for example, a low-temperature buffer layer made of an amorphous or polycrystalline boron phosphide-based semiconductor formed at a relatively low temperature is arranged on a substrate made of silicon single crystal, and the above-mentioned problem of peeling occurs. A technical means capable of solving the above problems is disclosed (US Pat. No. 6,069,02 mentioned above).
(See No. 1).

【0005】しかし、一方で、導電性基板とのより良い
導通を得ることを目的として、p形或いはn形不純物を
添加して導電性に優れる低温緩衝層を得る際に、これら
の不純物が基板内部へ拡散、浸透し、基板表層部に歪や
結晶欠陥を発生させる問題が生じている。リン化硼素系
半導体からなる低温緩衝層と例えば、シリコン基板との
界面近傍の領域に導入される歪等に因り、緩衝層と基板
間の正常な通流は阻害される欠点がある。
However, on the other hand, when a p-type or n-type impurity is added to obtain a low-temperature buffer layer having excellent conductivity, for the purpose of obtaining better conduction with the conductive substrate, these impurities are not included in the substrate. There is a problem that it diffuses and permeates into the inside, and causes strain and crystal defects in the surface layer of the substrate. There is a drawback that normal flow between the buffer layer and the substrate is hindered due to strain or the like introduced in a region near the interface between the low temperature buffer layer made of a boron phosphide-based semiconductor and the silicon substrate, for example.

【0006】本発明では、低温緩衝層に良導性を与える
不純物の基板材料への浸透、拡散を回避しつつ、導電性
に優れる低温緩衝層を提供できる技術手段を提示する。
また、その技術手段を利用して構成した積層構造体、及
びその積層構造体から構成された発光素子、ランプ並び
に光源を提供するものである。
The present invention proposes a technical means capable of providing a low temperature buffer layer having excellent conductivity while avoiding the penetration and diffusion of impurities that give good conductivity to the low temperature buffer layer to the substrate material.
Further, the present invention provides a laminated structure constituted by utilizing the technical means, and a light emitting element, a lamp and a light source constituted by the laminated structure.

【0007】[0007]

【課題を解決するための手段】即ち、本発明は、導電性
の単結晶からなる基板と、該基板の表面上に設けられ
た、硼素(B)とリン(P)とを構成元素として含むリ
ン化硼素(BP)系半導体からなる、非晶質体を含む多
結晶からなる、不純物を添加した低温緩衝層とを備えた
積層構造体であって、特に次の(1)から(5)項に記
載の特徴を有する積層構造体を提供する。 (1)低温緩衝層に添加する不純物が、リン(P)以上
の原子半径を有する元素からなることを特徴とする積層
構造体。 (2)導電性の基板が珪素(Si(シリコン))単結晶
からなり、低温緩衝層に添加する不純物が、珪素(S
i)以上の原子半径を有する元素からなることを特徴と
する上記(1)に記載の積層構造体。 (3)導電性の基板がp形伝導性の単結晶からなり、低
温緩衝層に添加する不純物が、亜鉛(Zn)からなるこ
とを特徴とする上記(1)または(2)に記載の積層構
造体。 (4)低温緩衝層上に、低温緩衝層に添加された不純物
とは異なる元素を添加した、リン化硼素(BP)系半導
体からなる導電層を備えていることを特徴とする上記
(1)乃至(3)の何れか1項に記載の積層構造体。 (5)導電性の基板がp形伝導性の単結晶からなり、低
温緩衝層上に設ける導電層をマグネシウム(Mg)を添
加したリン化硼素系半導体層から構成したことを特徴と
する上記(3)に記載の積層構造体。
That is, the present invention contains a substrate made of a conductive single crystal and boron (B) and phosphorus (P) provided on the surface of the substrate as constituent elements. What is claimed is: 1. A laminated structure comprising a boron phosphide (BP) -based semiconductor, a polycrystal containing an amorphous body, and a low-temperature buffer layer to which an impurity is added, comprising the following (1) to (5): A laminated structure having the characteristics described in (1) above is provided. (1) A laminated structure characterized in that the impurities added to the low temperature buffer layer are composed of an element having an atomic radius of phosphorus (P) or more. (2) The conductive substrate is made of silicon (Si) single crystal, and the impurity added to the low temperature buffer layer is silicon (S).
i) The laminated structure according to (1) above, which is composed of an element having an atomic radius of the above. (3) The laminate as described in (1) or (2) above, wherein the conductive substrate is made of p-type conductive single crystal, and the impurities added to the low temperature buffer layer are made of zinc (Zn). Structure. (4) The conductive layer made of a boron phosphide (BP) -based semiconductor, to which an element different from the impurities added to the low temperature buffer layer is added, is provided on the low temperature buffer layer. The laminated structure according to any one of (1) to (3). (5) The conductive substrate is made of p-type conductive single crystal, and the conductive layer provided on the low temperature buffer layer is made of a boron phosphide-based semiconductor layer to which magnesium (Mg) is added. The laminated structure according to 3).

【0008】また、本発明は、次の(6)及び(7)項
に記載の発光素子を提供する。 (6)上記(1)乃至(5)の何れか1項に記載の積層
構造体の表面をなす半導体層に接触させてオーミック
(Ohmic)性の表面電極を設け、基板をなす導電性
単結晶の裏面にオーミック性の裏面電極を設けて構成し
たことを特徴とする発光素子。 (7)積層構造体の表面の半導体層がn形であり、基板
がp形伝導性の単結晶であることを特徴とする上記
(6)に記載の発光素子。
The present invention also provides a light emitting device described in the following items (6) and (7). (6) A conductive single crystal that forms a substrate by providing an ohmic surface electrode in contact with the semiconductor layer that forms the surface of the laminated structure according to any one of (1) to (5) above. A light-emitting element comprising an ohmic back surface electrode provided on the back surface of. (7) The light emitting device according to the above (6), wherein the semiconductor layer on the surface of the laminated structure is n-type, and the substrate is a p-type conductive single crystal.

【0009】また、本発明では、次記のランプ及び光源
を提供する。 (8)上記(6)または(7)に記載の発光素子を利用
して構成したことを特徴とするランプ。 (9)上記(8)に記載のランプを集合させて構成した
ことを特徴とする光源。
The present invention also provides the following lamp and light source. (8) A lamp comprising the light emitting device described in (6) or (7) above. (9) A light source comprising the lamp as set forth in (8) above.

【0010】[0010]

【発明の実施の形態】本発明の第1の実施形態に係わる
LED1B用途の積層構造体1Aの断面構造を図1に模
式的に例示する。
BEST MODE FOR CARRYING OUT THE INVENTION A cross-sectional structure of a laminated structure 1A for use in an LED 1B according to a first embodiment of the present invention is schematically illustrated in FIG.

【0011】ダブルヘテロ(DH)構造型発光ダイオー
ド(LED)用途の積層構造体1Aは、基本的に次記の
(A)〜(E)項に記載の要素から構成できる。 (A)n形またはp形伝導性の導電性シリコン(Si)
或いはBP(特公昭55−3834号公報参照)、Ga
P、GaAs、SiC等からなる基板101 (B)非晶質体を含む多結晶のリン化硼素系半導体から
なる導電性の低温緩衝層102 (C)リン化硼素系半導体層からなる下部障壁層103 (D)好ましくは下部障壁層103に格子整合する例え
ば、窒化ガリウム・インジウム(GaXIn1-XN:0≦
X≦1)(上記の特公昭55−3834号公報参照)ま
たは窒化リン化ガリウム(GaN1-YY:0≦Y≦1)
等のIII族窒化物半導体からなる発光層104 (E)リン化硼素系半導体からなる上部障壁層105
The laminated structure 1A for use in a double hetero (DH) structure type light emitting diode (LED) can basically be composed of the elements described in the following items (A) to (E). (A) n-type or p-type conductive conductive silicon (Si)
Alternatively, BP (see Japanese Patent Publication No. 55-3834), Ga
Substrate 101 made of P, GaAs, SiC, etc. (B) Low-temperature conductive conductive buffer layer 102 made of polycrystalline boron phosphide-based semiconductor containing amorphous material (C) Lower barrier layer made of boron phosphide-based semiconductor layer 103 (D) Preferably lattice-matched to the lower barrier layer 103. For example, gallium indium nitride (Ga x In 1-x N: 0 ≦
X ≦ 1) (see Japanese Patent Publication No. 55-3834 mentioned above) or gallium nitride phosphide (GaN 1-Y P Y : 0 ≦ Y ≦ 1)
Emitting layer 104 made of III-nitride semiconductor such as (E) Upper barrier layer 105 made of boron phosphide-based semiconductor

【0012】硼素(B)とリン(P)とを構成元素とし
て含むリン化硼素(BP)系半導体からなる低温緩衝層
102は、例えば、一般式BαAlβGaγIn1- α -
β - γ 1- δAsδ(0<α≦1、0≦β<1、0≦γ
<1、0<α+β+γ≦1、0≦δ<1)で表記される
リン化硼素系半導体から好適に構成できる。また、例え
ば、一般式BαAlβGaγIn1- α - β - γ1- δδ
(0<α≦1、0≦β<1、0≦γ<1、0<α+β+
γ≦1、0<δ<1)で表記される窒素(N)を含むリ
ン化硼素系半導体から構成できる。低温緩衝層102
は、好ましくは構成元素数が少なく、簡便に構成できる
2元結晶或いは3元混晶から構成する。例えば、単量体
リン化硼素(BP)、リン化アルミニウム・硼素混晶
(BαAlβP:0<α≦1、α+β=1)、リン化硼
素・ガリウム混晶(BαGaδP:0<α≦1、α+δ
=1)、或いはリン化硼素・インジウム混晶(BαIn
1- αP:0<α≦1)などから構成する。
Boron (B) and phosphorus (P) are constituent elements.
Temperature buffer layer made of boron phosphide (BP) based semiconductor containing
102 is, for example, the general formula BαAlβGaγIn1- α -
β - γP 1- δAsδ(0 <α ≦ 1, 0 ≦ β <1, 0 ≦ γ
<1, 0 <α + β + γ ≦ 1, 0 ≦ δ <1)
It can be preferably composed of a boron phosphide-based semiconductor. Also, for example
For example, general formula BαAlβGaγIn1- α - β - γP1- δNδ
(0 <α ≦ 1, 0 ≦ β <1, 0 ≦ γ <1, 0 <α + β +
Li containing nitrogen (N) represented by γ ≦ 1, 0 <δ <1)
It can be composed of a boron nitride semiconductor. Low temperature buffer layer 102
Preferably has a small number of constituent elements and can be simply constructed.
It is composed of a binary crystal or a ternary mixed crystal. For example, monomer
Boron phosphide (BP), aluminum phosphide-boron mixed crystal
(BαAlβP: 0 <α ≦ 1, α + β = 1), boron phosphide
Elemental-gallium mixed crystal (BαGaδP: 0 <α ≦ 1, α + δ
= 1) or boron phosphide / indium mixed crystal (BαIn
1- αP: 0 <α ≦ 1) or the like.

【0013】非晶質体を含む多結晶からなるリン化硼素
系半導体は、例えば、有機金属化学的気相堆積成長(M
OCVD)手段に依り、約250℃〜750℃で形成で
きる(米国特許6,194,744号参照)。特に、非
晶質体を含む多結晶の低温緩衝層102は、基板101
と下部障壁層103との格子不整合性を緩和して、ミス
フィット(misfit)転位等の結晶欠陥密度の小さ
い下部障壁層103をもたらす作用を発揮する(上記の
米国特許6、069、021号参照)。また、低温緩衝
層102を、下部障壁層103をなすリン化硼素系半導
体を構成する元素(構成元素)を含むリン化硼素半導体
から構成すると、その構成元素の「成長核」としての作
用により、連続性のある下部障壁層103の形成が促進
される利点がある。低温緩衝層102が単結晶層か非晶
質を含む多結晶層であるかは、例えば、一般的なX線回
折法、電子線回折法に依る回折像の解析から知ることが
できる。低温緩衝層102を構成する多結晶層の層厚は
望ましくは約1nm以上で500nm以下、更に望まし
くは2nm以上で100nm以下とする。
A boron phosphide-based semiconductor composed of a polycrystal containing an amorphous material is, for example, a metal organic chemical vapor deposition growth (M
It can be formed at about 250 ° C. to 750 ° C. by means of OCVD) (see US Pat. No. 6,194,744). In particular, the polycrystalline low temperature buffer layer 102 containing an amorphous material is used as the substrate 101.
The lattice mismatch between the lower barrier layer 103 and the lower barrier layer 103 is relaxed, and the lower barrier layer 103 having a low crystal defect density such as misfit dislocations is exerted (US Pat. No. 6,069,021). reference). When the low-temperature buffer layer 102 is composed of a boron phosphide semiconductor containing an element (constituent element) that constitutes the boron phosphide-based semiconductor forming the lower barrier layer 103, the constituent element acts as a “growth nucleus”. There is an advantage that the formation of the continuous lower barrier layer 103 is promoted. Whether the low-temperature buffer layer 102 is a single crystal layer or a polycrystalline layer containing amorphous can be known from, for example, analysis of a diffraction image by a general X-ray diffraction method or electron beam diffraction method. The thickness of the polycrystalline layer forming the low-temperature buffer layer 102 is preferably about 1 nm or more and 500 nm or less, and more preferably 2 nm or more and 100 nm or less.

【0014】本発明の第1の実施形態に係わる技術手段
の特徴は、低温緩衝層102に添加するp形またはn形
不純物を限定していることにある。低温緩衝層102を
構成する硼素(B)およびリン(P)以上の原子半径を
有する不純物は、その大きな原子半径故に、リン化硼素
(BP)系半導体結晶の内部でさして自由に移動できな
い。従って、基板材料内部への不純物の拡散を防止で
き、低温緩衝層102との接合界面近傍の領域に於ける
基板101の内部での歪みの発生を回避できる。硼素
(B)の原子半径(atomic radius)は約
0.98Åである。また、リン(P)の原子半径(=
r)は約1.28Åである。従って、第1の実施形態に
好適な低温緩衝層に添加するn形不純物として、例え
ば、Si(r=1.32Å)、ゲルマニウム(Ge;r
=1.37Å)、錫(Sn;r=1.62Å)、またp
形不純物として、亜鉛(Zn;r=1.38Å)、カド
ミウム(Cd;r=1.54Å)等のリン(P)以上の
原子半径を有する元素が例示できる。
A feature of the technical means according to the first embodiment of the present invention is that the p-type or n-type impurities added to the low temperature buffer layer 102 are limited. Impurities having an atomic radius greater than that of boron (B) and phosphorus (P) forming the low temperature buffer layer 102 cannot move freely inside the boron phosphide (BP) based semiconductor crystal because of the large atomic radius. Therefore, diffusion of impurities into the substrate material can be prevented, and occurrence of strain inside the substrate 101 in the region near the bonding interface with the low temperature buffer layer 102 can be avoided. The atomic radius of boron (B) is about 0.98Å. Also, the atomic radius of phosphorus (P) (=
r) is about 1.28Å. Therefore, as the n-type impurity added to the low temperature buffer layer suitable for the first embodiment, for example, Si (r = 1.32Å), germanium (Ge; r;
= 1.37Å), tin (Sn; r = 1.62Å), p
Examples of the form impurities include elements having an atomic radius of phosphorus (P) or more such as zinc (Zn; r = 1.38Å) and cadmium (Cd; r = 1.54Å).

【0015】また、特に導電性のシリコン(Si)単結
晶を基板として、その表面上に低温緩衝層102を設け
る構成にあって、低温緩衝層102に添加するp形また
はn形不純物を、基板101を構成する珪素(Si)原
子の原子半径(r=1.32Å)以上の元素とすると、
シリコン基板101の内部への不純物の浸透をも抑制で
き、シリコン基板101に導入される歪みや結晶欠陥を
減ずるに効果が奏される。硼素(r=0.98Å)、リ
ン(r=1.28Å)及び珪素(r=1.32Å)以上
の原子半径を有するn形またはp形不純物として、ゲル
マニウム(Ge;r=1.37Å)や亜鉛(Zn;r=
1.38Å)を例示できる。従って、本発明の第2の実
施形態の好例として、p形シリコン基板上に、亜鉛を添
加したp形リン化硼素(BP)からなる低温緩衝層を設
ける構成を挙げられる。
Further, in particular, in a structure in which a conductive silicon (Si) single crystal is used as a substrate and the low temperature buffer layer 102 is provided on the surface thereof, the p type or n type impurity added to the low temperature buffer layer 102 is removed from the substrate. Assuming that the element has an atomic radius (r = 1.32Å) or more of silicon (Si) atoms constituting 101,
Impurities can be suppressed from penetrating into the silicon substrate 101, and the strain and crystal defects introduced into the silicon substrate 101 can be effectively reduced. As an n-type or p-type impurity having an atomic radius of boron (r = 0.98Å), phosphorus (r = 1.28Å) or silicon (r = 1.32Å) or more, germanium (Ge; r = 1.37Å) And zinc (Zn; r =
1.38Å) can be illustrated. Therefore, as a good example of the second embodiment of the present invention, a structure in which a low temperature buffer layer made of p-type boron phosphide (BP) to which zinc is added is provided on a p-type silicon substrate.

【0016】本発明の第3の実施形態に係る発明は、p
形導電性の単結晶からなる基板101上に設けるに好適
なp形低温緩衝層102の構成を提供するものである。
亜鉛(Zn)は、硼素(B)、リン(P)及び珪素(S
i)よりも原子半径が大であり、リン化硼素系緩衝層1
02内部での移動が抑制される。また、例えば、シリコ
ン基板の内部にも拡散し難いため基板の表層部が乱雑と
なるのを防止できる。亜鉛(Zn)より原子半径を大と
する例えば、カドミウム(r=1.54Å)または水銀
(r=1.57Å)では、結晶内の移動はより抑制され
得る。しかし、結晶の格子間にこの様な原子半径の不純
物が侵入すると規則的な結晶格子が乱れる。このため、
不純物の電気的活性化が妨げられ、低い抵抗率のp形導
電性の低温緩衝層102を安定して得るに妨げとなる。
また、亜鉛(Zn)より、原子半径の大きな不純物の浸
透に因り結晶格子が乱れると、例えばLEDにあって、
逆方向耐圧の不良を発生させるため好ましくない。
The invention according to the third embodiment of the present invention is p
A p-type low temperature buffer layer 102 suitable for being provided on a substrate 101 made of a conductive type single crystal is provided.
Zinc (Zn) is boron (B), phosphorus (P) and silicon (S).
The atomic radius is larger than that of i), and the boron phosphide-based buffer layer 1
02 Movement inside 02 is suppressed. Further, for example, since it is difficult to diffuse into the inside of the silicon substrate, it is possible to prevent the surface layer portion of the substrate from becoming disordered. For example, cadmium (r = 1.54Å) or mercury (r = 1.57Å) having an atomic radius larger than that of zinc (Zn) can further suppress the movement in the crystal. However, if an impurity having such an atomic radius enters between the crystal lattices, the regular crystal lattice is disturbed. For this reason,
The electrical activation of impurities is hindered, which hinders stable low-resistivity p-type low-temperature buffer layer 102 from being obtained.
Further, when the crystal lattice is disturbed due to the penetration of impurities having a larger atomic radius than zinc (Zn), for example, in an LED,
It is not preferable because it causes a reverse breakdown voltage failure.

【0017】低温緩衝層102から基板101の表層領
域へ浸透、拡散する低温緩衝層102に添加した不純物
の原子濃度並びに濃度分布は、例えば2次イオン質量分
析法(SIMS)等の分析手段により解析できる。ま
た、低温緩衝層102との接合界面近傍の基板101の
内での歪み、積層欠陥等の結晶欠陥の発生の模様は、例
えば透過型電子顕微鏡(TEM)を利用した断面TEM
技法により解析できる。断面TEM像にあって、歪みの
存在は明視野像に於ける黒色コントラストとして認めら
れる。
The atomic concentration and concentration distribution of impurities added to the low temperature buffer layer 102 that permeates and diffuses from the low temperature buffer layer 102 into the surface layer region of the substrate 101 are analyzed by an analyzing means such as secondary ion mass spectrometry (SIMS). it can. The pattern of strain and crystal defects such as stacking faults in the substrate 101 near the bonding interface with the low-temperature buffer layer 102 is a cross-sectional TEM using, for example, a transmission electron microscope (TEM).
It can be analyzed by the technique. In the cross-sectional TEM image, the presence of distortion is recognized as black contrast in the bright field image.

【0018】本発明の第4の実施形態に係る発明は、特
に発光素子用途の積層構造体に関する好適な構成を提供
する。即ち、非晶質体を含む多結晶のリン化硼素系半導
体からなる低温緩衝層102上には、特に結晶性に優れ
るリン化硼素系半導体層を積層され得ることを利用して
積層構造体を構成するものである。特に、導電性に優れ
るリン化硼素系半導体層は例えば、下部障壁層103と
して好適に利用できる。
The invention according to the fourth embodiment of the present invention provides a preferable structure particularly for a laminated structure for use in a light emitting device. That is, a laminated structure is formed by utilizing the fact that a boron phosphide-based semiconductor layer having particularly excellent crystallinity can be laminated on the low-temperature buffer layer 102 made of a polycrystalline boron phosphide-based semiconductor containing an amorphous material. It is what constitutes. In particular, a boron phosphide-based semiconductor layer having excellent conductivity can be suitably used as the lower barrier layer 103, for example.

【0019】本発明の第4の実施形態では、リン化硼素
系半導体層(例えば、下部障壁層103)は、750℃
を越え1200℃以下の温度で低温緩衝層102上に形
成した単結晶層から構成するのが適する。1200℃を
越える高温では、例えば、B132等の多量体のリン化
硼素が形成され易くなり、組成的に均質なリン化硼素系
半導体層の形成が阻害され好ましくはない(J.Am.
Ceramic Soc.,47(1)(1964)、
44〜46頁参照)。特に、好ましくは800℃〜95
0℃の温度で形成した、例えば、基板101の表面に平
行に配列した{110}結晶面から主に構成されるリン
化硼素系半導体層から構成する。
In the fourth embodiment of the present invention, the boron phosphide-based semiconductor layer (eg, the lower barrier layer 103) is 750 ° C.
A single crystal layer formed on the low-temperature buffer layer 102 at a temperature of over 1,200 ° C. is suitable. At a high temperature of more than 1200 ° C., for example, a polymeric boron phosphide such as B 13 P 2 is easily formed, which hinders the formation of a compositionally uniform boron phosphide-based semiconductor layer, which is not preferable (J. Am. .
Ceramic Soc. , 47 (1) (1964),
See pages 44-46). Particularly preferably 800 ° C to 95
For example, it is formed of a boron phosphide-based semiconductor layer mainly formed of {110} crystal planes arranged in parallel with the surface of the substrate 101, which is formed at a temperature of 0 ° C.

【0020】導電率の制御されたリン化硼素系半導体層
は、p形またはn形不純物を添加して得ることができ
る。導電性のリン化硼素系半導体層を得るには、低温緩
衝層102と同一の不純物も利用できる。例えば、珪素
(Si)ドープn形低温緩衝層102上に、同じくSi
をドーパント(dopant)としてリン化硼素系半導
体層を積層させる例を挙げられる。リン化硼素系半導体
層(例えば、下部障壁層103)については、低温緩衝
層102により基板101とは距離的に隔離されている
ため、上記以外の原子半径を有する不純物をも利用でき
る。導電性のリン化硼素系半導体層を得るに好適な不純
物では、原子半径の大小よりも、”浅い”ドナ(don
or)またはアクセプタ(acceptor)準位を形
成する不純物であることが重要である。例えば、p形の
リン化硼素系半導体層を得るに好適に利用できる不純物
としてマグネシウム(Mg)、ベリリウム(Be)を例
示できる。p形伝導層の低温緩衝層102とリン化硼素
系半導体層とから積層構造を構成するに際し、特に好適
なのは低温緩衝層102のp形ドーパントを亜鉛(Z
n)とし、リン化硼素系半導体層のp形ドーパントをマ
グネシウム(Mg)とする場合である。
The boron phosphide-based semiconductor layer with controlled conductivity can be obtained by adding p-type or n-type impurities. In order to obtain a conductive boron phosphide-based semiconductor layer, the same impurities as the low temperature buffer layer 102 can be used. For example, on the silicon (Si) -doped n-type low temperature buffer layer 102, the same Si
An example in which a boron phosphide-based semiconductor layer is laminated using s as a dopant. Since the boron phosphide-based semiconductor layer (for example, the lower barrier layer 103) is separated from the substrate 101 by the low temperature buffer layer 102 in distance, it is possible to use impurities having an atomic radius other than the above. Impurities suitable for obtaining an electrically conductive boron phosphide-based semiconductor layer include “shallow” don's rather than atomic radii.
or) or an acceptor that forms an acceptor level. For example, magnesium (Mg) and beryllium (Be) can be exemplified as impurities that can be preferably used to obtain a p-type boron phosphide-based semiconductor layer. In forming a laminated structure from the low-temperature buffer layer 102 of the p-type conductive layer and the boron phosphide-based semiconductor layer, it is particularly preferable to use zinc (Z) as the p-type dopant of the low-temperature buffer layer 102.
n), and the p-type dopant of the boron phosphide-based semiconductor layer is magnesium (Mg).

【0021】750℃〜1200℃において、(1)成
長速度を毎分2nm以上で30nm以下とし、(2)V
族原料とIII族原料との供給比率(V/III比)を
好ましくは15以上で60以下として形成した単量体の
リン化硼素は、室温での禁止帯幅(band gap)
が3.0±0.2eVと高く、障壁層として好適に利用
できる。また、この高い禁止帯幅のリン化硼素を基材と
したリン化硼素系半導体からも障壁層を構成できる。例
えば、禁止帯幅を3.1eVとする単量体リン化硼素
(BP)とリン化ガリウム(GaP:室温での禁止帯幅
≒2.3eV)との混晶である、室温での禁止帯幅を約
2.7eVとする窒化リン化ガリウム混晶(B0.50Ga
0.50P)から好適に下部障壁層103を構成できる。禁
止帯幅は例えば、屈折率(=n)と消衰係数(=k)か
ら求められる複素誘電率の虚数部(ε 2=2・n・k)
の光エネルギー依存性から求められる。
At 750 ° C to 1200 ° C, (1)
Long speed is 2nm or more per minute and 30nm or less, and (2) V
The supply ratio (V / III ratio) of group III raw material and group III raw material
Preferably, the monomer is formed as 15 or more and 60 or less.
Boron phosphide has a band gap at room temperature.
Is as high as 3.0 ± 0.2 eV and is suitable for use as a barrier layer.
it can. In addition, this high bandgap boron phosphide as a base material
The barrier layer can be formed also from the boron phosphide-based semiconductor. An example
For example, monomeric boron phosphide having a bandgap of 3.1 eV
(BP) and gallium phosphide (GaP: bandgap at room temperature)
≈ 2.3 eV), which is a mixed crystal with a bandgap at room temperature of about
2.7 eV gallium nitride phosphide mixed crystal (B0.50Ga
0.50The lower barrier layer 103 can be preferably formed from P). Prohibition
The tongue width is, for example, the refractive index (= n) and the extinction coefficient (= k)
The imaginary part of the complex permittivity (ε 2= 2 ・ n ・ k)
It is required from the light energy dependence of.

【0022】また、低温緩衝層102との接合界面で低
温緩衝層102と同一の格子定数を有し、且つ、発光層
104側の表面で発光層104に格子整合するリン化硼
素系半導体層は、ミスフィット(misfit)転位、
積層欠陥等の結晶欠陥密度の低い良質の発光層104を
もたらすに貢献できる。緩衝層102及び発光層104
の双方の層に格子整合するリン化硼素系半導体層は、硼
素(B)等の第III族の若しくはリン(P)等の第V
族の構成元素の組成に勾配を付した組成勾配層から構成
できる(特開2000−22211号公報参照)。構成
元素の組成勾配は、層厚の増加方向に一律に、または段
階的に、或いは非直線的に増減させる何れの様式でも付
すことができる。例えば、シリコン基板101に格子整
合するリン化硼素・ガリウム混晶(B0.02Ga0.98P)
からなる低温緩衝層102上に、緩衝層102との接合
面から例えば、窒化ガリウム・インジウム(Ga0.90
0. 10N:格子定数≒4.557Å)からなる発光層1
04との接合面に向けて、硼素組成比(=X)を0.0
2からを0.98に直線的に増加させたリン化硼素・ガ
リウム組成勾配層(BαGaδP:α=0.02→0.
98、対応してδ=0.98→0.02)から構成でき
る。
Further, a boron phosphide-based semiconductor layer having the same lattice constant as that of the low temperature buffer layer 102 at the junction interface with the low temperature buffer layer 102 and having a lattice matching with the light emitting layer 104 on the surface of the light emitting layer 104 side is formed. , Misfit rearrangement,
This can contribute to providing a high-quality light emitting layer 104 having a low density of crystal defects such as stacking faults. Buffer layer 102 and light emitting layer 104
A boron phosphide-based semiconductor layer lattice-matched to both layers of the above is a group III group such as boron (B) or a group V group such as phosphorus (P).
It can be composed of a composition gradient layer in which the composition of the constituent elements of the group has a gradient (see JP-A-2000-22211). The composition gradient of the constituent elements can be added uniformly, stepwise, or non-linearly in the increasing direction of the layer thickness. For example, a mixed crystal of boron phosphide and gallium (B 0.02 Ga 0.98 P) lattice-matched to the silicon substrate 101.
On the low temperature buffer layer 102 made of, for example, gallium indium nitride (Ga 0.90 I).
n 0. 10 N: luminescent layer 1 made of a lattice constant ≒ 4.557Å)
A boron composition ratio (= X) of 0.0
2 to 0.98 and the boron phosphide / gallium composition gradient layer (B α Ga δ P: α = 0.02 → 0.
98, and correspondingly δ = 0.98 → 0.02).

【0023】発光層104は、例えば、青色帯の短波長
可視光を放射できる窒化ガリウム・インジウム(GaX
In1-XN:0≦X≦1)等のIII族窒化物半導体か
ら構成する(上記の特公昭55−3834号公報参
照)。また、窒化リン化ガリウム(GaN1-XX:0≦
X≦1)から構成できる(Appl.Phys.Let
t.,60(20)(1992)、2540〜2542
頁参照)。また、砒化窒化ガリウム(GaN1-XAsX
0≦X≦1)から構成できる。発光層104は、これら
のIII−V族化合物半導体層を井戸(well)層と
する単一(single)または多重(multi)量
子井戸(quantum well)構造から構成でき
る。量子井戸構造から構成された発光層104からは単
色性の良好な発光がもたらされる利点がある。
The light emitting layer 104 is, for example, gallium indium nitride (Ga X) capable of emitting short wavelength visible light in the blue band.
In 1-X N: 0 ≦ X ≦ 1) or other group III nitride semiconductor (see Japanese Patent Publication No. 55-3834). In addition, gallium nitride phosphide (GaN 1-X P X : 0 ≦
X ≦ 1) (Appl.Phys.Let)
t. , 60 (20) (1992), 2540-2542.
See page). Further, gallium arsenide nitride (GaN 1-X As X :
0 ≦ X ≦ 1). The light emitting layer 104 may have a single or multiple quantum well structure in which these group III-V compound semiconductor layers are used as a well layer. The light emitting layer 104 formed of the quantum well structure has an advantage of emitting light with good monochromaticity.

【0024】発光層104上に、上部障壁層105を設
ければ、ダブルヘテロ(DH)構造型の発光部を構成で
きる。上部障壁層105は、上記の室温での禁止帯幅を
3.0±0.2eVとする単量体のリン化硼素及びそれ
を基材としたリン化硼素系混晶から構成できる。また、
窒化ガリウム(GaN)或いは窒化アルミニウム・ガリ
ウム混晶(AlXGa1-XN:0<X<1)等のIII族
窒化物半導体から構成できる。
If the upper barrier layer 105 is provided on the light emitting layer 104, a double hetero (DH) structure type light emitting portion can be formed. The upper barrier layer 105 can be composed of a monomeric boron phosphide having a bandgap of 3.0 ± 0.2 eV at room temperature and a boron phosphide-based mixed crystal based on the same. Also,
It can be composed of a group III nitride semiconductor such as gallium nitride (GaN) or an aluminum nitride / gallium mixed crystal (Al x Ga 1-x N: 0 <X <1).

【0025】本発明に係わるダブルヘテロ接合構造型の
LED1Bは、例えば上部障壁層105上にオーミック
性の表面電極106を設け、また、基板101の裏面に
オーミック性の裏面電極107を配置して構成する。上
部障壁層105をリン化硼素系半導体から構成した場
合、p形オーミック電極は、例えば、金・亜鉛(Au・
Zn)合金、金・ベリリウム(Au・Be)合金等から
構成できる。また、金・ゲルマニウム(Au・Ge)合
金、金・インジウム(Au・In)合金、並びに金・錫
(Au・Sn)合金などの金合金等からn形オーミック
電極を形成できる。良好なオーミック接触性を発揮する
電極を形成するために、表面電極106を良導性のコン
タクト(contact)層上に設けることもできる。
本発明に係わる高い禁止帯幅のリン化硼素系半導体層か
らは、発光を取り出し方向に透過する窓層を兼用する表
面オーミック電極106用途のコンタクト層を好適に構
成できる。
The LED 1B of the double heterojunction structure according to the present invention is constructed by providing an ohmic front surface electrode 106 on the upper barrier layer 105 and disposing an ohmic back surface electrode 107 on the back surface of the substrate 101. To do. When the upper barrier layer 105 is made of a boron phosphide-based semiconductor, the p-type ohmic electrode is formed of, for example, gold / zinc (Au /
Zn) alloy, gold / beryllium (Au / Be) alloy, or the like. Further, the n-type ohmic electrode can be formed from a gold alloy such as a gold-germanium (Au.Ge) alloy, a gold-indium (Au.In) alloy, and a gold-tin (Au.Sn) alloy. The surface electrode 106 may be provided on the contact layer having good conductivity in order to form an electrode exhibiting good ohmic contact.
From the boron phosphide-based semiconductor layer having a high bandgap according to the present invention, a contact layer for use as the surface ohmic electrode 106, which also serves as a window layer for transmitting emitted light in the extraction direction, can be preferably formed.

【0026】本発明に係わるランプ10は、例えば、次
の如くの手順をもって構成できる。図2に例示する如
く、例えば、LED1Bを、台座15上の銀(Ag)或
いはアルミニウム(Al)等の金属を鍍金した金属性碗
体16の中央部に、導電性の接合材で固定する。これよ
り、LED1Bを構成するために利用した導電性の基板
11の裏面に設けた裏面電極14を台座15に付属する
一端子17に電気的に接続させる。また、LED1Bの
例えば、上部障壁層12上に設置した表面電極13を台
座15に付属する他の一方の端子18に結線する。次ぎ
に、LED1Bをエポキシ樹脂等の封止材料で囲繞して
ランプとする。
The lamp 10 according to the present invention can be constructed, for example, by the following procedure. As illustrated in FIG. 2, for example, the LED 1B is fixed to a central portion of a metallic bowl body 16 plated with a metal such as silver (Ag) or aluminum (Al) on the pedestal 15 with a conductive bonding material. As a result, the back surface electrode 14 provided on the back surface of the conductive substrate 11 used to form the LED 1B is electrically connected to the one terminal 17 attached to the pedestal 15. Further, for example, the surface electrode 13 provided on the upper barrier layer 12 of the LED 1B is connected to the other one terminal 18 attached to the pedestal 15. Next, the LED 1B is surrounded by a sealing material such as epoxy resin to form a lamp.

【0027】また、本発明に係わるランプ10を集合さ
せれば、光源を構成できる。例えば、複数のランプ10
を電気的に並列に接続させて、定電圧駆動型の光源を構
成できる。また、電気的に直列にランプを接続して定電
流駆動型の光源を構成できる。これらの光源は、従来の
白熱蛍光型ランプに比較して、点灯に電力を要しないた
め、低消費電力型でしかも長寿命の光源として特に有用
に利用できる。例えば、室内照明用光源として利用でき
る。また、例えば、屋外表示器用途や間接照明用途の光
源として利用できる。
A light source can be constructed by assembling the lamps 10 according to the present invention. For example, a plurality of lamps 10
Can be electrically connected in parallel to form a constant voltage drive type light source. Further, a constant current drive type light source can be configured by electrically connecting lamps in series. These light sources do not require electric power for lighting as compared with conventional incandescent fluorescent lamps, and thus can be particularly usefully utilized as light sources of low power consumption and long life. For example, it can be used as a light source for indoor lighting. Further, for example, it can be used as a light source for outdoor display applications and indirect lighting applications.

【0028】[0028]

【実施例】(第1実施例)本実施例では、p形珪素(S
i)単結晶基板上にp形不純物を添加したリン化硼素系
半導体からなる低温緩衝層を備えた積層構造体から、青
色LEDを構成する場合を例にして、本発明を具体的に
説明する。
EXAMPLE (First Example) In this example, p-type silicon (S
i) The present invention will be specifically described with reference to a case where a blue LED is formed from a laminated structure including a low temperature buffer layer made of a boron phosphide-based semiconductor to which a p-type impurity is added, on a single crystal substrate. .

【0029】本第1実施例に係わるLED2Bの断面模
式図を図3に示す。LED2Bは、次記の(1)項に記
す基板101上に順次、(2)〜(5)項に記載の機能
層を積層させた積層構造体2Aに、(6)〜(7)項に
記載のオーミック性の表面及び裏面電極を配置して構成
した。 (1)硼素(B)ドープでp形の(111)面を有する
Si単結晶基板101 (2)トリエチル硼素((C253B)/ホスフィン
(PH3)/水素(H2)系常圧MOCVD法により35
0℃で成長させた、亜鉛(Zn;原子半径(r)≒1.
38Å)ドープの非晶質を主体とした多結晶のリン化硼
素(BP)からなる低温緩衝層102。低温緩衝層10
2中の亜鉛の原子濃度は4×1018cm-3とし、層厚は
25nmとした。 (3)上記のMOCVD気相成長手段を利用して、85
0℃でマグネシウム(Mg)をドーピングした、基板1
01表面に略平行に配列した{110}結晶面から主に
なるp形リン化硼素(BP)からなる下部障壁層103
(キャリア濃度≒4×1018cm-3、層厚≒700n
m) (4)立方晶のn形Ga0.94In0.06N層(格子定数=
4.538Å)から主になる発光層104(キャリア濃
度≒4×1017cm-3、層厚≒180nm) (5)上記のMOCVD反応系により400℃で成長さ
せた、室温での禁止帯幅を3.1eVとする、非晶質を
主体とする珪素(Si)ドープn形のリン化硼素(B
P)層からなる上部障壁層105(キャリア濃度≒6×
1016cm-3、層厚≒650nm) (6)上部障壁層105の中央に配置した金・ゲルマニ
ウム(Au・Ge)円形電極(直径=120μm)から
なるオーミック性の表面電極106 (7)p形Si基板101の裏面の略全面に設けた、ア
ルミニウム(Al)からなるオーミック性の裏面電極1
07。
FIG. 3 is a schematic sectional view of the LED 2B according to the first embodiment. The LED 2B has the same structure as the laminated structure 2A in which the functional layers described in (2) to (5) are sequentially laminated on the substrate 101 described in (1) below, and the LEDs (2) to (6) to (7). The ohmic front and back electrodes described above were arranged and configured. (1) Boron (B) -doped Si single crystal substrate 101 having p-type (111) plane 101 (2) Triethylboron ((C 2 H 5 ) 3 B) / phosphine (PH 3 ) / hydrogen (H 2 ) By atmospheric pressure MOCVD method
Zinc (Zn; atomic radius (r) ≈1.
38 Å) Low temperature buffer layer 102 made of polycrystalline boron phosphide (BP) mainly composed of doped amorphous. Low temperature buffer layer 10
The atomic concentration of zinc in 2 was 4 × 10 18 cm −3 , and the layer thickness was 25 nm. (3) Using the MOCVD vapor phase growth means described above, 85
Substrate 1 doped with magnesium (Mg) at 0 ° C.
01 lower barrier layer 103 mainly made of p-type boron phosphide (BP) having {110} crystal planes arranged substantially parallel to the surface
(Carrier concentration ≈ 4 × 10 18 cm -3 , layer thickness ≈ 700 n
m) (4) Cubic n-type Ga 0.94 In 0.06 N layer (lattice constant =
4.538Å) as the main emission layer 104 (carrier concentration ≈ 4 × 10 17 cm -3 , layer thickness ≈ 180 nm) (5) Forbidden band width at room temperature grown by the MOCVD reaction system at 400 ° C. Is 3.1 eV and is mainly composed of amorphous silicon (Si) -doped n-type boron phosphide (B
P) layer upper barrier layer 105 (carrier concentration ≈ 6 ×
10 16 cm -3 , layer thickness ≈ 650 nm) (6) Ohmic surface electrode 106 (7) p made of gold-germanium (Au.Ge) circular electrode (diameter = 120 μm) arranged in the center of the upper barrier layer 105. Ohmic back electrode 1 made of aluminum (Al) provided on almost the entire back surface of the Si substrate 101
07.

【0030】2次イオン質量分析法に依り、深さ方向の
亜鉛(Zn)の原子濃度を測定したところ、低温での緩
衝層102の成長後において、Si基板101内部への
亜鉛不純物の浸透は殆ど確認されなかった。また、高温
(=850℃)での成長過程を経て積層構造体2Aを構
成した後においても、Si基板101への内部への亜鉛
の浸透距離は高々、50nm以内となった。また、透過
型電子顕微鏡(TEM)を利用した明視野断面TEM技
法に依る解析では、低温緩衝層102と接合をなすSi
基板101の表層部には、歪みに因る黒色コントラスト
も特に視認されなかった。
The atomic concentration of zinc (Zn) in the depth direction was measured by secondary ion mass spectrometry. As a result, it was confirmed that the zinc impurities did not penetrate into the Si substrate 101 after the buffer layer 102 was grown at a low temperature. Almost never confirmed. Even after the laminated structure 2A was configured through the growth process at high temperature (= 850 ° C.), the permeation distance of zinc into the Si substrate 101 was at most 50 nm. In addition, in the analysis by the bright field cross-section TEM technique using a transmission electron microscope (TEM), Si that forms a junction with the low temperature buffer layer 102.
In the surface layer portion of the substrate 101, black contrast due to strain was not particularly visible.

【0031】構成された青色LED2Bは、次の(a)
〜(d)項に記載の特性を呈する高輝度のLEDとなっ
た。 (a)発光中心波長:410nm (b)輝度:6ミリカンデラ(mcd) (c)順方向電圧:3ボルト(V)(順方向電流=20
mA) (d)逆方向電圧:8V(逆方向電流=10μA) 特に、低温緩衝層102に添加した亜鉛(Zn)のSi
基板101内部への拡散が抑制され、低温緩衝層102
との接合界面の近傍の領域でSi基板101が乱雑とな
るのが回避されたため、LED2Bに逆方向電圧を印加
した際の局所的な耐圧の不良(ローカルブレイクダウ
ン:local breakdown)は殆ど認められ
なかった。
The constructed blue LED 2B has the following (a)
It became a high-brightness LED exhibiting the characteristics described in (d). (A) Emission center wavelength: 410 nm (b) Brightness: 6 millicandelas (mcd) (c) Forward voltage: 3 V (V) (forward current = 20
mA) (d) Reverse voltage: 8 V (reverse current = 10 μA) Particularly, Si of zinc (Zn) added to the low temperature buffer layer 102.
The diffusion into the substrate 101 is suppressed, and the low temperature buffer layer 102
Since the Si substrate 101 was prevented from becoming disordered in the region near the junction interface with and, the local breakdown voltage (local breakdown) when the reverse voltage was applied to the LED 2B was almost recognized. There wasn't.

【0032】(第2実施例)本実施例では、n形Si単
結晶基板上にn形不純物を添加したリン化硼素系半導体
からなる低温緩衝層を備えた積層構造体から、青色LE
Dを構成する場合を例にして本発明を具体的に説明す
る。
(Second Embodiment) In this embodiment, a blue LE is obtained from a laminated structure having a low temperature buffer layer made of an n-type impurity-doped boron phosphide-based semiconductor on an n-type Si single crystal substrate.
The present invention will be specifically described by taking the case of configuring D as an example.

【0033】本第2実施例では、次記の(1)項に記す
基板上に順次、(2)〜(5)項に記載の機能層を積層
させた積層構造体に、(6)〜(7)項に記載のオーミ
ック性の表面及び裏面電極を配置して構成した。 (1)アンチモン(Sb)ドープでn形の(100)面
を有するSi単結晶基板 (2)トリエチル硼素((C253B)/ホスフィン
(PH3)/水素(H2)系常圧MOCVD法により40
0℃で成長させた、錫(Sn:r≒1.62Å)ドープ
の非晶質を主体とした、基板のSiと同一の格子定数の
リン化硼素・インジウム(B0.67In0.33P:格子定数
≒5.431Å)からなる多結晶の低温緩衝層。低温緩
衝層の内部の2次イオン質量分析法(SIMS)に依る
錫(Sn)の原子濃度は2×1018cm-3とした。ま
た、層厚は35nmとした。 (3)上記のMOCVD気相成長手段を利用して、80
0℃で珪素(Si)をドーピングした、(100)基板
表面に略平行に配列した{110}結晶面から主になる
n形リン化硼素・インジウム(BXIn1-XP:X=0.
33→0.99)組成勾配層からなる下部障壁層(キャ
リア濃度≒1×1018cm-3、層厚≒520nm)。組
成勾配層の硼素(B)組成比(=X)は、低温緩衝層と
の接合界面で0.33とし、それより発光層との接合界
面に向けて0.99と一律に増加させてある。 (4)800℃で成長させた、B0.99In0.01Pと同一
の格子定数を有する立方晶のn形Ga0.90In0.10N層
(格子定数=4.557Å)から主になる発光層(キャ
リア濃度≒5×1017cm-3、層厚≒95nm)。 (5)上記のMOCVD反応系により350℃で成長さ
せた、室温での禁止帯幅を3.0eVとする、非晶質を
主体とするマグネシウム(Mg)ドープp形リン化硼素
・インジウム混晶(B0.99In0.01P)層からなる上部
障壁層(キャリア濃度≒9×1016cm-3、層厚≒70
0nm) (6)上部障壁層の中央に配置した金・亜鉛(Au・Z
n)円形電極(直径=130μm)からなるオーミック
性の表面電極 (7)n形Si基板の裏面の略全面に設けた、アルミニ
ウム(Al)からなるオーミック性の裏面電極。
In the second embodiment, (6) to (6) are added to the laminated structure in which the functional layers described in (2) to (5) are sequentially laminated on the substrate described in (1) below. The ohmic front and back electrodes as described in the item (7) are arranged and configured. (1) Antimony (Sb) -doped Si single crystal substrate having an n-type (100) plane (2) Triethylboron ((C 2 H 5 ) 3 B) / phosphine (PH 3 ) / hydrogen (H 2 ) system 40 by atmospheric pressure MOCVD method
Boron phosphide / indium (B 0.67 In 0.33 P: lattice constant) having the same lattice constant as that of Si of the substrate, which is mainly composed of tin (Sn: r≈1.62Å) -doped amorphous material grown at 0 ° C. A polycrystalline low temperature buffer layer consisting of ≈5.431 Å). The atomic concentration of tin (Sn) determined by secondary ion mass spectrometry (SIMS) inside the low-temperature buffer layer was set to 2 × 10 18 cm −3 . The layer thickness was 35 nm. (3) Using the MOCVD vapor phase growth means described above, 80
0 doped with silicon (Si) at ° C., (100) substantially in parallel arranged to the substrate surface {110} n-type boron indium phosphide composed mainly of crystal plane (B X In 1-X P : X = 0 .
33 → 0.99) Lower barrier layer composed of a composition gradient layer (carrier concentration≈1 × 10 18 cm −3 , layer thickness≈520 nm). The boron (B) composition ratio (= X) of the composition gradient layer is 0.33 at the bonding interface with the low-temperature buffer layer, and is uniformly increased to 0.99 toward the bonding interface with the light emitting layer. . (4) Emission layer (carrier concentration) mainly composed of cubic n-type Ga 0.90 In 0.10 N layer (lattice constant = 4.557Å) grown at 800 ° C. and having the same lattice constant as B 0.99 In 0.01 P ≈5 × 10 17 cm -3 , layer thickness ≈95 nm). (5) Magnesium (Mg) -doped p-type boron phosphide / indium mixed crystal mainly composed of amorphous material, which is grown at 350 ° C. by the MOCVD reaction system and has a band gap at room temperature of 3.0 eV Upper barrier layer consisting of (B 0.99 In 0.01 P) layer (carrier concentration ≈ 9 × 10 16 cm −3 , layer thickness ≈ 70
0 nm) (6) Gold / Zinc (Au / Z) arranged in the center of the upper barrier layer
n) Ohmic front surface electrode made of circular electrode (diameter = 130 μm) (7) Ohmic back surface electrode made of aluminum (Al) provided on substantially the entire back surface of the n-type Si substrate.

【0034】2次イオン質量分析法に依り、深さ方向の
錫(Sn)の原子濃度を測定したところ、低温での緩衝
層の成長後において、Si基板内部への錫(Sn)原子
の浸透は殆ど確認されなかった。また、高温(=800
℃)での成長過程を経て積層構造体を構成した後におい
ても、Si基板への内部への亜鉛の浸透距離は高々、2
0nm以内となった。また、透過型電子顕微鏡(TE
M)を利用した明視野断面TEM技法に依る解析では、
低温緩衝層と接合をなすSi基板の表層部には、錫(S
n)の浸透に伴う歪みに因る黒色コントラストも特に視
認されなかった。
When the atomic concentration of tin (Sn) in the depth direction was measured by secondary ion mass spectrometry, the penetration of tin (Sn) atoms into the Si substrate was observed after the buffer layer was grown at a low temperature. Was hardly confirmed. Also, high temperature (= 800
The permeation distance of zinc into the Si substrate is at most 2 even after the laminated structure is formed through the growth process at
It was within 0 nm. In addition, a transmission electron microscope (TE
In the analysis by the bright field cross-section TEM technique using M),
The surface layer of the Si substrate forming a bond with the low-temperature buffer layer has tin (S)
The black contrast due to the distortion accompanying the penetration of n) was not particularly visible.

【0035】上記の手段に依れば、次の(a)〜(d)
項に記載の特性を呈する高輝度の青色LEDが提供され
た。 (a)発光中心波長:430nm (b)輝度:8ミリカンデラ(mcd) (c)順方向電圧:3ボルト(V)(順方向電流=20
mA) (d)逆方向電圧:8V(逆方向電流=10μA) 特に、低温緩衝層に添加した錫(Sn)のSi基板内部
への拡散が抑制され、低温緩衝層との接合界面の近傍の
領域でSi基板が乱雑となるのが回避されたため、逆方
向電圧を印加した際の局所的な耐圧の不良(local
breakdown)は殆ど認められなかった。
According to the above means, the following (a) to (d)
A high brightness blue LED having the characteristics described in the above paragraph is provided. (A) Central emission wavelength: 430 nm (b) Brightness: 8 millicandelas (mcd) (c) Forward voltage: 3 V (V) (forward current = 20
mA) (d) Reverse voltage: 8 V (reverse current = 10 μA) In particular, diffusion of tin (Sn) added to the low-temperature buffer layer into the Si substrate is suppressed, and the vicinity of the junction interface with the low-temperature buffer layer is suppressed. Since the Si substrate was prevented from becoming disordered in the region, local breakdown voltage failure (local) when a reverse voltage was applied.
Almost no breakdown was observed.

【0036】[0036]

【発明の効果】本発明に依れば、リン化硼素(BP)系
半導体層からなる非晶質を含む多結晶の低温緩衝層に添
加する不純物をリン(P)原子よりも原子半径を大とす
る元素としたので、低温緩衝層内部での不純物の移動が
避けられ、しいては、低温緩衝層との接合領域において
基板結晶が乱雑となるのを回避できるため、耐圧に優れ
る高輝度の発光素子を提供できる。
According to the present invention, impurities added to a polycrystalline low temperature buffer layer containing an amorphous material composed of a boron phosphide (BP) based semiconductor layer have an atomic radius larger than that of phosphorus (P) atoms. Since the element is used as the element, the movement of impurities inside the low temperature buffer layer can be avoided, and since it is possible to prevent the substrate crystal from becoming disordered in the junction region with the low temperature buffer layer, it is possible to achieve high withstand voltage with high brightness. A light emitting device can be provided.

【0037】特に、本発明に依れば、導電性のシリコン
単結晶基板上にリン化硼素系半導体からなる低温緩衝層
を設ける構成にあって、低温緩衝層に添加する不純物を
硼素、リン及び珪素(Si)の何れよりも原子半径を大
とする元素としたので、不純物の低温緩衝層内部での移
動、並びにシリコン単結晶基板内部への浸透が抑制され
るため、低温緩衝層との接合界面近傍の領域でSi基板
が乱雑となるのを防止でき、従って、耐圧特性に優れる
発光素子を提供できる。
In particular, according to the present invention, in a structure in which a low temperature buffer layer made of a boron phosphide-based semiconductor is provided on a conductive silicon single crystal substrate, impurities added to the low temperature buffer layer are boron, phosphorus and Since the element whose atomic radius is larger than that of silicon (Si) is used, movement of impurities inside the low-temperature buffer layer and permeation into the silicon single crystal substrate are suppressed, so that bonding with the low-temperature buffer layer is achieved. It is possible to prevent the Si substrate from becoming disordered in the region near the interface, and thus it is possible to provide a light emitting element having excellent withstand voltage characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係わるLED用途の積層構造体の断面
模式図である。
FIG. 1 is a schematic sectional view of a laminated structure for LED application according to the present invention.

【図2】本発明に係わるランプの構造を示す断面模式図
である。
FIG. 2 is a schematic sectional view showing the structure of a lamp according to the present invention.

【図3】本発明の第1実施例に係わるLEDの断面模式
図である。
FIG. 3 is a schematic sectional view of an LED according to the first embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1A、2A 積層構造体 1B、2B LED 10 ランプ 11 基板 12 上部障壁層 13 表面電極 14 裏面電極 15 台座 16 碗体 17、18 端子 19 封止樹脂 101 単結晶基板 102 低温緩衝層 103 下部障壁層 104 発光層 105 上部障壁層 106 表面電極 107 裏面電極 1A, 2A laminated structure 1B, 2B LED 10 lamps 11 board 12 Upper barrier layer 13 Surface electrode 14 Back electrode 15 pedestal 16 bowl 17, 18 terminals 19 Sealing resin 101 single crystal substrate 102 low temperature buffer layer 103 Lower barrier layer 104 light emitting layer 105 upper barrier layer 106 surface electrode 107 Back electrode

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】導電性の単結晶からなる基板と、該基板の
表面上に設けられた、硼素(B)とリン(P)とを構成
元素として含むリン化硼素(BP)系半導体からなる、
非晶質体を含む多結晶からなる、不純物を添加した低温
緩衝層とを備えた積層構造体であって、低温緩衝層に添
加する不純物が、リン(P)以上の原子半径を有する元
素からなることを特徴とする積層構造体。
1. A substrate made of a conductive single crystal, and a boron phosphide (BP) -based semiconductor provided on the surface of the substrate and containing boron (B) and phosphorus (P) as constituent elements. ,
What is claimed is: 1. A laminated structure comprising a polycrystalline low-temperature buffer layer containing an amorphous material, the impurity being added to the low-temperature buffer layer from an element having an atomic radius of phosphorus (P) or more. And a laminated structure.
【請求項2】導電性の基板が珪素(Si(シリコン))
単結晶からなり、低温緩衝層に添加する不純物が、珪素
(Si)以上の原子半径を有する元素からなることを特
徴とする請求項1に記載の積層構造体。
2. The conductive substrate is silicon (Si).
The stacked structure according to claim 1, wherein the stacked structure is made of a single crystal, and the impurity added to the low temperature buffer layer is an element having an atomic radius of silicon (Si) or more.
【請求項3】導電性の基板がp形伝導性の単結晶からな
り、低温緩衝層に添加する不純物が、亜鉛(Zn)から
なることを特徴とする請求項1または2に記載の積層構
造体。
3. The laminated structure according to claim 1, wherein the conductive substrate is made of a p-type conductive single crystal, and the impurities added to the low-temperature buffer layer are made of zinc (Zn). body.
【請求項4】低温緩衝層上に、低温緩衝層に添加された
不純物とは異なる元素を添加した、リン化硼素(BP)
系半導体からなる導電層を備えていることを特徴とする
請求項1乃至3の何れか1項に記載の積層構造体。
4. Boron phosphide (BP), on which an element different from the impurities added to the low temperature buffer layer is added on the low temperature buffer layer.
The laminated structure according to any one of claims 1 to 3, further comprising a conductive layer made of a system semiconductor.
【請求項5】導電性の基板がp形伝導性の単結晶からな
り、低温緩衝層上に設ける導電層をマグネシウム(M
g)を添加したリン化硼素系半導体層から構成したこと
を特徴とする請求項3に記載の積層構造体。
5. The conductive substrate is made of p-type conductive single crystal, and the conductive layer provided on the low temperature buffer layer is made of magnesium (M).
The laminated structure according to claim 3, which is composed of a boron phosphide-based semiconductor layer to which g) is added.
【請求項6】請求項1乃至5の何れか1項に記載の積層
構造体の表面をなす半導体層に接触させてオーミック
(Ohmic)性の表面電極を設け、基板をなす導電性
単結晶の裏面にオーミック性の裏面電極を設けて構成し
たことを特徴とする発光素子。
6. A conductive single crystal forming a substrate, which is provided with an ohmic surface electrode in contact with a semiconductor layer forming a surface of the laminated structure according to claim 1. A light emitting device characterized in that an ohmic back electrode is provided on the back surface.
【請求項7】積層構造体の表面の半導体層がn形であ
り、基板がp形伝導性の単結晶であることを特徴とする
請求項6に記載の発光素子。
7. The light emitting device according to claim 6, wherein the semiconductor layer on the surface of the laminated structure is n-type, and the substrate is a p-type conductive single crystal.
【請求項8】請求項6または7に記載の発光素子を利用
して構成したことを特徴とするランプ。
8. A lamp comprising the light emitting device according to claim 6 or 7.
【請求項9】請求項8に記載のランプを集合させて構成
したことを特徴とする光源。
9. A light source constituted by assembling the lamps according to claim 8.
JP2001248587A 2001-08-20 2001-08-20 Laminated structure and light emitting element, lamp, and light source using the same Expired - Fee Related JP3649170B2 (en)

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