JP2003057271A - Watthour meter using hall element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of an unbalanced voltage unable to be be removed completely, because of not synchronizing the variation period of the unbalanced voltage with the integration period of an integrator circuit, resulting in the electrical energy involving the unbalanced power as error component being measured. SOLUTION: A zero-cross detector circuit 27 generates a zero-cross signal from a measured voltage V, a frequency divider circuit 28 divide the frequency of this signal, and a control signal generator circuit 29 generates control signals S1, S2 from the frequency-divided signal; the signals S1, S2 being for control current switches 25a, 25b for reversing the direction of a Hall current Ic, flowing in a Hall element 22 and an amplifier output switch 26 for reversing the polarity of a signal amplified by a differential amplifier circuit 23. An integrator circuit 24 integrates a signal output from the switch 26 in the period-units of the control signal S1 to output an integrated electrical energy. Thus the integration period of the integrator circuit 24 coincides with the variation period of an unbalanced voltage, and the unbalanced voltage is completely removed, to accurately measure the electrical energy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric energy meter for measuring the amount of electric power used, and more particularly to an electric energy meter for measuring electric energy using a hall element.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a configuration of an internal circuit of a watt hour meter using a conventional Hall element. Figure 2
Shows the signal waveform of each part of the circuit of FIG.

The Hall current Ic shown in FIG. 2A corresponding to the measured voltage V is supplied to the current input terminals 2a and 2b of the Hall element 2.
When a magnetic field having the magnetic flux density B shown in FIG. 3B corresponding to the measured current I is applied to the Hall element 2 at the same time, the Hall element 2 corresponds to the electric power value from the Hall voltage output terminals 2c and 2d (FIG. Hall voltage shown in c) Vh = K × B × Ic
(K: product sensitivity of Hall element 2) is output.

At the output of the Hall element 2 at this stage, in addition to the Hall voltage Vh, the common mode voltage Vcm shown in FIG. 6D and the unbalanced voltage Vho shown in FIG.
It is included. The common-mode voltage Vcm is a voltage that appears at both the output terminals 2c and 2d of the hall element 2, and is the hall current Ic.
Is multiplied by half the input resistance Rin of the Hall element 2. The unbalanced voltage Vho is a voltage generated between the output terminals 2c and 2d similarly to the hall voltage Vh, and the hall current Ic
To the unbalanced resistance Rho.

When the electric energy is measured using the Hall element 2, a differential amplifier circuit 3 is used as an amplifier circuit for a minute Hall voltage.
Is used. Since the differential amplifier circuit 3 amplifies and outputs the potential difference between the two input terminals, it removes the common-mode voltage Vcm of the same value appearing at both of the two input terminals. In addition, the integrating circuit 4 is used to convert the electric power value into the electric energy,
The integrator circuit 4 removes the unbalanced voltage Vho shown in FIG. 7E, which is periodically inverted between positive and negative, at the same time as the conversion processing of the hall voltage Vh shown in FIG. As a result, from the output of the integrating circuit 4, the Hall voltage G × corresponding to the electric energy
A time integral of Vh (G: amplification factor of the differential amplifier circuit 3) is detected.

In the configuration shown in FIG. 1, the common mode voltage Vcm and the unbalanced voltage Vho, which are error components of power measurement, can be removed. However, since the differential amplifier circuit 3 has an operational amplifier as a constituent element, the input offset voltage Voff shown in FIG. 2 (f) is generated at the output of the differential amplifier circuit 3 and becomes an error factor in power measurement. Hall voltage Vh at light load current
Is a unit level of microvolt, and even if a high-precision operational amplifier is used, the offset voltage Voff of the same level is obtained.
Therefore, the offset voltage Voff is a large error factor.

FIG. 3 is a block diagram showing an internal circuit configuration of another conventional watt hour meter having a configuration for removing the offset voltage Voff. In the figure, the same elements as the circuit elements shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. 4 and 5 show signal waveforms at various parts of the circuit shown in FIG.

In the watt-hour meter shown in FIG. 3, the oscillator 7 generates the clock signal Scl shown in FIG. 4 (a), and the control signal generation circuit 8 inputs the clock signal Scl to input the clock signal Scl. The control signals S1 and S2 shown in (c) are generated. The control signals S1 and S2 have signal levels opposite to each other and are output to the current changeover switches 5a and 5b, the amplification output changeover switch 6 and the integrating circuit 4.

The current changeover switches 5a and 5b invert the direction in which the hall current Ic is input to the input terminals 2a and 2b based on the control signals S1 and S2 at every predetermined period shown in FIG. The polarity of the hall current Ic shown in FIG. 9B is periodically inverted as shown in FIG. Therefore, at the output terminals 2c and 2d of the Hall element 2, the Hall voltage Vh shown in FIG. 7E obtained by multiplying the Hall current Ic shown in FIG. 7C by the magnetic flux density B shown in FIG. appear. The differential amplifier circuit 3 inputs the hall voltage Vh, amplifies it, and outputs it to the amplified output changeover switch 6. Amplified output selector switch 6
Is the control signal S1, the polarity of the output signal of the differential amplifier circuit 3,
It is periodically inverted based on S2. As a result, the Hall voltage Vh, which has been inverted by the current changeover switches 5a and 5b as shown in FIG. 7E, is returned to inversion as shown in FIG. Further, the offset voltage Voff included in the output of the differential amplifier circuit 3 shown in FIG. 9G is converted into a waveform signal of positive and negative equal areas for each cycle by the amplification output changeover switch 6 as shown in FIG. To be done. Therefore, the offset voltage Voff is eliminated by being passed through the integrating circuit 4 in the subsequent stage to cancel the positive and negative.

Even in the conventional electric energy meter shown in FIG.
The in-phase voltage Vcm shown in (d) is removed by the differential amplification performed by the differential amplifier circuit 3, and the unbalanced voltage Vho shown in (e) of the figure is integrated circuit 4 for each cycle of the control signal S1.
Are removed by integration at.

[0011]

However, the integration period of the integrating circuit 4 in the conventional watt-hour meter shown in FIG. 3 uses a divided signal obtained by dividing the clock signal from the oscillator 7 into an appropriate period. Since it is determined, it is not exactly synchronized with the fluctuation cycle of the unbalanced voltage Vho. Therefore, if the integration operation is performed in this integration cycle, the integration is not performed over one cycle of the fluctuation cycle of the unbalanced voltage Vho, and the unbalanced voltage Vho has a signal component corresponding to the deviation between the fluctuation cycle and the integration cycle. It remains as an error component and is output. As a result,
The unbalanced voltage Vho could not be removed completely and the power could not be measured accurately.

Further, the signal entering the integrating circuit 4 is an analog signal, and the integrating circuit 4 has an operational amplifier as a constituent element for integrating the analog signal. Therefore, the integrating circuit 4 that removes the unbalanced voltage Vho also generates and outputs the offset voltage Voff. As a result, the offset voltage Voff cannot be completely removed, and the power cannot be measured accurately.

When the oscillation frequency of the oscillator 7 fluctuates and the duty ratio of the control signals S1 and S2 is not 1: 1, the offset voltage Voff inverted by the amplification changeover switch 6 is as shown in FIG. The waveform is not the same as the positive and negative areas shown in. Therefore, even if the integrating circuit 4 performs integration processing, the offset voltage Voff cannot be completely removed, and power measurement becomes inaccurate.

[0014]

The present invention has been made in order to solve these problems, and has an input terminal for inputting a hall current corresponding to a measurement voltage and an output terminal for outputting a hall voltage. Hall element placed in a magnetic field corresponding to, a control signal generating means for generating a control signal that is inverted every predetermined period, and the direction in which the Hall current is input to the input terminal is determined every predetermined period based on the control signal. First switching means for inverting, differential amplifying means for differentially amplifying the Hall voltage output from the output terminal, and second inverting the output of the differential amplifying means at predetermined intervals based on the control signal. In the watt-hour meter using the Hall element, the control signal is composed of the switching means and the integrating means for integrating the output of the second switching means at a predetermined cycle based on the control signal. The forming means includes a zero-cross detecting means for generating a zero-cross signal from the measured voltage and a dividing means for dividing the frequency of the zero-cross signal, and a control signal is generated based on the divided signal output from the dividing means. It is characterized by generating.

According to this structure, the integration period of the integrating means is
It is determined by the control signal generated based on the zero-cross signal of the measurement voltage that is synchronized with the unbalanced voltage, and it comes to coincide with the fluctuation period of the unbalanced voltage.

Further, the present invention comprises an analog-digital conversion means for converting an input of the integration means from an analog signal to a digital signal, and the integration means comprises a digital circuit for integrating the digital signal converted from the analog signal. And

According to this structure, the integrating means is composed of a digital circuit and does not include an operational amplifier.

Further, the present invention is characterized in that the analog-digital converting means is a delta-sigma converter using a 1-bit quantizer.

According to this structure, the digital signal is output from the delta-sigma converter bit by bit, and the circuit scale of the integrating means for integrating the 1-bit output is reduced.

Further, the present invention is characterized in that the second switching means is composed of a digital circuit which inverts the digital signal converted by the analog-digital converting means every predetermined period.

According to this structure, the second switching means is composed of a digital circuit, and the second switching means can be composed of a logic circuit. Therefore, the circuit scale of the second switching means is also reduced.

Further, according to the present invention, a hall element having an input terminal for inputting a hall current corresponding to a measurement voltage and an output terminal for outputting a hall voltage, which is placed in a magnetic field corresponding to the measurement current, and at a predetermined cycle. Control signal generating means for generating a control signal to be inverted based on a predetermined clock signal; first switching means for inverting the direction in which the hall current is input to the input terminal every predetermined period based on the control signal; Differential amplifying means for differentially amplifying the Hall voltage output from the output terminal, second switching means for inverting the output of the differential amplifying means at predetermined intervals based on a control signal, and the second switching means. In a watt hour meter using a Hall element, which is configured to have an integrating means for integrating the output of the switching means based on the control signal at predetermined intervals, a high level time and a low level of the control signal Detects Le time, characterized by comprising the duty ratio correcting means for correcting the duty ratio of the control signal is corrected to a frequency variation of these high level time and the low level time.

According to this structure, the duty ratio of the control signal is kept at 1: 1 by the duty ratio correcting means, and the offset voltage and the like are converted into the signal waveform of the positive and negative equal areas by the second switching means.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of a watt hour meter using a Hall element according to the present invention will be described.

FIG. 6 is a block diagram showing the configuration of the internal circuit of the watt hour meter using the Hall element according to the present embodiment.

Hall element 2 of the electric energy meter according to the present embodiment
2 has input terminals 22a and 22b for inputting the Hall current Ic corresponding to the measurement voltage V and output terminals 22c and 22d for outputting the Hall voltage Vh, and has a magnetic flux density B corresponding to the measurement current I. Placed in a magnetic field. Hall current I
c is input from the input terminal 21 via the resistor 31. Between the Hall element 22 and the resistor 31, current changeover switches 25a and 25b are provided.

The current changeover switches 25a and 25b are
The Hall current Ic is input to the input terminals 22a, 2 of the Hall element 22.
It constitutes a first switching means for inverting the direction input to 2b every predetermined period based on control signals S1 and S2 described later. The current selector switch 25a has a resistor 31
And a switch S1 for connecting / disconnecting the input terminal 22a and a switch S2 for connecting / disconnecting the input terminal 22a and the ground.
It consists of and. The current changeover switch 25b is a switch S1 for connecting and disconnecting between the input terminal 22b and the ground.
And a switch S2 for connecting and disconnecting the resistor 31 and the input terminal 22b.

The differential amplifier circuit 23 constitutes a differential amplifier means for differentially amplifying the Hall voltage Vh output from the output terminals 22c and 22d of the Hall element 22 with an amplification factor G.
The amplification output changeover switch 26 includes two switches S1 and S2.
This switch is composed of a plurality of switches S2, and constitutes a second switching means for inverting the output of the differential amplifier circuit 23 every predetermined period based on the control signals S1 and S2. The switch S1 connects and disconnects between the non-inverting output terminal of the differential amplifier circuit 23 and one input terminal of the integrating circuit 24, and the differential amplifier circuit 2
In some cases, the inverting output terminal 3 and the other input terminal of the integrating circuit 24 are intermittently connected. The switch S2 connects and disconnects between the inverting output terminal of the differential amplifier circuit 23 and one input terminal of the integrating circuit 24, and connects between the non-inverting output terminal of the differential amplifier circuit 23 and the other input terminal of the integrating circuit 24. There is something to do. The integrating circuit 24 uses the amplification output changeover switch 2
Integrating means for integrating the output of 6 on the basis of the control signal S1 every predetermined period is configured.

The on / off state of each switch S1 constituting the current changeover switches 25a and 25b and the amplification output changeover switch 26 is controlled by the control signal S1 and the control signal S1.
Closes when is high and opens when is low. Further, the on / off state of each switch S2 is controlled by the control signal S2, which is closed when the control signal S2 is at high level and opened when it is at low level.

Further, the electric energy meter according to the present embodiment is provided with a zero cross detection circuit 27 for generating a zero cross signal from the measured voltage V. The zero-cross detection circuit 27 is connected to the input terminal 21 via the resistor 31 and inputs the measurement voltage V from the input terminal 21. The frequency divider circuit 28 divides the frequency of the zero-cross signal input from the zero-cross detection circuit 27 and outputs a divided signal. Control signal generation circuit 2
Reference numeral 9 generates control signals S1 and S2 based on the frequency division signal input from the frequency division circuit 28. The control signal generating circuit 29 is composed of a normal logic element 29a and an inverting logic element 29b whose inputs are connected together to the output of the frequency dividing circuit 28.
The normal logic element 29a receives the input signal as it is as the control signal S1.
Then, the inverting logic element 29b outputs the control signal S2 which is the inverted input signal. Zero-cross detection circuit 27,
The frequency dividing circuit 25 and the control signal generating circuit 29 constitute a control signal generating means for generating control signals S1 and S2 which are inverted every predetermined period.

Next, the operation of the electric energy meter according to the present embodiment having the above-mentioned structure will be described. FIG. 7 shows the signal waveform of each part of the circuit of the control signal generating means in FIG.

The zero-cross detection circuit 27 generates the zero-cross signal Sz shown in FIG. 7B based on the sine-waveform measured voltage V shown in FIG. The zero-cross signal Sz is a rectangular wave that is inverted at the zero-cross point of the measurement voltage V. The frequency dividing circuit 28 generates the frequency dividing signal Sdiv shown in FIG. 7C based on the zero cross signal Sz. Divided signal Sdiv
Is a signal obtained by dividing the zero-cross signal Sz by two here, but it may be a signal obtained by dividing the zero-cross signal by two or more. The control signal generation circuit 29 inputs the frequency-divided signal Sdiv, outputs the control signal S1 shown in FIG. 7D from the normal logic element 29a, and outputs the control signal S2 shown in FIG. Output from the element 29b. The control signals S1 and S2 have opposite signal level states.

FIG. 8 shows the signal waveforms of the respective elements of the Hall element 22, the differential amplifier circuit 23, and the integrating circuit 24 in FIG.

The inversion period shown in FIG. 8A is as shown in FIG.
It is generated based on the control signals S1 and S2 shown in (d) and (e), and is synchronized with the low level state of the control signal S1 and the high level state of the control signal S2. The measured voltage V shown in FIG. 7A applied to the input terminal 21 is converted into the Hall current Ic shown in FIG. 8B by the resistor 31 and input to the current changeover switches 25a and 25b.

When the control signal S1 is in the high level state and the control signal S2 is in the low level state, the current changeover switch 25
In a and 25b, the switch S1 is closed and the switch S2 is opened. Therefore, the hall current Ic passes through the switch S1 of the current changeover switch 25a and the hall element 22.
From the input terminal 22a to the input terminal 22b, and then to the ground through the switch S1 of the current changeover switch 25b. Therefore, the Hall current Ic flows through the Hall element 22 in the same shape as the signal waveform shown in FIG. 7B before passing through the current changeover switches 25a and 25b, as shown in FIG. When the control signal S1 is in the low level state and the control signal S2 is in the high level state, the switch S1 is opened and the switch S2 is closed. Therefore, the hall current Ic flows from the input terminal 22b to the input terminal 22a through the hall element 22 through the switch S2 of the current changeover switch 25b and to the ground through the switch S2 of the current changeover switch 25a. For this reason, the Hall current Ic flows through the Hall element 22 in the signal waveform shown in FIG. 7C which is the inverted signal waveform shown in FIG. As a result, the Hall current Ic is converted by the current change-over switches 25a and 25b into the signal waveform shown in FIG. 7C in which the direction of the flow is inverted at every inversion synchronization shown in FIG.

At the same time as the Hall current Ic is flown in this way, the measurement current I is flown in the coil 32 to generate the magnetic field having the magnetic flux density B shown in FIG. When this magnetic field is applied to the Hall element 22, the Hall element 22 produces the Hall voltage Vh = K × B × Ic (K: product sensitivity) shown in FIG. 8E from the voltage output terminals 22c and 22d by the Hall effect. Output. The differential amplifier circuit 23 uses the hall voltage V
h is input and differentially amplified, and the amplified Hall voltage GVh is output.

At this time, the Hall voltage Vh necessary for power measurement is applied to the voltage output terminals 22c and 22d of the Hall element 22.
In addition, the common mode voltage Vcm and the unbalanced voltage Vho shown in (f) and (g) of the same figure which are unnecessary for power measurement also appear, but the differential amplifier circuit 23 amplifies the difference input to the two input terminals. Therefore, the common mode voltage Vcm that appears at each input terminal with the same value
To remove. Therefore, in the output of the differential amplifier circuit 23, the unbalanced voltage GVho appears in addition to the Hall voltage GVh. Further, since the differential amplifier circuit 23 has an operational amplifier as a constituent element, an offset voltage Voff shown in (h) of FIG.

The output of the differential amplifier circuit 23 is input to the amplification output changeover switch 26. This amplification output switch 2
6 is in a state in which the switch S1 is closed and the switch S2 is opened when the control signal S1 is in the high level state and the control signal S2 is in the low level state. Therefore, the non-inverting output terminal of the differential amplifier circuit 23 is connected to one input terminal of the integrating circuit 24, and the inverting output terminal of the differential amplifier circuit 23 is connected to the other input terminal of the integrating circuit 24. As shown in (i), the Hall voltage Vh shown in (e) of the drawing passes through the signal waveform as it is, and is output to the integrating circuit 24.

When the control signal S1 is in the low level state and the control signal S2 is in the high level state, in the amplification output changeover switch 26, the switch S1 is opened and the switch S2 is closed. Therefore, the non-inverting output terminal of the differential amplifier circuit 23 is connected to the other input terminal of the integrating circuit 24, and the inverting output terminal of the differential amplifier circuit 23 is connected to one input terminal of the integrating circuit 24. The hall signal Vh shown in e) has its waveform signal inverted in polarity as shown in FIG. That is, the output of the differential amplifier circuit 23 is inverted by the amplification output changeover switch 26 at every inversion synchronization shown in FIG.

Further, the unbalanced voltage Vcm and the offset voltage Voff included in the output of the differential amplifier circuit 23 are simultaneously inverted by the amplification output changeover switch 26 in every inversion cycle shown in FIG. That is, the unbalanced voltage Vcm is converted into the waveform shown in FIG. 9G and the offset voltage Voff is converted into the waveform shown in FIG.

The integrator circuit 24 integrates the input signal for each cycle of the control signal S1. Therefore, the inverted unbalanced voltage GVho shown in FIG. 7 (j) and the inverted offset voltage Voff shown in FIG. 9 (k), which have signal waveforms of positive and negative equal areas, are positive and negative for each cycle of the control signal S1. It is offset and removed. Further, the hall voltage GVh shown in FIG.
Since all the signal waveforms are positive, when integration processing is performed, they are integrated and converted into electric energy.

The Hall element 2 according to the present embodiment as described above
According to the power meter using 2, the integration period of the integrating circuit 24 is determined by the control signal S1 generated based on the zero-cross signal Sz of the measurement voltage V synchronized with the unbalanced voltage Vho, and the unbalanced voltage Vho. It comes to match the fluctuation cycle of.
Therefore, the unbalanced voltage Vho is integrated over one period of the fluctuation period and completely removed. As a result, the power amount is measured accurately.

Next, a second embodiment of the electric energy meter using the Hall element according to the present invention will be described.

FIG. 9 is a block diagram showing the configuration of the internal circuit of the watt hour meter using the Hall element according to the present embodiment. In the figure, parts that are the same as or correspond to those in FIG. 6 are assigned the same reference numerals and explanations thereof are omitted.

The electric energy meter according to the present embodiment has a control signal S
Control signal generating means for generating 1, S2, Hall element 22 and current changeover switches 25a, 2 for switching the input thereof.
The configuration of the portion 5b is the same as that of the watthour meter of the first embodiment described above, and the configuration subsequent to differentially amplifying the output of the hall element 22 is different from that of the first embodiment described above. That is,
In the present embodiment, one output terminal of the differential amplifier circuit 23A is an analog-digital converter (hereinafter referred to as an AD converter).
It is connected to one input terminal of 30. Although the case where one output terminal of the differential amplifier circuit 23A is connected to one input terminal of the AD converter 30 is described here, a plurality of output terminals of the differential amplifier circuit 23A are AD. It may be configured to be connected to a plurality of input terminals of the converter 30. The AD converter 30 constitutes an AD conversion means for converting the input of the integrating circuit 24A from an analog signal to a digital signal, and has a plurality of output terminals.

The amplification output changeover switch 26A has a number of exclusive NOR (Ex) corresponding to the number of output terminals of the AD converter 30.
It is composed of a digital circuit including a NOR element.
Each ExNOR element takes the exclusive NOR of each output signal of the AD converter 30 and the control signal S1 and outputs it. Here, the case where the amplification output changeover switch 26A is composed of the number of ExNOR elements corresponding to the number of output terminals of the AD converter 30 has been described, but the number and the type of elements are limited to this example. It is not something that will be done. The integrating circuit 24A is also composed of a digital circuit, and integrates the digital output of the amplified output changeover switch 26A for each cycle of the control signal S1.

In such a configuration, the differential amplifier circuit 2
3A differentially amplifies the Hall voltage Vh output from the output terminals 22c and 22d of the Hall element 22 with an amplification factor G, and outputs the amplified Hall voltage GVh. AD converter 30
Converts the Hall voltage GVh of the analog signal output from the differential amplifier circuit 23A into a parallel digital signal of a plurality of bits, and outputs the parallel digital signal from a plurality of output terminals. Each ExNOR element of the amplification output changeover switch 26A has an AD converter 3
Each output signal of 0 and the control signal S1 are input, and a high level signal is output if the input levels of these signals match, and a low level signal is output if they differ. As a result, the control signal S
Amplified Hall voltage GVh when 1 is high level period
Is output as it is and the control signal S1 has a low level period, the polarity of the Hall voltage GVh inverted by the current changeover switches 25a and 25b is returned to the original polarity.
The integrator circuit 24A integrates and integrates the output of the amplification output changeover switch 26A for each cycle of the control signal S1, converts the output into an integrated power amount, and outputs it.

Also in the configuration of this embodiment, the common-mode voltage Vcm and the unbalanced voltage Vho which are unnecessary for measuring the amount of electric power appear in the output of the Hall element 22, and the offset voltage Voff is generated in the output of the differential amplifier circuit 23A. The in-phase voltage Vcm is removed by performing differential amplification in the differential amplifier circuit 23A, as in the first embodiment. The unbalanced voltage Vho is AD
After being converted into a digital signal by the converter 30, it is inverted every half cycle of the control signal S1 by the amplification output changeover switch 26A, and therefore removed by being integrated by the integration circuit 24A every cycle of the control signal S1. To be done. The offset voltage Voff is also converted into a digital signal by the AD converter 30 and then inverted every half cycle of the control signal S1 by the amplification output changeover switch 26A. Therefore, the offset voltage Voff is integrated every one cycle of the control signal S1 by the integrating circuit 24A. It is removed by being processed. An offset voltage is also generated from the AD converter 30, but it is removed by the same process.

According to the electric energy meter according to the second embodiment, the AD converter 30 for converting the input of the integrating circuit 24A from an analog signal into a digital signal is provided, and the integrating circuit 24A is constituted by a digital circuit. Therefore, the operational amplifier is not included in the components. Therefore, the integrating circuit 24A itself does not generate the offset voltage as in the conventional case, and the power measurement is accurately performed.

In the electric energy meter of this embodiment, the amplification output changeover switch 26A is composed of a digital circuit which inverts the digital signal converted by the AD converter 30 every half cycle of the control signal S1. According to this configuration, the amplification output changeover switch 26A is composed of a digital circuit, and the amplification output changeover switch 26A can be composed of a logic circuit. Therefore, the amplification output changeover switch 26A can be realized smaller than the amplification output changeover switch 26 using the analog switch, and the circuit scale thereof can be reduced.

Next, a third embodiment of the watt hour meter using the Hall element according to the present invention will be described.

FIG. 10 is a block diagram showing the configuration of the internal circuit of the watt hour meter using the Hall element according to the present embodiment. In the figure, parts that are the same as or correspond to those in FIG. 9 are assigned the same reference numerals and explanations thereof are omitted.

The watt-hour meter according to this embodiment has a control signal S
Control signal generating means for generating 1 and S2, current changeover switches 25a and 25b, hall element 22 and differential amplifier circuit 2
The configuration of the portion 3A is the same as that of the watthour meter of the second embodiment described above, and the configuration after the output of the differential amplifier circuit 23A is different from that of the second embodiment. That is, in the present embodiment, the AD that is a constituent element of the electric energy meter of the second embodiment described above.
The converter 30 is composed of a delta-sigma converter 30A. The delta-sigma converter 30A is composed of a 1-bit quantizer, and has one input terminal connected to one output terminal of the differential amplifier circuit 23A and one output terminal for outputting a 1-bit output signal. have.

The amplification output changeover switch 26B has one E
It is composed of a digital circuit consisting only of xNOR elements. This ExNOR element takes the exclusive NOR of the 1-bit output signal of the delta-sigma converter 30A and the control signal S1 and outputs it. The integrating circuit 24B is also composed of a digital circuit, and integrates the digital output of the amplified output changeover switch 26B for each cycle of the control signal S1.

In such a configuration, the delta-sigma converter 30A converts the Hall voltage GVh of the analog signal output from the differential amplifier circuit 23A into a 1-bit serial digital signal and outputs it. The ExNOR element of the amplification output changeover switch 26B is the delta-sigma converter 30A.
Output signal and the control signal S1 are input, and if the input levels of these signals match, a high level signal is output, and if they differ, a low level signal is output. As a result, when the control signal S1 has a high level cycle, the amplified hall voltage GVh is output as it is, and when the control signal S1 has a low level cycle, the polarity of the hall voltage GVh inverted by the current changeover switches 25a and 25b. Is returned to the original polarity. The integrating circuit 24B integrates and integrates the output of the amplification output changeover switch 26B for each cycle of the control signal S1, and converts the integrated output into an integrated power amount for output.

Also in the configuration of this embodiment, the common-mode voltage Vcm and the unbalanced voltage Vho, which are unnecessary for measuring the electric energy, appear at the output of the Hall element 22, and the offset voltage Voff is generated at the output of the differential amplifier circuit 23A. The in-phase voltage Vcm is removed by performing differential amplification in the differential amplifier circuit 23A, as in the first and second embodiments. Unbalance voltage V
Since ho is converted into a digital signal by the delta-sigma converter 30A and then inverted by the amplification output changeover switch 26B every half cycle of the control signal S1, the integration circuit 24B
Is removed by performing integration processing for each cycle of the control signal S1. The offset voltage Voff is also converted into a digital signal by the delta-sigma converter 30A,
Since the amplification output changeover switch 26B inverts every half cycle of the control signal S1, it is removed by being integrated by the integration circuit 24B every cycle of the control signal S1.

According to the electric energy meter according to the third embodiment, the digital signal is output from the delta-sigma converter 30A bit by bit, and the integration circuit 24B for integrating the 1-bit output is reduced in circuit scale. To be done.

In the watt hour meter of this embodiment, the amplification output changeover switch 26B inverts the 1-bit digital signal converted by the delta-sigma converter 30A every half cycle of the control signal S1. Composed of elements. According to this configuration, the amplification output changeover switch 26B
Is composed of only one ExNOR element,
The circuit scale is further reduced as compared with the amplification output changeover switch 26A of the second embodiment which is composed of a plurality of ExNOR elements.

Next, a fourth embodiment of a watt hour meter using the Hall element according to the present invention will be described.

FIG. 11 is a block diagram showing the configuration of the internal circuit of the watt hour meter using the Hall element according to the present embodiment. In the figure, parts that are the same as or correspond to those in FIG. 9 are assigned the same reference numerals and explanations thereof are omitted.

The electric energy meter according to the present embodiment includes the frequency dividing circuit 2
8 and the control signal generation circuit 29 are different from the watthour meter of the second embodiment in that a duty ratio correction circuit 40 for correcting the duty ratio is inserted, and other than this point, the duty ratio correction circuit 40 of the second embodiment is different. It has the same configuration as the watt hour meter. The duty ratio correction circuit 40 detects the control signal S by detecting the high level time and the low level time of the divided signal Sdiv.
The duty ratio correction means detects the high level time and the low level time of S1 and S2 and corrects the high level time and the low level time to correct the duty ratio of the control signals S1 and S2. FIG. 12 is a block diagram showing a configuration of an internal circuit of the duty ratio correction circuit 40.

The duty ratio correction circuit 40 uses the clock signal fs having a frequency sufficiently faster than the frequency of the zero-cross signal Sz.
A D flip-flop (D-FF) 41 which is a synchronizing means for synchronizing the divided signal Sdiv to / 2 is provided. DF
The frequency-divided signal Sdiv output from the frequency dividing circuit 28 is input to the D input terminal of F41, and the clock signal fs / is input to the CK terminal.
2 has been entered. The clock signal fs is input to each of the delay means 42, the duty ratio deviation number detection means 43, and the waveform generation means 44. The delay means 42 is D
The sync signal C shown in FIG. 13 (b) output from the Q output terminal of the -FF 41 is output for a predetermined time, for example, FIG.
The clock signal fs shown in FIG. 13 is delayed by N / 2 clocks and output as a delay signal D shown in FIG.

The duty ratio deviation number detecting means 43 is set to D
The high level time and the low level time of the synchronizing signal C output from the -FF 41 are detected to detect the deviation of the duty ratio of the control signals S1 and S2, and a correction value for correcting this deviation is output. The waveform generation means 44 inputs this correction value and generates a correction waveform signal E for correcting the duty ratio of the control signals S1 and S2. The waveform synthesizing means 45 is shown in FIG.
A switch which is switched by the control signal S3 shown in FIG. 1 is used to replace the predetermined correction section of the waveform of the delay signal D delayed by the delay means 42 with the correction waveform signal E to generate the corrected frequency division signal F.

The control signal S3 is a correction section for N clocks provided at the same time at the end of a certain cycle of the delay signal D and at the start of the next cycle, that is, N clocks of the clock signal fs in this example. During this period, the signal is high level. The waveform synthesizing means 45 switches to the point A side to connect the delay means 42 and the output terminal 46 when the control signal S3 is in the low level state, and switches to the point B side to switch to the point B side in the high level state. And the output terminal 46 are connected.

Next, the operation of the duty ratio correction circuit 40 will be described with reference to the waveform signal of FIG.

The synchronizing means 41 outputs the frequency-divided signal output from the frequency-dividing circuit 28 (see FIG. 11) to the clock signal fs / 2 having a frequency sufficiently higher than the frequency of the frequency-divided signal shown in FIG.
, And outputs the synchronization signal C shown in FIG.
In the illustrated synchronizing signal C, the high level time of the first cycle is 8 clocks of the clock signal fs, the low level time is 6 clocks of the clock signal fs, and the high level of the next cycle is the clock signal. Six clocks of fs and low level time are eight clocks of the clock signal fs. The delay means 42 receives this synchronization signal C and inputs N / 2 clocks of the clock signal fs signal shown in FIG.
In this example, it is delayed by 2 clocks and the delayed signal D shown in FIG. The waveform synthesizing means 45 outputs the delay signal D to the delay signal D during the correction period other than the correction section in which the time A at the end of one cycle of the delay signal D and the time B at the start of the next cycle are combined.
As shown in FIG. The time A and the time B are set equal, and the time delayed by the delay means 42 is also set equal to this time.

The duty ratio deviation number detecting means 43 inputs the synchronizing signal C in parallel with the delay means 42, and detects the deviation between the high level time and the low level time for each cycle of the synchronizing signal C by the number of clocks of the clock signal fs. Ask as. And
The calculated number of clocks is output to the waveform generation means 44 as a correction value. That is, in the section I corresponding to the first one cycle of the synchronization signal C, the high level time is longer than the low level time by two clocks of the clock signal fs, and therefore the correction value +2 is output, and in the section II, the high level time is Since the clock signal fs is shorter than the low level time by 2 clocks, the correction value -2 is output.

The waveform generating means 44 inputs this correction value and outputs the correction waveform signal E shown in FIG. 9 (f) so that the high level time and the low level time become equal in each section of the synchronization signal C. To generate. That is, when the correction value +2 is input in the section I, the waveform generation means 44 generates and outputs the corrected waveform signal E including the low level signal for three clocks and the high level signal for one clock. Further, when the correction value -2 is input in the section II, the correction waveform signal E including the low level signal for one clock and the high level signal for three clocks is generated and output.

In the correction section in which the control signal S3 is in the high level state, the waveform synthesizing means 45 has the waveform generating means 4
The corrected waveform signal E output from the terminal 4 is output to the terminal 46. Therefore, at the output terminal 46, the corrected frequency-divided signal F shown in (g) of the figure, in which the delayed signal D shown in (e) of the figure and the correction waveform signal E shown in (f) of the figure are combined, appears. . As a result, in each section I ′, II ′, the high level time and the low level time are equal in seven in the clock signal fs unit, and the modified frequency division signal F whose duty ratio is corrected to 1: 1 is the control signal. It is output to the generation circuit 29 (see FIG. 11).

In the above description, the delay signal D of one cycle is cut by two clock signals fs before and after the delay signal D, and four correction intervals are set, but this correction interval is set to the measured voltage V.
Is set in consideration of the frequency fluctuation of

According to the electric energy meter according to the fourth embodiment, the control signal S generated by the control signal generation circuit 29 is generated.
The duty ratios of 1 and S2 are maintained at 1: 1 by the duty ratio correction circuit 40, and the unbalanced voltage Vho and the offset voltage Voff are converted into signal waveforms of positive and negative equal areas by the amplification output changeover switch 26A. Therefore, the unbalanced voltage Vho
The offset voltage Voff is completely removed by the integration circuit 24A, and the power measurement is accurately performed. Therefore, according to the present embodiment, even when the control signals S1 and S2 are generated based on the measured voltage V in which the frequency fluctuation is occurring, the control signals S1 and S2 having the duty ratio of 1: 1 can be obtained. Power measurement is accurate.

In the fourth embodiment, as shown in FIG. 11, the duty ratio correction circuit 40 is described as being inserted in the circuit of the watt hour meter of the second embodiment, but the first and third embodiments are described. The combination with the embodiment can be similarly performed, and the same operation and effect as those of the fourth embodiment can be obtained.

Further, in the fourth embodiment, the duty ratio correction circuit 40 for correcting the duty ratio of the divided signal generated from the zero-cross signal Sz has been described. However, the duty ratio correction circuit is provided at the subsequent stage of the oscillator 7 shown in FIG. Insert 40
The same can be applied to the case where the oscillation frequency of the oscillator 7 fluctuates, and the same actions and effects as those of the fourth embodiment can be obtained.

[0074]

As described above, according to the present invention, the integration period of the integrating means is determined by the control signal generated based on the zero cross signal of the measurement voltage synchronized with the unbalanced voltage, and the unbalanced voltage is obtained. It comes to match the fluctuation cycle of.
Therefore, the unbalanced voltage is integrated over one period of its fluctuation period and completely removed. As a result, the power measurement is accurate.

When the input of the integrating means is an analog-digital converting means for converting an analog signal into a digital signal, and the integrating means is a digital circuit for integrating the digital signal converted from the analog signal, the integrating means is Since it is composed of a digital circuit, the operational amplifier is not included in the constituent elements. Therefore, the integrating means itself does not generate the offset voltage as in the conventional case, and the power measurement is accurately performed.

When the analog-to-digital conversion means is composed of a delta-sigma converter using a 1-bit quantizer, the digital signal is output from the delta-sigma converter bit by bit, and the 1-bit output is integrated. The circuit scale of the integrating means is reduced.

Further, when the second switching means is a digital circuit which inverts the digital signal converted by the analog-digital conversion means every predetermined period, the second switching means
The switching means of is composed of a digital circuit,
The switching means can be composed of a logic circuit. Therefore, the circuit scale of the second switching means is also reduced.

Further, when the duty ratio correction means for detecting the high level time and the low level time of the control signal and correcting the high level time and the low level time to correct the duty ratio of the control signal is provided, The duty ratio of the control signal is 1: 1 by the duty ratio correction means.
The offset voltage and the like are converted into a signal waveform of equal positive and negative areas by the second switching means. Therefore, the offset voltage and the like are completely removed when the integrating process is performed by the integrating means, and the power measurement is accurately performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an internal circuit of a watt hour meter using a conventional Hall element.

FIG. 2 is a waveform diagram showing signal waveforms of respective parts of the circuit of the watt hour meter shown in FIG.

FIG. 3 is a block diagram showing a configuration of an internal circuit of another watt-hour meter using another conventional Hall element.

FIG. 4 is a waveform diagram showing signal waveforms of the oscillator, the frequency divider, and the respective circuit parts of the control signal generating circuit of the watthour meter shown in FIG.

5 is a waveform diagram showing signal waveforms of respective parts of the circuit of the hall element, the differential amplifier circuit, and the integration circuit of the watthour meter shown in FIG.

FIG. 6 is a block diagram showing a configuration of an internal circuit of a watt hour meter using the Hall element according to the first embodiment of the present invention.

7 is a waveform diagram showing signal waveforms of respective parts of the circuit of the control signal generating means of the watt hour meter shown in FIG.

8 is a waveform diagram showing signal waveforms of circuit elements of a Hall element, a differential amplifier circuit, and an integrating circuit of the watt hour meter shown in FIG.

FIG. 9 is a block diagram showing a configuration of an internal circuit of a watt hour meter using a Hall element according to a second embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of an internal circuit of a watt hour meter using a Hall element according to a third embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of an internal circuit of a watthour meter using a Hall element according to a fourth embodiment of the present invention.

12 is a block diagram showing an internal configuration of the duty ratio correction circuit shown in FIG.

13 is a waveform diagram showing signal waveforms of an input / output signal of the delay unit shown in FIG. 12 and a control signal for controlling the waveform synthesizing unit.

FIG. 14 is a waveform diagram showing signal waveforms at various parts of the circuit of the duty ratio correction circuit shown in FIG.

[Explanation of symbols]

21 ... Input terminal 22 ... Hall element 22a, 22b ... Hall current input / output terminals 22c, 22d ... Hall voltage output terminals 23 ... Differential amplifier circuit 24, 24A, 24B ... Integrating circuit 25a, 25b ... Current changeover switch 26, 26A, 26B ... Amplification output selector switch 27 ... Zero cross oscillator 28 ... Divider 29 ... Control signal generation circuit 30 ... AD converter 30A ... Delta Sigma Converter 31 ... Resistance 32 ... coil 40 ... Duty ratio correction circuit 41 ... Synchronizing means 42 ... delay means 43 ... Duty ratio deviation number detecting means 44 ... Waveform generating means 45 ... Waveform synthesizing means S1, S2, S3 ... Control signal fs ... Clock signal of frequency fs fs / 2 ... Clock signal of frequency fs / 2

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Koji Imaizumi             63-24 Sunakubo, Kawagoe City, Saitama Prefecture (72) Inventor Naoto Kawashima             743-6- Soyado-cho, Kohoku-ku, Yokohama-shi, Kanagawa             401

Claims (7)

[Claims] 1. A Hall element which has an input terminal for inputting a Hall current corresponding to a measurement voltage and an output terminal for outputting a Hall voltage and is placed in a magnetic field corresponding to a measurement current, and a control signal which is inverted every predetermined period. Control signal generating means for generating a Hall current, first switching means for inverting the direction in which the Hall current is input to the input terminal at each of the predetermined cycles based on the control signal, and the Hall output from the output terminal. A differential amplifying means for differentially amplifying the voltage; a second switching means for inverting the output of the differential amplifying means based on the control signal every predetermined period; and an output of the second switching means. In a watt-hour meter using a Hall element configured to have an integrator that integrates the control signal based on the control signal in each predetermined cycle, the control signal generator may convert the measured voltage from the measured voltage. A zero-cross detection unit for generating a cross signal and a frequency dividing unit for dividing the frequency of the zero-cross signal are provided, and the control signal is generated based on the frequency-divided signal output from the frequency dividing unit. Electricity meter using a hall element. 2. An analog-to-digital conversion means for converting an input of the integration means into a digital signal from an analog signal is provided, and the integration means comprises a digital circuit for integrating the digital signal converted from the analog signal. An electric energy meter using the Hall element according to claim 1. 3. The watt-hour meter using a hall element according to claim 2, wherein the analog-digital conversion means is a delta-sigma converter using a 1-bit quantizer. 4. The second switching means comprises a digital circuit which inverts the digital signal converted by the analog-digital conversion means at each of the predetermined cycles, according to claim 2 or 3. Electricity meter using a hall element. 5. A Hall element which has an input terminal for inputting a Hall current corresponding to a measurement voltage and an output terminal for outputting a Hall voltage and is placed in a magnetic field corresponding to a measurement current, and a control signal which is inverted every predetermined period. And a first switching means for inverting the direction in which a Hall current is input to the input terminal at every predetermined cycle based on the control signal, Differential amplifying means for differentially amplifying the Hall voltage output from the output terminal; second switching means for inverting the output of the differential amplifying means based on the control signal every predetermined period; and A watt-hour meter using a Hall element configured to integrate the output of the second switching means on the basis of the control signal in each of the predetermined cycles, Electric power using a hall element, characterized in that it comprises a duty ratio correction means for detecting a bell time and a low level time and correcting the high level time and the low level time to correct the duty ratio of the control signal. Total. 6. The duty ratio correction means includes a synchronization means for synchronizing the predetermined clock signal with a clock signal having a frequency higher than the frequency, and a delay means for delaying the synchronization signal output from the synchronization means by a predetermined time. , A duty ratio deviation detecting means for detecting a deviation of a duty ratio of the control signal by detecting a high level time and a low level time of the synchronization signal, and outputting a correction signal for correcting the deviation, and inputting the correction signal And a waveform synthesizing means for replacing a predetermined section of the waveform of the delayed signal delayed by the delay means with the corrected waveform. The watt-hour meter using the hall element according to claim 5, wherein 7. The predetermined section replaced with the correction waveform is provided at the same time at the end of a certain cycle of the delay signal and at the start of the next cycle, and the predetermined time delayed by the delay means is: The electric energy meter using the hall element according to claim 6, wherein the time is set to be equal to this time.