JP2003052025A - Data slicer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To acquire a data slicer circuit for setting a Fleming's code by a function other than a CPU. SOLUTION: This data slicer circuit is provided with a clock run-in detection pulse generating circuit 14 for generating a pulse in a clock run-in period, a counter 15 for counting the generated output pulse period and for detecting the bit rate of the clock run-in, a decoder 16 for decoding the count value, a code data generating circuit 17 for generating a Fleming's code corresponding to the decode value and for setting it in a register 10, and a code data comparator circuit 11 for comparing the Fleming's code held in the register 10 with a Fleming's code superimposed on a video signal in order to obtain data superimposed on the video signal according to the matching of those codes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character broadcasting service for providing character signals or graphic information to a video signal transmitted by TV broadcasting, cable broadcasting or the like, and a character superposed on a video signal at a receiving device side. The present invention relates to a data slicer circuit that acquires character information data for broadcasting.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional data slicer circuit. In the figure, 1 is an A / D circuit for digitizing (quantizing) data superimposed on a video signal,
Reference numeral 2 is an arithmetic circuit that arithmetically corrects the digital data output from the A / D circuit 1. 3 is a sync separation circuit for separating a vertical sync signal and a horizontal sync signal from a video signal, and 4 is a P
A clock generation circuit 5 configured of an LL (Phase Locked Loop) circuit or the like, which generates a reference clock necessary for the slicer operation synchronized with the horizontal synchronization signal separated by the synchronization separation circuit 3, and a horizontal scanning 5 for counting the horizontal synchronization signal. The line counter 6 is a timing control circuit that generates a basic timing for receiving data. 7 is an address control circuit that has various registers for holding address information transmitted by the processing of a program of a CPU (not shown), and an address control circuit for accessing the register 10 and the memory 13 by the held address information, and 8 is an internal address Bus 9 is an internal data bus. Reference numeral 10 is a register that holds the Fleming code, 11 is a code data comparison circuit that compares the Fleming code held in the register 10 with the Fleming code that is superimposed on the video signal, and detects a match between them, and 12 is a code data comparison circuit. When 11 detects a match, it is a data shift circuit that shifts the serially received data after the Fleming code and performs serial / parallel conversion, and 13 is a memory such as a RAM that holds the data.

Next, the operation will be described. Text broadcasting in Japan and CCD (Closed Caption) in the United States
The Teletext service, which is implemented in Europe, such as Teletext and Teletext, provides textual information data superimposed in the vertical blanking period of a video signal. When such character information data is received, data is acquired by detecting a recognition code based on a standard called a Fleming code on the receiving device side due to the difference in the standard and format of data transmission.

FIG. 4 is a timing chart showing the operation of the conventional data slicer circuit, and shows an example of receiving teletext data. The operation will be described below with reference to FIGS. 3 and 4. First, the sync separation circuit 3
In the above, the vertical synchronizing signal and the horizontal synchronizing signal are separated from the input video signal, and a slicer interrupt request signal of one shot pulse synchronized with the vertical synchronizing signal is generated.
The CPU that has received the slicer interrupt request signal
The Fleming code ("17 ₁₆ " in the case of teletext data) stored in advance in the memory or the like is written in the register 10 by the processing of the program in the interrupt routine. The setting of the fleming code is performed by transmitting an address data through the internal address bus 8 and a framing code through the internal data bus 9 according to a command from the CPU, and the address control circuit 7 transmits the address data to the register 10 corresponding to the address data. Control so that the Fleming code is set. Further, the horizontal scanning line counter 5 counts the horizontal synchronization signals separated by the synchronization separation circuit 3 and detects the horizontal synchronization signal on which the teletext data is superimposed. The clock generation circuit 4 generates a reference clock necessary for the slicer operation synchronized with the horizontal sync signal separated by the sync separation circuit 3. The timing control circuit 6 is
In response to the detection of the horizontal synchronizing signal on which the teletext data is superimposed by the horizontal scanning line counter 5, the basic timing based on the reference clock generated by the clock generating circuit 4 is set to the A / D circuit 1, the arithmetic circuit 2, and the register 10. Supply to. Further, the basic timing is supplied to the data shift circuit 12 and the memory 13 in response to detection of a match by the code data comparison circuit 11 described later.

On the other hand, in the A / D circuit 1, the input video signal is sampled based on the basic timing and converted into digital data (n bits in FIG. 3), and the arithmetic circuit 2 is digital data (n bits). Is arithmetically corrected based on the basic timing to output digital data (1 bit). As shown in FIG. 4, the teletext data superimposed on the video signal is sent in the order of clock run-in, framing code, and teletext data. Here, the code data comparison circuit 11 compares the Fleming code held in the register 10 with the Fleming code superposed on the video signal and output from the arithmetic circuit 2 to detect a match between them. If they match, the code data comparison signal is activated (off → in FIG. 4).
on). In the data shift circuit 12, when the code data comparison signal becomes active, the data output from the arithmetic circuit 2, that is, the teletext data after the Fleming code is input, and the bit shift operation is performed bit by bit based on the basic timing. After that, serial / parallel conversion is performed. Further, the memory 13 holds the teletext data that has been parallel-converted based on the basic timing. After that, the CPU acquires the teletext data from the memory 13 through the internal data bus 9. If the Fleming codes do not match, the code data comparison signal is not activated, and the basic timing is not supplied to the data shift circuit 12 and the memory 13. Therefore, the data shift circuit 12 and the memory 13 receive the teletext data. Is not entered.

[0006]

Since the conventional data slicer circuit is configured as described above, the collation of the Fleming code is performed by writing the Fleming code in the register 10 by the instruction of the CPU and then performing the Fleming of the video signal. Since it is checked against the code, it is necessary to always set the Fleming code according to the instruction of the CPU for each transmission format, which causes a problem that the effective instruction load by the software of the CPU increases.

The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a data slicer circuit that reduces the load on a CPU without setting a framing code (recognition code) by an instruction from the CPU. To aim.

[0008]

A data slicer circuit according to the present invention includes a bit rate detecting circuit for detecting a bit rate of a clock run-in superimposed on a video signal,
The generated Fleming code generation circuit that generates a Fleming code according to the detected bit rate is compared with the Fleming code generated on the video signal. If they match, the Fleming code is superimposed on the video signal. And a Fleming code comparison circuit for acquiring data.

A data slicer circuit according to the present invention measures a certain period of character information data, detects a bit rate of the character information data, and generates a recognition code according to the detected bit rate. And a generating means.

In the data slicer circuit according to the present invention, the detecting means has a bit rate detecting circuit for detecting the bit rate of the clock run-in superimposed on the video signal,
The generation means is provided with a Fleming code generation circuit for generating a Fleming code according to the bit rate.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. 1 is a block diagram showing a data slicer circuit according to a first embodiment of the present invention, in which 1 is an A / D circuit for digitizing (quantizing) data superimposed on a video signal, and 2 is an A / D circuit. It is an arithmetic circuit that arithmetically corrects the digital data output from the D circuit 1.
Reference numeral 3 is a sync separation circuit for separating a vertical sync signal and a horizontal sync signal from a video signal, and 4 is a PLL (Phase Loc).
Ked Loop) circuit and the like, and a clock generation circuit 5 for generating a reference clock necessary for the slicer operation synchronized with the horizontal synchronization signal separated by the synchronization separation circuit 3; a horizontal scanning line counter 5 for counting the horizontal synchronization signal; A timing control circuit 6 generates a basic timing for receiving data. 7 is an address control circuit that has various registers for holding address information transmitted by the processing of a program of a CPU (not shown), and an address control circuit for accessing the register 10 and the memory 13 by the held address information, and 8 is an internal address Bus 9 is an internal data bus. Reference numeral 10 is a register that holds the Fleming code, 11 is a code data comparison circuit that compares the Fleming code held in the register 10 with the Fleming code that is superimposed on the video signal, and detects a match between them, and 12 is a code data comparison circuit. When 11 detects a match, it is a data shift circuit that shifts the serially received data after the Fleming code and performs serial / parallel conversion, and 13 is a memory such as a RAM that holds the data. Further, 14 is a clock run-in detection pulse generation circuit that detects a clock run-in and generates a pulse in the clock run-in period, and 15 is based on the CPU clock.
A counter for counting the output pulse period generated by the clock run-in detection pulse generation circuit 14 and detecting the bit rate of the clock run-in, 16 is a counter 15
The decoder 17 decodes the count value of, and 17 is a code data generation circuit that has a table in which the decoded value and the Fleming code correspond, and extracts the Fleming code according to the decoded value of the decoder 16 and sets it in the register 10. The code data comparison circuit 11 constitutes a Fleming code comparison circuit, the clock run-in detection pulse generation circuit 14 and the counter 15 constitute detection means: a bit rate detection circuit, and the decoder 16 and the code data generation circuit 17 constitute generation means. : Configure a Fleming code generation circuit.

Next, the operation will be described. FIG. 2 is a timing chart showing the operation of the data slicer circuit according to the first embodiment of the present invention, and shows reception of teletext data as an example. The operation will be described below with reference to FIGS. 1 and 2. First, the sync separation circuit 3 separates a vertical sync signal and a horizontal sync signal from an input video signal and generates a slicer interrupt request signal of a one-shot pulse synchronized with the vertical sync signal. This slicer interrupt request signal can be used for initialization when changing the received transmission format. Further, the horizontal scanning line counter 5 counts the horizontal synchronization signals separated by the synchronization separation circuit 3 and detects the horizontal synchronization signal on which the teletext data is superimposed. The clock generation circuit 4 generates a reference clock necessary for the slicer operation synchronized with the horizontal sync signal separated by the sync separation circuit 3. The timing control circuit 6 sets the basic timing based on the reference clock generated by the clock generation circuit 4 to the A / D circuit 1, in response to the detection of the horizontal synchronizing signal on which the teletext data is superimposed by the horizontal scanning line counter 5. It is supplied to the arithmetic circuit 2, the register 10, and the clock run-in detection pulse generation circuit 14. In addition, the basic timing is set to the data shift circuit 12 and the memory 13 in response to detection of a match by the code data comparison circuit 11 described later.
Supply to.

On the other hand, in the A / D circuit 1, the input video
Signal is sampled based on the basic timing and
Converted to digital data (n bits in Fig. 1), arithmetic circuit
2 uses digital data (n bits) as basic timing
Performs arithmetic correction based on digital data (1 bit)
Output. As shown in Figure 2, it is superimposed on the video signal.
Teletext data, clock run-in, Fleming
The code and teletext data are sent in that order. Ku
In the lock-run-in detection pulse generation circuit 14, the arithmetic circuit
Clock run-in from digital data output from 2
After detecting the rising edge of, a predetermined clock run-in period is detected
Then, a clock run-in detection pulse is generated. In addition,
The counter 15 uses the clock clock based on the CPU clock.
The clock generated by the input detection pulse generation circuit 14
Count the generation period of the clan-in detection pulse and
Detect the clan-in bit rate. In the case of Figure 2
Counts the "H" period of the clock run-in detection pulse.
To The decoder 16 counts from the counter 15.
The value is decoded, and the code data generation circuit 17
Fleming code corresponding to the code value (in this case, "17
₁₆)) Is automatically generated and the register set
Signal to generate a Fleming code in register 10.
Write the code. In this way, the Fleming code is
Focused on the rock run-in bit rate
Based on the clock run-in bit rate.
Automatically generate and set the encoding code.

Hereinafter, taking the case of teletext data as an example,
The above operation will be described in detail. The bit rate of teletext data (PCD format) is 6.9375 MHz (about 144 ns), and the CPU clock is 16 MHz.
(About 62.5 ns). The clock run-in detection pulse (6 cycles in FIG. 2) generated by the clock run-in detection pulse generation circuit 14 is counted by the counter 15 using the CPU clock as the count source. Count value: 144 ns × 12 / 62.5 ns =
27.648 → “1B ₁₆ ” This “1B ₁₆ ” is decoded by the decoder 16, and the code data generation circuit 17 decodes the Fleming code (“1B ₁₆ ” according to the decoded value).
7 ₁₆ ″) is automatically generated and a Fleming code is written in the register 10 by generating a register set signal.

Thereafter, as in the conventional technique, the code data comparison circuit 11 compares the framing code held in the register 10 with the framing code superposed on the video signal and output from the arithmetic circuit 2, and then compares them. To find a match. If they match, the code data comparison signal is activated (off → on in FIG. 2). In the data shift circuit 12, when the code data comparison signal becomes active, the data output from the arithmetic circuit 2, that is, the teletext data after the Fleming code is input, and the bit shift operation is performed bit by bit based on the basic timing. After that, serial / parallel conversion is performed.
Further, the memory 13 holds the teletext data that has been parallel-converted based on the basic timing. afterwards,
The CPU acquires teletext data from the memory 13 via the internal data bus 9. If the Fleming codes do not match, the code data comparison signal is not activated, and the basic timing is not supplied to the data shift circuit 12 and the memory 13. Therefore, the data shift circuit 12 and the memory 13 receive the teletext data. Is not entered. Further, since the line between the register 10 and the internal data bus 9 is provided as in the conventional technique, the CPU can inspect the Fleming code automatically generated by the code data generation circuit 17 and set in the register 10. it can. Further, the count source of the counter 15 is not limited to the CPU clock, and another clock may be used as the count source.

As described above, according to the first embodiment, in the collation of the Fleming code, the Fleming code corresponding to the bit rate of the clock run-in is automatically set without setting the Fleming code by the instruction of the CPU. Since it is generated and set in, and it is collated with the framing code of the video signal, the CPU is always used for each transmission format.
C does not need to set the Fleming code by the command
It is possible to reduce the effective instruction load due to PU software.

[0017]

As described above, according to the present invention, the bit rate detecting circuit for detecting the bit rate of the clock run-in superposed on the video signal, and the framing code according to the detected bit rate are generated. And a fleming code comparison circuit for comparing the generated framing code with the framing code superimposed on the video signal and acquiring the data superimposed on the video signal when they match. With this configuration, the Fleming code generation circuit automatically generates the Fleming code according to the bit rate of the clock run-in, so that the load of the CPU can be reduced without setting the Fleming code by the CPU. is there.

According to the present invention, the detecting means for measuring a certain period of the character information data and detecting the bit rate of the character information data, and the generating means for generating the recognition code according to the detected bit rate. Since it is configured so that the generation means automatically generates a recognition code according to the bit rate of the character information data, the CPU
Thus, there is an effect that the load on the CPU can be reduced without setting a recognition code.

According to the present invention, the detecting means has a bit rate detecting circuit for detecting the bit rate of the clock run-in superposed on the video signal, and the generating means generates the Fleming code according to the bit rate. Since the Fleming code generation circuit is configured to have the Fleming code generation circuit, the Fleming code generation circuit automatically generates the Fleming code according to the bit rate of the clock run-in.
C without setting Fleming code by CPU
This has the effect of reducing the load on the PU.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data slicer circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the data slicer circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional data slicer circuit.

FIG. 4 is a timing chart showing the operation of a conventional data slicer circuit.

[Explanation of symbols]

1 A / D circuit, 2 arithmetic circuit, 3 sync separation circuit, 4
Clock generation circuit, 5 horizontal scanning line counter, 6 timing control circuit, 7 address control circuit, 8 internal address bus, 9 internal data bus, 10 register, 11
Code data comparison circuit (Fleming code comparison circuit), 12 data shift circuit, 13 memory, 14
Clock run-in detection pulse generation circuit (detection means: bit rate detection circuit), 15 counter (detection means: bit rate detection circuit), 16 decoder (generation means: Fleming code generation circuit), 17 code data generation circuit (generation means: Fleming code generation circuit).

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Jun Nakahara             3-1-1 Chuo 3-chome, Itami City, Hyogo Prefecture             Machine System LSI Design Co., Ltd.             Inside the company F-term (reference) 5C063 EB03 EB06

Claims (3)

[Claims] 1. A bit rate detection circuit for detecting a bit rate of a clock run-in superimposed on a video signal,
A Fleming code generation circuit that generates a Fleming code according to the bit rate detected by the bit rate detection circuit, and compares the Fleming code generated by the Fleming code generation circuit and the Fleming code superimposed on the video signal, A data slicer circuit including a Fleming code comparison circuit that acquires data superimposed on a video signal when they match. 2. A data slicer circuit for obtaining character information data for character broadcasting superimposed on a video signal,
It is provided with a detecting means for measuring a certain period of the character information data and detecting a bit rate of the character information data, and a generating means for generating a recognition code according to the bit rate detected by the detecting means. Characteristic data slicer circuit. 3. The detection means has a bit rate detection circuit for detecting the bit rate of the clock run-in superimposed on the video signal, and the generation means generates a Fleming code generation circuit for generating a Fleming code according to the bit rate. The data slicer circuit according to claim 2, further comprising: