JP2003046809A - Nonlinear processor and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonlinear processor capable of supporting a difference in a nonlinear characteristic according to a type or individual difference of a display device. SOLUTION: A three-dimensional correction on a signal level is made to an image signal which is subjected to a nonlinear process (γcorrection), in correspondence to a horizontal and vertical position of a pixel on a display screen of an image display part and the signal level of the pixel data by a three-dimensional correction value. Thus, a precise γ correction can be made, and besides a level boundary value on the signal level in the three-dimensional correction can be variably set. By doing so, the three-dimensional correction with optimum correction precision is possible with respect to a nonlinear characteristic of various display devices and each display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-linear processing device for correcting a level of a video signal by non-linear processing according to a display characteristic of an image display section for displaying an image based on the video signal, and a non-linear processing device thereof. The present invention relates to an image display device using.

[0002]

2. Description of the Related Art In order to obtain an image based on a video signal by supplying the video signal to an image display section such as a liquid crystal display panel section for displaying an image, the image display of the level of the video signal is performed. It has been proposed to perform correction by non-linear processing according to the display characteristics of the part. Such a correction of the level (voltage level) of the video signal by the non-linear processing is usually called "γ correction".

For example, when the image display section is formed by a liquid crystal display panel section for image display, the image display based on the video signal is performed in the liquid crystal panel incorporated in the liquid crystal display panel section. In principle, this is due to the change in the light transmittance in response to the change in the level of the video signal in the liquid crystal panel. FIG. 21 shows an input voltage-light transmittance characteristic showing a relationship between an input voltage V and a light transmittance T for an example of a liquid crystal panel incorporated in a liquid crystal display panel section for image display. This input voltage-optical transmittance characteristic is a non-linear characteristic as apparent at a glance, and a video signal supplied to a liquid crystal display panel section for displaying an image in a liquid crystal panel having such a display characteristic is Level correction is required to correct the non-linear characteristic.

The level correction applied to the video signal in accordance with this request is γ correction. Therefore, when the liquid crystal display panel section for image display is used, the γ correction is a display characteristic of the liquid crystal display panel section. This is a non-linear correction of the level of the video signal supplied to the liquid crystal display panel section according to the input voltage-light transmittance characteristics of the liquid crystal panel built in the panel section.

FIG. 22 shows γ for the level of the video signal.
The example of the conventional image display apparatus which corrects is shown. In this case, the red primary color video signal S forming the color video signal
R, green primary color video signal SG, blue primary color video signal SB
An analog / digital (A / D) converter 121R,
The signals 121G and 121B are digitized into a digital red primary color signal DR, a digital green primary color signal DG, and a digital blue primary color signal DB. These digital red primary color signal DR, digital green primary color signal DG, and digital blue primary color signal DB are stored in the contrast / brightness adjusting unit 1.
Then, the contrast adjustment and the brightness adjustment are performed for each of them. Then, the adjusted digital red primary color signal DRA and digital green primary color signal DG obtained from the contrast / brightness adjustment unit 122
The A and digital blue primary color signal DBA is supplied to the white balance adjustment unit 123.

In the white balance adjustment unit 123, the gain adjustment by the gain adjustment unit 124R for the digital red primary color signal DRA and the DC level adjustment unit 1 are performed.
DC level adjustment by 25R is performed, and the digital red primary color signal DRB adjusted by the DC level adjusting unit 125R
Is obtained. Further, the digital green primary color signal DGA is similarly processed by the gain adjusting unit 124G and the DC level adjusting unit 125G, and the digital blue primary color signal DBA is also processed by the gain adjusting unit 124B and the DC level adjusting unit 125B. Is done. Digital red primary color signal DRB, digital green primary color signal DGB and digital blue primary color signal DB obtained in this way
In B, it is assumed that the relative DC level between them is properly set and the white balance is adjusted.

The digital red primary color signal DRB, the digital green primary color signal DGB, and the digital blue primary color signal DBB obtained from the white balance adjustment unit 123 are the γ correction unit 1
26. In the γ correction unit 126, the digital red primary color signal DRB is processed by the nonlinear processing unit 127R,
Receive a non-linear process for that level. The digital green primary color signal DGB and the digital blue primary color signal DBB are also subjected to the non-linear processing by the non-linear processing units 127G and 127B.

The non-linear processing section 127R has a display characteristic of the liquid crystal display panel section 118R, which will be described later, that is, a non-linear characteristic having an inverse relationship to the input voltage-light transmittance characteristic of the liquid crystal panel incorporated in the liquid crystal display panel section 118R. The built-in correction signal data table that represents the digital red primary color signal DRB is sequentially collated with the correction signal data table to read out the corresponding correction signal data, and the correction signal data table It is derived as a corrected digital red primary color signal DRC. Thereby, the digital red primary color signal DRC derived from the non-linear processing unit 127R corrects the input voltage-light transmittance characteristic of the liquid crystal panel incorporated in the liquid crystal display panel unit 118R, for example, as shown in FIG. Therefore, it is assumed that the signal level is corrected by non-linear processing, that is, γ correction is performed. Similarly, the non-linear processing unit 127G performs the γ correction processing corresponding to the liquid crystal panel incorporated in the liquid crystal display panel unit 118G on the digital green primary color signal DGB and outputs the digital green primary color signal DGC. Further, the non-linear processing unit 127B also performs γ correction processing corresponding to the liquid crystal panel built in the liquid crystal display panel unit 118B on the digital green primary color signal DBB and outputs the digital green primary color signal DBC.

The .gamma.-corrected digital red primary color signal DRC, digital green primary color signal DGC, and digital blue primary color signal DBC output from the .gamma. And the γ-corrected red primary color image signal SR
C ', green primary color video signal SGC', blue primary color video signal S
The display drive unit 117 is set to BC '.
R, 117G, 117B. As a result, the display drive signal SDR ′ based on the red primary color image signal SRC ′ is obtained from the display drive unit 117R and is supplied to the liquid crystal display panel unit 118R. Further, a display drive signal SDG 'based on the green primary color image signal SGC' is obtained from the display drive section 117G and is supplied to the liquid crystal display panel section 118G. Further, the display drive unit 117B
A display drive signal SDB ′ based on the blue primary color video signal SBC ′ is obtained from the liquid crystal display panel unit 118B.
Is supplied to.

Further, in the case of the image display device of FIG. 22,
A timing signal generation unit 119 and a PLL unit 120 that form timing signals T1 to T6 based on the horizontal synchronization signal SH and the vertical synchronization SV are provided. The timing signal generation unit 119 supplies the timing signals T1 to T6 to the display drive units 117R, 117G, 117B and the liquid crystal display panel units 118R, 118G, 118B, respectively, and these parts are set to predetermined preset values. Operate with timing.

As a result, the liquid crystal display panel section 118R is driven by the display drive signal SDR 'from the display drive section 117R, and in the liquid crystal display panel section 118R, γ
The red primary color image corresponding to the corrected red primary color video signal SRC 'is displayed. Similarly, in the liquid crystal display panel units 118G and 118B, a green primary color image and a blue primary color image corresponding to the green primary color image signal SGC ′ and the blue primary color image signal SBC ′ which have been subjected to the γ correction are displayed.

Liquid crystal display panel sections 118R, 118G, 1
The red primary color image, the green primary color image, and the blue primary color image respectively obtained in 18B are superimposed and projected on the projection screen through a projection optical system including a projection lens, and the red primary color image signal SR and the green primary color image are projected on the projection screen. Signal SG
And a color image based on the color video signal formed by the blue primary color video signal SB is obtained.

With such a conventional image display device, γ
Correction, that is, in this case, the liquid crystal display panel section 118R, 1
The input voltage-light transmittance characteristic of the liquid crystal panel incorporated in each of 18G and 118B can be corrected. In this case, the γ correction is performed by the liquid crystal display panel sections 118R and 118R.
The pixel data of the digital video signal corresponding to each of the pixels distributed over the entire image screen obtained in the liquid crystal panel incorporated in each of G and 118B will be commonly used. That is, for example, the pixel data of the digital video signal corresponding to the pixel in the central portion of the image screen obtained in the liquid crystal panel and the pixel data of the digital video signal corresponding to the pixels in the peripheral portion of the image screen have the same non-linear characteristic. The .gamma.-correction is performed based on the .gamma. Correction, and the .gamma.-correction cannot correct the difference in the input voltage-light transmittance characteristic depending on the position in the screen of the liquid crystal panel.

Further, the liquid crystal display panel sections 118R, 118G and 118B are generated due to the level fluctuations of the input video signals, that is, the red primary color video signal SR, the green primary color video signal SG and the blue primary color video signal SB, respectively. Undesired variations in luminance and chromaticity in the obtained red primary color image, green primary color image, and blue primary color image are not corrected.

Therefore, the present applicant can previously correct the input voltage-light transmittance characteristic according to the horizontal and vertical directions of the screen, that is, the position on the screen, and also the correction according to the signal level. A non-linear processing device and an image display device capable of achieving the above are proposed (Japanese Patent Application No. 9-271598).
issue). This means that the γ-corrected pixel data is further corrected according to the position in the two-dimensional direction (horizontal / vertical direction) on the screen and the level, that is, the three-dimensional correction is added to the γ-correction process. is there.

First, the correction in the horizontal and vertical directions is as follows. FIG. 23 shows a lattice block that serves as horizontal and vertical area information for horizontal and vertical correction. The grid block is divided into units of, for example, 128 pixels in the X direction (horizontal direction) and the Y direction (vertical direction) on the screen, and a plurality of areas are set in a grid pattern. It is formed by the correction value C given to each intersection of the horizontal line and the vertical line. For example, if coordinates 0 to p are given in the X direction and coordinates 0 to q are given in the Y direction, C (0,0), C
(0, 1) ... Each correction value shown as C (p, q) is set. That is, (p + 1) × (q + 1) correction values are set. Then, this forms (p × q) areas surrounded by the four intersection coordinates (correction values). Each area is [1,1] [1,2] ... [p,
q].

In further horizontal and vertical correction for the γ correction, it is first detected to which area the pixel data belongs to such a lattice block. Then, when the area is discriminated, the position in the area is also discriminated, and the two-dimensional correction value is calculated from the four correction values forming the area. Then, by further correcting the γ-corrected image data with the calculated two-dimensional correction value, correction according to the horizontal / vertical directions becomes possible. For example, taking a certain pixel data dxy as an example, it is first determined that this pixel data dxy is data included in the area [5, 3], and further, at what position in the area [5, 3]. Determine if there is. And area [5,
3], the four correction values C (4,2), C (5,2), C (4,3), and C around it are included in the data.
Since (5, 3) is used, the two-dimensional correction value is calculated from the intersection coordinates of the correction values and the distance of the pixel data dxy in the area [5, 3].

The three-dimensional correction is three-dimensionally expanded by taking a signal level on the Z axis in addition to the two-dimensional correction. FIG. 24 shows a state in which the lattice blocks of FIG. 23 are stacked in the Z-axis direction to form a three-dimensional structure. In the Z-axis direction, level boundaries of several stages are set as shown by signal levels 0, 1, ... A two-dimensional lattice block as shown in FIG. 23 is set at each level boundary to form a three-dimensional correction value configuration. That is, in this case,
The correction value C is set for each three-dimensional coordinate intersection,
The correction value C is C (0,0,0) ... C (p, q, r)
Is set. That is, (p + 1) × (q + 1) × (r +
1) One correction value is set. The level blocks L1, L2 ... Lr are defined between the level boundaries. In addition, the areas [1, 1] ... [p, q] shown in FIG.
A block penetrating each of these into each level block in the Z direction is called a position block. Although described in detail later, FIG. 2 shows the position block A [i, j].

In this case, in the three-dimensional correction according to the horizontal and vertical directions and the level for the γ correction, first, the level block and the position block including the pixel data are discriminated. Then, when the level block and the position block are discriminated, the level in the level block and the position in the position block are also discriminated, and the three-dimensional correction value is calculated. In this case, certain pixel data is located in the three-dimensional block where the level block and the position block intersect. This three-dimensional block is a block surrounded by eight correction values C. Therefore, from the eight correction values, the three-dimensional correction value corresponding to the pixel data is calculated according to the position and level in the three-dimensional block, and the γ-corrected image data is calculated by the calculated three-dimensional correction value. By further correcting, it becomes possible to perform correction according to the horizontal / vertical direction and the signal level.

[0020]

When a non-linearly corrected video signal is obtained by the technique previously proposed by the applicant, the non-linearly corrected video signal is displayed on the display screen. Undesired brightness fluctuations and chromaticity fluctuations depending on the horizontal and vertical positions of the image are corrected, and further, undesired brightness fluctuations of the display screen obtained in the image display unit caused by level fluctuations in the original video signal and The chromaticity variation can be corrected.

By the way, generally, the non-linear characteristics are different for each display device. For example, LCD (Liquid C
rystal Display: LCD panel, CRT (Cathode Ray)
Tube: cathode ray tube, PDP (Plasma Display Panel),
PALC (Plasma Addressed Liquid Crystal), DL
There are various display devices such as P (Digital Light Processing), but these have different nonlinear characteristics. Even with the same type of display device, there are variations in non-linear characteristics among individuals. For example, when considering a plurality of liquid crystal panels, the non-linear characteristics are roughly the same, but there are variations among individuals.

In such a situation, when considering the above-described three-dimensional correction, the setting of the level boundary in the Z-axis direction is not always appropriate, and the effect of the above-mentioned three-dimensional correction is satisfactorily obtained. There were cases where it was not possible. For example, when the non-linear processing device including the above-mentioned three-dimensional correction is applied to the circuit system of various display devices, it is not possible to deal with the difference in the non-linear characteristics of each display device. Further, even when mounted on the same type of display device, it is not possible to cope with individual differences in nonlinear characteristics. Due to these circumstances, the three-dimensional correction accuracy for γ correction may be deteriorated.

[0023]

In view of such a situation, the present invention provides a non-linear processing apparatus capable of coping with a difference in non-linear characteristic due to a type of display device or individual difference. In addition, such a nonlinear processing device can be realized with a relatively small-scale circuit configuration. An image display device equipped with such a non-linear processing device is also provided.

The non-linear processing device of the present invention comprises a non-linear processing means for correcting a video signal by a non-linear processing of a signal level according to a display characteristic of an image display section for displaying an image based on the video signal, and the above-mentioned video signal. The horizontal and vertical position discriminating means for discriminating the position of the pixel in the horizontal and vertical directions, the level discriminating means for discriminating the signal level of the pixel in the video signal, and the level boundary value used for discrimination by the level discriminating means can be variably set. According to the level boundary setting means, the position in the horizontal and vertical directions discriminated by the horizontal and vertical position discriminating means, and the signal level discriminated by the level discriminating means, a three-dimensional correction value for the signal level is generated to generate a video signal. A three-dimensional correction means for performing three-dimensional correction, a video signal corrected by the non-linear processing means, and an image corrected by the three-dimensional correction means. So that and a synthesizing means for outputting a signal synthesized by.

Further, the image display device of the present invention comprises a non-linear processing means for correcting the video signal by a non-linear processing of the signal level according to the display characteristic of the image display section for displaying the image based on the video signal, and the above-mentioned video. Horizontal / vertical position discriminating means for discriminating the position of the pixel in the horizontal / vertical direction in the signal, level discriminating means for discriminating the signal level of the pixel in the video signal, and level boundary values used for discrimination by the level discriminating means are variably set. A level boundary setting means, a horizontal / vertical position determined by the horizontal / vertical position determination means, and a three-dimensional correction value for the signal level according to the signal level determined by the level determination means. Three-dimensional correction means for performing three-dimensional correction, the video signal corrected by the non-linear processing means, and the three-dimensional correction means Synthesizing means for outputting an image signal synthesized and, so and an image display unit having an image display unit for displaying an image based on the video signal outputted from said synthesizing means.

Further, in these non-linear processing devices or image display devices, the level boundary setting means has a register for storing the level boundary value, and the level boundary value of the register is rewritten to thereby make the level discrimination means. The level boundary value used for the discrimination in (1) is variably set. Alternatively, the level boundary setting means stores various level boundary values, and supplies the level boundary value selected from the stored level boundary values to the level determining means, so that the level determining means determines the level boundary values. The level boundary value used for is set. Further, a boundary value offset means for offsetting the level boundary value set for use in the discrimination by the level discriminating means by further supplying an offset value to the level discriminating means is further provided.

That is, according to the present invention, the position of the pixel in the horizontal and vertical directions on the display screen of the image display unit and the pixel data thereof are added to the video signal subjected to the non-linear processing (γ correction) by the non-linear processing means by the three-dimensional correction value. Three-dimensional correction is performed on the signal level according to the signal level of. Since the level boundary value relating to the signal level in the three-dimensional correction can be variably set, optimum three-dimensional correction can be performed for various display devices and non-linear characteristics of each display device.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in the following order. 1. 1. Configuration of image display device Position block and level block 3. 3. Configuration example of non-linear correction unit 4. Configuration example of non-linear correction unit 5. Configuration example of non-linear correction unit Configuration example of non-linear correction unit 7. Configuration example of non-linear correction unit 8. Non-linear correction unit configuration example

1. Configuration of Image Display Device First, a configuration example of the image display device according to the embodiment will be described with reference to FIG. This image display device is an example of an image display device that employs a liquid crystal display panel as a display device, and has a configuration example in which a video signal is digitized to perform signal processing such as white balance and nonlinear processing. In particular, the configuration of the non-linear correction unit 16 is characteristic, and the configuration of the non-linear correction unit 16 is
Will be described later in detail. As the image display device of the present invention, various types of signal processing systems up to the preceding stage of the non-linear correction unit 16, signal processing systems subsequent to the non-linear correction unit 16, and types of display devices to be adopted are conceivable. The invention is not limited to the configuration example of the image display device described below.

In the example shown in FIG. 1, a red primary color video signal SR and a green primary color video signal S forming a color video signal.
The G and blue primary color video signals SB are respectively supplied to the A / D converter 1
It is digitized in 1R, 11G, and 11B to be a digital red primary color signal DR, a digital green primary color signal DG, and a digital blue primary color signal DB. Then, the digital red primary color signal DR, the digital green primary color signal DG, and the digital blue primary color signal DB are supplied to the contrast / brightness adjustment unit 12, and the contrast adjustment and the brightness adjustment are performed for each. Then, the adjusted digital red primary color signal DRA and digital green primary color signal D obtained from the contrast / brightness adjustment unit 12
The GA and digital blue primary color signal DBA are supplied to the white balance adjustment unit 13.

In the white balance adjusting section 13,
Gain adjustment unit 1 for digital red primary color signal DRA
The gain adjustment by the 4R and the DC level adjustment by the DC level adjusting unit 15R are performed, and the adjusted digital red primary color signal DRB is obtained. Similarly, the gain adjustment unit 14G performs the gain adjustment for the digital green primary color signal DGA, and the direct current level adjustment unit 15G performs the direct current level adjustment to obtain the adjusted digital green primary color signal DGB. Similarly, digital blue primary color signal DBA
The gain adjustment by the gain adjustment unit 14B and the DC level adjustment by the DC level adjustment unit 15B are performed to obtain the adjusted digital blue primary color signal DBB. Digital red primary color signal DR obtained in this way
B, the digital green primary color signal DGB and the digital blue primary color signal DBB are assumed to have been subjected to white balance adjustment by appropriately setting the relative DC level between them.

Digital red primary color signal DRB and digital green primary color signal D obtained from the white balance adjusting section 13.
The GB and digital blue primary color signal DBB are supplied to the non-linear correction unit 16. In the non-linear correction unit 16, the digital red primary color signal DRB is supplied to the non-linear processing unit 17R and the three-dimensional correction unit 18R, and the digital green primary color signal DGB is supplied to the non-linear processing unit 17G and the three-dimensional correction unit 18R. Further, the digital blue primary color signal DBB is supplied to the non-linear processing unit 17B and the three-dimensional correction unit 18B.

Further, in the case of the configuration example shown in FIG. 1,
A timing signal generator 53 and an address data generator 5 to which a horizontal synchronizing signal SH and a vertical synchronizing SV in a color video signal formed by the red primary color video signal SR, the green primary color video signal SG and the blue primary color video signal SB are supplied.
5R, 55G, 55B are provided. The PLL unit 54 is connected to the timing signal generating unit 53. Timing signal generator 53 and address data generator 55
Horizontal sync signal S supplied to each of R, 55G and 55B
Regarding H and the vertical synchronization SV, the red primary color video signal SR, the green primary color video signal SG, and the blue primary color video signal SB are in synchronization with them.

The timing signal generator 53 forms timing signals T1 to T6 based on each of the horizontal synchronization signal SH and the vertical synchronization SV. Address data generator 55R
According to the horizontal synchronizing signal SH and the vertical synchronizing signal SV,
A horizontal address data QRH and a vertical address data QRV corresponding to each pixel in an image screen obtained on a liquid crystal panel incorporated in a liquid crystal display panel unit 52R described later are generated, and these are generated by a three-dimensional correction unit in the digital nonlinear correction unit 16. Supply to 18R. In addition, the address data generation unit 55G causes the horizontal synchronization signal SH and the vertical synchronization signal SV.
Accordingly, horizontal address data QGH and vertical address data QGV corresponding to each pixel on the image screen obtained on the liquid crystal panel in the liquid crystal display panel unit 52G are generated and supplied to the three-dimensional correction unit 18G. The address data generator 55B also generates horizontal address data QBH and vertical address data corresponding to each pixel in an image screen obtained on the liquid crystal panel in the liquid crystal display panel unit 52B in accordance with the horizontal sync signal SH and the vertical sync signal SV. Q
BVs are generated and supplied to the three-dimensional correction unit 18B.

In the non-linear correction section 16, the non-linear processing section 17R, the three-dimensional correction section 18R and the synthesizing section 19 are provided as parts corresponding to the input digital red primary color signal DRB.
R and ROM 20R are provided. Further, as a part corresponding to the digital green primary color signal DGB, a non-linear processing part 17G,
A three-dimensional correction unit 18G, a combining unit 19G, and a ROM 20G are provided. Further, as a part corresponding to the digital blue primary color signal DBB, a non-linear processing part 17B and a three-dimensional correction part 18 are provided.
B, a synthesizing unit 19B, and a ROM 20B.

A non-linear processing section 17R corresponding to the digital red primary color signal DRB, a three-dimensional correction section 18R, a combining section 19
The R and ROM 20R will be described. Non-linear processing unit 17
R represents a display characteristic of the liquid crystal display panel section 52R, that is, a γ correction data that represents a non-linear characteristic that has an inverse relationship to the input voltage-light transmittance characteristic of the liquid crystal panel incorporated in the liquid crystal display panel section 52R. And the digital red primary color signal D obtained from the white balance adjustment unit 13
According to the signal level of RB, the corresponding γ correction data is read out, and they are subjected to the nonlinear processing (γ
It is derived as a digital red primary color signal DRC that has been subjected to (correction). As a result, the digital red primary color signal DRC derived from the non-linear processing unit 17R becomes the liquid crystal display panel unit 5
The liquid crystal panel incorporated in the 2R is, for example, subjected to γ correction for correcting the input voltage-light transmittance characteristic shown in FIG. 21, and is supplied to the combining unit 19R.

On the other hand, the three-dimensional correction unit 18R, in accordance with the horizontal address data QRH and the vertical address data QRV from the address data generation unit 55R, outputs each pixel data in the digital red primary color signal DRB obtained from the white balance adjustment unit 13. The signal level corresponds to the pixel data in the horizontal and vertical positions of the pixel on the image screen obtained on the liquid crystal panel built in the liquid crystal display panel section 52R, and the signal of the pixel data in the digital red primary color signal DRB. Perform 3D correction according to the level. Each correction value C in the three-dimensional coordinate space in the horizontal direction, the vertical direction, and the level direction for the three-dimensional correction is RO
It is stored in the M20R and the three-dimensional correction unit 18R
The correction value C of M20R is loaded and used for calculation. Then, the three-dimensional corrected digital red primary color signal DRS, which is obtained from the three-dimensional correction unit 18R and is formed by the pixel data on which the three-dimensional correction has been performed on the signal level,
It is supplied to the synthesis unit 19R.

In the synthesizing unit 19R, the nonlinear processing unit 1
The digital red primary color signal DRC corrected by the non-linear processing of the signal level obtained from 7R and the three-dimensional corrected digital red primary color signal DR subjected to the three-dimensional correction of the signal level obtained from the three-dimensional correction unit 18R.
S and S are combined. Thereby, from the synthesizing unit 19R,
The digital red primary color signal DRD which is further three-dimensionally corrected with respect to the γ correction is transmitted.

Corresponding to the digital green primary color signal DGB,
Non-linear processing unit 17G, three-dimensional correction unit 18G, combining unit 19
The G, ROM 20G, and address data generator 55G also function in the same manner as described above. That is, the non-linear processing unit 47G performs γ correction on the input voltage-light transmittance characteristic of the liquid crystal panel incorporated in the liquid crystal display panel unit 52G, derives the γ-corrected digital green primary color signal DGC, and supplies it to the synthesizing unit 49G. To do. The three-dimensional correction unit 18G uses the horizontal address data Q from the address data generation unit 55G.
Using the GH and the vertical address data QGB, three-dimensional correction is performed according to the horizontal and vertical positions of the pixel data with respect to the digital green primary color signal DGB and the signal level of the pixel data in the digital green primary color signal DGB. The original corrected digital green primary color signal DGS is supplied to the combining unit 49G. In the combining unit 49G, the digital green primary color signal DGC obtained from the non-linear processing unit 47G.
And the three-dimensional corrected digital green primary color signal DGS obtained from the three-dimensional correction unit 48G are combined and output.
The digital green primary color signal DGD that has been three-dimensionally corrected with respect to the correction is transmitted.

Corresponding to the digital blue primary color signal DBB,
Non-linear processing unit 17B, three-dimensional correction unit 18B, combining unit 19
The B, the ROM 20B, and the address data generator 55B also function in the same manner as described above. That is, the non-linear processing unit 47B performs γ correction on the input voltage-light transmittance characteristics of the liquid crystal panel incorporated in the liquid crystal display panel unit 52B, derives the γ-corrected digital blue primary color signal DBC, and supplies it to the combining unit 49B. To do. The three-dimensional correction unit 18B uses the horizontal address data Q from the address data generation unit 55B.
BH and vertical address data QBV are used to perform three-dimensional correction according to the horizontal and vertical positions of the pixel data with respect to the digital green primary color signal DBB and the signal level of the pixel data in the digital blue primary color signal DBB. The original corrected digital blue primary color signal DBS is supplied to the combining unit 49B. In the combining unit 49B, the digital blue primary color signal DBC obtained from the non-linear processing unit 47B.
And the three-dimensional corrected digital blue primary color signal DBS obtained from the three-dimensional correction unit 48B are combined and output.
The digital blue primary color signal DBD, which is further three-dimensionally corrected with respect to the correction, is transmitted.

Then, the non-linearly corrected digital red primary color signal DRD obtained from the digital non-linear correction unit 16
Is converted into an analog signal by the D / A conversion unit 50R, and the non-linearly corrected red primary color image signal SRD is supplied to the display drive unit 51R. Similarly, the non-linearly corrected digital green primary color signal DGD is analogized by the D / A conversion unit 50G and is supplied to the display drive unit 51G as the non-linearly corrected green primary color video signal SGD. Furthermore, the non-linearly corrected digital blue primary color signal DBD is
The blue primary color image signal SBD which has been analogized by the D / A conversion unit 50B and has been nonlinearly corrected is used as the display drive unit 5
1B is supplied.

The display drive section 51R is the liquid crystal display panel section 5
2R, the display drive section 51R and the liquid crystal display panel section 52R are connected to the timing signal generation section 5R.
Timing signals T1 and T4 from 3 are respectively supplied,
It operates at a preset timing according to the timing signals T1 and T4. As a result, the display drive signal SPR based on the red primary color video signal SRD is obtained from the display drive section 51R and is supplied to the liquid crystal display panel section 52R. And the non-linearly corrected red primary color image signal SR obtained from the D / A converter 50R
A state in which a red primary color image corresponding to D is displayed is obtained.

The display drive section 51G is connected to the liquid crystal display panel section 52G, and the display drive section 5G is connected to the liquid crystal display panel section 52G.
The 1G and liquid crystal display panel section 52G are supplied with timing signals T2 and T5 from the timing signal generating section 53, respectively, and operate at preset timings according to the timing signals T2 and T5. As a result, the display drive signal SPG based on the green primary color video signal SGD is obtained from the display drive section 51G, and this is supplied to the liquid crystal display panel section 52G, and the liquid crystal display panel section 52G.
At the built-in liquid crystal panel, the D / A converter 5
A state in which a green primary color image corresponding to the non-linearly corrected green primary color video signal SGD obtained from 0G is displayed is obtained.

Further, the display drive section 51B is connected to the liquid crystal display panel section 52B, and the display drive section 51B and the liquid crystal display panel section 52B receive the timing signals T3 and T6 from the timing signal generation section 53. They are supplied respectively and operate at preset timings according to the timing signals T3 and T6. As a result, a display drive signal SPB based on the blue primary color image signal SBD is obtained from the display drive section 51B, and this is supplied to the liquid crystal display panel section 52B.
At the built-in liquid crystal panel, the D / A converter 5
A state in which a blue primary color image corresponding to the non-linearly corrected blue primary color image signal SBD obtained from 0B is displayed is obtained.

In this way, the liquid crystal display panel section 52
The red primary color image, the green primary color image, and the blue primary color image obtained in R, 52G, and 52B are superimposed and projected on the projection screen through a projection optical system including a projection lens, and the red primary color image signal SR is projected on the projection screen. A color image based on the color video signal formed by the green primary color video signal SG and the blue primary color video signal SB is obtained.

Liquid crystal display panel sections 52R, 52G and 52
Each of the red primary color image, the green primary color image, and the blue primary color image obtained in B is based on the non-linearly corrected digital red primary color signal DRD, the digital green primary color signal DGD, and the digital blue primary color signal DBD obtained from the non-linear correction unit 16. As will be understood, the nonlinear correction of this example is performed by the
For example, the γ correction performed to correct the input voltage-light transmittance characteristic shown in FIG. 21 and the digital red primary color signal DR
B, digital green primary color signal DGB, digital blue primary color signal DBB, and horizontal and vertical positions performed for the signal level of each pixel data, and three-dimensional correction according to the signal level. As a result, not only the undesired change of the display screen due to the difference in the display characteristics due to the position on the image screen of the liquid crystal panel built in the liquid crystal display panel units 52R, 52G, 52B, but also the original analog video signal Undesired luminance fluctuations and chromaticity fluctuations of the display screen caused by level fluctuations in a certain red primary color video signal SR, green primary color video signal SG or blue primary color video signal SB are also properly corrected. .

Although FIG. 1 shows the CPU 1, the ROM 2 and the RAM 3, the CPU 1 functions as an operation control section of the image display device. The ROM 2 stores the operation program of the CPU 1 and various control constants. The RAM 3 is used as a work area for storing various control coefficients and for calculations. Particularly for the circuit system shown in FIG. 1, the contrast / brightness adjusting unit 12 and the white balance adjusting unit 1
3, operation control for the non-linear correction unit 16, the timing signal generation unit 53, etc. is performed. For example, setting of adjustment coefficients for the contrast / brightness adjustment unit 12 and the white balance adjustment unit 13, setting of register coefficients or supply of selection control signals to the three-dimensional correction units 18R, 18G, and 18B of the nonlinear correction unit 16 are performed. Process. The control for each of the three-dimensional correction units 18R, 18G, and 18B will be described in each of Configuration Examples to be described later.

As described above, the image display device of the present invention is characterized by the non-linear correction section 16, and other signal processing systems and types of display devices adopted are limited to the example of FIG. It is not something that will be done. As the signal processing circuit, for example, a configuration in which a frame memory, a pixel number conversion processing unit, or the like is provided between the A / D conversion units 11R, 11G, and 11B and the contrast / brightness adjustment unit 12 can be considered. As a display device, for example, a CRT (Cathod
e Ray Tube: Cathode ray tube, PDP (Plasma Display Pan)
el), PALC (Plasma Addressed Liquid Crysta
l), DLP (Digital Light Processing), and other types of display devices can be assumed. Of course, the signal processing system is appropriately changed according to the adopted display device.

2. After the position block and the level block, the γ correction and the three-dimensional correction will be described as configuration examples of the non-linear correction unit 16. First, the concept of the position block and the level block used for the three-dimensional correction will be described.

As described with reference to FIGS. 23 and 24, for three-dimensional correction, horizontal, vertical, and level X, Y, and
A correction value is set at each intersection coordinate of the three-dimensional coordinates by the Z axis. That is, first, as a two-dimensional grid block in the horizontal and vertical directions of the screen, a plurality of grid blocks are divided in the X direction (horizontal direction) and the Y direction (vertical direction) on the screen in units of, for example, about 128 pixels. Set the area. Then, for example, 0 to p coordinates are given in the X direction and 0 to p in the Y direction.
Give the coordinates of q. Further, in the Z-axis direction, level boundaries of several levels of signal levels 0, 1, ... R are set. A two-dimensional lattice block is set at each level boundary to form a three-dimensional correction value configuration. That is, the correction value C
Is set for each intersection of the three-dimensional coordinates, and the correction value C
Is set to C (0,0,0) ... C (p, q, r). That is, (p + 1) × (q + 1) × (r + 1) correction values are set. The level blocks L1, L2 ... Lr are defined between the level boundaries. In addition, the area [1, 1] shown in FIG. 23 in the lattice block ...
A block that penetrates each [p, q] into each level block in the Z direction is called a position block.

In FIG. 2, the correction value C is C (0,0,0) .multidot.
.. indicates a three-dimensional space in which C (p, q, r) is set. That is, the X coordinate is 0, 1 ... i-1, i ...
At the level boundaries 0, 1 ... k, k + 1 ... It is a formed three-dimensional structure.

X coordinate values i-1, i and Y coordinate values j-1,
Considering the area of j, the position block A [i, j] is, as shown in the figure, the area [i, j at level 0].
j] to the area [i, j] at level r. That is, the correction value C is C (i-
1, j-1, 0), C (i, j-1, 0), C (i-
1, j, 0), C (i, j, 0) ... C (i-1,
j-1, r), C (i, j-1, r), C (i-1,
j, r) and C (i, j, r), and is a block that specifies an area (position on the screen) in a two-dimensional lattice block regardless of the level (Z coordinate). . Therefore, the position block basically means each correction value C (i-1, j-1), C (i, at the intersection of the two-dimensional coordinates.
j-1), C (i-1, j), and C (i, j).

Further, the level blocks L1, L2 ... L
Although r is shown in FIG. 24, the level block L is
A space sandwiched between grid blocks at two level boundary values. FIG. 3 shows the level block Lk.
This is a lattice block at level boundary value k, that is, correction values C (0,0, k), C (p, 0, k), C (0, q,
k), a two-dimensional space surrounded by C (p, q, k) and a lattice block at the level boundary value k−1, that is, the correction value C
(0,0, k−1), C (p, 0, k−1), C (0,
q, k-1) and a two-dimensional space surrounded by C (p, q, k-1). That is, the level block L is a block that specifies which level of the pixel data signal level is divided by the level boundary value, regardless of the area (position on the screen) in the lattice block.

In the three-dimensional correction processing described later, these position blocks and level blocks are discriminated for pixel data, and further, the position within the position block and the level within the level block are also specified for the pixel data.

The position in the position block will be described with reference to FIG. Although FIG. 4 shows the position block A [i, j], consider the pixel data dxy included in this position block A [i, j]. X coordinate value of pixel data dxy is d
Let x and Y coordinate values be dy. At this time, the X coordinate value i-1
To dx, the distance from the X coordinate value i to dx is b '.
And The distance from the Y coordinate value j-1 to dy is c, and the distance from the Y coordinate value j to dy is c '.

The distances b, b ', c and c'are corrected values C (i-1, j-1) and C in two-dimensional coordinates, respectively.
The information can present the distance of the pixel data dxy from each of (i, j-1), C (i-1, j), and C (i, j). For example, the pixel data dxy has a correction value C (i-1,
j-1), the distance b is in the X direction and the distance c is in the Y direction.
It is shown to be in a remote location. That is, the distance b,
b ′, c, and c ′ are information that can present the distance from each of the four correction values C to the pixel data dxy, and the correction value in the horizontal and vertical directions at the position of the pixel data dxy is set to the set correction value C ( i-1, j-1), C (i, j-1),
It is information for calculating from C (i-1, j) and C (i, j). The position in the position block is information thus indicated by the distance from the four correction values of the position block.

Next, the level in the level block will be described with reference to FIG. In FIG. 5, the level block Lk is shown only on the Z axis. The level block Lk has level boundary values k and k-
Consider the pixel data that will be included in this level block Lk, although it will be a space between 1 in the Z-axis direction. The Z coordinate value of the pixel data is dz. At this time, on the Z coordinate, the distance from the level boundary value k−1 to dz is a, and the distance from the level boundary value k to dz is a ′. This distance a, a '
Is information that can present the distance of the pixel data dz from each of the correction values C at the level boundary value k−1 and the level boundary value k.

Here, considering the position in the position block and the level in the level block together, the distance a,
It is understood that a ′, b, b ′, c, and c ′ are information that can define the position (distance) of the pixel data viewed from each of the eight correction values in the three-dimensional section where the position block and the level block intersect. To be done. That is, as the position in the position block and the level in the level block, the distance a,
If the information of a ', b, b', c, c'is obtained, the correction value corresponding to the position of the pixel data in the three-dimensional space can be calculated from the eight correction values forming the three-dimensional space. Becomes

3. Configuration Example of Non-Linear Correction Unit Configuration examples in the non-linear correction unit 16 in FIG. 1 will be sequentially described below as configuration examples 1 to 3. In addition, as each configuration example, a non-linear processing unit 17R corresponding to the digital red primary color signal DRB, a three-dimensional correction unit 18R, a combining unit 19R, a ROM
The configuration and operation of 20R will be described.
Non-linear processing unit 1 corresponding to digital green primary color signal DGB
7G, 3D correction unit 18G, combining unit 19G, ROM 20
Non-linear processing unit 17B and three-dimensional correction unit 1 corresponding to the configuration and operation of G, or the digital blue primary color signal DBB
The configurations and operations of the 8B, the synthesizing unit 19B, and the ROM 20B are substantially the same, so description thereof will be omitted.

FIG. 6 shows, as an example of the configuration of the non-linear correction unit 16, a portion for processing the digital red primary color signal DRB in the non-linear correction unit 16 shown in FIG.
Non-linear processing unit 17R, three-dimensional correction unit 18R, combining unit 19
The part including the R and ROM 20R and the address data generating part 55R connected to the part are shown as an example of a specific configuration of the non-linear processing part 17R and the three-dimensional correction part 18R.

The non-linear processing section 17R comprises a lookup table 61 composed of, for example, a dual port RAM, a γ correction data generating section 62, and a γ correction data storage section 63 composed of, for example, a ROM. The three-dimensional correction unit 18R includes a level block identification processing unit 65, a level block internal level calculation processing unit 66, a three-dimensional correction data generation unit 70, a three-dimensional interpolation processing unit 71, a position block identification processing unit 72, a position block internal position calculation. Processing unit 73, position block correction data forming unit 7
4, for example, a correction data storage unit 75 using a dual port RAM, a correction data storage register 76 in the position block,
A level allocation data storage register 77 is provided. Synthesis part 1
9R is configured by the data output processing unit 64.

In the configuration of FIG. 6, the digital red primary color signal DRB from the white balance adjusting unit 13 of FIG.
Are supplied to both the non-linear processing unit 17R and the three-dimensional correction unit 18R.

In the non-linear processing section 17R, the digital red primary color signal DRB is supplied to the look-up table 61. In the look-up table 61, the signal level of the digital red primary color signal DRB is sequentially detected, and the table is referred according to the detected signal level. That is, the look-up table 61 is used for the liquid crystal display panel section 52.
It incorporates a γ-correction data table that represents a nonlinear characteristic that is the inverse relationship to the input voltage-light transmittance characteristic of the liquid crystal panel incorporated in R. Then, the γ correction data corresponding to the signal level of the digital red primary color signal DRB is sequentially read.

The γ correction data in the γ correction data table is stored in the γ correction data storage unit 63, and is set in the γ correction data table in the lookup table 61 by the operation of the γ correction data generation unit 62.

According to such a non-linear processing section 17R,
The signal level of the digital red primary color signal DRB supplied to the non-linear processing unit 17R is collated with a γ correction data table, and γ correction data corresponding to the signal level of the digital red primary color signal DRB is sequentially read out. The data will be derived as a γ-corrected digital red primary color signal DRC by non-linear processing of the signal level. The digital red primary color signal DRC derived from the lookup table 61 in this way is, for example, as shown in FIG. 21 of the liquid crystal panel incorporated in the liquid crystal display panel section 52R.
In order to correct the input voltage-light transmittance characteristics as shown in
The signal level is γ-corrected and supplied to the data output processing unit 64 in the synthesizing unit 19R.

On the other hand, in the three-dimensional correction section 18R, the digital red primary color signal DRB is supplied to the level block identification processing section 65 and the level block internal level calculation processing section 66. The level block identification processing unit 65 identifies the range of signal levels to which the digital red primary color signal DRB belongs, that is, the level block described above. That is, the level boundary values 1, 2, ... R set on the Z-axis are compared with the signal level of the supplied digital red primary color signal DRB, and as shown in FIG. By discriminating the upper and lower level boundary values k and k−1, the level block L
Specify k. That is, when the signal level of the pixel data is set to dz as shown in FIG. 5, if (k−1) ≦ dz <k, it is determined to be the level block Lk. Then, the level block identification processing unit 65 sends the level block data DLk representing the identified level block Lk to the in-level block level calculation processing unit 66 and the three-dimensional correction data generation unit 70.

Level calculation processing unit 66 in level block
Performs a calculation process for calculating the level in the level block Lk corresponding to the signal level of the supplied digital red primary color signal DRB according to the level block data DLk. Because of this calculation processing, the Z-coordinate values for all the correction values C shown in FIG. 2 are stored in the level-block level calculation processing section 66.

This calculation process is a process for obtaining the distances a and a'as described with reference to FIG. That is, assuming that the Z coordinate representing the level corresponding to the signal level of the supplied digital red primary color signal DRB is, for example, dz, the Z coordinate difference is based on the relationship of dz = (k−1) + a = k−a ′. As a and a ′, a = dz− (k−1) and a ′ = k−dz are calculated. Then, the Z coordinate difference data DZa and DZa ′ representing the Z coordinate differences a and a ′ are supplied to the three-dimensional interpolation processing unit 71.

The clock signal CL is also supplied to the address data generating section 55R to which the horizontal synchronizing signal SH and the vertical synchronizing signal SV are supplied, and the address data generating section 55R changes the horizontal direction sequentially with the cycle of the clock signal CL. Address data QRH and vertical address data QR
V is output, and these are supplied to the position block specifying processing unit 72 and the position block position calculation processing unit 73.

The position block identification processing section 72 determines the liquid crystal display panel section 52R for the target pixel data.
Position blocks A [1,1], A [1,2], A [1,3], ... Within the above-mentioned lattice block corresponding to the image screen formed on the liquid crystal panel built in ., A
[1, q], A [2,0], ..., A [2, q], A
[3,0], ..., A [3, q] ,.
Any one of [p, 0], ..., A [p, q] is specified. That is, according to the horizontal address data QRH and the vertical address data QRV from the address data generator 55R, the liquid crystal display panel unit 52R has a built-in liquid crystal panel corresponding to each pixel data of the supplied digital red primary color signal DRB. It is detected which of the position blocks A [1,1] to A [p, q] the pixel (corresponding pixel) in the formed image screen belongs to, and the corresponding pixel belongs to, for example, the position block A [ i, j] are specified.

Assuming that the X coordinate is dx and the Y coordinate is dy for the corresponding pixel dxy as shown in FIG. 4, if (i-1) ≤dx <i (j-1) ≤dy <j, the corresponding pixel dxy. Is the position block A [i, j]
To be included in.

Then, the position block identification processing section 72
A pair of position block data DXi and DYj representing the specified position block A [i, j] are sent to the position block position calculation processing unit 73, the position block correction data forming unit 74, and the three-dimensional correction data generation unit 70. To do.

The position block position calculation processing unit 73 determines the horizontal address data QRH and the vertical address data QR.
V and a calculation process for calculating the position of the corresponding pixel in the position block A [i, j] according to the pair of position block data DXi and DYj representing the specified position block A [i, j]. . This calculation process is a process of obtaining the distances b, b ′, c, c ′ as described with reference to FIG. That is, when the X and Y coordinates representing the position of the corresponding pixel of the supplied digital red primary color signal DRB are dx and dy, then dx = (i-1) + b = i-b 'dy = (j-1 ) + C = j−c ′, X coordinate difference b, b ′, Y seat difference c, c ′
As follows, b = dx- (i-1) b '= i-dxc = dy- (j-1) c' = j-dy. Then, X coordinate difference data DXb and DXb ′ representing the X coordinate differences b and b ′ and Y coordinate difference data DYc and DYc ′ representing the Y coordinate differences c and c ′ are supplied to the three-dimensional interpolation processing unit 71. .

The correction data forming section 74 in the position block
The data read control signal CXY corresponding to the position block data DXi and DYj is sent to the correction data storage unit 75.
As shown in FIG. 2, the correction data storage unit 75 stores the correction value C set at each intersection in the coordinate space set by the coordinate axes X, Y, and Z orthogonal to each other.
(0,0,0) ... C (p, q, r) is stored. That is, the correction value C corresponding to each of the (p + 1) × (q + 1) × (r + 1) intersection coordinates is built in.
These correction values C are loaded from the ROM 20R and stored. Therefore, therefore, the correction value C is stored in the ROM 20R.
(0,0,0) ... If the correction value group as C (p, q, r) is stored in plural units, the correction value group is selected to change the correction value. It is also possible.

Then, in the correction data storage section 75, the position block A [i,
The correction values C included in j] are read out as correction data DPC and output to the in-position-block correction data forming unit 74. That is, the correction data DPC has the level boundary 0 (Z =
0) correction values C (i-1, j-1, 0) of the four intersection coordinates that define the position block A [i, j] on the plane,
C (i-1, j, 0), C (i, j-1,0), C
(I, j, 0) and the correction value C (i-1, j-1, 1) of the four intersection coordinates that define the position block A [i, j] on the plane of the level boundary 1 (Z = 1). ), C (i-1,
j, 1), C (i, j-1,1), C (i, j, 1) and so on ... Position block A [i, j in the plane of level boundary r (Z = r) Correction values C (i-1, j-1, r), C (i-1, j,
r), C (i, j-1, r), and C (i, j, r), which are a total of 4 × (r + 1) correction values.

In this way, the position block correction data forming unit 74 outputs the position block data DXi and DYj.
Correction data DP as 4 × (r + 1) correction values C read according to the data read control signal CXY corresponding to
C is a correction data forming unit 74 in the position block,
It is stored in the correction data storage register 76 in the position block.

The three-dimensional correction data generating section 70 has a pair of position block data DXi and DYj representing the position block A [i, j] from the position block specifying processing section 72.
In addition, according to the level block data DLk representing the level block Lk from the level block identification processing unit 65, the level among the 4 × (r + 1) correction values C stored in the position block correction data storage register 76 A total of eight intersection point correction values C that define the position blocks A [i, j] on the Z (k-1) plane and the Zk plane that define the block Lk are read out. That is, the three-dimensional correction data generator 70 sends a data read control signal (address) to the correction data storage register 76 in the position block for reading the correction values C of the eight intersection coordinates, and thereby the position block From the internal correction data storage register 76,
Position block A [i, j] in the plane of level boundary value (k-1)
Of the four correction values C (i-1, j-1, k-
1), C (i-1, j, k-1), C (i, j-1, k)
−1), C (i, j, k−1), and level boundary value k
Defining the position block A [i, j] in the plane of 4
Correction values C (i-1, j-1, k), C (i-1,
j, k), C (i, j−1, k), C (i, j, k), a total of eight correction values C are read out as correction data DPC ′, and the three-dimensional correction data generation unit 70 Through the three-dimensional interpolation processing unit 71.

The three-dimensional interpolation processing unit 71 has Z coordinate difference data DZa and DZa 'representing the Z coordinate differences a and a'calculated by the level block internal level calculation processing unit 66.
X coordinate difference data DXb and DX representing the X coordinate differences b and b ′ calculated by the position block position calculation processing unit 73.
Six coordinate difference data in total are supplied as b ′ and Y coordinate difference data DYc and DYc ′ representing Y coordinate differences c and c ′. Then, the three-dimensional interpolation processing unit 71 uses the six pieces of coordinate difference data as parameters to read a total of 8 pieces of data read from the position block correction data storage register 76.
Correction data DPC ', that is, correction values C (i-1, j-1, k-1), C (i-1, j, k) of eight intersection coordinates.
-1), C (i, j-1, k-1), C (i, j, k-
1), C (i-1, j-1, k), C (i-1, j,
k), C (i, j-1, k), and C (i, j, k) are subjected to three-dimensional interpolation processing. As a result, a three-dimensional correction signal relating to the signal level of the pixel data of the digital red primary color signal DRB defining the corresponding pixel is formed, and this is sent from the three-dimensional interpolation processing unit 71 as the three-dimensional corrected digital red primary color signal DRS.

Performed in the three-dimensional interpolation processing unit 71,
Z coordinate difference data DZa and DZa ′, X coordinate difference data D
Xb and DXb ', and Y coordinate difference data DYc and D
The three-dimensional interpolation process for each of the eight correction values using Yc 'as a parameter is, for example, a linear interpolation process and corresponds to the correction data corresponding to the coordinate position (X, Y, Z) represented by the following. To be done.

(X, Y, Z) = C (i-1, j-1, k)
−1) × b ′ × c ′ × a ′ + C (i, j−1, k−1)
× b × c ′ × a ′ + C (i−1, j, k−1) × b ′ ×
c * a '+ C (i, j, k-1) * b * c * a' + C
(I-1, j-1, k) * b '* c' * a + C (i, j
−1, k) × b × c ′ × a + C (i−1, j, k) ×
b ′ × c × a + C (i, j, k) × b × c × a

In this way, the three-dimensional corrected digital red primary color signal DRS sent from the three-dimensional interpolation processing unit 71 is obtained.
Is supplied to the data output processing unit 64 of the combining unit 49R. Then, in the data output processing unit 64, the digital red primary color signal DRC from the non-linear processing unit 47R is combined with the three-dimensional corrected digital red primary color signal DRS, and the γ-corrected and three-dimensional corrected digital red primary color signal DRD.
To form.

In the non-linear correction unit 16, the γ correction and the three-dimensional correction are performed by the configuration described so far, and the non-linear correction is performed in obtaining the non-linearly corrected video signal. A display screen obtained on the image display unit, which corrects an undesired luminance fluctuation and chromaticity fluctuation according to the horizontal and vertical positions on the display screen, and is caused by the level fluctuation in the original video signal. It is possible to correct the undesired luminance fluctuation and chromaticity fluctuation.

Further, in the non-linear correction unit 16 of this example, the three-dimensional correction unit 18R is provided with the level allocation data storage register 77. The level allocation data storage register 77 is used to define boundary levels 1 and 2 in the Z-axis direction.
.. (r +) as each boundary level value described as r
1) A register that holds a group of actual level values.
As shown in FIG. 7, the level allocation data storage register 77 includes r + 1 registers 77-0, 77-1, 77-2.
..77-r is provided. Now, assuming that the boundary level values described as the boundary levels 1, 2, ... R in the Z-axis direction in FIG. 2 are represented as Z0, Z1, Z2, ... Zr, the registers 77-0, 77-1, 77-2 ... 77
For each of the −r, each boundary level value Z0, by the register write control signal DLS from the CPU 1 shown in FIG.
Z1, Z2 ... Zr are set.

Then, the level allocation data storage register 77
Are registers 77-0, 77-1, 77-2 ... 77.
Each boundary level value Z0, Z1, Z2 stored in -r
... Zr is supplied to the level block identification processing unit 65 as level arrangement data Zn. The level block identification processing unit 65 uses the supplied level arrangement data Zn (Z0 to Zr) as the actual level boundary values as the boundary levels 1, 2, ... The processing for specifying is performed.

That is, in the case of this example, the CPU 1 receives the register write control signal DLS and sets the boundary level values Z0, Z1,
By rewriting Z2 ... Zr, the actual level boundary values for the respective boundary levels 1, 2, ...
It is configured so that it can be variably set.

For example, it is assumed that level discrimination is performed with a resolution of 1024 in the Z-axis direction, and that the level block is divided into eight level blocks. At this time, each boundary level 1, 2 ...
・ If r is to be arranged at equal intervals, see Fig. 8 (a).
, The boundary level values Z0 to Zr (= Z8) are
Registers 77-0, 77-1, 77-2 ... 77-r
You can write in. That is, Z0 = 0, Z1 = 127, Z2
= 255 ... Z8 (Zr) = 1023. Then, the level block identification processing unit 65 performs the above-described level block identification processing, assuming that eight level blocks l1, L2, ..., L8 are set at equal intervals. For example, if it is shown in accordance with the γ correction characteristics when the display device is a CRT, level blocks L1 to L8 are set at equal intervals with respect to the input data level as shown in FIG.

Further, FIG. 10 shows the γ correction characteristic in the case of the liquid crystal panel. In the case of such a characteristic, the level block is finely set in the region where the inclination is steep, so that the three-dimensional correction is made precise. it can. In such a case, CPU1
As shown in FIG. 8B, the boundary level values Z0 to Zr (= Z
As values of 8), Z0 = 0, Z1 = va1, Z2 = va
..Z8 (Zr) = va8 (= 1023) is written in the registers 77-0, 77-1, 77-2, ... 77-r. Then, the level block identification processing unit 65
It is assumed that eight level blocks l1, L2, ...
As a result, as shown in FIG. 10, the level block can be set according to the γ correction characteristic curve of the liquid crystal panel.

Further, FIG. 11 shows the γ correction characteristic in the case of the CRT as in the case of FIG. The original correction can be refined. in this case,
The CPU 1, as shown in FIG. 8C, has boundary level values Z0 to Z.
As the value of r (= Z8), Z0 = 0, Z1 = vb1, Z
2 = vb2 ... Z8 (Zr) = vb8 (= 102
3) to registers 77-0, 77-1, 77-2 ...
Write to 77-r. Then, the level block identification processing unit 65 finely divides the high level area into eight level blocks l1, L2 ... L8 which are rough in the low level area.
Is set, the above-described level block identification processing is performed. As a result, as shown in FIG.
The level block can be set according to the γ correction characteristic curve of

The example of the level boundary arrangement shown in FIGS. 8 and 9 to 11 is merely an example. That is, in the case of this example, the CPU 1 is used as the type of the display device or the work in the adjustment process. Are registers 77-0, 77-1, 77
By writing the actual level boundary value in -2 ... 77-r, the level block setting can be arbitrarily set. Therefore, it is possible to set the optimum level block according to the type of the display device and the variation in the characteristics of each device, and it is possible to improve the accuracy of the three-dimensional correction. In this example, it is sufficient that the level boundary value (the boundary of the level block) can be variably set, and it is not necessary to change the correction data C according to the change of the level boundary value. That is, for example, in terms of the level boundary (Z axis) k, the correction values C (0,0, k) to C at the k level
Even if the k value is arbitrarily changed, (p, q, k) is corrected values C (0, 0, k) to (p, q, k) at the changed k value.
It is used as it is as k). Therefore, making the level boundary value variable does not mean that a huge correction value C must be prepared in consideration of the variable range.

4. Configuration Example of Non-Linear Correction Unit FIG. 12 shows a configuration example of the non-linear correction unit 16. In addition, in the configuration examples to be described below, the configuration shown in FIG.
The same parts as those in the configuration example of FIG. Basic operations related to γ correction and three-dimensional correction are the same.

The configuration example of FIG. 12 is different from the above configuration example in that a level allocation data selection section 78 is provided in place of the level allocation data storage register 77 of FIG. The level allocation data selection unit 78 is configured as shown in FIG. That is, the level allocation data memory 78a and the level allocation data selector 78b are provided. The level allocation data memory 78a includes various display devices A,
A storage area corresponding to each of B, ... x is set, and display devices A, B, ...
・ Level allocation data ZnA, ZnB corresponding to x ...
Znx is stored. For example, level allocation data Zn
A is a data group as boundary level values Z0 to Zr corresponding to a certain display device A (for example, a liquid crystal panel). Further, for example, the level allocation data ZnB is the boundary level value Z corresponding to a certain display device B (for example, CRT).
It is a data group as 0 to Zr.

Then, the level allocation data selector 78b
Is selected from the level allocation data ZnA, ZnB ... Znx by the selection control signal DSEL from the CPU 1 and read from the level allocation data memory 78a. The level values Z0, Z1, Z2 ... Zr are supplied to the level block identification processing unit 65 as level arrangement data Zn. The level block identification processing unit 65 of FIG. 12 receives the supplied level arrangement data Zn (Z0 to Z
r) is an actual level boundary value for each of the boundary levels 1, 2, ... R in the Z-axis direction, and the processing for specifying the level block described above is performed.

That is, in the case of this example, the boundary level value Z used by the CPU 1 for level block discrimination in the level block identification processing section 65 by the selection control signal DSEL.
0, Z1, Z2 ... Zr can be variably set. For example, the value of the boundary level values Z0 to Zr (= Z8) as the level arrangement data ZnA stored in the level arrangement data memory 78a is Z as shown in FIG. 8B.
0 = 0, Z1 = va1, Z2 = va2 ... Z8 (Z
Assuming that r) = va8 (= 1023), when the level arrangement data ZnA is selected by the selection control signal DSEL, the level block state shown in FIG. 10 is obtained. Further, for example, the boundary level values Z0 to Zr (= Z8) as the level arrangement data ZnB stored in the level arrangement data memory 78a are Z0 = 0, Z1 = vb1, as shown in FIG. 8C. Z2 = vb2 ... Z
Assuming that 8 (Zr) = vb8 (= 1023), the level allocation data Zn is set by the selection control signal DSEL.
When B is selected, the level block state as shown in FIG. 11 is obtained.

That is, in the case of this configuration example, the level block setting can be changed within the range of the number of types of the level arrangement data ZnA, ZnB ... Stored in the level arrangement data memory 78a. Also in this case, for example, if various level arrangement data ZnA, ZnB ... Are stored corresponding to various display devices, level block setting corresponding to various display devices is performed to improve three-dimensional correction accuracy. it can. Also, for example, a plurality of types of level allocation data ZnA1 corresponding to a certain type of display device,
If it is stored as ZnA2 ..., it is possible to improve the three-dimensional correction accuracy by setting an optimal level block setting in response to variations in characteristics among individuals when corresponding to a specific display device. You can also

Of course, in comparison with the above configuration example in which the boundary level values can be variably set arbitrarily, in the case of this example, the level arrangement data ZnA, ZnB ... Since the level block setting is variable within the range of the number of types, the level block setting is relatively arbitrary. This means that the level allocation data ZnA, ZnB, ... To be stored are highly practical data. So, in practice, it's hardly a problem. Further, since the actual variable can be selected by selecting the optimum one, the level block setting process is also simplified. For example, the setting work in the adjustment process is simplified,
Also, the processing software load on the CPU 1 can be reduced.

Moreover, the circuit scale can be considerably reduced as compared with the configuration example, and the circuit can be made highly practical. In particular, the level allocation data ZnA, Zn to be stored
Depending on the design of the data value as B ..., Reduction of the circuit scale can be promoted. In the level block identification processing unit 65 as a digital processing circuit, if each level boundary value is a power of 2, the calculation load is reduced and the circuit configuration of the level block identification processing unit 65 can be simplified. . On the other hand, when the level boundary values that can be set are completely arbitrary, as in the configuration example, it is necessary to deal with level boundary values that are not powers of 2, so that the calculation capability must be increased. However, it becomes a factor to increase the circuit scale. Here, all the level boundary values in the level allocation data ZnA, ZnB, ... To be stored are powers of 2 (for example ... 32, 64, 128, ...
(Values such as 192, 256 ...), level boundary values other than powers of 2 cannot be set, that is, the level block identification processing unit 65 can be greatly simplified. It will be.

From the above, in the case of the configuration example, the accuracy of the three-dimensional correction can be improved to some extent, and the circuit scale can be reduced, so that a highly practical nonlinear processing device can be obtained. There is.

5. Configuration Example of Non-Linear Correction Unit Next, a configuration example of the non-linear correction unit 16 will be described with reference to FIG. Unlike the above-described configuration example, this configuration example does not include means for variably setting the level allocation data Zn itself, but the level offset data register 79 is provided.
Is provided. Further, since the level allocation data Zn itself is not variably set, the level block identification processing unit 65 stores fixed level allocation data Zn (Z0, Z1).
A storage unit 65a for storing (Zr) is provided. For example, when a liquid crystal panel is used as a display device as shown in FIG. 1, the storage unit 65a stores level allocation data Z0, Z1 ... As values corresponding to va1, va2. ..Zr is stored, and the level blocks L1 to L8 are set as shown.

A certain offset value Zs is written in the level offset data register 79 by the write control signal DLOF from the CPU 1. Then, the offset value Zs is supplied to the level block identification processing unit 65 and the level block internal level calculation processing unit 66. The level block identification processing unit 65 and the level block internal level calculation processing unit 66 shift the level boundary values Z1 to Zr by the offset value Zs, and then perform the level block identification processing and the level block internal level calculation processing. Will be done.

As described in the configuration example, the level block identification processing section 65 determines that the digital red primary color signal DRB
Specifies the level block to which the belongs. That is, the level boundary values 1 to r set on the Z axis (in this case, Z1 to Zr stored in the storage unit 65) are compared with the signal levels of the supplied digital red primary color signal DRB, and described with reference to FIG. As described above, the level block Lk is specified by discriminating the upper and lower level boundary values k (= Zk) and k-1 (= Zk-1) as the range including the signal level. That is, basically, if the signal level dz of pixel data is Zk−1 ≦ dz <Zk, it is determined to be the level block Lk.

Here, in the case of this configuration example, the level block identification processing unit 65, for example, when shifting each level block in the low level direction by the offset value Zs, regarding the signal level dz of the pixel data, (Zk-1 ) -Zs≤dz <Zk-Zs, it is determined as the level block Lk.
When each level block is shifted in the high level direction by the offset value Zs, if (Zk−1) + Zs ≦ dz <Zk + Zs, it is determined as the level block Lk.

Further, the intra-level-block level calculation processing unit 66 determines the Z coordinate difference a and the level in the level block Lk corresponding to the signal level of the supplied digital red primary color signal DRB in accordance with the level block data DLk. Although a ′ is calculated and supplied to the three-dimensional interpolation processing unit 71 as Z coordinate difference data DZa and DZa ′, in the present example, when shifting each level block in the low level direction by the offset value Zs, , Z coordinate differences a and a ′ are performed as follows using the offset value Zs. a = dz− (Zk−1) + Zs a ′ = Zk−dz−Zs. When each level block is shifted in the high level direction by the offset value Zs, a = dz− (Zk−1) −Zs a ′ = Zk−dz + Zs may be set.

In the level block identification processing unit 65 and the level block internal level calculation processing unit 66, the processing using the offset value Zs is performed so that the actual level boundary changes from the state of FIG. 15A to the state of FIG. It will be shifted to the state of (b) by the offset value Zs,
That is, the level block setting state is changed. That is, in the case of this configuration example, the level boundary value is set to the offset value Zs.
By shifting, in other words, the CPU 1 sets the optimum offset value Zs by the write control signal DLOF, so that the accuracy of the three-dimensional correction can be improved. Further, the level block can be variably set only by providing the offset data register 79, so that the circuit configuration becomes simple and the practicability is high. Further, it is stored in the storage unit 65a. If all of the level boundary values Z0 to Zr are powers of 2, the circuit configuration of the level block identification processing section 65 can be simplified.

In this example, one offset value Zs
Is set to any value, but a plurality of offset values may be set, for example. For example, it is possible to provide different offset values Zs corresponding to the respective level boundary values of the low level area, the middle level area, and the high level area, or the level boundary value Z0.
It may be possible to individually give an offset value to each of Zr. By doing so, it is possible to set the level block with higher accuracy.

6. Configuration Example of Non-Linear Correction Unit Next, a configuration example of the non-linear correction unit 16 will be described with reference to FIG. This configuration example is a combination of the above configuration examples. That is, for example, the level allocation data selection unit 78 having the configuration as shown in FIG. 13 is provided, and the level allocation data Zn can be variably set by the selection control signal DSEL from the CPU 1. Further, an offset data register 79 is further provided, the offset value Zs is set by the write control signal DLOF from the CPU 1, and the offset value Zs is supplied to the level block identification processing unit 65 and the level block internal level calculation processing unit 66, and the above configuration example is provided. As described above, the boundary value (level arrangement data) of the level block is shifted.

Therefore, according to this configuration example, the level block setting can be made appropriate according to the display device and the like as in the configuration example, and the offset value Z can be further set.
It becomes possible to adjust to a more optimal state by setting s.

7. Configuration Example of Non-Linear Correction Unit Next, a configuration example of the non-linear correction unit 16 will be described. This configuration example does not change the level boundary value (level block setting) in the level direction, but in the horizontal and vertical directions,
The relative positional relationship between the image area and the lattice block by the video signal is made appropriate.

It is optimum that the lattice blocks of the correction values in the horizontal and vertical two-dimensional directions and the image area are aligned at the top, bottom, left and right ends. That is, for example, the coordinates (0,0) (p, 0) (0, q) (p, q) of the four corners in the lattice block of FIG.
However, it is ideal that the four corners of the image area remain as they are. However, although the image area varies depending on the image resolution, it is not realistic to prepare a large number of grid blocks (correction values) in order to deal with various resolutions because of an increase in circuit scale and the like.

Therefore, although one grid block is adapted to support display devices of various resolutions, this makes the relationship between the grid block and the image region asymmetrical in the vertical and horizontal directions. Correcting the non-linear characteristic in the dimensional direction may result in an unnatural image state. For example, when a non-linear correction circuit in which a lattice block corresponding to a device with high resolution is set is incorporated in a signal processing system for a display device with low resolution, the relative relationship between the lattice block and the image area is shown in FIG. The state will be as shown in. That is, since the coordinates (0, 0) are made to correspond to each other as a starting point, the amount of deviation between the lattice block and the image area becomes asymmetrical in both the horizontal direction and the vertical direction, and as a result, the image becomes unnatural.

Therefore, in this example, the relative positional relationship between the image area and the lattice block can be adjusted in the horizontal and vertical directions.
Even if the resolution of the display device does not match the lattice block, the unnatural image is corrected by the correction.

A configuration example for this is shown in FIG. In this configuration example, an H-direction offset register 80 and a V-direction offset register 81 are provided. Further, the level allocation data Zn is not variably set unlike the above-described respective configuration examples, and therefore the level block identification processing unit 65 has a fixed level allocation data Zn (Z
A storage unit 65a for storing 0, Z1 ... Zr) is provided. For example, when a liquid crystal panel is used as a display device as shown in FIG. 1, the storage unit 65a stores, for example, FIG.
Level allocation data Z0, Z1 ... Zr as values corresponding to va1, va2 ... Va8 shown in FIG. In this example, the level block setting is fixed.

The H-direction offset register 80 contains CP
A certain offset value Xs is written by the write control signal DHOF from U1. And the offset value Xs
Is supplied to the position block identification processing unit 72 and the position block internal position calculation processing unit 73. A certain offset value Ys is written in the V-direction offset register 81 by the write control signal DVOF from the CPU 1. Then, the offset value Ys is supplied to the position block identification processing unit 72 and the position block position calculation processing unit 73.

The position block identification processing unit 72 and the position block internal position calculation processing unit 73 shift the lattice blocks forming each position block by the offset values Xs and Ys in the H (horizontal) direction and the V (vertical) direction. Then, the position block identifying process and the position block position calculating process are performed.

As described in the configuration example, the position block identification processing unit 72, based on the horizontal address data QRH and the vertical address data QRV, for the target pixel data, the position block A [in the lattice block]. 1, 1] ... A position block A [i, j] as any of A [p, q] is specified. Here, in the case of this configuration example, the level block identification processing unit 65 is supplied with the offset values Xs and Ys, and determines the relative positions of the image region and the lattice block by the offset values Xs and Ys.
The position block is determined by shifting in the horizontal and vertical directions.

That is, in this case, assuming that the X coordinate is dx and the Y coordinate is dy for the corresponding pixel dxy as shown in FIG. 18A, (i-1) ≤ (dx-Xs) <i (j-1) ) ≦ (dy−Ys) <j, the corresponding pixel dxy is the position block A [i, j].
To be included in. This means that the position of the corresponding pixel dxy on the lattice block has been moved by the offset values Xs and Ys as shown in FIG.

Then, the position block identification processing section 72
A pair of position block data DXi and DYj representing the specified position block A [i, j] are sent to the position block position calculation processing unit 73, the position block correction data forming unit 74, and the three-dimensional correction data generation unit 70. To do.

The position block position calculation processing unit 73 determines the horizontal address data QRH and the vertical address data QR.
V and a calculation process for calculating the position of the corresponding pixel in the position block A [i, j] according to the pair of position block data DXi and DYj representing the specified position block A [i, j]. . Further, at this time, the offset values Xs and Ys are also used in the calculation.

The information on the position in the position block is, for example, in the configuration example, as described in FIG. 4, the distances b, b ′,
This is a process for obtaining c and c ′. This distance b, b'is X
The coordinate difference data DXb and DXb 'are obtained, and the distances c and c'
Are Y coordinate difference data DYc and DYc '. However, in specifying the position block, the offset values Xs, Y
By giving s, FIG.
As can be seen by comparing (b), the distances b, b ', c, c'
(DXb, DXb ', DYc, DYc') changes.
Therefore, in the case of this example, the position block position calculation processing unit 7
3 is the distances b, b ', c, c'in FIG. 18 (b).
(DXb, DXb ', DYc, DYc') will be calculated.

Therefore, it is performed by obtaining b = dx-Xs- (i-1) b '= i-dx + Xsc = dy-Ys- (j-1) c' = j-dy + Ys. Then, X coordinate difference data DXb and DXb ′ representing X coordinate differences b and b ′ and Y coordinate difference data DYc and DYc ′ representing Y coordinate differences c and c ′ are supplied to the three-dimensional interpolation processing unit 71.

As described above, the position block identification processing unit 7
2. In the position block position calculation processing unit 73, the processing using the offset values Xs and Ys is performed, so that the relationship between the lattice block and the image region is changed from the state of FIG. ) State can be changed. That is, in the case of this configuration example, the relationship between the lattice block and the image region can be adjusted by setting the offset values Xs and Ys, whereby the upper and lower edges of the image region and the lattice block do not match due to the resolution. Even in such a case, it is possible to eliminate an unnatural image due to the result of the correction of the nonlinear characteristic. Particularly, for example, as shown in FIG. 19B, it is most suitable to eliminate an unnatural image in which the relative positional relationship is changed so that the shift amount between the lattice block and the image area is averaged in the vertical or horizontal direction. Is.

Further, the H-direction offset register 80, V
Adjustment is possible only by providing the direction offset register 81, and since it is only necessary to prepare one lattice block (correction value group in the horizontal and vertical directions), it is possible to realize a small-scale circuit configuration, which is highly practical. Becomes

8. Configuration Example of Non-Linear Correction Unit FIG. 20 shows a configuration example. This configuration example is a combination of the above configuration examples and. That is, for example, the level allocation data selection unit 78 having the configuration as shown in FIG. 13 is provided, and the level allocation data Zn can be variably set by the selection control signal DSEL from the CPU 1. Further, an offset data register 79 is provided, and the CPU
Offset value Zs according to the write control signal DLOF from 1
Is set and supplied to the level block identification processing unit 65 and the level block internal level calculation processing unit 66, and the boundary value (level arrangement data) of the level block is shifted as described in the above configuration example. ing. Further, an H-direction offset register 80 and a V-direction offset register 81 are provided. The H-direction offset register 80 stores the write control signal DHOF from the CPU 1.
The offset value Xs is written by, and the offset value Xs is supplied to the position block identification processing unit 72 and the position block position calculation processing unit 73. A write control signal D from the CPU 1 is applied to the V direction offset register 81.
The offset value Ys is written by VOF, and the offset value Ys is supplied to the position block identification processing unit 72 and the position block position calculation processing unit 73. As a result, the relative positional relationship between the lattice block and the image area can be adjusted to a suitable state as described above.

Therefore, according to this configuration example, the level block setting can be made appropriate according to the display device and the like as in the configuration example, and the offset value Zs can be set more optimally as in the configuration example. It can be adjusted to any condition. Further, as in the configuration example, the unnatural image can be eliminated by adjusting the relative positional relationship between the lattice block and the image region to a suitable state.

As described above, the non-linear correction section 1 is used as a configuration example.
Although the configuration example of No. 6 has been described, other examples of the configuration of the non-linear correction unit 16 are conceivable. Also, a configuration example ~
Other examples of combinations are also possible. Further, the image display device including such a non-linear correction unit 16 may have various configuration examples and can be realized as a device that can be applied to various display devices.

[0125]

As can be seen from the above description, according to the present invention, the horizontal direction of the pixel on the display screen of the image display section is adjusted by the three-dimensional correction value on the video signal subjected to the non-linear processing (γ correction) by the non-linear processing means. By performing three-dimensional correction on the signal level according to the position in the vertical and vertical directions and the signal level of the pixel data, precise γ correction is possible, and the signal level in the three-dimensional correction is related. Since the level boundary value can be set variably,
There is an effect that it becomes possible to perform three-dimensional correction with optimum correction accuracy for various display devices and non-linear characteristics of individual display devices. As a result, the non-linear processing device of the present invention can be suitably applied to an image display device using various types of display devices, and it is also possible to adjust each image display device to an optimum three-dimensional correction state. Become.

Further, by having a register for storing the level boundary value and rewriting the level boundary value of the register, the level boundary value used for the discrimination by the level discriminating means can be variably set. Boundary values can be set with a high degree of freedom, and optimal level boundary values can be set. Further, the level boundary setting means stores various level boundary values and supplies the level boundary value selected from the stored level boundary values to the level discriminating means so that the level boundary values are set. As a result, the level boundary value can be variably set with a small-scale circuit configuration, which is highly practical. Even when the boundary value offset means for offsetting the level boundary value is provided, the level boundary value can be variably set by a small-scale circuit configuration, which is highly practical.

[Brief description of drawings]

FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a position block according to the embodiment.

FIG. 3 is an explanatory diagram of level blocks according to the embodiment.

FIG. 4 is an explanatory diagram of positions in a position block according to the embodiment.

FIG. 5 is an explanatory diagram of levels within a level block according to the embodiment.

FIG. 6 is a block diagram of a configuration example of a non-linear correction unit according to the embodiment.

FIG. 7 is a block diagram of a level allocation data storage register in a configuration example of a non-linear correction unit according to an embodiment.

FIG. 8 is an explanatory diagram of variable setting of level boundary values according to the embodiment.

FIG. 9 is an explanatory diagram of a level boundary value setting example according to the embodiment.

FIG. 10 is an explanatory diagram of a level boundary value setting example according to the embodiment.

FIG. 11 is an explanatory diagram of a level boundary value setting example according to the embodiment.

FIG. 12 is a block diagram of a configuration example of a non-linear correction unit according to the embodiment.

FIG. 13 is a block diagram of a level allocation data selection unit in the configuration example of the nonlinear correction unit according to the embodiment.

FIG. 14 is a block diagram of a configuration example of a non-linear correction unit according to the embodiment.

FIG. 15 is an explanatory diagram of offsets of level boundary values in the configuration example of the embodiment.

FIG. 16 is a block diagram of a configuration example of a non-linear correction unit according to the embodiment.

FIG. 17 is a block diagram of a configuration example of a non-linear correction unit according to the embodiment.

FIG. 18 is an explanatory diagram of horizontal and vertical offsets in the configuration example of the embodiment.

FIG. 19 is an explanatory diagram of a relationship between an image area and a lattice block according to the configuration example of the embodiment.

FIG. 20 is a block diagram of a configuration example of a non-linear correction unit according to the embodiment.

FIG. 21 is an explanatory diagram of characteristics of input voltage-light transmittance of the liquid crystal panel.

FIG. 22 is a block diagram of a conventional image display device.

FIG. 23 is an explanatory diagram of two-dimensional correction of γ characteristic.

FIG. 24 is an explanatory diagram of three-dimensional correction of γ characteristic.

[Explanation of symbols]

1 CPU, 2 ROM, 3 RAM, 11R, 11
G, 11B A / D conversion unit 12 Contrast / brightness adjustment unit, 13 White balance adjustment unit 16 Non-linear correction unit, 17R, 17G, 17B, Non-linear processing unit 18R, 18G, 18B Three-dimensional correction unit, 19
R, 19G, 19B, synthesizer, 50R, 50G, 50B
D / A conversion section, 51R, 51G, 51B Display drive section, 52R, 52G, 52B Liquid crystal display panel section, 53
Timing signal generator, 54 PLL, 55R, 5
5G, 55B address data generation unit, 61 lookup table, 62 γ correction data generation unit, 63 γ correction data storage unit, 64 data output processing unit, 65 level block identification processing unit, 66 level block internal level calculation processing unit, 70 Three-dimensional correction data generation unit, 71 Three-dimensional interpolation processing unit, 72 Position block identification processing unit, 73
Position block position calculation processing unit, 74 Position block correction data forming unit, 75 Correction data storage unit, 76
Position block correction data storage register, 77 level layout data storage register, 78 level layout data selection section, 79 level offset data register, 80 H
Direction offset register, 81 V direction offset register

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 1/407 H04N 1/40 101E 5C080 (72) Inventor Makoto Haitani 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Kenichiro Saito 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo F-Term (Sony Corporation) 5B057 CA01 CA08 CB01 CB08 CE08 CE11 CH11 DA07 5C006 AA11 AA21 AF46 AF85 BC11 BC16 FA43 FA56 5C021 PA16 PA53 PA58 PA66 PA87 PA99 RB00 RB03 XA34 5C076 AA12 AA19 BA05 BA06 5C077 MP08 NN02 PP15 PP23 PP58 PQ22 RR15 SS06 5C080 AA05 AA10 BB05 CC03 DD01 DD22 DD27 EE17 GG08KKJJ02JJ02

Claims (8)

[Claims] 1. A non-linear processing means for correcting a video signal by a non-linear processing of a signal level according to a display characteristic of an image display section for displaying an image based on the video signal, and horizontal and vertical directions of pixels in the video signal. The horizontal and vertical position determining means for determining the position of the image signal, the level determining means for determining the signal level of the pixel in the video signal, the level boundary setting means for variably setting the level boundary value used for the determination by the level determining means, Generates a three-dimensional correction value for the signal level in accordance with the horizontal and vertical position determined by the horizontal and vertical position determination means and the signal level determined by the level determination means,
A three-dimensional correction means for performing three-dimensional correction of the video signal; and a combining means for combining and outputting the video signal corrected by the non-linear processing means and the video signal corrected by the three-dimensional correction means. A nonlinear processing device characterized by the above. 2. The level boundary setting means has a register for storing a level boundary value, and by rewriting the level boundary value of the register, the level boundary value used for discrimination by the level discrimination means is variably set. The non-linear processing device according to claim 1, wherein 3. The level boundary setting means stores various level boundary values, and supplies the level boundary value selected from the stored level boundary values to the level judging means, thereby the level judging means. The non-linear processing device according to claim 1, wherein a level boundary value used for the determination in (1) is set. 4. A boundary value offset means for offsetting a level boundary value set for use in the discrimination by said level discriminating means by further supplying an offset value to said level discriminating means. The non-linear processing device according to claim 1, wherein 5. A non-linear processing means for correcting a video signal by a non-linear processing of a signal level according to a display characteristic of an image display section for displaying an image based on the video signal, and horizontal and vertical directions of pixels in the video signal. The horizontal and vertical position determining means for determining the position of the image signal, the level determining means for determining the signal level of the pixel in the video signal, the level boundary setting means for variably setting the level boundary value used for the determination by the level determining means, Generates a three-dimensional correction value for the signal level in accordance with the horizontal and vertical position determined by the horizontal and vertical position determination means and the signal level determined by the level determination means,
A three-dimensional correction means for performing three-dimensional correction of the video signal; a combining means for combining and outputting the video signal corrected by the non-linear processing means and the video signal corrected by the three-dimensional correction means; and the combining means. An image display device comprising: an image display unit having an image display unit that displays an image based on a video signal output from the image display device. 6. The level boundary setting means has a register for storing the level boundary value, and by rewriting the level boundary value of the register, the level boundary value used for discrimination by the level discrimination means is variably set. The image display device according to claim 5, wherein 7. The level boundary setting means stores various level boundary values, and supplies the level boundary value selected from the stored level boundary values to the level judging means, thereby the level judging means. The image display apparatus according to claim 5, wherein a level boundary value used for the determination in step 1 is set. 8. A boundary value offset means for offsetting a level boundary value set for use in the discrimination by the level discriminating means by supplying an offset value to the level discriminating means. The image display device according to claim 5, wherein.