JP2003046048A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003046048A JP2003046048A JP2001230010A JP2001230010A JP2003046048A JP 2003046048 A JP2003046048 A JP 2003046048A JP 2001230010 A JP2001230010 A JP 2001230010A JP 2001230010 A JP2001230010 A JP 2001230010A JP 2003046048 A JP2003046048 A JP 2003046048A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- heat
- conductive member
- semiconductor device
- conductive members
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に係
り、例えば、駆動回路の電力供給などに使用される半導
体チップ（パワー半導体素子）を実装する半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a semiconductor device on which a semiconductor chip (power semiconductor element) used for supplying power to a driving circuit is mounted.
【０００２】[0002]
【従来の技術】従来の装置においては、パワー半導体素
子をパッケージに包んだＩＣも使用されるが、特に大電
流を制御するシステムでは、発熱量が多いため、放熱を
考慮し、パワー半導体素子をチップそのまま（例えばシ
リコンチップ）で実装するようにしている。2. Description of the Related Art In a conventional device, an IC in which a power semiconductor element is wrapped in a package is also used. However, in a system for controlling a large current, a large amount of heat is generated. The chip is mounted as it is (for example, a silicon chip).
【０００３】例えば表裏（両面）に電極（例えば、ソー
ス電極，ドレイン電極，ゲート電極）を配置した半導体
チップの場合には、放熱体（ヒートシンク）の要素とな
る金属ベース上に、配線パターンを形成した回路基板
（電気絶縁板）を接合し、さらにその上にはんだ層を介
して半導体チップ（例えばＭＯＳＦＥＴ，ＩＧＢＴ，バ
イポーラトランジスタ等）を接合する構造が提案されて
いる。半導体チップの裏面に形成した電極（例えばドレ
イン電極）は、はんだ層を介して回路基板上の配線パタ
ーンに接続され、半導体チップの表面に形成した電極
（ソース電極、ゲート電極）はワイヤを介して回路基板
上の配線パターンに接続される。For example, in the case of a semiconductor chip in which electrodes (eg, source electrode, drain electrode, gate electrode) are arranged on the front and back (both sides), a wiring pattern is formed on a metal base which is an element of a heat sink. There has been proposed a structure in which the above-mentioned circuit board (electrical insulating plate) is joined, and a semiconductor chip (for example, MOSFET, IGBT, bipolar transistor, etc.) is further joined thereon via a solder layer. The electrodes (for example, drain electrodes) formed on the back surface of the semiconductor chip are connected to the wiring pattern on the circuit board through the solder layer, and the electrodes (source electrode, gate electrode) formed on the front surface of the semiconductor chip are connected through wires. Connected to the wiring pattern on the circuit board.
【０００４】配線パターンや金属ベース，放熱体などは
銅などの高熱伝導部材よりなる。The wiring pattern, the metal base, the radiator, etc. are made of a high heat conductive material such as copper.
【０００５】半導体チップで発熱した熱は、金属ベー
ス，冷却フィンなどの放熱体を介して空冷や水冷などの
冷却媒体に放熱される。The heat generated by the semiconductor chip is radiated to a cooling medium such as air cooling or water cooling through a heat radiator such as a metal base and cooling fins.
【０００６】接合される半導体チップと配線パターン
（銅など）は、線膨張率差が大きく、そのままでは運転
状態での電流変動による熱サイクル変動により、はんだ
接合部が熱応力破壊に至る懸念がある。There is a large difference in linear expansion coefficient between the semiconductor chip and the wiring pattern (copper or the like) to be joined, and if it is left as it is, thermal cycle fluctuations due to current fluctuations in operating conditions may lead to thermal stress destruction of the soldered joints. .
【０００７】このため、配線パターンを施した回路基板
は、窒化アルミ材などシリコン材と線膨張率が近い絶縁
材を使い、配線パターンを回路基板に蝋付け加工で接合
した複合材にしておく。このようにすれば、配線は、膜
厚が回路基板に対して極めて薄いために、線熱膨張率が
実質的に回路基板に支配されることになる（複合材の平
均熱膨張率が回路基板に近い値となる）。その結果、半
導体チップと配線パターンをはんだ付けしても、その接
合部は、熱サイクルが大きい使用環境においても線膨張
率差による熱疲労に耐えることができる。Therefore, the circuit board provided with the wiring pattern is made of a composite material in which an insulating material having a linear expansion coefficient close to that of the silicon material such as an aluminum nitride material is used, and the wiring pattern is joined to the circuit board by brazing. In this case, since the wiring has an extremely thin film thickness with respect to the circuit board, the linear thermal expansion coefficient is substantially controlled by the circuit board (the average thermal expansion coefficient of the composite material is Will be close to). As a result, even if the semiconductor chip and the wiring pattern are soldered, the joint can withstand thermal fatigue due to a difference in linear expansion coefficient even in a use environment in which a thermal cycle is large.
【０００８】最近では、特開２０００−３１３７８号公
報、特開平１０−７４８９０号公報に開示されるよう
に、放熱効率（冷却効率）を高めるために、金属ベース
上に配線パターンを形成した基板を接合し、この基板上
にはんだ接合を介して第１の外部引き出し用端子板，電
力用半導体チップ（パワー半導体チップ），第２の外部
引き出し用端子板を積層し、前記第１の外部引き出し用
端子板に加えて第２の外部引き出し用端子板も金属ベー
ス上の回路基板に熱伝導可能に接合した半導体モジュー
ルが提案されている。このような構成によれば、半導体
チップの熱は、第１の外部引き出し端子板を介して金属
ベースに伝えられるほかに、第２の外部引き出し端子板
を介して金属ベースに伝えられる。Recently, as disclosed in Japanese Unexamined Patent Publication Nos. 2000-31378 and 10-74890, a substrate having a wiring pattern formed on a metal base has been used in order to enhance heat radiation efficiency (cooling efficiency). The first external lead-out terminal board, the power semiconductor chip (power semiconductor chip), and the second external lead-out terminal board are laminated on the substrate through solder joining, and the first external lead-out terminal board is provided. In addition to the terminal plate, a semiconductor module has been proposed in which a second external lead-out terminal plate is joined to a circuit board on a metal base so as to be able to conduct heat. According to such a configuration, the heat of the semiconductor chip is transferred to the metal base via the first external lead terminal plate, and is also transferred to the metal base via the second external lead terminal plate.
【０００９】[0009]
【発明が解決しようとする課題】本発明の目的は、部品
点数の合理化を図りつつ、上記従来技術以上に半導体チ
ップの放熱効率を高めることができ、半導体チップと導
電体とのはんだ接合部や配線に用いるアルミワイヤーと
半導体チップの線膨張率差に基づく熱サイクル耐量を改
善し、小形、低コストを図り得る半導体装置を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to increase the heat dissipation efficiency of a semiconductor chip more than the above-mentioned prior art while aiming to rationalize the number of parts and to achieve a solder joint between the semiconductor chip and a conductor. An object of the present invention is to provide a semiconductor device capable of improving the thermal cycle resistance based on the difference in linear expansion coefficient between an aluminum wire used for wiring and a semiconductor chip, and achieving a small size and low cost.
【００１０】[0010]
【課題を解決するための手段】本発明は、上記目的を達
成するために、次のような半導体実装構造を提案する。In order to achieve the above object, the present invention proposes the following semiconductor mounting structure.
【００１１】図１に本発明の基本的原理図を示す。FIG. 1 shows a basic principle of the present invention.
【００１２】図１を参照して説明すると、本発明は、表
裏両面に電極（図示省略）が配設された半導体チップ１
と、この半導体チップ１をサンドイッチ状に挟む板状の
導電部材３０，３１とを有し、これらの導電部材３０，
３１が半導体チップ１の両面に設けた電極に接合される
半導体装置であって、
前記導電部材３０，３１のうち一方の導電部材３１が半
導体チップ１の金属ベースを兼ね、もう一方の導電部材
３０は、前記金属ベースに相当する導電部材３１と同等
の板厚構造をなしていることを特徴とする。Referring to FIG. 1, according to the present invention, a semiconductor chip 1 in which electrodes (not shown) are provided on both front and back surfaces.
And plate-shaped conductive members 30 and 31 sandwiching the semiconductor chip 1 in a sandwich shape.
A semiconductor device 31 is joined to electrodes provided on both sides of the semiconductor chip 1. One of the conductive members 30, 31 serves as a metal base of the semiconductor chip 1, and the other conductive member 30. Has the same plate thickness structure as the conductive member 31 corresponding to the metal base.
【００１３】導電部材３０，３１は、高熱伝導性を有す
る材料で厚さは、１ｍｍ以上の板厚のものであることが
好ましい。The conductive members 30 and 31 are preferably made of a material having high thermal conductivity and have a thickness of 1 mm or more.
【００１４】上記構成によれば、導電部材３０，３１と
して例えば銅材を用い、半導体チップ１としてシリコン
を用いた場合、両者の線膨張率差により接合部（はんだ
等）２２，２３に熱サイクル応力が生じるが、本発明で
は、次の理由により接合部の熱サイクル寿命を向上させ
ることができる。According to the above construction, when copper is used as the conductive members 30 and 31 and silicon is used as the semiconductor chip 1, the joint portions (solders) 22 and 23 are thermally cycled due to the difference in linear expansion coefficient between the two. Although stress is generated, the present invention can improve the thermal cycle life of the joint for the following reasons.
【００１５】半導体チップ１の両面接合構造で寿命が向
上するメカニズムとしては、次の二つのメカニズムがあ
り、両者が相乗的に作用する。
（１）導電部材（リード端子）３０，３１が半導体チッ
プ１に対して両面配置の金属ベースを兼ねるので、いず
れの導電部材３０，３１も厚板構造（厚み１ｍｍ以上）
確保でき、チップの発熱に対して、チップ両面からの放
熱（冷却）による温度上昇の低減による熱応力の低減を
図り得る。
（２）半導体チップ１とその両面に接合された導電部材
３０，３１との間の線膨張率差で生じる熱応力は、両面
接合部２２、２３で分担する。これを図２により説明す
る。図２（ａ）が本発明における両面接合構造の熱応力
説明図、図２（ｂ）が本発明に対する比較説明図（片面
接合構造）である。There are the following two mechanisms as a mechanism for improving the life of the double-sided bonding structure of the semiconductor chip 1, and both act synergistically. (1) Since the conductive members (lead terminals) 30 and 31 also serve as the metal bases arranged on both sides of the semiconductor chip 1, both conductive members 30 and 31 have a thick plate structure (thickness of 1 mm or more).
It can be ensured, and the heat stress of the chip can be reduced by reducing the temperature rise due to heat dissipation (cooling) from both sides of the chip. (2) The double-sided joint portions 22 and 23 share the thermal stress caused by the difference in linear expansion coefficient between the semiconductor chip 1 and the conductive members 30 and 31 joined to both surfaces thereof. This will be described with reference to FIG. FIG. 2A is a thermal stress explanatory view of the double-sided bonding structure according to the present invention, and FIG. 2B is a comparative explanatory diagram (single-sided bonding structure) with respect to the present invention.
【００１６】半導体チップ・導電部材の接合構造におい
て、導電部材（例えば銅材）の線膨張係数は半導体チッ
プ（シリコン）と大きく異なるので、両者の熱膨張差に
より熱サイクルが加わると熱応力が発生する。解析によ
れば、この熱応力により接合層端部にせん断力が作用
し、これによって半導体チップ１の中央は、導電部材３
０，３１の膨張に一致するまで引き伸ばされる。力の釣
り合いから、片面接合構造の場合、半導体チップ１中央
を引き伸ばす力と接合層２３の端部に生じるせん断力は
等しい（図２（ｂ）参照）。このせん断力により、はん
だ層のせん断ひずみが生じる。このひずみの繰返しによ
りはんだの疲労が生じ、ある繰返し数で破壊を生じるこ
とになる。In the joining structure of the semiconductor chip and the conductive member, the linear expansion coefficient of the conductive member (for example, copper material) is greatly different from that of the semiconductor chip (silicon). Therefore, thermal stress is generated when a thermal cycle is applied due to the difference in thermal expansion between the two. To do. According to the analysis, a shearing force acts on the end portion of the bonding layer due to this thermal stress, whereby the center of the semiconductor chip 1 is placed in the conductive member 3
Stretched to match expansion of 0,31. Due to the balance of forces, in the case of the single-sided bonding structure, the force for stretching the center of the semiconductor chip 1 and the shearing force generated at the end of the bonding layer 23 are equal (see FIG. 2B). This shear force causes shear strain in the solder layer. Repetition of this strain causes fatigue of the solder, resulting in destruction at a certain number of repetitions.
【００１７】両面接合構造においても、上下の材料（導
電部材）３０，３１が同じであれば、半導体チップ１中
央は片面接合の場合と同じだけ引き伸ばされることにな
る。すなわち、半導体チップ１中央を引き伸ばす力Ｆは
同じである。一方、はんだ接合層は上下にほぼ対称に二
つあるから、Ｆと釣り合うはんだ層端部に生じるせん断
力は上下の層でそれぞれ半分のＦ／２となる（図１
（ａ）参照）。したがって、この力によって生じるはん
だ層のひずみも１／２となり、このひずみの繰返しによ
って生じるはんだ層の疲労破壊寿命は大幅に向上する。Also in the double-sided bonding structure, if the upper and lower materials (conductive members) 30 and 31 are the same, the center of the semiconductor chip 1 is stretched by the same amount as in the single-sided bonding. That is, the force F for stretching the center of the semiconductor chip 1 is the same. On the other hand, since the two solder bonding layers are almost symmetrical in the vertical direction, the shearing force generated at the solder layer end portion that balances F is half that of F / 2 in the upper and lower layers (Fig. 1).
(See (a)). Therefore, the strain of the solder layer generated by this force is also halved, and the fatigue fracture life of the solder layer caused by the repeated strain is significantly improved.
【００１８】本発明によれば、はんだ接合２２，２３内
の熱応力が図２（ｂ）の片面接合構造（従来構造）に比
べて１／２に低減することができる。はんだの熱サイク
ル耐量は、熱応力の２乗に反比例するため、従来比約４
倍の熱サイクル耐量とすることができる。According to the present invention, the thermal stress in the solder joints 22 and 23 can be reduced to 1/2 as compared with the single-sided joint structure (conventional structure) of FIG. 2B. Since the thermal cycle resistance of solder is inversely proportional to the square of the thermal stress,
Double heat cycle resistance can be achieved.
【００１９】また、本発明者らは、両面接合構造におけ
る熱応力分担メカニズムによって、導電部材の厚みを１
ｍｍ以上確保しても導電部材・半導体チップ間の熱膨張
差により発生する熱応力について問題ないことを見出し
（従来は、半導体チップと銅材とは線膨張率が大きいこ
とから半導体チップに銅材などの端子板を接合する場合
に端子板を厚板構造にする発想はなかった）、この厚板
により導電部材が放熱体としても機能することになり、
それにより図２（ｂ）の従来の片面接合冷却構造に対し
約２倍の冷却効果が得られる。このため、半導体チップ
１の発熱による温度上昇幅を１／２にする効果がある。
はんだの熱サイクル耐量は、温度変動幅の約３乗に反比
例し、約７〜８倍の熱サイクル耐量を得ることができ
る。Further, the present inventors set the thickness of the conductive member to 1 by the thermal stress sharing mechanism in the double-sided bonding structure.
It was found that there is no problem with the thermal stress generated by the difference in thermal expansion between the conductive member and the semiconductor chip even if it is secured at a value of at least 10 mm. There was no idea to make the terminal plate a thick plate structure when joining terminal plates such as), and this thick plate will cause the conductive member to also function as a radiator.
As a result, a cooling effect about twice that of the conventional single-sided joint cooling structure shown in FIG. 2B can be obtained. Therefore, there is an effect that the temperature rise width due to heat generation of the semiconductor chip 1 is halved.
The thermal cycle resistance of the solder is inversely proportional to the cube of the temperature fluctuation width, and a thermal cycle resistance of about 7 to 8 times can be obtained.
【００２０】以上の相乗作用〔（４×（７〜８）〕によ
り、従来構造比、１桁以上（約３０倍）の耐熱サイクル
を実現することができる。Due to the above synergistic action [(4 × (7-8)], it is possible to realize a heat resistance cycle having a conventional structural ratio of one digit or more (about 30 times).
【００２１】さらにシリコンチップの表裏両面はんだ接
合構造により、従来の太い大電流アルミワイヤ配線構造
に代わって、ワイヤーレス構造とし、アルミ配線とシリ
コンの接合部における線膨張率の差に起因する接合信頼
度低下の懸念をなくし、耐熱サイクル性能を改善するこ
とができる。Furthermore, the front and back side solder joint structure of the silicon chip replaces the conventional thick high-current aluminum wire wiring structure with a wireless structure, and the joint reliability resulting from the difference in linear expansion coefficient at the joint portion of aluminum wiring and silicon. The heat cycle performance can be improved by eliminating the fear of deterioration of the temperature.
【００２２】なお、上記以外にも、放熱の向上を図り得
る発明を提案するが、これらについては、発明の実施の
形態の項で説明する。In addition to the above, there are proposed inventions capable of improving heat dissipation, which will be described in the section of the embodiments of the invention.
【００２３】[0023]
【発明の実施の形態】本発明の実施の形態を、図３〜図
７を用いて説明する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS.
【００２４】図３は、本発明の第１実施例に係る半導体
装置の断面図である。FIG. 3 is a sectional view of a semiconductor device according to the first embodiment of the present invention.
【００２５】図３において、半導体チップ（例えばシリ
コンチップ、以下、単に「チップ」と称することもあ
る）１は、両面に電極が配設されている。チップ１がＦ
ＥＴである場合は、一面にドレイン電極（第１の電極）
３が配設され、もう一面に、ソース電極２（第２の電
極）とゲート電極４（第３の電極；入力制御電極）とが
配設される。なお、チップ１がバイポーラトランジスタ
である場合には、コレクタ電極がドレイン電極３に相当
し、エミッタ電極がソース電極２に相当し、ベース電極
がゲート電極４に相当する。In FIG. 3, a semiconductor chip (for example, a silicon chip, which may be simply referred to as a “chip” hereinafter) 1 has electrodes provided on both sides. Chip 1 is F
In the case of ET, the drain electrode (first electrode) is on one surface
3 is provided, and the source electrode 2 (second electrode) and the gate electrode 4 (third electrode; input control electrode) are provided on the other surface. When the chip 1 is a bipolar transistor, the collector electrode corresponds to the drain electrode 3, the emitter electrode corresponds to the source electrode 2, and the base electrode corresponds to the gate electrode 4.
【００２６】導電部材（リード端子）３０，３１は、厚
みが１ｍｍ以上（例えば２〜３ｍｍ）の板状をなす高熱
伝導性の金属材（例えば銅材）により構成され、チップ
１をサンドイッチ状に挟んで、第１の導電部材３０がド
レイン電極３にはんだ接合され、第２の導電部材３１が
ソース電極２に接合されている。The conductive members (lead terminals) 30 and 31 are made of a plate-shaped highly heat-conductive metal material (for example, copper material) having a thickness of 1 mm or more (for example, 2 to 3 mm), and the chip 1 is sandwiched. The first conductive member 30 is solder-bonded to the drain electrode 3 and the second conductive member 31 is bonded to the source electrode 2 by sandwiching them.
【００２７】導電部材３１は、その上のチップ１、導電
部材３０、放熱体８の積層構造体を支持する金属ベース
の機能を兼ねるものである。一方、導電部材３０は、金
属ベースに相当する導電部材３０と同等の板厚構造をな
している。The conductive member 31 also functions as a metal base for supporting the laminated structure of the chip 1, the conductive member 30, and the radiator 8 on the conductive member 31. On the other hand, the conductive member 30 has the same plate thickness structure as the conductive member 30 corresponding to the metal base.
【００２８】第１，第２の導電部材３０，３１は、金属
ベースに相当する厚板構造にすることで高効率の放熱機
能を有し、且つチップ１の両面の接合部（はんだ層）２
２，２３における熱サイクル応力を分担する構造をなし
ている。The first and second conductive members 30 and 31 have a high-efficiency heat dissipation function by having a thick plate structure corresponding to a metal base, and have a joint portion (solder layer) 2 on both sides of the chip 1.
2 and 23 share the thermal cycle stress.
【００２９】第３の導電部材（リード端子）３４の厚み
ｔ３は、第１，第２の導電部材３０，３１の厚みｔ１，
ｔ２に対してはるかに小さい耐熱薄板金属板（銅板）に
より構成されている。The thickness t3 of the third conductive member (lead terminal) 34 is equal to the thickness t1 of the first and second conductive members 30, 31.
It is composed of a heat-resistant thin metal plate (copper plate) which is much smaller than t2.
【００３０】第１，第２の導電部材３０，３１は、チッ
プ１全体を覆い隠す面積を有している。第２の導電部材
３１は、その内面一端３１′に段差を設けて、内面一端
３１′に凹みを形成している。ゲート電極（第３の電
極）４は、凹み３１′に対向するように配置されてお
り、この凹み３１′の空間を利用して第３の導電部材３
４が第２の導電部材３１と干渉することなくゲート電極
（第３の電極）４とはんだ付けにより直接接合されてい
る。The first and second conductive members 30 and 31 have an area that covers the entire chip 1. The second conductive member 31 has a step formed at one end 31 ′ of the inner surface thereof, and a recess is formed at the one end 31 ′ of the inner surface. The gate electrode (third electrode) 4 is arranged so as to face the recess 31 ', and the space of the recess 31' is used to utilize the third conductive member 3 '.
4 is directly joined to the gate electrode (third electrode) 4 by soldering without interfering with the second conductive member 31.
【００３１】上記した両導電部材３０，３１の外面に、
電気絶縁層３２，３３を介して放熱体（例えば冷却フィ
ン）８，９が接合されている。この接合層１０は、放熱
体８，９に熱を伝導する構造であり、高熱伝導性接着や
はんだ接合による。On the outer surfaces of the above-mentioned conductive members 30 and 31,
Radiators (for example, cooling fins) 8 and 9 are joined to each other through the electric insulating layers 32 and 33. The bonding layer 10 has a structure that conducts heat to the radiators 8 and 9, and is formed by high thermal conductive bonding or solder bonding.
【００３２】導電部材３０，３１，３４は、それぞれの
外部接続端子３５に接続される。The conductive members 30, 31, 34 are connected to their respective external connection terminals 35.
【００３３】チップ１の発熱は、高熱伝導性の導電部材
３０，３１が金属ベースを兼ねる厚板効果、および導電
部材３０，３１の外面に接合した放熱体８，９の存在に
より、熱流３６，３７となってチップ１の表面より導電
部材３０，３１を通して直接広がり始め、主にチップの
両面から導電部材の配線方向に対し直角方向に拡散を伴
って熱伝導して、放熱体８，９にて効果的な放熱を実現
する。特に、導電部材３０，３１は、放熱抵抗低減効果
を目的として、放熱路の面積拡大を図り、また厚板構造
により、金属ベースとしての機能を兼ねることができ、
ベース構造を特に設ける必要が無く、簡素な構成とする
ことができる。The heat generation of the chip 1 is caused by the heat flow 36, due to the thick plate effect in which the conductive members 30 and 31 having high thermal conductivity also serve as a metal base and the existence of the radiators 8 and 9 joined to the outer surfaces of the conductive members 30 and 31. 37, it begins to spread directly from the surface of the chip 1 through the conductive members 30 and 31, and mainly conducts heat from both surfaces of the chip in a direction perpendicular to the wiring direction of the conductive member with diffusion, to the radiators 8 and 9. To achieve effective heat dissipation. In particular, the conductive members 30 and 31 can increase the area of the heat dissipation path for the purpose of reducing the heat dissipation resistance, and can also function as a metal base due to the thick plate structure.
It is not necessary to provide a base structure, and a simple structure can be obtained.
【００３４】さらに、本実施例では、チップ１の主電流
を流す表電極（ドレイン電極）３と裏電極（ソース電
極）２に、厚板導電部材３０，３１をはんだ接合２２，
２３により接続する。Further, in the present embodiment, the thick plate conductive members 30 and 31 are soldered to the front electrode (drain electrode) 3 and the back electrode (source electrode) 2 of the chip 1 through which the main current flows, by solder bonding 22 ,.
23 to connect.
【００３５】このようなシリコンと銅の関係の如く、線
膨張率差が大きい材質のはんだ接合構造であっても、本
発明の実装構造によれば、シリコンチップ１両面のはん
だ接合部２２，２３は熱応力分担されることで、既述し
たように熱応力を軽減でき、上記放熱作用との相乗によ
り熱サイクル寿命を大幅に向上させることができる。According to the mounting structure of the present invention, even if the solder joint structure is made of a material having a large difference in linear expansion coefficient such as the relation between silicon and copper, the solder joint portions 22 and 23 on both surfaces of the silicon chip 1 are provided. As described above, the heat stress can be alleviated, so that the heat stress can be reduced, and the heat cycle life can be significantly improved by the synergistic effect with the heat dissipation effect.
【００３６】したがって、従来懸念されたはんだ接合部
の耐熱サイクル性能の改善を図ることができる。具体的
には、片面接合構造に比べて、１桁以上（約３０倍）の
耐熱サイクルを実現することができ、特に自動車搭載半
導体装置のように温度環境が厳しいものであっても、耐
熱，耐久性に優れた回路デバイスを実現することができ
る。Therefore, it is possible to improve the heat-resistant cycle performance of the solder joint portion, which has been a concern in the past. Specifically, it can realize a heat cycle of one digit or more (about 30 times) as compared with the single-sided junction structure, and even if the temperature environment is harsh such as a semiconductor device mounted on an automobile, It is possible to realize a circuit device having excellent durability.
【００３７】また、本実施例によれば、従来の太い大電
流アルミワイヤ配線構造に代わって、ワイヤーレス構造
とし、アルミ配線とシリコンの接合部における線膨張率
の差に起因する接合信頼度低下の懸念をなくし、耐熱サ
イクル性能を改善することができる。Further, according to this embodiment, a wireless structure is used in place of the conventional thick high-current aluminum wire wiring structure, and the bonding reliability is reduced due to the difference in linear expansion coefficient between the aluminum wiring and the silicon. The heat cycle performance can be improved by eliminating the concern.
【００３８】図４は、本発明の第２実施例の要部断面図
である。本実施例の基本的な構成は図３の第１実施例と
同様であり、その中から、半導体チップ１と導電部材３
０，３１，３４の接合構造体を取り出したものである。
第１実施例との相違点は、薄板導電部材３４とゲート電
極（入力制御電極）４とをワイヤ３８を介して接続した
点であり、このワイヤ３８による接続も導電部材３１の
内面に設けた凹部３１′を利用し、導電部材３１がワイ
ヤ３８に干渉しないようにしている。FIG. 4 is a sectional view of the essential portions of the second embodiment of the present invention. The basic structure of this embodiment is the same as that of the first embodiment shown in FIG. 3, and among them, the semiconductor chip 1 and the conductive member 3 are included.
The bonded structure of 0, 31, 34 is taken out.
The difference from the first embodiment is that the thin plate conductive member 34 and the gate electrode (input control electrode) 4 are connected via a wire 38, and the connection by this wire 38 is also provided on the inner surface of the conductive member 31. The recess 31 ′ is used to prevent the conductive member 31 from interfering with the wire 38.
【００３９】図５に第３の実施例を示す。図中、図１，
図２と同一の符号は、同一或いは共通する要素を示すも
のである。FIG. 5 shows a third embodiment. In the figure,
2 that are the same as those in FIG. 2 indicate the same or common elements.
【００４０】半導体チップ１と導電部材３０，３１，３
４との接合構造は、図２と同様であるが、導電部材３０
と放熱体８との間、および導電部材３１と放熱体９との
間には、導電部材から放熱体に熱を拡散させて伝える熱
拡散板４０，４１を介在させている。The semiconductor chip 1 and the conductive members 30, 31, 3
4 is similar to that of FIG. 2, but the conductive member 30
The heat diffusion plates 40 and 41 are provided between the heat sink 8 and the heat sink 8 and between the conductive member 31 and the heat sink 9 to diffuse and transmit heat from the conductive member to the heat sink.
【００４１】すなわち、厚板構造の導電部材３０，３１
ではんだ層２２，２３を介して半導体チップ１を挟むこ
とにより、電気的接続、伝熱接合構造を呈した半導体ユ
ニット４４を構成し、この導電部材３０，３１の両外面
（半導体ユニット４４の両面）に、はんだ或いは良熱伝
導接着剤１０により電気絶縁層３２，３３、熱拡散板４
０，４１、放熱板８，９を対称配置で層状に積層する。That is, the conductive members 30 and 31 having a thick plate structure
By sandwiching the semiconductor chip 1 with the solder layers 22 and 23 interposed therebetween, a semiconductor unit 44 having an electrical connection and a heat transfer bonding structure is formed, and both outer surfaces of the conductive members 30 and 31 (both sides of the semiconductor unit 44). ), The electrical insulating layers 32 and 33, and the heat diffusion plate 4 by solder or a good thermal conductive adhesive 10.
Layers 0 and 41 and heat sinks 8 and 9 are laminated symmetrically.
【００４２】熱拡散板４０と４１は銅厚板よりなり、こ
の熱拡散板により半導体ユニット４４を熱接合構造で挟
むことで、熱流４２，４３のように放熱路を拡大して、
チップ１の発熱を放熱体８，９に熱伝達し、効果的な放
熱を実現することができる。The heat diffusion plates 40 and 41 are made of a thick copper plate, and the semiconductor unit 44 is sandwiched by the heat diffusion plates in a heat-bonding structure to expand the heat radiation paths like the heat flows 42 and 43.
The heat generated by the chip 1 can be transferred to the radiators 8 and 9 to realize effective heat radiation.
【００４３】図６に本発明の第４の実施例を示す。図６
の（ａ）は、本実施例に係る半導体装置の断面正面図、
（ｂ）はそのＡ―Ａ′断面図である。FIG. 6 shows a fourth embodiment of the present invention. Figure 6
(A) is a sectional front view of the semiconductor device according to the present embodiment,
(B) is the AA 'cross section figure.
【００４４】本実施例においても、半導体チップ（例え
ばシリコンチップ）１を金属ベースに相当する厚板構造
の導電部材６０，６１（例えば銅厚板で、図１，図３の
導電部材３０，３１に相当する）で構成する。また、導
電部材６０，６１は、シリコンチップ１に対して両面配
置構造をなして、シリコンチップ１の電極をサンドイッ
チ状に挟み、これらの電極と接合される。Also in this embodiment, the conductive members 60 and 61 (for example, copper thick plates, which are semiconductor plates (for example, silicon chips) 1) having a thick plate structure corresponding to the metal base are made of the conductive members 30, 31 shown in FIGS. Equivalent to). Further, the conductive members 60 and 61 have a double-sided arrangement structure with respect to the silicon chip 1, sandwich the electrodes of the silicon chip 1 in a sandwich shape, and are joined to these electrodes.
【００４５】本実施例では、シリコンチップ１を導電部
材６０，６１でサンドイッチ状に挟んで成る積層構造体
が、電気絶縁板（電気絶縁層）６４を介して放熱体８上
面に配置される。金属ベースを兼ねる一方の導電部材６
０が放熱体８に電気絶縁層６４を介して伝熱可能に接合
されると共に、もう一方の導電部材６１は、導電部材６
０とブリッジ状に交差して放熱体８に電気絶縁層６４を
介して伝熱可能に接合されている。すなわち、本実施例
では、いずれの導電部材６０，６１も共通の放熱体８の
片面に電気絶縁層６４を介して接合される。In this embodiment, a laminated structure in which the silicon chip 1 is sandwiched between the conductive members 60 and 61 is arranged on the upper surface of the radiator 8 with the electric insulating plate (electrical insulating layer) 64 interposed therebetween. One conductive member 6 also serving as a metal base
0 is joined to the radiator 8 via the electric insulating layer 64 so as to be able to transfer heat, and the other conductive member 61 is the conductive member 6
0 crosses in a bridge shape and is joined to the radiator 8 via the electric insulating layer 64 so that heat can be transferred. That is, in this embodiment, both of the conductive members 60 and 61 are joined to one surface of the common heat radiator 8 via the electric insulating layer 64.
【００４６】本実施例によれば、導電部材６０，６１が
拡大された放熱路構造をなして半導体チップ１で発熱し
た熱を、両面放熱の熱流６５，６６により効率良く放熱
体８に導くことができ、また、半導体チップ１とその両
面に接合された導電部材６０，６１との間の線膨張率差
で生じる熱応力は、両面接合部６２、６３で分担する。According to the present embodiment, the conductive members 60 and 61 form an enlarged heat dissipation path structure to efficiently guide the heat generated in the semiconductor chip 1 to the heat radiator 8 by the heat flows 65 and 66 for double-sided heat dissipation. The double-sided joints 62 and 63 share the thermal stress caused by the difference in linear expansion coefficient between the semiconductor chip 1 and the conductive members 60 and 61 joined to both surfaces thereof.
【００４７】したがって、本実施例においても、部品点
数の合理化を図りつつ、効率の良い放熱構造を実現し、
また半導体チップと導電体とのはんだ接合部の熱サイク
ル応力を軽減して熱サイクル寿命を向上させることがで
きる。Therefore, also in this embodiment, an efficient heat dissipation structure is realized while rationalizing the number of parts.
Further, it is possible to reduce the thermal cycle stress at the solder joint portion between the semiconductor chip and the conductor and improve the thermal cycle life.
【００４８】図７に本発明の第５の実施例を示す。図７
の（ａ）は、本実施例に係る半導体装置の断面正面図、
（ｂ）はそのＡ―Ａ′断面図である。FIG. 7 shows a fifth embodiment of the present invention. Figure 7
(A) is a sectional front view of the semiconductor device according to the present embodiment,
(B) is the AA 'cross section figure.
【００４９】本実施例は、既述した各実施例と異なり、
板状の導電部材（リード端子）３０，３１については、
金属ベースを兼用させず、導電部材と別個に金属ベース
５０とブリッジ状の伝熱体（ブリッジ伝熱体５１）を備
える。This embodiment is different from the above-mentioned embodiments,
Regarding the plate-shaped conductive members (lead terminals) 30 and 31,
A metal base 50 and a bridge-shaped heat transfer body (bridge heat transfer body 51) are provided separately from the conductive member without being used also as a metal base.
【００５０】半導体チップ１については、既述した実施
例同様に板状の導電部材３０，３１によってサンドイッ
チ状に挟み込まれ、導電部材３０，３１が半導体チップ
１の両面に設けた電極に接合される。The semiconductor chip 1 is sandwiched between the plate-shaped conductive members 30 and 31 as in the above-described embodiment, and the conductive members 30 and 31 are bonded to the electrodes provided on both surfaces of the semiconductor chip 1. .
【００５１】この半導体チップ１及び導電部材３０，３
１の積層構造体４４を金属ベース５０上に電気絶縁層３
３を介して載置（接合）する。ブリッジ伝熱体５３は、
金属ベース５０上で積層構造体４４にブリッジ状にまた
がって、その内面が積層構造体４４の上面に電気絶縁層
３２を介して接触し、伝熱体５３の両端が金属ベース５
０に接触する。金属ベース５０の外面には放熱体８が接
合（接着）により配置されている。The semiconductor chip 1 and the conductive members 30, 3
The laminated structure 44 of No. 1 on the metal base 50 and the electrically insulating layer 3
Place (join) via 3. The bridge heat transfer body 53 is
On the metal base 50, the laminated structure 44 is straddled in a bridge shape, the inner surface of which is in contact with the upper surface of the laminated structure 44 via the electrically insulating layer 32, and both ends of the heat transfer body 53 are the metal base 5.
Touch 0. The radiator 8 is arranged on the outer surface of the metal base 50 by bonding (adhesion).
【００５２】本実施例によれば、チップ１の発熱は、上
面，下面より拡大された放熱路（伝熱路）６１，６０を
介して拡散された熱流６６，６５となって同一の放熱体
８に導かれ、効率の良い両面冷却構造によりチップ１の
熱を放熱させることができる。According to the present embodiment, the heat generated by the chip 1 becomes the heat flows 66, 65 diffused through the heat dissipation paths (heat transfer paths) 61, 60 which are enlarged from the upper and lower surfaces, and the same heat radiator is formed. The heat of the chip 1 can be radiated by the efficient double-sided cooling structure.
【００５３】また、半導体チップ１とその両面に接合さ
れた導電部材３０，３１との間の線膨張率差で生じる熱
応力は、両面接合部２２、２３で分担する。Further, the double-sided joint portions 22 and 23 share the thermal stress caused by the difference in linear expansion coefficient between the semiconductor chip 1 and the conductive members 30 and 31 joined to both surfaces thereof.
【００５４】したがって、本実施例においても、部品点
数の合理化を図りつつ、効率の良い放熱構造を実現し、
また半導体チップと導電体とのはんだ接合部の熱サイク
ル応力を軽減して熱サイクル寿命を向上させることがで
きる。Therefore, also in this embodiment, an efficient heat dissipation structure is realized while rationalizing the number of parts.
Further, it is possible to reduce the thermal cycle stress at the solder joint portion between the semiconductor chip and the conductor and improve the thermal cycle life.
【００５５】これまで接合部をはんだ接合で説明したが
導電接着剤等による接合でも同様な効果が有る。また３
０、３１等の伝熱構造材を銅材で説明したが、一般に、
銅、アルミ等を主体とする複合材や粉末焼結体など、線
膨張率を比較的抑えた材質で、高熱伝導性と高電気伝導
性を有す部材であれば本発明に適用できる。Although the joint portion has been described so far by soldering, the same effect can be obtained by joining with a conductive adhesive or the like. Again 3
Although the heat transfer structural material such as 0, 31 has been described as a copper material, in general,
Any member having a relatively low coefficient of linear expansion and having high thermal conductivity and high electrical conductivity, such as a composite material mainly composed of copper or aluminum or a powder sintered body, can be applied to the present invention.
【００５６】[0056]
【発明の効果】本発明によれば、次のような効果を奏す
る。
（１）半導体チップと板状導電部材の接合構造におい
て、両面接合構造により接合層に生じる熱応力を分散
し、また半導体チップの両面を部品点数の合理化を図り
つつ拡大された冷却構造（放熱構造）にて高い放熱性能
を実現し、温度上昇を低減することにより、熱サイクル
耐量が従来比１桁以上（約３０倍）優れた実装構造とで
きる。
（２）また、導電部材（リード端子）を金属ベースに兼
用させること、及び、半導体チップの大電流電極配線を
銅板等で接続するワイヤレス配線とすることにより、配
線接合層の熱サイクル耐量の改善と配線占有空間を省略
し、半導体装置を小型簡素な構造とすることができる。The present invention has the following effects. (1) In the joint structure of the semiconductor chip and the plate-shaped conductive member, the double-sided joint structure disperses the thermal stress generated in the joint layer, and the both sides of the semiconductor chip are expanded while the ratio of the number of components is increased (the heat dissipation structure). By realizing high heat dissipation performance and reducing the temperature rise, it is possible to realize a mounting structure with a heat cycle resistance of one digit or more (about 30 times) superior to the conventional one. (2) Further, by using the conductive member (lead terminal) also as the metal base and by using the wireless wiring for connecting the large current electrode wiring of the semiconductor chip with a copper plate or the like, the thermal cycle resistance of the wiring bonding layer is improved. The wiring occupying space can be omitted, and the semiconductor device can have a small and simple structure.
【図１】本発明に係る半導体チップの基本実装構造を示
す一部省略断面図。FIG. 1 is a partially omitted sectional view showing a basic mounting structure of a semiconductor chip according to the present invention.
【図２】（ａ）が本発明における両面接合構造の熱応力
説明図、図２（ｂ）が本発明に対する比較説明図（片面
接合構造）。FIG. 2A is an explanatory view of thermal stress of a double-sided bonding structure according to the present invention, and FIG. 2B is a comparative explanatory view of the present invention (single-sided bonding structure).
【図３】本発明の第１実施例に係る半導体装置の断面
図。FIG. 3 is a sectional view of a semiconductor device according to a first embodiment of the present invention.
【図４】本発明の第２実施例に係る要部を抜粋して示す
断面図。FIG. 4 is a sectional view showing an essential part of a second embodiment of the present invention.
【図５】本発明の第３実施例に係る断面図。FIG. 5 is a sectional view according to a third embodiment of the present invention.
【図６】本発明の第４実施例に係る断面図。FIG. 6 is a sectional view according to a fourth embodiment of the present invention.
【図７】本発明の第５実施例に係る断面図。FIG. 7 is a sectional view according to a fifth embodiment of the present invention.
１…半導体チップ、２…ソース電極（第２の電極）、３
…ドレイン電極（第１の電極）、４…ゲートなど制御電
極（第３の電極）、８，９…放熱体、１０…はんだ接
合、２２，２３…はんだ接合部、３０，３１…導電部
材、３２，３３…絶縁層、４０，４１…熱拡散板、４４
…半導体ユニット（積層構造体）、５０…金属ベース、
５１…ブリッジ伝熱体。1 ... Semiconductor chip, 2 ... Source electrode (second electrode), 3
... Drain electrode (first electrode), 4 ... Control electrode (third electrode) such as gate, 8, 9 ... Radiator, 10 ... Solder joint, 22, 23 ... Solder joint part, 30, 31 ... Conductive member, 32, 33 ... Insulating layer, 40, 41 ... Thermal diffusion plate, 44
... Semiconductor unit (laminated structure), 50 ... Metal base,
51 ... Bridge heat transfer element.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 保川 彰夫 茨城県ひたちなか市大字高場2520番地 株 式会社日立製作所自動車機器グループ内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Akio Hogawa Hitachinaka City, Ibaraki Prefecture 2520 Takaba Ceremony Company Hitachi Ltd. Automotive equipment group
Claims (8)
ー半導体素子（以下、「半導体チップ」と称する）と、
この半導体チップをサンドイッチ状に挟む板状の導電部
材とを有し、これらの導電部材が前記半導体チップの両
面に設けた電極に接合される半導体装置であって、 前記導電部材のうち一方の導電部材が前記半導体チップ
の金属ベースを兼ね、もう一方の導電部材は、前記金属
ベースに相当する導電部材と同等の板厚構造をなしてい
ることを特徴とする半導体装置。1. A chip-shaped power semiconductor device having electrodes on both sides (hereinafter referred to as "semiconductor chip"),
A semiconductor device having plate-shaped conductive members sandwiching the semiconductor chip in a sandwich shape, wherein these conductive members are bonded to electrodes provided on both surfaces of the semiconductor chip, wherein one of the conductive members has conductivity. A semiconductor device, wherein the member also serves as a metal base of the semiconductor chip, and the other conductive member has a plate thickness structure equivalent to that of a conductive member corresponding to the metal base.
のである請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the conductive member has a plate thickness of 1 mm or more.
む前記両導電部材の外面に電気絶縁層を介して放熱体が
接合されている請求項１又は２記載の半導体装置。3. The semiconductor device according to claim 1, wherein a heat radiator is joined to the outer surfaces of the both conductive members sandwiching the semiconductor chip in a sandwich shape, with an electric insulating layer interposed therebetween.
電部材でサンドイッチ状に挟んで成る積層構造体が電気
絶縁層を介して配置され、前記導電部材のうち金属ベー
スを兼ねる一方の導電部材が前記放熱体に前記電気絶縁
層を介して伝熱可能に接合されると共に、もう一方の導
電部材は、前記金属ベース兼用の導電部材とブリッジ状
に交差して前記放熱体に電気絶縁層を介して伝熱可能に
接合されている請求項１又は２記載の半導体装置。4. A laminated structure in which the semiconductor chip is sandwiched between the conductive members in a sandwich shape is arranged on a heat radiator via an electrically insulating layer, and one of the conductive members also serves as a metal base. Is joined to the heat radiator via the electric insulating layer so that heat can be transferred, and the other conductive member crosses the conductive member also serving as the metal base in a bridge shape to form the electric insulating layer on the heat radiator. The semiconductor device according to claim 1, wherein the semiconductor device is heat-conductively bonded via the semiconductor device.
と、前記半導体チップに設けた電極に接続される板状の
導電部材と、前記半導体チップの発熱を放熱する放熱体
とを備え、 前記半導体チップの一面に、ドレイン或いはコレクタ電
極に相当する第１の電極が配設され、もう一面に、ソー
ス或いはエミッタ電極に相当する第２の電極と、ゲート
或いはベース電極に相当する第３の電極とが配設され、 前記導電部材は、前記第１の電極と接続される第１の導
電部材と、前記第２の電極と接続される第２の導電部材
と、前記第３の電極と接続される第３の導電部材よりな
り、前記第１，第２の導電部材の板厚は、第３の導電部
材の板厚より厚くしてあり、 前記第１，第２の導電部材が前記半導体チップをサンド
イッチ状に挟んで該半導体チップの両面に設けた前記第
１，第２の電極に接合され、かつ前記第２の導電部材の
内面一端を凹ませ、前記第３の電極は前記凹みに対向す
るように配置されており、この凹みの空間を利用して前
記第３の導電部材と前記第３の電極とが直接或いはワイ
ヤを介して接合されていることを特徴とする半導体装
置。5. A semiconductor chip having electrodes on both sides thereof, a plate-shaped conductive member connected to the electrodes provided on the semiconductor chip, and a radiator for radiating heat generated by the semiconductor chip, A first electrode corresponding to a drain or collector electrode is provided on one surface of the semiconductor chip, and a second electrode corresponding to a source or emitter electrode and a third electrode corresponding to a gate or base electrode are provided on the other surface. And a conductive member that is connected to the first electrode, a second conductive member that is connected to the second electrode, and a third electrode. And a plate thickness of the first and second conductive members is larger than a plate thickness of the third conductive member, and the first and second conductive members are the semiconductors. Sandwiching the chips in a sandwich The third electrode is arranged so as to be joined to the first and second electrodes provided on both surfaces, and one end of the inner surface of the second conductive member is recessed, and the third electrode is opposed to the recess. The semiconductor device, wherein the third conductive member and the third electrode are bonded to each other directly or via a wire by utilizing the space.
と、この半導体チップをサンドイッチ状に挟む板状の導
電部材とを有し、これらの導電部材が前記半導体チップ
の両面に設けた電極に接合される半導体装置であって、 前記半導体チップの両面に配置される両導電部材の外側
に、該導電部材から熱を拡散させて伝える熱拡散板と、
この熱拡散板からの熱を放熱させる放熱体とを積層させ
てなることを特徴とする半導体装置。6. A semiconductor chip having electrodes on both sides thereof, and a plate-shaped conductive member sandwiching the semiconductor chip in a sandwich shape, the conductive members being electrodes provided on both sides of the semiconductor chip. A semiconductor device to be joined, wherein, on the outside of both conductive members arranged on both sides of the semiconductor chip, a heat diffusion plate for diffusing and transmitting heat from the conductive members,
A semiconductor device characterized by being laminated with a radiator for radiating heat from the heat diffusion plate.
と、この半導体チップをサンドイッチ状に挟む板状の導
電部材とを有し、これらの導電部材が前記半導体チップ
の両面に設けた電極に接合される半導体装置であって、 前記導電部材は、一方が金属ベースを兼ね、もう一方は
前記金属ベースを兼ねる導電部材にブリッジ状にまたが
って交差し、これらの導電部材は、半導体チップの発熱
を逃がすための伝熱体として機能するように、放熱体の
片面に電気絶縁層を介して伝熱可能に接合されているこ
とを特徴とする半導体装置。7. A semiconductor chip having electrodes arranged on both sides thereof, and a plate-shaped conductive member sandwiching the semiconductor chip in a sandwich shape, and these conductive members are electrodes provided on both sides of the semiconductor chip. In the semiconductor device to be joined, one of the conductive members intersects with a conductive member having one serving also as a metal base and the other serving as the metal base in a bridge shape, and these conductive members serve to generate heat of a semiconductor chip. A semiconductor device, which is heat-transferably bonded to one surface of a radiator via an electrically insulating layer so as to function as a heat conductor for releasing heat.
と、この半導体チップをサンドイッチ状に挟む板状の導
電部材とを有し、これらの導電部材が前記半導体チップ
の両面に設けた電極に接合される半導体装置であって、 前記半導体チップ及び導電部材の積層構造体を載置する
金属ベースと、前記金属ベース上で前記積層構造体にブ
リッジ状にまたがって内面が前記積層構造体の上面に接
触し両端が前記金属ベースに接触するブリッジ伝熱体
と、前記金属ベースの外面に配置された放熱体とを備え
てなることを特徴とする半導体装置。8. A semiconductor chip having electrodes on both sides thereof, and a plate-like conductive member sandwiching the semiconductor chip in a sandwich shape, the conductive members being electrodes provided on both sides of the semiconductor chip. A semiconductor device to be joined, comprising: a metal base on which the laminated structure of the semiconductor chip and the conductive member is mounted; and an inner surface that straddles the laminated structure on the metal base in a bridge shape, and the inner surface is the upper surface of the laminated structure. A semiconductor device, comprising: a bridge heat transfer member that contacts a metal base and has both ends contacting the metal base; and a heat radiator disposed on an outer surface of the metal base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001230010A JP2003046048A (en) | 2001-07-30 | 2001-07-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001230010A JP2003046048A (en) | 2001-07-30 | 2001-07-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003046048A true JP2003046048A (en) | 2003-02-14 |
Family
ID=19062284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001230010A Pending JP2003046048A (en) | 2001-07-30 | 2001-07-30 | Semiconductor device |
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| Country | Link |
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| JP (1) | JP2003046048A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007025950B4 (en) * | 2006-06-05 | 2012-08-30 | Denso Corporation | Semiconductor device and its manufacturing method |
| EP3358617A1 (en) * | 2017-02-02 | 2018-08-08 | JTEKT Corporation | Semiconductor device with substantially equal tensile forces acting on chip surfaces |
| JP2020009868A (en) * | 2018-07-06 | 2020-01-16 | 日立オートモティブシステムズ株式会社 | Semiconductor module |
-
2001
- 2001-07-30 JP JP2001230010A patent/JP2003046048A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007025950B4 (en) * | 2006-06-05 | 2012-08-30 | Denso Corporation | Semiconductor device and its manufacturing method |
| US8309434B2 (en) | 2006-06-05 | 2012-11-13 | Denso Corporation | Method for manufacturing semiconductor device including semiconductor elements with electrode formed thereon |
| EP3358617A1 (en) * | 2017-02-02 | 2018-08-08 | JTEKT Corporation | Semiconductor device with substantially equal tensile forces acting on chip surfaces |
| JP2020009868A (en) * | 2018-07-06 | 2020-01-16 | 日立オートモティブシステムズ株式会社 | Semiconductor module |
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