JP2003046001A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for speeding up and at the some time, for relatively prolonging of the refresh time of a DRAM. SOLUTION: N-channel type memory cell selecting MISFETs, having gate electrodes 9A (word lines WL) using a p<+> poly-SiGe film 9p are formed in a memory array, and n-channel MISFETs, having gate electrodes 9B using an n<+> poly-SiGe film 9n and p-channel MISFETs, having gate electrodes 9C using the p<+> poly-SiGe film 9p, are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and more particularly to a DRAM (dynamic random).
access memory), or a technique effectively applied to a semiconductor integrated circuit device having a logic (logic circuit) embedded memory in which a memory circuit and a logic circuit are provided on the same substrate.

[0002]

2. Description of the Related Art For example, IMD (International Electron Device Meetings. "A Fully
working 0.14 μm DRAM technology with polymetal (W
/ WN / Poly-Si) gate ", 2000),
Since the sheet resistance of polymetal in which a polysilicon film and a refractory metal film are sequentially deposited from the lower layer is as low as about 2 Ω / □, for example, a MISFET (metal insulator se) for selecting a memory cell of a memory array in a DRAM is used.
Adoption of a gate electrode of a miconductor field effect transistor) and a gate electrode of a MISFET of a peripheral circuit is under study.

As the refractory metal film, tungsten (W), molybdenum (Mo), titanium (Ti) or the like, which has good resistance characteristics even at a low temperature process of 800 ° C. or less and has high electromigration resistance, is used.

Further, when a refractory metal film is laminated directly on a polysilicon film, the adhesive force between the two is lowered, and a high-resistance silicide layer is formed at the interface between the two, so that a high-resistance silicide layer is usually formed. A barrier layer made of a metal nitride film such as tungsten nitride (WN) or titanium nitride (TiN) is sandwiched between the refractory metal film and the polysilicon film.

[0005]

However, the present inventor has found that the gate electrode having the above-mentioned laminated structure made of polymetal has the following problems.

First, since the contact resistance at the interface between the barrier layer and the polysilicon film is increased, the gate delay time of the MISFET is increased despite the use of the low resistance refractory metal film.

For example, the contact resistance between the tungsten / tungsten nitride laminated film and the polysilicon film is 5 × 10 ⁻⁶ Ω.
cm ² with a gate length of 0.1 μm and a gate width of 10 μm
In the gate electrode of m, the resistance (interface resistance) at the interface between the tungsten / tungsten nitride laminated film and the polysilicon film is 500Ω. The thickness of the gate insulation film is 3.5n
When m, the capacitance of the gate insulating film is 1 μF / cm ² , and the RC delay time (5 psec) between the interface resistance and the capacitance of the gate insulating film occupies about 1/3 of the gate delay time.

Further, in the memory cell selecting MISFET of the memory array, normally, the conductivity type of the polysilicon film forming the lower layer of the gate electrode is n type, and the threshold voltage of the memory cell selecting MISFET is increased. Therefore, the substrate concentration is set relatively high. However, when the substrate concentration is increased, the electric field strength at the drain end, which is the storage node of the memory cell selection MISFET, is increased, the leak current is increased and the refresh time is shortened, or the parasitic capacitance of the bit line is increased. Occurs.

Further, as the substrate concentration increases, the substrate bias effect increases and the threshold voltage during data writing rises. Therefore, it is necessary to increase the boosted word voltage, which limits the thinning of the gate insulating film.

An object of the present invention is to provide a technique capable of realizing a high speed operation in a DRAM and at the same time making the refresh time relatively long.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the present invention, an n-channel type memory cell selecting MISFET is formed in a memory array and an n-channel type MISFET is formed in a peripheral circuit.
When forming the channel MISFET and the p-channel MISFET, a deep n-type well is formed in the memory array, and the n-channel MISF of the memory array and the peripheral circuit is formed.
Forming a p-type well in the region where the ET is formed, forming an n-type well in the region where the p-channel MISFET of the peripheral circuit is formed, forming a gate insulating film on the surface of the substrate, and A step of sequentially forming a polysilicon film and a silicon germanium (SiGe) layer on the substrate, and introducing a p-type impurity into the semiconductor layer in the region where the n-channel MISFET of the memory array and the peripheral circuit is formed so that the p-channel MISFET of the peripheral circuit is formed. The step of introducing an n-type impurity into the semiconductor layer in the region to be formed, the step of sequentially forming a barrier layer and a refractory metal film on the substrate, the step of refractory metal film, the barrier layer, the silicon germanium layer and the polysilicon film are performed. MISFE for memory cell selection by sequentially processing
T, n-channel MISFET and p-channel MISF
And a step of forming a gate electrode of ET.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) An example of a method of manufacturing a DRAM according to the first embodiment of the present invention will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 1, a p-type substrate 1 having a specific resistance of about 10 Ωcm is prepared, and a shallow groove 2 is formed in the main surface of the substrate 1. Then, the substrate 1 is subjected to thermal oxidation to form a silicon oxide film 3. Further, a silicon oxide film is deposited and is deposited by CMP (Chemical Mechanical Polishing).
By the method g), the isolation region 4 is formed by leaving the silicon oxide film only in the shallow groove 2 by polishing.

Next, an n-type impurity, for example, phosphorus (P) is ion-implanted into the substrate 1 in the region (A region: memory array) where the memory cell is formed to form a deep n-type well 5 and the memory array and the periphery. Part of circuit (B area) (n
P-type impurities in a region for forming the channel MISFET),
For example, boron (B) is ion-implanted to form the p-type well 6, and another part of the peripheral circuit (p-channel MISF) is formed.
An n-type impurity, for example, phosphorus is ion-implanted into a region (where ET is formed) to form an n-type well 7. In addition, following this ion implantation, impurities such as boron fluoride (BF) for adjusting the threshold voltage of the MISFET are used.
₂ ) is ion-implanted into the p-type well 6 and the n-type well 7. The deep n-type well 5 is formed to prevent noise from entering the p-type well 6 of the memory array from the input / output circuit or the like through the substrate 1.

Next, as shown in FIG. 2, the surfaces of the p-type well 6 and the n-type well 7 are washed with a hydrofluoric acid (HF) solution, and then the substrate 1 is wet-oxidized at about 850 ° C. Then, a clean gate insulating film 8 made of silicon oxide and having a film thickness of about 6 to 7 nm is formed on each surface of the p-type well 6 and the n-type well 7.

Next, gate electrodes 9A, 9B and 9C are formed on the gate insulating film 8. The gate electrode 9A constitutes a part of the memory cell selecting MISFET, and functions as a word line WL in a region other than the active region. The gate electrode 9B and the gate electrode 9C are the n-channel M of the peripheral circuit.
It constitutes a part of each of the ISFET and the p-channel MISFET.

Gate electrode 9A (word line WL) and gate electrodes 9B and 9C are formed, for example, by the following method.

First, for example, MBE (molecular beam e)
A material having a band gap smaller than that of silicon (Si), for example, a silicon germanium layer is epitaxially grown to a thickness of about 50 to 100 nm on the entire surface by the pitaxy method or the CVD method. After that, p-type impurities, for example, boron are ion-implanted into a region where the p-channel MISFET of the memory array and the peripheral circuit is formed to make the silicon germanium layer a p-type conductivity type, and the p ⁺ -type silicon germanium layer (hereinafter, 9p is formed as a p ⁺ poly-SiGe film. Further, an n-type impurity, for example, phosphorus is ion-implanted into a region of the peripheral circuit where the n-channel MISFET is formed, and an n ⁺ -type silicon germanium layer (hereinafter,
n ⁺ poly-SiGe film) 9n. Instead of silicon germanium, germanium (Ge) or silicon germanium carbon (SiGeC) may be deposited.

Then, the p ⁺ poly-SiGe film 9p and the n ^{+ are formed.}
A barrier layer made of, for example, tungsten nitride and a refractory metal film made of, for example, tungsten are sequentially deposited on the poly-SiGe film 9n by a sputtering method, and a silicon nitride film 10 is further deposited thereon by a CVD method.
These films are patterned using the resist film as a mask. As a result, the p ⁺ poly
The Ge film 9p, the gate electrode 9A (word line WL) in which the barrier layer and the refractory metal film are stacked, and n ⁺ poly S from the lower layer in the region where the n channel MISFET of the peripheral circuit is formed.
iGe film 9n, a gate electrode 9B in which a barrier layer and a refractory metal film are stacked, and a p-channel MISFET of a peripheral circuit
P ⁺ poly-SiGe film 9p from the lower layer in the region where
Gate electrode 9 in which a barrier layer and a refractory metal film are laminated
C is formed. The thickness of the barrier layer is, for example, 1
The thickness of the refractory metal film is about 0 nm and is 100 n, for example.
m, and the thickness of the silicon nitride film 10 is, for example, 150.
It is about nm.

Although the band gap of silicon germanium depends on the concentration of germanium, it is 0.2 eV more than that of silicon at a germanium concentration of 20%.
It gets smaller. As a result, the tunnel barrier between the silicon germanium layer and the refractory metal film becomes lower than the tunnel barrier between the silicon film and the refractory metal film, and the interface resistance between the silicon germanium layer and the refractory metal film is reduced. It is lower than the interface resistance with the film. Furthermore, since both the solid solubility limit and the activation rate of impurities in the silicon germanium layer are larger than the values in the silicon film, it is possible to introduce many impurities into the silicon germanium layer to increase the carrier concentration. The interface resistance of the silicon germanium layer can be reduced.

The work function of the p ⁺ poly-SiGe film 9p is about 4.97 eV, and the work function of the n ⁺ poly-SiGe film 9n is about 4.15 eV. Therefore, the same substrate concentration (p
(Type well 6 concentration), the threshold voltage of the memory cell selecting MISFET using the p ⁺ poly-SiGe film 9p is n
⁺ N-channel MISFET using poly-SiGe film 9n
About 0.8 V higher than the threshold voltage of. That is,
Even if the substrate concentration (concentration of the p-type well 6) is set relatively low in order to obtain the threshold voltage of about 0.1 V necessary for low voltage operation in the n-channel MISFET, Therefore, a threshold voltage of about 0.9 V necessary for holding data can be obtained.

Thus, the substrate concentration (p
Since the concentration of the mold well 6 can be set relatively low, the electric field at the drain end of the storage node can be reduced and the leak current can be reduced. Further, since the subthreshold coefficient of the memory cell selecting MISFET can be reduced, even if the threshold voltage is the same, the memory cell selecting MISFE can be reduced.
The leak current of T can be reduced. By reducing these leak currents, the refresh time can be made longer than before. Further, by setting the substrate concentration (concentration of the p-type well 6) relatively low, the substrate bias effect is reduced, and the boosted word line voltage can be reduced accordingly, so the thickness of the gate insulating film 8 is reduced. be able to.

Next, after removing the resist film, an etching solution such as hydrofluoric acid is used to remove the dry etching residue and the resist residue remaining on the surface of the substrate 1.

Next, as shown in FIG. 3, p-type impurities, for example, boron are ion-implanted into the n-type well 7 of the peripheral circuit to form the p ^-- type semiconductor regions 11 in the n-type wells 7 on both sides of the gate electrode 9C. Form. Further, n-type impurities such as phosphorus are ion-implanted into the p-type well 6 of the peripheral circuit to form the n ⁻ -type semiconductor regions 12 in the p-type wells 6 on both sides of the gate electrode 9B. To n
An n-type semiconductor region 13 is formed in the p-type well 6 on both sides of the gate electrode 9A by ion-implanting a type impurity, for example, phosphorus.
ISFET is almost completed.

Next, after depositing a silicon nitride film 14 having a thickness of about 50 nm on the substrate 1 by the plasma CVD method, the silicon nitride film 14 of the memory array is covered with a resist film and the silicon nitride film 14 of the peripheral circuit is changed. The sidewall spacers 15 are formed on the sidewalls of the gate electrodes 9B and 9C by performing the anisotropic etching.

Next, after removing the resist film, p-type impurities such as boron are ion-implanted into the n-type well 7 of the peripheral circuit to form the p ⁺ -type semiconductor region 16 (source, drain) of the p-channel MISFET. Then, an n-type impurity such as arsenic (As) is ion-implanted into the p-type well 6 of the peripheral circuit to form the n ⁺ -type semiconductor region 17 (source, drain) of the n-channel MISFET. As a result, the p-channel MISFET and the n-channel MISFET are substantially completed in the peripheral circuit.

Next, as shown in FIG. 4, an SOG (Spin On Glass) film 18 having a film thickness of about 300 nm is spin-coated on the substrate 1, and then the substrate 1 is heat-treated at 800 ° C. for about 60 seconds to obtain the SOG film 18. Are sintered.

Next, a film thickness of 600 n is formed on the SOG film 18.
After depositing the silicon oxide film 19 of about m, the silicon oxide film 19 is polished by the CMP method to flatten its surface. The silicon oxide film 19 is formed of, for example, TEOS (Tetra).
Ethyl Ortho Silicate: Si (OC ₂ H ₅ ) ₄ ) and ozone (O ₃ ) are deposited by a plasma CVD method using source gases.

Next, a film thickness of 1 is formed on the upper layer of the silicon oxide film 19.
A silicon oxide film 20 having a thickness of about 00 nm is deposited. The silicon oxide film 20 is deposited in order to repair fine scratches on the surface of the silicon oxide film 19 that occur when the silicon oxide film 20 is polished by the CMP method. The silicon oxide film 20 is, for example, TE
The plasma CVD method using OS and ozone as source gas is deposited. Instead of the silicon oxide film 20, PSG (Phospho Silicate Glass) is formed on the silicon oxide film 19.
The film may be deposited.

Next, a resist film is formed on the silicon oxide film 20, and the silicon oxide on the n-type semiconductor region 13 (source, drain) of the memory cell selection MISFET is dry-etched by using the resist film as a mask. The films 20, 19 and the SOG film 18 are removed. Then, the silicon nitride film 14 and the gate insulating film 8 above the n-type semiconductor region 13 (source, drain) of the memory cell selecting MISFET are removed by dry etching using the resist film as a mask, thereby n-type Semiconductor region 13
A contact hole 21 is formed in one upper part of (source, drain), and a contact hole 22 is formed in the other upper part.

Next, after removing the resist film, plugs 23 are formed inside the contact holes 21 and 22. As the plug 23, a polysilicon film having an n-type impurity (for example, phosphorus) introduced into the upper layer of the silicon oxide film 20 is CV.
After being deposited by the D method, the polysilicon film is polished by the CMP method and left inside the contact holes 21 and 22 to be formed.

Next, as shown in FIG. 5, a silicon oxide film 24 having a thickness of about 200 nm is formed on the silicon oxide film 20.
After depositing, the substrate 1 is heat-treated at about 800 ° C. The silicon oxide film 24 is deposited by, for example, a plasma CVD method using TEOS and ozone as source gases. Also,
By this heat treatment, the n-type impurities in the polysilicon film forming the plug 23 diffuse from the bottoms of the contact holes 21 and 22 to the n-type semiconductor region 13 (source, drain) of the MISFET for memory cell selection, and the n-type semiconductor region. 1
3 has a low resistance.

Next, the silicon oxide film 24 on the contact hole 21 is removed by dry etching using the resist film as a mask to expose the surface of the plug 23.
Next, after removing the resist film, the silicon oxide films 24, 20, 19 of the peripheral circuit, the SOG film 18 and the gate insulating film 8 are dry-etched using the resist film as a mask.
By removing the n-channel MISFET n ⁺
A contact hole 25 is formed in the upper part of the type semiconductor region 17 (source, drain), and p-channel MISFET p
^A contact hole 26 is formed above the ⁺ type semiconductor region 16 (source, drain).

Next, after removing the resist film, as shown in FIG.
As shown in FIG.
L and the first layer wiring 27 of the peripheral circuit are formed. The bit line BL and the first layer wiring 27 are, for example, a titanium film with a film thickness of about 50 nm and a film thickness of 50 n on the upper layer of the silicon oxide film 24.
and a titanium nitride film of about m are deposited by the sputtering method,
Further, a CV film having a film thickness of about 150 nm and a silicon nitride film 28a having a film thickness of about 200 nm are formed on the upper surface thereof by CV.
After the deposition by the D method, the resist film is used as a mask to pattern these films.

After depositing a titanium film on the silicon oxide film 24, the substrate 1 is heat-treated at about 800 ° C., so that the titanium film and the substrate 1 react with each other to form the p-channel MISF.
Surface of p ⁺ type semiconductor region 16 (source, drain) of ET, n ⁺ type semiconductor region 17 of n channel MISFET
Surface of (source, drain) and contact hole 2
A low-resistance titanium silicide (TiSi ₂ ) layer 29 is formed on the surface of the plug 23 embedded in the No. 1 plug. As a result, the contact resistance of the wiring (bit line BL, first layer wiring 27) connected to the p ⁺ type semiconductor region 16, the n ⁺ type semiconductor region 17, and the plug 23 can be reduced. Further, by forming the bit line BL with a tungsten film / titanium nitride film / titanium film, its sheet resistance is 2Ω /
Since it can be reduced to □ or less, the bit line BL and the first layer wiring 27 of the peripheral circuit can be simultaneously formed in the same step.

Next, the bit line BL and the first layer wiring 27
Side wall spacers 28b are formed on the side walls of the. The sidewall spacer 28b is formed by depositing a silicon nitride film on the bit line BL and the upper layer of the first layer wiring 27 by the CVD method, and then anisotropically etching the silicon nitride film.

Next, as shown in FIG. 7, an SO having a film thickness of about 300 nm is formed on the bit line BL and the first layer wiring 27.
After spin-coating the G film 30, the substrate 1 is heated to 800 ° C. and 60 ° C.
The SOG film 30 is heat-treated for about 2 seconds to be sintered.

Next, a film thickness of 600 n is formed on the upper layer of the SOG film 30.
After depositing the silicon oxide film 31 of about m, the silicon oxide film 31 is polished by the CMP method to flatten its surface. The silicon oxide film 31 is deposited by the plasma CVD method using TEOS and ozone as source gases, for example.
Then, a silicon nitride film 32 having a film thickness of about 100 nm is deposited on the silicon oxide film 31.

Next, the silicon nitride film 32 and the silicon oxide film 3 on the plug 23 embedded in the contact hole 22 by dry etching using the resist film as a mask.
1, the SOG film 30 and the silicon oxide film 24 are removed to form a through hole 33 reaching the surface of the plug 23.

Next, after removing the resist film, a plug 34 is formed inside the through hole 33, and a barrier metal film 35 is further formed on the surface of the plug 34. The plug 34 and the barrier metal film 35 are formed by the following method, for example.

First, a polysilicon film having an n-type impurity (for example, phosphorus) introduced is formed as a CV on the upper layer of the silicon nitride film 32.
It is deposited by the D method, and a polysilicon film is embedded inside the through hole 33. Then, the polysilicon film outside the through hole 33 is removed by the CMP method or the etch back method to form the plug 34. After that, a conductive film such as a titanium nitride film or a silicon titanium nitride (TiNSi) film is formed on the silicon nitride film 32 by a sputtering method.
Aluminum titanium nitride (TiNAl) film, tantalum nitride (TaN) film, silicon tantalum nitride (TaNSi) film
Film, tungsten nitride film or silicon tungsten nitride (WNSi) is deposited, a conductive film is embedded in the upper portion of the plug 34 in the through hole 33, and then the conductive film outside the through hole 33 is formed by the CMP method or the etch back method. A barrier metal film 35 is formed by removing.
This barrier metal film 35 is formed of ruthenium (R) that constitutes the lower electrode of the capacitor during the heat treatment at about 650 to 800 ° C. performed in the dielectric material forming process of the capacitor.
u) It is formed in order to suppress undesired reactions from occurring at the interface between the film and the polysilicon film forming the plug 34.

Next, as shown in FIG. 8, a silicon oxide film 36 having a film thickness equal to or higher than the required height of the lower electrode of the capacitor is formed on the silicon nitride film 32 by the CVD method. After the deposition, the silicon oxide film 36 is dry-etched using the resist film as a mask to form a groove 37 in the upper portion of the through hole 33.
The silicon oxide film 36 is deposited by, for example, a plasma CVD method using TEOS and ozone as a source gas, and the silicon oxide film 36 is etched by using the silicon nitride film 32 as an etching stopper. Try not to scrape.

After the resist film is removed, a ruthenium seed layer (not shown) is formed on the upper layer of the silicon oxide film 36 including the inside of the groove 37 by the sputtering method, and then the seed layer is used as a seed by the CVD method. A ruthenium film 38 is deposited. Then, after applying a resist film 39 on the substrate 1,
The entire surface is exposed and developed to remove the resist film 39 in the exposed portion outside the groove 37, and the resist film 39 in the unexposed portion is left inside the groove 37. After this, a dry etching method using chlorine (Cl ₂ ) + oxygen (O ₂ ) gas or C
The ruthenium film 38 is etched back to a desired position by the MP method, and the ruthenium film 38 is left only inside the groove 37.

Further, as shown in FIG. 9, by removing the resist film 39 inside the groove, a lower electrode 40 constituted by a ruthenium film 38 is formed inside the groove 37. The removal of the resist film 39 is performed by an ashing process using oxygen + ozone-based gas.

Thereafter, a film thickness of 20 n is formed on the lower electrode 40.
The tantalum oxide film 41 having a thickness of about m was formed by using pentaethoxytantalum (Ta (C ₂ H ₅ ) ₅ ) and oxygen as the source gas.
It is deposited by a CVD method at about 00 to 450 ° C. Then
The tantalum oxide film 41 is crystallized by heat-treating the substrate 1 at about 650 to 800 ° C. for about 60 seconds in a nitrogen atmosphere. After this, 600 ° C in an oxygen atmosphere.
Substrate RTA (Rapid Thermal Annealing) processing
May be applied to. Further, the substrate 1 is subjected to ozone treatment at 600 ° C. or lower to repair oxygen defects in the tantalum oxide film 41. The tantalum oxide film 41 thus crystallized and ozone-treated is used as the dielectric material of the capacitor C.

Next, a metal film such as a ruthenium film or a titanium nitride film is deposited on the upper layer of the tantalum oxide film 41 by a sputtering method or a CVD method, and then the metal film is formed by a dry etching method using a resist film as a mask. The upper electrode 42 is formed by patterning, and the upper electrode 42 made of a metal film and the tantalum oxide film 4 are formed.
A capacitor C composed of a dielectric material composed of 1 and a lower electrode 40 composed of a ruthenium film 38 is formed. As a result, a DRAM memory cell including the memory cell selection MISFET and the capacitor C connected in series with the MISFET is completed.

Next, after removing the resist film, a silicon oxide film is deposited on the upper electrode 42 to form an insulating film 43.
Then, a connection hole connected to the first layer wiring 27 is formed in the peripheral circuit to form the plug 44. For the plug 44, an adhesive layer 44a made of a titanium film and a titanium nitride film is deposited on the insulating film 43, a tungsten film 44b is further deposited by a blanket CVD method, and then the tungsten film 44b and the adhesive layer 44a are etched back. Can be formed. Note that the titanium film and the titanium nitride film can be formed by a sputtering method, but can also be formed by a CVD method. further,
A titanium film 45a, aluminum (A
l) A film 45b and a titanium nitride film 45c are sequentially deposited by a sputtering method, and these are patterned to form a second film.
The layer wiring 45 is formed.

Finally, as shown in FIG. 10, a silicon oxide film 46a, an SOG film 46b and a silicon oxide film 46c are sequentially deposited on the second layer wiring 45 to form an interlayer insulating film 4
6 is formed, and a plug 47 is formed in the same manner as the plug 44.
To form. The silicon oxide films 46a and 46c are deposited by the plasma CVD method using TEOS and O ₃ as source gases, for example. Further, the third layer wiring 48 is formed, and the DRAM is substantially completed.

After that, a passivation film is deposited on the multilayer wiring and the uppermost wiring, but the illustration thereof is omitted.

Although the first embodiment has been described as applied to the DRAM, the present invention can also be applied to a semiconductor memory device having a memory cell, for example, a logic embedded memory.

As described above, according to the first embodiment,
P to the gate electrode 9A (word line WL) ⁺Poly SiGe film 9
Memory cell selection with n-channel MISFET using p
A selection MISFET is formed, and n is formed on the gate electrode 9B.⁺Poly
N-channel MISFET using SiGe film 9n and
P on the gate electrode 9C⁺P-type using poly-SiGe film 9p
By forming the channel MISFET in the peripheral circuit,
The interface resistance between the silicon germanium layer and the refractory metal film is
Lower than interface resistance between silicon film and refractory metal film
Therefore, it is possible to speed up the DRAM operation.

Furthermore, since the substrate concentration of the memory array (the concentration of the p-type well 6) can be lowered, the leak current from the drain which is the storage node can be reduced, and the refresh time can be relatively lengthened. it can. Also,
Since the substrate bias effect is reduced and the voltage for boosting the word line can be reduced accordingly, the gate insulating film can be thinned.

(Second Embodiment) A DRAM according to a second embodiment of the present invention will be described with reference to a sectional view of an essential part of a substrate shown in FIG.

As shown in FIG. 11, the gate electrode 9A (word line WL) of the memory cell selecting MISFET of the memory array, the gate electrode 9B of the n-channel MISFET of the peripheral circuit and the gate electrode 9C of the p-channel MISFET.
All have the same structure, and the n ⁺ poly-SiGe film 9 is formed from the lower layer.
n, a barrier layer, and a refractory metal are laminated. That is, in the memory cell selection MISFET, the gate electrode 9A (word line WL) has the n ⁺ poly-SiGe film 9 formed therein.
In the peripheral circuit, an n ⁺ poly SiGe film 9n is formed on the gate electrode 9B.
Channel MISFET and gate electrode 9C using
P-channel MISF using n ⁺ poly-SiGe film 9n
ET is formed.

As a result, the substrate concentration of the memory array (p
Although it is difficult to reduce the concentration of the mold well 6), the interface resistance between the silicon germanium layer and the refractory metal film can be lower than the interface resistance between the silicon film and the refractory metal film.
Further, since the gate electrode 9A (word line WL) and the gate electrodes 9B and 9C have the same laminated structure, the manufacturing process can be simplified.

(Third Embodiment) A DRAM according to a third embodiment of the present invention will be described with reference to a sectional view of an essential part of a substrate shown in FIG.

As shown in FIG. 12, the MISFET for selecting the memory cell of the memory array is the same as in the first embodiment.
Is p ⁺ poly-SiG on the gate electrode 9A (word line WL).
It is composed of an n-channel type MISFET using an e film 9p, and the peripheral circuit has n ⁺ poly-SiGe for the gate electrode 9B.
N channel MISFET using film 9n and p channel M using p ⁺ poly-SiGe film 9p for gate electrode 9C
ISFET is formed. However, the deep n formed deeper than the p-type well 6 on the substrate 1 of the memory array.
The type well 5 is abolished, and no substrate bias is applied to the p-type well 6 of the memory array.

That is, MISFET for memory cell selection
Of the gate electrode 9A (word line WL) of p ⁺ poly-SiGe
Since the film 9p is used, the p-type well 6 of the memory array is
A desired threshold voltage can be obtained without applying a substrate bias to the substrate, and the substrate bias constant can be lowered. Furthermore, since the deep n-type well 5 is not formed, the manufacturing process can be simplified.

(Embodiment 4) A DRAM according to Embodiment 4 of the present invention will be described with reference to a sectional view of a main part of a substrate shown in FIG.

As shown in FIG. 13, the memory cell selecting MISFET of the memory array is composed of a p-channel type MISFET using an n ⁺ poly-SiGe film 9n for the gate electrode 9A (word line WL). That is, the n-type well 7 was formed in the substrate 1 of the memory array, and the gate electrode 9A (word line WL) of the memory cell selecting MISFET was laminated from the lower layer with the n ⁺ poly SiGe film 9n, the barrier layer and the refractory metal. The structure is adopted, and the source and drain are constituted by the p-type semiconductor region 49. Although the conductivity type of the gate electrode 9A and the substrate (p-type well 6) of the memory cell selecting MISFET of the first embodiment is reversed, the memory cell selecting MISFET of the first embodiment is reversed by reversing the applied voltage. Can work as well.

(Fifth Embodiment) An example of a logic mixed type DRAM according to a fifth embodiment of the present invention will be described with reference to the plan view of the essential part of the substrate shown in FIG.

As shown in FIG. 14, in one semiconductor chip 50, a DRAM memory array 51 (area indicated by relatively dark hatching in the figure), a peripheral circuit block 52 for controlling DRAM, A general logic circuit block 53 (a relatively thin hatched area in the drawing) is laid out. In the memory array 51 of the DRAM, an n channel type memory cell selecting MISFET using ap ⁺ poly-SiGe film for the gate electrode is formed, and in the other circuit blocks 52 and 53, an n ⁺ poly for the gate electrode is formed. N-channel MIS using SiGe film
P-channel M using FET and p ⁺ poly-SiGe film
ISFET is formed.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above embodiment, the DRAM
Alternatively, the case where the present invention is applied to the logic mixed type DRAM has been described, but the present invention can be applied to any semiconductor integrated circuit device having a MISFET.

[0068]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

MISF for selecting memory cells of memory array
By using the laminated film of the poly-SiGe film and the refractory metal film for the gate electrode of the ET and the gate electrode of the MISFET of the peripheral circuit, the interface resistance can be reduced and the operation speed of the DRAM can be increased. Further, since the substrate concentration of the memory array can be lowered, the leak current from the storage node can be reduced and the refresh time can be relatively lengthened.

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view of a substrate showing a method of manufacturing a DRAM which is Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view of the essential parts of the substrate, for showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 3 is a main-portion cross-sectional view of the substrate showing the method of manufacturing the DRAM which is Embodiment 1 of the present invention.

FIG. 4 is a main-portion cross-sectional view of the substrate showing the manufacturing method of the DRAM which is Embodiment 1 of the present invention.

FIG. 5 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 6 is a main-portion cross-sectional view of the substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 7 is a main-portion cross-sectional view of the substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 8 is a main-portion cross-sectional view of the substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 9 is a main-portion cross-sectional view of the substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 11 is a main-portion cross-sectional view of a substrate showing a DRAM which is Embodiment 2 of the present invention.

FIG. 12 is a main-portion cross-sectional view of a substrate showing a DRAM which is Embodiment 3 of the present invention.

FIG. 13 is a main-portion cross-sectional view of a substrate showing a DRAM which is Embodiment 4 of the present invention.

FIG. 14 is a main-portion plan view of a substrate showing a logic mixed-type DRAM according to a fifth embodiment of the present invention.

[Explanation of symbols]

1 substrate 2 shallow groove 3 silicon oxide film 4 isolation region 5 deep n-type well 6 p-type well 7 n-type well 8 gate insulating film 9A gate electrode 9B gate electrode 9C gate electrode 9p p ⁺ poly SiGe film 9n n ⁺ poly SiGe film Reference Signs List 10 silicon nitride film 11 p ^- type semiconductor region 12 n ^- type semiconductor region 13 n-type semiconductor region 14 silicon nitride film 15 sidewall spacer 16 p ⁺ type semiconductor region 17 n ⁺ type semiconductor region 18 SOG film 19 silicon oxide film 20 oxidation Silicon film 21 Contact hole 22 Contact hole 23 Plug 24 Silicon oxide film 25 Contact hole 26 Contact hole 27 First layer wiring 28a Silicon nitride film 28b Side wall spacer 29 Titanium silicide layer 30 SOG film 31 Silicon oxide film 32 Silicon nitride film 33 Through hole 34 plug 35 barrier metal film 36 silicon oxide film 37 groove 38 ruthenium film 39 resist film 40 lower electrode 41 tantalum oxide film 42 upper electrode 43 insulating film 44 plug 44a adhesive layer 44b tungsten film 45 second layer wiring 45a titanium film 45b aluminum film 45c titanium nitride film 46 interlayer insulating film 46a silicon oxide film 46b SOG film 46c silicon oxide film 47 plug 48 third layer wiring 49 p-type semiconductor region 50 semiconductor chip 51 memory array 52 peripheral circuit block 53 for controlling DRAM logic circuit block WL Word line BL Bit line C Capacitor

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F083 AD31 AD48 AD49 GA01 GA02                       GA06 GA25 JA06 JA31 JA35                       JA36 JA38 JA39 JA40 MA03                       MA06 MA17 MA20 PR03 PR21                       PR23 PR40 PR43 PR44 PR45                       PR53 PR54 PR55 ZA06

Claims (5)

[Claims] 1. An n-channel first MISFET for selecting a memory cell in a first region of a substrate, an n-channel second MISFET in a second region, and a p-type in a third region.
A method of manufacturing a semiconductor integrated circuit device for forming a channel type third MISFET, comprising: (a) forming a deep n-type well in the first region and forming a p-type well in the first and second regions. Forming a well and forming an n-type well in the third region; (b) forming a gate insulating film on the surface of the substrate; and (c) a polysilicon film and silicon on the substrate. Sequentially forming a semiconductor layer having a band gap smaller than the band gap of,
(D) introducing a p-type impurity into the semiconductor layer in the first and third regions and introducing an n-type impurity into the semiconductor layer in the second region, and (e) a barrier on the substrate. A step of sequentially forming a layer and a refractory metal film, and (f) sequentially processing the refractory metal film, the barrier layer, the semiconductor layer and the polysilicon film to form the first, second and third layers. And a step of forming a gate electrode of the MISFET. 2. An n-channel first MISFET for selecting a memory cell in a first region of a substrate, an n-channel second MISFET in a second region, and a p-type in a third region.
A method of manufacturing a semiconductor integrated circuit device for forming a channel type third MISFET, comprising: (a) forming a deep n-type well in the first region and forming a p-type well in the first and second regions. Forming a well and forming an n-type well in the third region; (b) forming a gate insulating film on the surface of the substrate; and (c) a polysilicon film and silicon on the substrate. Sequentially forming a semiconductor layer having a band gap smaller than the band gap of,
(D) introducing an n-type impurity into the semiconductor layer,
(E) a step of sequentially forming a barrier layer and a refractory metal film on the substrate, and (f) a step of sequentially processing the refractory metal film, the barrier layer, the semiconductor layer, and the polysilicon film to obtain the first And a step of forming gate electrodes of the first, second, and third MISFETs. 3. An n-channel first MISFET for selecting a memory cell in a first region of a substrate, an n-channel second MISFET in a second region, and a p-type in a third region.
A method of manufacturing a semiconductor integrated circuit device for forming a channel-type third MISFET, comprising: (a) forming a p-type well in the first and second regions and forming an n-type well in the third region.
Forming a mold well; (b) forming a gate insulating film on the surface of the substrate; and (c) a polysilicon film on the substrate and a semiconductor layer having a band gap smaller than that of silicon. And (d) introducing a p-type impurity into the semiconductor layer in the first and third regions and introducing an n-type impurity into the semiconductor layer in the second region, (d) e) a step of sequentially forming a barrier layer and a refractory metal film on the substrate,
(F) The refractory metal film, the barrier layer, the semiconductor layer, and the polysilicon film are sequentially processed to form the first,
And a step of forming gate electrodes of the second and third MISFETs. 4. A p-channel first MISFET for selecting a memory cell in a first region of a substrate, an n-channel second MISFET in a second region, and a p-type in a third region.
A method of manufacturing a semiconductor integrated circuit device for forming a channel-type third MISFET, comprising: (a) forming a deep n-type well in the first region and n-type in the first and third regions. Forming a well and forming a p-type well in the second region; (b) forming a gate insulating film on the surface of the substrate; and (c) a polysilicon film and silicon on the substrate. Sequentially forming a semiconductor layer having a band gap smaller than the band gap of,
(D) introducing an n-type impurity into the semiconductor layer in the first and second regions and introducing a p-type impurity into the semiconductor layer in the third region, and (e) a barrier on the substrate. A step of sequentially forming a layer and a refractory metal film, and (f) sequentially processing the refractory metal film, the barrier layer, the semiconductor layer and the polysilicon film to form the first, second and third layers. And a step of forming a gate electrode of the MISFET. 5. An n-channel first MISFET for selecting a memory cell in a first region of a substrate, an n-channel second MISFET in a second region, and a p-type in a third region.
A method of manufacturing a semiconductor integrated circuit device for forming a channel type third MISFET, comprising: (a) forming a deep n-type well in the first region and forming a p-type well in the first and second regions. Forming a well and forming an n-type well in the third region; (b) forming a gate insulating film on the surface of the substrate; and (c) a polysilicon film and silicon on the substrate. Sequentially forming a semiconductor layer having a band gap smaller than the band gap of,
(D) introducing a p-type impurity into the semiconductor layer in the first and third regions and introducing an n-type impurity into the semiconductor layer in the second region, and (e) a barrier on the substrate. A step of sequentially forming a layer and a refractory metal film, and (f) sequentially processing the refractory metal film, the barrier layer, the semiconductor layer and the polysilicon film to form the first, second and third layers. And a step of forming a gate electrode of a MISFET, wherein the semiconductor layer is made of silicon germanium, germanium, or silicon germanium carbon.