JP2003044010A - Active matrix type display device and control device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type display device having a drawing speed capable of displaying a moving picture and being small in power consumption. SOLUTION: The active matrix type display device is switched by a selector 27 between the moving picture mode in which a data processing part 21 processes a video signal inputted at any time by a predetermined operation and displays the signal at any time, and the still picture mode in which a video signal is displayed based on video signals stored in a frame memory 25. Then, the display quality is improved without unsightly display at the time of switching between the modes by making the timing for switching from a still picture to a moving picture differ from that for switching from a moving picture to a still picture.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for switching and displaying a moving image mode in which an image signal input at any time is displayed and a still image mode in which an image signal stored in a frame memory is displayed.

[0002]

2. Description of the Related Art With the spread of personal digital assistants (PDAs) such as mobile phones and notebook computers in recent years, liquid crystal display devices (LCD) and electroluminescence (EL) display devices have been used as display devices with low power consumption. A display device is used.

FIG. 4 shows an active matrix type LCD as an example of a conventional display device. The active matrix display device is configured by connecting a control circuit 200 to the liquid crystal panel 100.

In the liquid crystal panel 100, liquid crystal is sealed between a first substrate on which a plurality of pixel electrodes 1 are formed and a second substrate on which one common electrode 10 facing the plurality of pixel electrodes is formed. It becomes. A plurality of pixel electrodes 1 on the first substrate,
Switching elements 2 made of, for example, thin film transistors (TFTs) are arranged in a matrix corresponding to the respective pixel electrodes 1. The gate lines 3 are arranged in the row direction and the data lines 4 are arranged in the column direction corresponding to the matrix of the pixel electrodes 1. Each pixel TFT2
The gate is connected to the gate line 3 and the drain is connected to the data line 4. The gate line 3 is connected to a gate line shift register 5 arranged around the display area. The data line 4 is connected to the data bus line 7 via the data line selection TFT 6, and the gate of the data line selection TFT 6 is connected to the output of the data line shift register 8. Data line selection T
The FT 6 and the data line shift register 8 are sequentially connected to the data line 4
To form a data line driver for supplying a data signal. In each pixel, an auxiliary capacitor 9 is arranged in parallel with the liquid crystal capacitor to hold the pixel voltage.

The control circuit 200 includes a data processing unit 21, C
PU interface 22, timing controller 2
3. It has a digital-analog converter (DAC) 24. When the video signal is an analog signal, the data processing unit 21 first samples the video signal at an appropriate timing, converts it into a digital signal, adjusts brightness and contrast, and applies gamma correction. Then, an optimum signal is created for the liquid crystal panel 100. The CPU interface 22 receives a command (command) of a CPU (not shown) that controls a device including an LCD such as a PDA or a mobile phone, and transmits a control signal to each unit according to the command. The timing controller 23 outputs various timing signals to the liquid crystal panel 100 based on the vertical start signal and the horizontal synchronizing signal extracted from the video signal. The DAC 24 converts the RGB digital data output by the data processing unit into a voltage optimum for the pixel voltage of the liquid crystal panel 100, and outputs the voltage.

Next, the operation of the active matrix LCD will be described together with the drive control signal. 5 and 6 are timing charts showing some timing signals. The vertical synchronization signal Vsync is a clock that is output high once at the start of each vertical synchronization period, and indicates the start of a frame period. The vertical start signal STV is input to the gate line shift register 5. Gate line shift register 5
Is a shift register, which starts its operation in response to the vertical start signal STV. The gate line clock CKG is input to the gate line shift register 5, the shift register is switched next for each gate line clock CKG, and the gate signal is sequentially supplied to the gate line 3. The half cycle of the gate line clock CKG corresponds to the horizontal synchronization period. All the pixel TFTs 2 connected to the gate line 3 to which the gate signal is supplied are turned on. The horizontal start signal STH is the gate line clock CKG
It is input to the data line shift register 8 of the data line driver with a clock slightly delayed by a double cycle. The data line shift register 8 receives the horizontal start signal STH and starts its operation. The data line clock CKD is input to the data line shift register 8, the shift register is switched next for each data line clock CKD, and the data line selection TFT 6 is selected.
To sequentially supply the data line selection signal. The data line selection TFT 6 to which the data line selection signal is supplied is turned on, and the data signal DATA is supplied to the pixel electrode 1 from the data bus line 7 via the data line 4 and the pixel TFT 2. As shown in the figure, there may be a case where a plurality of data bus lines 7 are provided and the same gate signal is input to the corresponding data line selection TFTs 6 to simultaneously apply the pixel voltage to the plurality of pixel electrodes 1. When the data line shift register 8 finishes selecting all the data lines 4, the gate line clock CKG is returned again.
Is input and the next gate line 3 is selected. Similarly, when the gate line shift register 5 finishes selecting all the gate lines 3, one screen is finished to be displayed. There is a horizontal blanking period during which data is not input for a certain period of time each time data for one row, for example, data for 176 pixels is written. Also, every time data is written to all pixels, for example 220 lines, a fixed period (about several horizontal periods)
There is a vertical blank period in which no data is input. The next vertical synchronizing signal Vsync is input during the vertical blanking period, the next frame is started, and the above operation is repeated from the beginning.

By the way, in a PDA such as a mobile phone, it is important to reduce power consumption in order to secure an operating time. Therefore, in a mobile phone or the like, a display device is often used, which is equipped with a frame memory having a capacity capable of storing one screen of video data and displays the data stored in the frame memory. FIG. 7 shows a display device equipped with a frame memory. The same numbers are given to the same components as those of the display device shown in FIG. 4, and detailed description thereof will be omitted. The frame memory 25 is an SRAM that receives digital image data of all pixels of the liquid crystal panel 100 via the CPU interface 22 and holds the digital image data. The video data stored in the frame memory 25 is the DAC 24
Is converted into a pixel voltage by and is supplied to each pixel electrode.

When the video data stored in the frame memory 25 is displayed, a timing signal such as a vertical synchronizing signal Vsync is not supplied from the outside, so it is necessary to create a timing signal. The oscillator 26 creates a basic clock and supplies it to the timing controller 23. The timing controller 23 multiplies the basic clock to create the data line clock CKD. By counting the basic clock with the counter in the timing controller,
Data line clock CKD A pulse is generated at a rate of once every predetermined number, and the horizontal start signal STH and the gate line clock C are generated.
Create KG, etc. Then, the basic clock is counted by another counter to generate the vertical start signal STV and the like.

[0009]

The display device having the frame memory 25 is advantageous in that it consumes less power because it does not need to input display data from the outside. However, since it is necessary to temporarily store the video data in the frame memory 25 and this storage takes time, the drawing speed is not sufficient to display a moving image.

Therefore, an object of the present invention is to provide a display device which can display a moving image and consumes less power.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and includes a plurality of gate lines, a plurality of data lines intersecting the gate lines, and an intersection of the gate lines and the data lines. A switching element to be arranged and a plurality of pixel electrodes connected to each of the switching elements are provided, and a video signal is supplied from a data line to all the pixel electrodes for each frame period, and the pixel electrodes and the common electrode are connected. In an active matrix type display device that performs display according to a pixel voltage that occurs between them, a moving image mode in which display is performed at any time according to the output of a data processing unit that performs a predetermined process on an input video signal, An active matrix type display device for switching and displaying a still image mode in which display is performed according to the output of a memory holding a video signal, and a control device therefor.

Further, the switching timing from the still image mode to the moving image mode and the switching timing from the moving image mode to the still image mode are different.

Regarding the timing of switching from the still image mode to the moving image mode, when a still / moving switching signal for switching the still image mode to the moving image mode is received in a certain frame period, the still image mode is continued until the frame period ends. Then, it is time to switch to the moving image mode from the next frame period.

Regarding the switching timing from the moving image mode to the still image mode, when a motion / switching switching signal for switching from the moving image mode to the still image mode is received in a certain frame period, the pixel supplying the pixel voltage at that time is received. The video signal is read from the corresponding memory address, and the timing immediately switches to the still image mode.

[0015]

1 shows a display device according to an embodiment of the present invention. The same numbers are given to the same configurations as the conventional ones, and the description is omitted. Liquid crystal panel 10 of the present embodiment
0 is exactly the same as the conventional one. Control circuit 20 of the present embodiment
0, the data processing unit 21 and the frame memory 25
Is provided, and a selector 27 for selecting and switching between these outputs is provided, which is different from the conventional one in that a moving image mode and a still image mode are switched and displayed. In the moving image mode, the data processing unit 21 adjusts the brightness and contrast of the input video signal at any time to perform gamma correction, and at any time creates and outputs an optimum signal to the liquid crystal panel 100. It is displayed accordingly. In still image mode,
Display is performed according to the video signal stored in the frame memory.

In the present embodiment, when displaying a moving image, a moving image mode with a high drawing speed, or a still image mode with a low drawing speed but low power consumption is normally displayed by switching between the moving image mode and the user's image. A display device with less power consumption can be provided without impairing convenience. For example, a CPU that normally displays in a still image mode and controls a PDA or a mobile phone equipped with a display device when a moving image signal is received or a user performs a key operation.
Is set to output a switching signal for switching from the still image mode to the moving image mode, and after the moving image display is ended in the moving image mode, or after a certain period of time has passed since the user ended the key operation, the CPU is stopped again. Set to output a switching signal for switching to the image mode. The switching signal from the CPU is output to the timing controller 23 via the CPU interface 22, and the timing controller 23 switches the selector 27 based on this. As a result, the output from the data processing unit 21 and the output from the frame memory 25 are switched, and the moving image mode and the still image mode are switched.

In any mode, during the operation mode, the display operation is performed in exactly the same manner as in the conventional case by the timing signals shown in FIGS. However, in the moving image mode, each timing signal is an external timing signal created using a clock extracted from an externally input video signal, and in the still image mode, it is output from the oscillator 26 connected to the timing controller 23. An internal timing signal created based on the basic clock is used. Although these timing signals are essentially similar signals, in the present specification, the timing signal extracted from the external signal is the external timing signal, and the built-in oscillator 26
In some cases, the timing signal created from the output of the above is distinguished as an internal timing signal. For example, also in the vertical sync signal Vsync, the one extracted from the external signal may be described as an external vertical sync signal, and the one based on the output of the oscillator 26 may be distinguished as the internal vertical sync signal.

The display device according to the present embodiment can be basically operated in the same manner as the conventional one, but further ingenuity is required when switching the operation mode. Because the external timing signal and the internal timing signal are created independently of each other, the external vertical synchronizing signal and the internal vertical synchronizing signal are not synchronized at all. A switching signal for mode switching is input from the CPU of the device through the CPU interface, and this command is also issued irrespective of both timing signals.

First, a first embodiment relating to mode switching will be described. In the first embodiment, the horizontal counter and the vertical counter of the timing controller are forcibly reset when the mode switching signal is input, and the display is started from the first row and the first column in the immediately switched mode. Specifically, when the mode switching signal is input, the timing controller 23 outputs the vertical start signal STV and the horizontal start signal STH to operate the shift register from the beginning. In this case, the timing controller 23
Is the gate line clock CKG and the data line clock CKD
It has a built-in counter that counts and, and knows the pixel voltage of which row and column the pixel voltage is supplied to, but it is necessary to reset this counter.

However, this first embodiment has the following problems. Mode switching signal is vertical sync signal Vs
Since it is not synchronized with ync, it is mostly input during the frame period. However, during the frame period,
The gate line shift register 5 and the data line shift register 8 have already started to operate. Now, it is assumed that a pixel voltage is supplied to the pixel electrodes in the nth row and the mth column. Therefore, when the mode switching signal is input, the pixel is forcibly reset and the pixel voltage is supplied again from the first row and the first column, but the shift register selects the first row and the first column and the nth row and the m + 1th column at the same time. Becomes As a result, in the frame in which the mode is switched, the second line, the n + 1th line, the third line and the n + 2th line are simultaneously selected, and the same image is displayed on the upper and lower parts of the screen, which is unsightly. .

Next, a more excellent second embodiment relating to mode switching will be described. First, switching from the moving image mode to the still image mode will be described. FIG. 2 is a timing chart when switching from the moving image mode to the still image mode. As described above, when displaying in the moving image mode, it operates based on the external timing signal input from the outside. The external timing signal is
If the video signal is digital, it is input as the timing signal itself, and the video signal is NTSC or PAL.
In the case of an analog signal such as the above, it is extracted from the video signal, created, and input. Although it may be extracted inside the control circuit 200, it is generically called an external timing signal here. Now, suppose that a switching signal for switching from the moving image mode to the still image mode is received during a certain frame period (particularly, it may be referred to as a motion / static switching signal because of switching from the moving image mode to the still image mode). The vertical counter incorporated in the timing controller is reset by the vertical start signal STV and counts the gate clock, and the horizontal counter is reset by the horizontal start signal STH and counts the data line clock. It is a count value (n, m).
Therefore, this count value indicates the coordinates of the pixel that is supplying the pixel voltage at that time. Therefore, if the video signal is read from the address of the frame memory 25 corresponding to this count value, the video signal corresponding to the next pixel electrode can be read from the frame memory 25. Therefore, when the motion / static switching signal is input to the timing controller 23 via the CPU interface 22, the timing controller 23 is based on the basic clock output from the oscillator 26 without resetting the count values of the vertical counter and the horizontal counter. The output of the internal timing signal is started, the selector 27 is switched to select the frame memory 25, and the still image mode is immediately switched. The video signal from the corresponding address of the frame memory 25 is supplied to the next pixel electrode. By switching in this way, two gate lines are not selected at the same time, so that the display is not unsightly when switching modes.

Here, the data clock (basic clock) of the external timing signal and the basic clock output from the oscillator 26 are not synchronized, but no problem occurs. This is because the counter incorporated in the timing controller is not reset, so that the operation is stopped for about one cycle of the basic clock when the mode is switched.
In this embodiment, the timing controller 23
Is not output because a clock having a period less than one cycle of the basic clock will cause a malfunction. Therefore, when switching modes, the operation must be stopped for at least one cycle of the basic clock for the period of Δt shown in the figure. become.

Next, switching from the still image mode to the moving image mode will be described. FIG. 3 is a timing chart when switching from the still image mode to the moving image mode. When a switching signal from the still image mode to the moving image mode (which may be referred to as a static / moving switching signal in particular) is received in a certain frame period, the operation is not particularly switched, and the oscillator 26 is operated until the frame period ends. The operation by the internal timing signal based on the output of the, and the still image mode are continued. And
The next internal vertical sync signal is not output. After that, period Δt
After the elapse of two, the external vertical synchronizing signal is input, and therefore, from the next frame period after the external vertical synchronizing signal, the mode is switched to the moving image mode based on the external timing signal. By switching in this way, the mode continues until one frame period is completed, so that two gate lines are not selected at the same time, and an unsightly display does not occur when switching modes.

Period between still image mode and moving image mode Δ
At t2, it is not necessary to supply a clock. But,
Since it is difficult to stably supply each external timing signal at exactly the same time that the external vertical sync signal is input, the external timing signal is output several basic clocks ahead of the external vertical sync signal being input. You should start doing it. In the period Δt2, even if the timing signal is supplied, the vertical start signal STV and the horizontal start signal STH
Is not supplied, the shift registers 5 and 8 do not start operating. Of course, the external timing signal may be switched to immediately after the frame period of the still image mode ends.

In the still picture mode, the control circuit 200 closes the supply of the video signal and the supply of the timing signal, whereas in the moving picture mode, the video signal is supplied from the outside and the display operation is synchronized with this. I have to do it. Therefore, as described above, in the second embodiment, the switching timing from the still image mode to the moving image mode and the switching timing from the moving image mode to the still image mode are different, and the modes are optimized by the respective procedures. The display quality can be further improved by switching.

In the above embodiment, the liquid crystal display device has been described as an example of the active matrix type display device, but the present invention is not limited to this, and the same applies to an EL display device, an LED display device, a vacuum fluorescent display device and the like. be able to.

[0027]

【The invention's effect】

As detailed above, according to the present invention,
Since the moving image mode in which the drawing speed is fast according to the output of the data processing unit 21 at any time and the still image mode with low power consumption in accordance with the output of the memory 25 are switched and displayed, the power consumption is low. In addition, the display device can have high display quality.

Furthermore, since the switching timing from the still image mode to the moving image mode and the switching timing from the moving image mode to the still image mode are different, the mode switching is performed by the procedure optimized for each switching, and the display quality is further improved. Can be improved.

Further, a data processing unit 21 which performs a predetermined process on an input video signal and outputs it at any time, a memory 25 which holds a video signal of a plurality of pixels, and a switch which switches between the data processing unit and the memory. If it is a control device for an active matrix type display device having the means, the display panel 100 has the same configuration as the conventional one, and the control device 2
The present invention can be implemented at a lower cost by changing only the configuration of No. 00.

[Brief description of drawings]

FIG. 1 is a diagram showing an active matrix type display device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining switching from the moving image mode to the still image mode of the present invention.

FIG. 3 is a timing chart for explaining switching from the still image mode to the moving image mode according to the present invention.

FIG. 4 is a diagram showing a conventional active matrix type display device.

FIG. 5 is a timing chart for explaining the operation of the active matrix display device.

FIG. 6 is a timing chart for explaining the operation of the active matrix display device.

FIG. 7 is a diagram showing a conventional active matrix type display device.

[Explanation of symbols]

1: Pixel electrode 2: Pixel switching element (TFT) 3: Gate line 4: Data line 5: Shift register 6: Data line selection switching element (TFT) 7: Data bus line 8: Shift register 9: Auxiliary capacitor 10: Common Electrode 21: Data processing unit 22: CPU interface 23: Timing controller 24: Digital-analog converter 25: Frame memory 26: Oscillator 27: Switching means (selector)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI Theme Coat (reference) G09G 3/20 660 G09G 3/20 660U 660V (72) Inventor Kobayashi Mitsugu Keihanhondori 2-chome, Moriguchi City, Osaka Prefecture 5-5 Sanyo Electric Co., Ltd. (72) Inventor Makoto Fujioka 2-5-5 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. F-term (reference) 2H093 NC13 NC15 NC16 NC29 ND32 ND39 5C006 AA01 AA02 AF02 AF03 AF04 AF44 AF45 AF51 AF53 AF61 AF69 AF71 BB16 BF02 BF16 FA12 FA16 FA47 5C080 AA10 BB05 DD26 EE19 FF11 JJ02 JJ04

Claims (8)

[Claims] 1. A plurality of gate lines, a plurality of data lines intersecting with the gate lines, a switching element disposed at an intersection of the gate line and the data line, and a plurality of pixels connected to each of the switching elements. And an electrode,
An active matrix type display device that supplies a video signal from the data line to all the pixel electrodes every one frame period and performs display according to a pixel voltage generated between the pixel electrode and the common electrode. A moving image mode in which display is performed at any time according to the output of a data processing unit that performs predetermined processing on the image signal, and a still image mode in which display is performed according to the output of a memory that holds the image signals of a plurality of pixels,
An active matrix type display device characterized by switching and displaying. 2. The active matrix display device according to claim 1, wherein the switching timing from the still image mode to the moving image mode and the switching timing from the moving image mode to the still image mode are different. 3. When a static / moving switching signal for switching a still image mode to a moving image mode is received in a certain frame period, the still image mode is continued until the frame period ends, and the moving image mode is changed from the next frame period. The active matrix display device according to claim 1, wherein 4. A video signal is read from an address of the memory corresponding to a pixel supplying a pixel voltage at that time when a motion switching signal for switching the video mode to the still image mode is received in a certain frame period, and immediately The active matrix display device according to claim 1, wherein the active matrix display device is switched to a still image mode. 5. A plurality of gate lines, a plurality of data lines intersecting the gate lines, a switching element arranged at an intersection of the gate line and the data line, and a plurality of pixels connected to each of the switching elements. And an electrode,
Control for supplying an image signal from the data line to all the pixel electrodes every one frame period to control an active matrix display device that performs display according to a pixel voltage generated between the pixel electrode and the common electrode In the device, there are provided a data processing unit for performing a predetermined process on an input video signal at any time and outputting the data at any time, a memory for holding a video signal of a plurality of pixels, and a switching unit for switching between the data processing unit and the memory. A control device for an active matrix display device, which comprises: 6. The method according to claim 5, wherein the timing of switching from the output of the data processing unit to the output of the memory is different from the timing of switching from the output of the memory to the output of the data processing unit. Control device for active matrix display device. 7. When a static switching signal for switching from the memory to the data processing unit is received in a certain frame period, the memory is continuously selected until the frame period ends, and the data processing starts in the next frame period. 6. The control device for the active matrix type display device according to claim 5, wherein the control unit is switched to another unit. 8. A video signal is read from an address of the memory corresponding to a pixel supplying a pixel voltage at that time when a motion switching signal for switching to the memory is received from the data processing unit in a certain frame period, The control device of the active matrix display device according to claim 5, wherein the control unit is switched to the data processing unit immediately.