JP2002169499A - Driving method of display panel and driving controller of display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further reduce power consumption of a display device. SOLUTION: Operations of driving circuits which drive pixels of a display panel for every prescribed frame are stopped while displaying a still image or during a power save mode. The circuits include a vertical direction driver 200 which successively selects pixels and a horizontal direction driver 300 which successively supplies display data to the pixels. For example, a vertical start pulse STV is thinned and the outputting of vertical clocks CKV is stopped during a thinned frame interval. By employing such a simple method, the operations of the driving circuits are stopped so that power consumption is reduced. Especially in the case of displaying a still picture, no adverse effect is given to the display quality by periodically stopping the operation of the drivers, resulting in reduction of power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a driving method and a driving device which can reduce the power consumption of a display panel.

[0002]

2. Description of the Related Art Flat displays such as a liquid crystal display (LCD) and an organic electroluminescence (organic EL) display have features such as a thin and compact device and low power consumption. It is used as a display device of a portable device. In these display devices, a plurality of pixels are provided on a substrate, and various images can be displayed by sequentially selecting each pixel for each frame and supplying data to be displayed.

[0003]

By the way, low power consumption is particularly strongly required for portable equipment and the like on which such a flat display is mounted.
Therefore, it is necessary to suppress the power consumption of the display. For example, for LCDs currently used in mobile phones and the like, the backlight is turned off if there is no key operation for a certain period of time. The display is stopped, and the transflective LCD is devised to shift to a reflection mode in which display is performed using only external light.

However, at present, the power consumption of the display panel itself is the same as that in the normal mode even when the device is in the low power consumption mode, and no special power saving is achieved. In order to cope with further reduction in power consumption in the future, it is necessary to devise a method of driving the display panel.

An object of the present invention is to propose a driving method for realizing power saving of a display panel.

[0006]

In order to achieve the above object, the present invention provides a method of driving a display panel having a plurality of pixels arranged in accordance with an image to be displayed or a power consumption mode of the apparatus. The operation of a drive circuit for sequentially selecting each of the plurality of pixels of the display panel for each frame and supplying display data is stopped.

Another feature of the present invention is a method of driving a self-luminous display panel including a plurality of self-luminous pixels each including a light-emitting layer between a first electrode and a second electrode.
According to an image to be displayed or a power consumption mode of the apparatus, the operation of a drive circuit for sequentially selecting each of the plurality of pixels of the display panel for each frame and supplying display data is stopped. I do.

[0008] By stopping the operation of the drive circuit for driving the display panel in accordance with the display image or the power consumption mode, it is possible to reduce the power that is unnecessarily consumed in the drive circuit of the display panel.

Another feature of the present invention is that, in the method of driving a display panel, when the display image is a still image or in a power saving mode or both, the display panel is driven every predetermined frame period. This is to stop the operation of the drive circuit.

In the case of displaying a still image, it is normal that there is no change in the image data to be displayed in one frame and the subsequent frame. Therefore, in such a display, the driving circuit is stopped every predetermined frame, for example, every other frame, so that the display data is maintained in each pixel even if the update of the display data in each pixel is omitted for that frame. If there is, there is no problem in display. By stopping the driving circuit, it is possible to reduce the power consumption by that amount. For example, when a self-luminous element having a diode configuration such as an organic EL element in an organic EL display is used for each pixel, the amount of retained charge required to operate this diode until the next pixel is selected is compared. Target small. Therefore, it is easy to store the necessary charges in each pixel for a sufficiently long period without lowering the aperture ratio of the pixel. Therefore, for example, even if the operation of the drive circuit is stopped for each frame and the display data writing to the pixels is thinned out for each frame, there is no need to add a special configuration.
The display during the frame period can be continued, and the power consumption of the display panel can be reduced.

The power consumption mode is, for example, a power consumption saving mode (power saving mode). In such a saving mode, if the operation of the driving circuit is stopped at a predetermined cycle, the driving of the display panel is ensured. Power consumption can be reduced. In particular, in the case of a display panel such as the above-mentioned organic EL display, which has sufficient charge retention for display in each pixel, the writing operation to each pixel can be stopped without adversely affecting display quality. it can.
Furthermore, in the power saving mode, a still image is often displayed. In such a case, the display quality can be maintained as described above even if the driving circuit is periodically stopped.

Another feature of the present invention is that in the method of driving a display panel, the drive circuit sequentially selects the plurality of pixels for each frame, and a display for supplying display data to the selected pixels. With a data supply circuit, depending on the image to be displayed or the power consumption mode of the device,
The operation of one or both of the selection circuit and the display data supply circuit is stopped.

For example, in the case of an active matrix type display panel having a switching element in each pixel,
A vertical driving circuit or the like that sequentially turns on each pixel switch of each row corresponds to this. If the operation of the vertical driving circuit is stopped as necessary, each pixel is not selected during that period. That is, the power consumption is reduced by the amount of time when the operation of the selection circuit is stopped, and each pixel switch is not inadvertently selected, so that the charge corresponding to the display content stored in each pixel is lost. Can be prevented, and the display content can be maintained.

The display data supply circuit corresponds to, for example, a horizontal drive circuit for supplying display data to each selected pixel in the case of the active matrix type display panel. If the operation of the horizontal driving circuit is stopped, no display data is output during that period, and it is possible to prevent the display data in each pixel from changing, and the power consumption due to stopping the driving circuit is reduced. In addition to the reduction, it is possible to prevent a change in display data at each pixel.

Further, if the operation of both the selection circuit and the display data supply circuit is stopped, the power consumption can be further reduced, and each pixel is not selected and the display data does not change. The display content of each pixel can be maintained more reliably during the suspension period.

According to the present invention, there is provided a drive control apparatus for a display panel including a plurality of pixels arranged therein, wherein a thinning circuit for thinning a vertical start pulse serving as a start reference of one frame at a predetermined frame cycle, A clock used by the circuit to sequentially select each pixel of the display panel,
A clock stop circuit for stopping the output during the thinned frame period, wherein the thinning circuit and the clock stop circuit periodically operate the drive circuit in accordance with the image to be displayed or the power consumption mode of the apparatus. It is characterized by being stopped at.

According to the present invention, with such a simple configuration, the power consumption of the device can be reduced while maintaining the display quality.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

In the following description, as a display panel, an organic EL element which is a self-luminous element for each pixel, and a switch (thin film transistor: TFT) for driving this element
And the active matrix type organic EL display panel provided with.

[First Embodiment] FIG. 1 conceptually shows a pixel portion and a part of a driving circuit of an organic EL panel. The display panel includes a plurality of gate lines 110 extending in the row direction.
In addition, a plurality of data lines 120 and power supply lines 130 extending in the column direction are formed, and pixels are respectively formed in regions defined by the gate lines 110, the data lines 120, and the power supply lines 130. One pixel includes an organic EL element 10, a switching TFT 20, and an EL driving TF.
T22, a storage capacitor SC is provided. TFT for switch
Reference numeral 20 denotes a gate connected to a corresponding gate line 110, which in this example is constituted by an n-ch TFT. The drain of the n-ch TFT is connected to the data line 1
The source is connected to the storage capacitor SC. The gate of the EL driving TFT 22 is connected to the drain of the switching TFT 20 and the storage capacitor SC. In this example, the EL driving TFT 22 is formed of a p-ch TFT. The source of the p-ch TFT is connected to an EL driving power supply Vdd common to each pixel, and the drain is connected to the anode of the organic EL element 10.

V-system driver (vertical driver) 200
Is a V-system shift register 210 provided with the number of stages corresponding to the number of gate lines, and data output from each shift register 210 as a selection signal to each gate line 1.
10 is provided. The V-system shift register 210 receives the vertical start pulse STV and the vertical clock CKV as inputs, sequentially transfers the start pulse STV in the V direction according to the clock CKV, and outputs data serving as a selection signal to the corresponding buffer 220.

H-system driver (horizontal driver) 3
Reference numeral 00 includes an H-system shift register 310 provided with a number of stages corresponding to the number of pixels in the horizontal direction, and a sample-and-hold circuit 320 for outputting video data to the corresponding data line 120 based on the output from each H-system shift register 310. The H-system shift register 310 receives the horizontal start pulse STH and the horizontal clock CKH as inputs, and sequentially transfers the start pulse STH in the H direction according to the clock CKH. The sample-and-hold circuit 320 outputs a video signal line 330 based on an output signal from each shift register 310.
And the corresponding data line 120 are connected to selectively supply video data to the data line 120, and substantially sample and hold the video data.

Here, assuming that the display panel is capable of displaying NTSC video signals, the V-system shift register 21
0 operates at 15.734 kHz, and the H-system shift register 310 operates at 2-3 MHz. In the data line 120, the data is normally updated once per frame, that is, at a cycle of 60 Hz. However, if the display image is a still image, in many cases, there is no difference in display data between consecutive frames, and it is unlikely to cause a problem that the display content is specially lost even if the display is thinned. Therefore, in the present embodiment, when such a still image is displayed, the operation of the drive circuit is stopped for each predetermined frame, and the data rewriting for each pixel is stopped.

FIG. 2 shows an outline of an example of the display panel driving method according to the present embodiment. Here, assuming that the vertical start pulse STV in the normal state is a reference vertical start pulse STV1, this is output at the start of one vertical period, that is, once per frame, as shown in FIG. 2A. . At this time, the vertical clock CKV1 shown in FIG.
One frame period determined by TV1 is generated as a clock having a period divided according to the number of gate lines (the number of scanning lines) of the display panel, and a vertical clock CKV
(FIG. 2B) is transferred as a transfer clock.

When it is detected that the display data is a still image, the reference vertical start pulse STV1 is thinned out for every predetermined frame as shown in FIG. Output to 210. As shown in FIG. 2D, the output of the vertical clock CKV2 is stopped during the frame period in which the reference vertical start pulse STV1 is thinned out, and during the remaining frame period, the output of the vertical clock CKV2 has the same period as the normal vertical clock CKV1. This is set and output to the V-system shift register 210 as a transfer clock. FIG.
The vertical start pulse STV2 shown in FIG.
By supplying the vertical clock CKV2 shown in (d),
The V-system driver 200 operates every other frame.

Here, since the display data at each pixel is not rewritten by stopping the driver 200, the display content is maintained. The driving method according to the present invention comprises an LCD
Is also applicable. However, it is particularly suitable for a display panel using a self-luminous organic EL element for a pixel as in this embodiment. In the LCD, a storage capacitor SC provided for each pixel is provided with the capacitor SC for the pixel switch TFT.
This is provided in order to maintain a liquid crystal capacitor having a large capacitance value electrically connected in parallel with the liquid crystal display device for a sufficiently long time. Therefore, the larger the area of the storage capacitor SC, the better, but there is a trade-off relationship with the pixel aperture ratio. Therefore, a very large storage capacitor SC cannot be formed. However, in the case of an organic EL element, in order to maintain the light emission of the element, an EL driving TFT is required.
It is sufficient that the gate voltage of the storage capacitor 22 can be maintained, and the storage capacitor SC need not be so large. Therefore, the display content can be sufficiently maintained for a plurality of frames, and the deterioration of the display quality due to thinning out the update interval of the display data is small.
Therefore, it is possible to stop the operation of the driver at a predetermined cycle without lowering the display quality, and to reduce the power consumption. In addition, since light from the self-luminous element spreads out from the pixels to a considerable extent, high luminance display is possible even if the aperture area is substantially smaller than that of an LCD having the same pixel size, for example. Therefore, a sufficiently large storage capacity SC
Can be secured in each pixel, and a signal corresponding to the display data can be held for a long period of time.

Further, in the driving method of the present invention, the driver is periodically stopped. Therefore, when the present invention is applied to an LCD which is driven by an alternating current, a device for inverting a driving signal between driver operation frames before and after a driver stop frame is used. Required. However, in a display panel having a self-luminous organic EL element in each pixel, the element is originally driven by a direct current, so that it is only necessary to periodically stop the driver. It is particularly suitable for a DC driven display panel such as an organic EL element.

FIG. 3 shows an example of a driver stop control circuit 400 which employs a panel as a drive control device to realize the operation as shown in FIG. FIG. 4 shows the operation of the circuit 400 of FIG. Here, based on various control signals for display, for example, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the dot clock Dotclk, the vertical start pulse STV, the horizontal start pulse STH, the vertical clock CKV, the horizontal clock CKH, etc. It is created by the timing controller circuit. The driver stop control circuit 400 can be configured as a part of the timing controller circuit. Of course, it may be constituted by an independent circuit different from the timing controller circuit.

The driver stop control circuit 400 generates a vertical start pulse STV2 and a vertical clock CKV2 from the reference vertical start pulse STV1 and the vertical clock CKV1 generated in the timing controller circuit. The (１ ／) frequency divider 410 is supplied with the signal shown in FIG.
The reference start pulse STV1 as shown in (a) is divided by 2 to obtain a divided output shown in FIG. 4 (b). AND gate 4
Reference numeral 12 denotes the divided output and the reference vertical start pulse ST
The logical product of V1 is taken. Therefore, the AND output is as shown in FIG.
As shown in (c), only when both the STV1 and the frequency-divided output are at the H level, the level becomes the H level.
TV2 is obtained. That is, the frequency divider 410 and the AND gate 412 function as a thinning circuit, and the vertical start pulse STV is subtracted for one frame.

The AND gate 414 takes the logical product of the frequency-divided output from the frequency divider 410 and the vertical clock CKV1 in FIG. The AND gate 414 functions as a circuit for stopping the output of the clock. As shown in FIG. 4E, the period during which the divided output is at the L level, that is, the frame period during which the reference vertical start pulse STV1 is thinned out, The vertical clock CKV2 having the same phase as the vertical clock CKV1 is obtained only when the clock output is fixed at the L level and the frequency divided output is at the H level.

The switching control circuit 450 determines whether the image to be displayed is a still image,
And STV1 are switched and the clocks CKV2 and CCK2 are output.
And KV1.

When the formed vertical start pulse STV2 and vertical clock CKV2 are supplied to the shift register 210 of the V driver 200 under the control of the switching control circuit 450, the start pulse transfer operation in the shift register 210 is performed every other frame. During the period, no selection signal is output to each gate line 110 of the display panel. Therefore, the switching TFT 20 of the pixel is kept off, the light emission of each organic EL element 10 is maintained according to the display data stored in the storage capacitor SC of each pixel, and the maximum power consumption reduction effect by stopping the driver is obtained. be able to.

When the apparatus is to display a moving image, the switching control circuit 450 switches a switch to switch the reference vertical start pulse S generated by the timing controller circuit.
TV1 and vertical clock CKV1 are connected to V-system driver 200.
, And selection of display pixels and display data writing are performed in each frame as usual.

In the above description, the V-system driver 200 is periodically stopped when the displayed image is a still image. However, the present invention is not limited to the case where the displayed image is a still image. Alternatively, the driver may be periodically stopped by the switching control circuit 450 irrespective of a moving image or a still image.
When frames are thinned out for a moving image, the movement becomes awkward, but in the power saving mode, for the device user, the movement of the displayed moving image is rather rough,
It is often emphasized that the use time is extended due to the power saving effect, and in this case, it is meaningful to perform the thinning process on the moving image as well. Further, only in the power saving mode and when the display image is a still image, or when the display image is a still image, the driver stop control may be performed regardless of the power saving mode.

In the above description, when driver stop control is performed, the switching control of the switching control circuit 450 switches the vertical start pulse output from the circuit 400 from STV1 to STV2 and changes the vertical clock output from CKV1 to CKV2. Switching. However, the present invention is not limited to this configuration. For example, a configuration may be adopted in which the STV1 is supplied to the frequency divider 410 and operated only when the driver stop control is performed.

Further, the first embodiment is not limited to the configuration in which the V-system driver 200 is stopped. In the H-system driver 300, the transfer operation of the horizontal start pulse STH in the H-system shift register 310 is stopped to display the display data. The output to each data line 120 may be stopped. Such stop control of the H-system driver 300 can also be realized by dividing the horizontal start pulse STH by a stop control circuit equivalent to the above-described FIG. 3 and stopping the output of the horizontal clock CKH in the thinned frame period. .

Further, it is also possible to adopt a configuration in which the H-system driver 300 is stopped at the same time when the V-system driver 200 is stopped. If both drivers are stopped, the power consumption reduction effect is further enhanced, and for each pixel, the pixel switch is not turned on and no display data is transmitted, so that the display data held in each pixel is lost. Rewriting can be reliably prevented. Therefore, it is possible to more reliably maintain the display content in the previous frame.

[Second Embodiment] In the second embodiment, a driving method for thinning out and displaying a frame is employed similarly to the first embodiment, and a reverse bias is applied to each organic EL element, so that the consumption in the display panel is reduced. Further reduce power consumption. Hereinafter, description will be made with reference to FIGS.

In the display controller 500, the video signal processing unit 510 processes the video input and
0, the R, G, B display data, and the sync separation processing circuit 530 converts the vertical sync signal Vsync from the video input as shown in FIG. 6 (a) or the horizontal sync signal as shown in FIG. 6 (c). The signal Hsync is separated, a non-display period provided at the beginning of one horizontal period is detected, and a blanking pulse BLP corresponding to the period is generated (see FIG. 6B).

The vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync from the sync separation processing circuit 530 are supplied to a timing controller (T / C) circuit 550, and the T / C circuit 55
0 indicates the vertical start pulse STV, the horizontal start pulse STH, the vertical clock CKV, and the horizontal clock CKH based on these as described in the first embodiment.
Create When the display image is a still image or in the power save mode, the vertical start pulse STV2 and the vertical clock CKV2 generated by the driver stop control circuit 400 are set to the normal start pulse as in the first embodiment. The STV1 and the clock CKV1 are supplied to the display panel 100 instead of the clock CKV1. Various timing control signals for controlling V-system and H-system drivers for driving each pixel are created and supplied.

Further, in the second embodiment, the reverse bias control circuit 540 controls the cathode voltage of each organic EL element of the display panel using the blanking pulse BLP supplied from the synchronization separation processing circuit 530, Apply a reverse bias to the device. The reverse bias control circuit 540 operates by receiving the non-inversion and inversion signals of the Bunranking pulse BLP at the gate, and operates between the power supply VBS having a higher voltage than the power supply Vdd for driving the organic EL element and the power supply Vcd having a low voltage. It has n-ch transistors 542 and 544 provided between them.

The blanking pulse BLP is shown in FIG.
As shown in (1), only the non-display period of the 1H period is at the H level and the display period is maintained at the L level. Since the pulse BLP having such a polarity is applied, the transistor 542 is turned on and the transistor 544 is turned off during the non-display period, and the terminal Tout is connected to the power supply VBS having a higher voltage than the organic EL element power supply Vdd. Conversely, in the display period, the transistor 542 is turned off and the transistor 544 is turned on, so that the terminal Tout is connected to the power supply Vcd lower than the power supply Vdd. The terminal Tout is connected to each organic E of the display panel 100.
6 is connected to the common cathode of the L element.
A voltage as shown in (d) is applied to the cathode of each organic EL element. That is, between the anode and the cathode of the organic EL element, 1
A reverse bias is applied every non-display period of the H period.

Here, if a reverse bias is applied to the organic EL element, the voltage is not limited to the above-mentioned cathode VBS-anode Vdd. In the present embodiment, “application of a reverse bias” also includes short-circuiting the anode and the cathode. Further, a driving method in which a forward bias and a reverse bias are alternately applied a plurality of times in the non-display period may be adopted.

Unlike an LCD which drives the liquid crystal capacitance of each pixel by AC, an organic EL panel is formed between an anode and a cathode by supplying a DC current between the anode and the cathode of each EL element. The organic light emitting layer emits light. Since the DC drive is performed as described above, electric charges are accumulated between the anode and the cathode of the organic EL element, and even when no DC current is supplied, current flows due to the accumulated electric charges, and power may be consumed correspondingly. It is pointed out.

Therefore, in the second embodiment, during the non-display period, a reverse bias is applied between the anode and the cathode to discharge unnecessary charges accumulated between the anode and the cathode. The application of the reverse bias is not limited to every 1H period. However, if the application of the reverse bias is performed every 1H using the blanking pulse BLP, unnecessary charges are frequently discharged without separately creating a special timing signal. And unnecessary power consumption of the organic EL element can be reduced. In addition, applying a reverse bias to eliminate charge accumulation can contribute to extending the life of the organic EL element.

Here, the application of the reverse bias may be executed only during normal display (without stopping the driver). Further, as in the first embodiment, it may be executed when the display image is in the still image or power save mode. In this case, the reverse bias application is performed periodically (for example, 1H) during the driver operation frame period.
It is preferable to carry out each process. When the reverse bias is applied, the organic EL element is completely turned off, that is, black display is performed. Therefore, during the driver stop frame period as shown in FIG. 2 or FIG. If the accumulated charge is not sufficient, black display is performed during the driver stop frame period, and the display content is not maintained. Therefore, it is preferable that the application of the reverse bias is also stopped during the driver stop frame period.

[0047]

As described above, according to the present invention, the operation of the driving circuit is periodically stopped in the case of displaying a still image or in the power save mode, so that the consumption of the display device can be reduced with a simple configuration. The power can be reduced. In particular, when an organic EL element or the like is used for each pixel, each pixel has a high ability to hold display data. Therefore, even if the drive circuit is periodically stopped, the display data is displayed in accordance with the display data before the stop. Can be maintained. Therefore, the display can be maintained even when the driving circuit is stopped, and the power consumption of the display device can be reduced without lowering the display quality.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an organic EL panel according to Embodiment 1 of the present invention.

FIG. 2 is a timing chart illustrating a method for driving the display panel according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration example of a driver stop control circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing an operation of the driver stop control circuit of FIG. 3;

FIG. 5 is a diagram illustrating a configuration of an organic EL panel and a display controller according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation of the reverse bias control circuit of FIG. 5;

[Explanation of symbols]

Reference Signs List 10 organic EL element, 20 switching TFT, 22
EL drive TFT, 100 display panel, 110 gate line, 120 data line, 130 power supply line, 200 V system driver, 210 V system shift register, 220 buffer, 300 H system driver, 310
H-system shift register, 320 sample and hold circuit, video signal line 330, 400 driver stop control circuit, 410 divider, 412, 414 AND gate, 450 switching control circuit, 500 display controller,
510 video signal processing circuit, 530 synchronization separation processing circuit, 540 reverse bias control circuit, 550 timing controller circuit.

Claims (8)

[Claims] 1. A method of driving a display panel having a plurality of pixels arranged therein, wherein each of the plurality of pixels of the display panel is sequentially arranged for each frame in accordance with an image to be displayed or a power consumption mode of a device. A method for driving a display panel, comprising: stopping an operation of a drive circuit for selectively supplying display data. 2. A method for driving a self-luminous display panel including a plurality of self-luminous pixels each including a light-emitting layer between a first electrode and a second electrode, comprising the steps of: A method of driving a display panel, comprising: sequentially selecting each of the plurality of pixels of the display panel for each frame in accordance with a power consumption mode, and stopping an operation of a driving circuit for supplying display data. 3. The method of driving a display panel according to claim 2, wherein the self-luminous pixels include an organic electroluminescence element. 4. The display panel driving method according to claim 1, wherein the driving circuit includes a selection circuit that sequentially selects the plurality of pixels for each frame, and a selected pixel. A display data supply circuit for supplying display data to the display device, wherein the operation of one or both of the selection circuit and the display data supply circuit is stopped according to an image to be displayed or a power consumption mode of the device. Panel driving method. 5. The method for driving a display panel according to claim 1, wherein the operation of the driving circuit is stopped every predetermined frame period when the display image is a still image. Characteristic display panel driving method. 6. The display panel driving method according to claim 1, wherein the operation of the selection circuit is stopped every predetermined frame period when the display device is in a power saving mode. A method for driving a display panel, comprising: 7. A drive control apparatus for a display panel having a plurality of pixels arranged therein, wherein a thinning circuit for thinning out a vertical start pulse serving as a start reference of one frame at a predetermined frame cycle, and a drive circuit for driving the display panel. A clock stop circuit for stopping the output of a clock used for sequentially selecting each pixel during the thinned frame period. The thinning circuit and the clock according to an image to be displayed or a power consumption mode of the device. A drive control device for a display panel, wherein an operation of the drive circuit is periodically stopped by a stop circuit. 8. The drive control device for a display panel according to claim 7, wherein the pixel includes an organic electroluminescence element.