JP2003036699A - Memory device and test data setting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device in which a test data setting time can be shortened by write-in with one word unit and the degree of freedom of test data setting is high. SOLUTION: This device is provided with a copy data storing section 202 having copy data storing cell rows CW0, CW1 constitution of which same as that of memory cell rows of a memory cell section 200 in a cell array 100, in a test data setting mode, after data for copy for setting test data is written in each of copy data storing cell rows, data is read out simultaneously from the copy data storing cell row CW0 to a sense amplifier column 101, batch write-in processing is successively performed for a plurality of first desired cell rows in the memory cell section 200, also, data is read out simultaneously from the copy data storing cell row CW1 to a sense amplifier column 101, and batch write-in processing is successively performed for a plurality of second desired cell rows being different from the first desired cell row in the memory cell section 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device and a test data setting method, and more particularly to a memory device and a test data setting method capable of shortening a data writing time for a pass / fail judgment test.

[0002]

2. Description of the Related Art As the capacity of a memory increases, the test time for determining the quality is increased, and writing in units of one memory cell is a major factor in increasing the time. Shortening the test time is one of the important items for cost reduction, and the actual situation is that the test items are shortened by deleting the test items, but it is not preferable because it is difficult to maintain high quality. As a technique for reducing the test time, Japanese Patent Laid-Open No. 61-12
A technique for simultaneously writing the same data to a plurality of bits is disclosed in Japanese Patent No. 2998, and at present, as a development of this technique, a flash write function that realizes writing in units of one word is known.

FIG. 11 is a block diagram of a conventional memory device having a flash write function. Memory device
A 4 × 4 dynamic RAM is used for simplification of description, and the row address strobe RA is used in the normal operation mode.
Two address signals A0 and A1 at the falling edge of S
Row address decoder 603 selects one of the four memory cell word lines X0 to X3 based on the logical state of the column address strobe CAS, and the logical state of the two address signals A0 and A1 at the fall of the column address strobe CAS. The column address decoder 602 causes the Y switch 1
02, one of four pairs of digit lines D40T / D40N to D43T / D43N via the sense amplifier array 101.
Select a pair. In the cell array 600, a memory cell connected to one of the selected digit line pair and the selected word line is selected. In addition, the RAS / CAS circuit 6
If the sense amplifier row 101 is activated by the sense amplifier activation signal SE from 01 and the write enable signal WE is at the low level, the write drive circuit 108 is activated and the input data Din is written in the selected memory cell. If the write enable signal WE is at the high level, the selected cell is read. Cell array 600
Has a redundant cell portion for collectively replacing the memory cell row including the defective cell when the memory cell has a failure and does not operate normally. The redundant cell portion word line selection circuit 104 replaces the defective memory cell row. The use of the memory cell row including the defective cell is prohibited by the signal NRS and replaced with the cell row of the redundant cell portion. The replaced cell row of the redundant cell section is driven through the redundant cell section word line drive circuit 111.

FIG. 12 is a diagram showing the internal structure of the cell array 600 and the connection between the peripheral row address decoder 603, the redundant cell section word line drive circuit 111 and the sense amplifier column 101. The cell array 600 includes the memory cell unit 2
00 and a redundant cell unit 201. The memory cell section 200 has positive memory cells M01T, M03T, M10T, M12 connected to one of the memory cell word lines X0 to X3 and one of the positive digit lines D40T to D43T.
Inversion side memory cells M00N, M02N, M11N, M13N, M22 connected to T, M21T, M23T, M30T, M32T and one of the memory cell section word lines X0 to X3 and one of the inversion side digit lines D40N to D43N.
N, M24N, M31N, M33N are provided alternately in a checkered pattern. Similarly, the redundant cell unit 201 is
Positive side redundant cell R connected to one of the redundant cell section word lines RX0 and RX2 and one of the digit lines D40T to D43T.
01T, R03T, R10T, R12T and word line R
One of X0 and RX1 and the inversion side digit lines D40N to D4
Inversion side redundant cell R00N, R0 connected to one of the 3N
2N, R11N and R13N are alternately provided in a checkered pattern. The row address decoder 603 is a RAS
Row / column switching signal RCS from the / CAS circuit 601
Is at a high level, the memory cell word line X0 is decoded based on the combination of the address signals A0 and A1.
One of X3 to X3 is selected, and the memory cell unit 200 is driven through the buffer circuit whose input and output are in phase. The redundant cell section word line drive circuit 111 outputs the redundant word selection signals PRX0, PRX from the redundant cell section word line selection circuit 104.
It includes a buffer circuit which inputs RX1 and outputs it as an in-phase signal to the redundant cell section word lines RX0 and RX1, respectively. The sense amplifier row 101 has a sense amplifier activation signal S
Sense amplifiers SA0 to SA3 activated by E are included.

FIG. 13A shows a RAS / CAS circuit 60.
13 is a diagram showing the configuration of No. 1 and FIG. 13B is a diagram showing the configuration of the column address decoder 602. RAS / C
In the AS circuit 601, the one-shot pulse generation circuit 301 generates a pulse at the fall of the row address strobe RAS, and the set / reset flip-flop (SR-F)
(Referred to as F) 303 is set, the row / column switching signal RCS becomes high level, and the row address decoder 603 is set.
Activate. In addition, the column address strobe CAS
The one-shot pulse generation circuit 302 generates a pulse at the trailing edge of, the SR-FF 303 is reset, the row / column switching signal RCS becomes low level, and the column address decoder 602 is activated. Also, RAS / CA
The S circuit 601 delays the pulse generated by the one-shot pulse generation circuit 301 by the delay circuit 308 to generate the SR-F.
Since it is supplied to the set input terminal of F309, when the row address strobe RAS falls, a row / row
The sense amplifier activation signal SE is output at a high level after the change of the column switching signal RCS to a high level.
The sense amplifier activation signal SE becomes a low level by resetting the SR-FF 309 with a pulse generated by the one-shot pulse generation circuit 305 when the row address strobe RAS rises.

When the control signal CONT is at low level, the column address decoder 602 decodes based on the combination of the address signals A0 and A1 when the row / column switching signal RCS from the RAS / CAS circuit 601 is at low level. One of the Y switch selection signals Y0 to Y3 is selected and output. When the control signal CONT is low level, all the Y switch selection signals Y0 to Y3 are high level.

In the conventional example of FIG. 11, a dynamic RAM is used.
The flash write function is used when setting the test data in the memory cell portion prior to the data retention test of the memory cell. The entry circuit 110 is pulled into the flash write mode according to the input order or combination of a plurality of input signals, and the control signal CONT changes to the high level. When the control signal CONT becomes high level, all the Y switch selection signals Y0 to Y3 output from the column address decoder 602 become high level and all the Y switches in the Y switch row 102 become conductive, and the Y switch row 1
The positive side write data line D2T is connected to the positive side Y switch output lines D30T, D31T, D32T, D33T via 02, and the reverse side write data line D2N is the reverse side Y switch output lines D30N, D31N, D32N, D33N. Connected to. In this flash write mode, the write enable signal WE is set to low level and the row address strobe RA
By changing S to the low level, all the sense amplifiers SA0 to SA3 are activated, and therefore the same as the input data Din depending on whether the digit line connected to the memory cell is the positive side or the inversion side. The data or the inverted data of Din can be simultaneously written in all the memory cells connected to the word line designated by the address signals A0 and A1.

FIG. 14 is an operation timing chart of the conventional flash light. At time t0, the control signal CONT is set to the high level to set the test data setting mode. At time t1, since the addresses A0 and A1 are both at the low level at the fall of the row address strobe RAS, the memory cell section word line X0 is connected. The input data Din is written in the positive side memory cells M01T and M03T, and the input data Din is written in the inversion side memory cells M00N and M02N connected to the memory cell section word line X1.
The inverted data of is written. Similarly, at time t3, when the row address strobe RAS falls, the address A0
Is high level and A1 is low level, the positive side memory cell M10T connected to the memory cell section word line X1.
And the input data Din are written in M12T and the inversion side memory cell M connected to the memory cell section word line X1.
The inverted data of the input data Din is written in 11N and M13N, and at time t5, the row address strobe RA
Since the address A0 is at the low level and A1 is at the high level at the fall of S, the input data Din is written to the positive memory cells M21T and M23T connected to the memory cell word line X2, and the memory cell word line X2 is written. The inversion data of the input data Din is written in the inversion side memory cells M20N and M22N connected to the time t7.
Since the addresses A0 and A1 are both at the high level at the fall of the row address strobe RAS, the positive side memory cell M30T connected to the memory cell word line X3.
And the input data Din are written in M32T and the inversion side memory cell M connected to the memory cell section word line X3.
The inverted data of the input data Din is written in 31N and M33N.

[0009]

As described above, in the conventional memory device having the flash write function, a plurality of memory cells can be written at the same time, so that the test data setting time can be shortened. The larger the memory capacity and the larger the number of memory cells included in one word, the greater the effect of shortening the writing time.

However, the conventional memory device of FIG. 11 has the following problems. The first problem is that since the input data Din is supplied from one write drive circuit 108 to all the sense amplifiers in the sense amplifier row 101 to perform simultaneous writing, the data can be changed only in units of one word. This is not possible, and different writing cannot be performed for each sense amplifier within the data of one word, which reduces the degree of freedom in setting test data. For this reason, it is often the case that various test data write patterns desirable for detecting a defective memory cell cannot be realized, and the detection capability of the defective memory cell in the memory test pattern is lowered.

The second problem is that in the flash light, one write drive circuit 108 is used for the sense amplifier array 10.
Since the input data is supplied to all the sense amplifiers of No. 1, the load of the write drive circuit 108 becomes very large, and the time required for one write is longer than the write time in the normal operation mode. This requires a long time and increases power consumption. Although the writing time can be shortened by increasing the driving force of the writing drive circuit 108 or providing a plurality of writing drive circuits, the power consumption cannot be reduced, and the area occupied by the writing drive circuit 108 is reduced. The new problem of increasing

As a technique for solving the first problem, the technique described in Japanese Patent Application Laid-Open No. 4-147500 can be applied. A memory circuit including a memory cell array and a register that can store multiple bits of write data are provided, and the data in the register is written into the memory circuit. A writing pattern can be realized. However,
Japanese Laid-Open Patent Publication No. 4-147500 discloses that writing to a memory circuit from a register provided outside the memory circuit is serial writing for each memory cell, or a plurality of memory cells similar to a flash write. There is no description of parallel writing with respect to. If writing serially, the writing time is not shortened because it is the same as the conventional writing bit by bit. If writing parallel, the same number of write driving circuits as the number of register bits are required. Since the second problem, that is, the increase in power consumption and the increase in occupied area, cannot be solved, the technique disclosed in Japanese Patent Laid-Open No. 147500/1992 does not solve the first problem and the second problem at the same time. Can not.

The main object of the present invention is that writing can be done in units of one word and the setting time of test data can be shortened, the degree of freedom in setting test data is higher than that of flash write, and power consumption is reduced. It is to provide a memory device having a function capable of performing.

[0014]

A memory device according to a first aspect of the present invention includes a state control section for setting first, second and third states of a test data setting mode based on an input signal from the outside. A memory cell section including a plurality of memory cells that can be selectively selected by a plurality of memory cell section word lines and a plurality of digit line pairs, and all the memory cell section word lines are unselected in the first and second states. In the third state, a row address decoder that selects and drives one of the memory cell word lines using the address signal as a row address and the copy data storage cell word line and the plurality of digit line pairs can be selectively selected. A copy data storage section having different copy data storage cells and one of the copy data storage section word lines based on a predetermined portion of the address signal in the first and second states. A copy data storage word line selection drive circuit that selects and drives all the copy data storage word lines in the third state and unselects them, and the first and second digit lines provided corresponding to the plurality of digit line pairs. And a sense amplifier row including a plurality of sense amplifiers that are activated in the third state, and one of the plurality of digit line pairs using the address signal as a column address when writing data in the first state.
A column address decoder for selecting a pair and a Y switch row, and a write drive circuit that inputs data from the outside in the first state and transfers the data to the Y switch row, and a write drive circuit from the outside in the first state , The data input via the Y switch row and the sense amplifier row is written to the copy data storage cell row connected to the copy data storage word line,
In the second state, the copy data stored in the copy data storage cell row is read out and held in the sense amplifier column,
In the state, the copy data held in the sense amplifier column is copied and written in the memory cell section cell row connected to the memory cell section word line.

A memory device according to a second aspect of the present invention includes a state control section for setting the first, second and third states of the test data setting mode based on an input signal from the outside, a plurality of memory cell section word lines and a plurality of memory cell section word lines. A memory cell portion including a plurality of memory cells that can be alternatively selected by a digit line pair of
In the first and second states, all the memory cell word lines are unselected, and in the third state, one of the memory cell word lines is selected and driven by using the address signal as a row address, and a redundant cell part. A redundant cell portion having a redundant cell which is selectively selectable by the word line and the plurality of digit line pairs and is used for replacement and repair when a memory cell fails; and a memory cell portion word line of the failed cell when the memory cell fails A redundant cell section word line selection circuit for selecting and outputting a redundant cell section word line to be replaced, and a word line for designating a cell column for storing copy data among the redundant cell section word lines in the first and second states. One of the shared redundant cell section shared word lines is selected and output based on a predetermined portion of the address signal, and in the third state, all redundant cell section shared word lines are selected. Selected by the copy data storage word line selection circuit by inputting the output of the copy data storage word line selection circuit, the output of the redundant cell part word line selection circuit, and the output of the copy data storage word line selection circuit A redundant cell word line drive circuit for driving a word line shared by redundant cells, and a plurality of sense amplifiers provided corresponding to the plurality of digit line pairs and operating in the first, second and third states are included. A sense amplifier row, a column address decoder and a Y switch row that select one pair from the plurality of digit line pairs by using an address signal as a column address when writing data in the first state, and externally input data in the first state. And a write drive circuit for transferring the write drive circuit to the Y switch train from the outside in the first state. The data input via the read column is written to the cell row connected to the redundant cell section shared word line, and in the second state, the copy data stored in the cell row connected to the redundant cell section shared word line is sensed. In the third state, the data for copying held in the sense amplifier column is copied and written in the memory cell section cell row connected to the memory cell section word line.

A memory device according to a third aspect of the present invention includes a state control section for setting the first, second and third states of the test data setting mode based on an external input signal, a plurality of memory cell section word lines and a plurality of memory cell section word lines. A memory cell portion including a plurality of memory cells that can be alternatively selected by a digit line pair of
In the first and second states, one of the memory cell word lines that is also shared as a word line for designating a cell column for storing copy data is selected based on an address signal and output. In the first and second states, the data storage section word line selection circuit and the memory cell section common word line corresponding to the output from the copy data storage section word line selection circuit are selected and driven, and the address signal is set low in the third state. A row address decoder for selecting and driving one of the memory cell word lines as an address, and a plurality of senses provided corresponding to the plurality of digit line pairs and operating in the first, second and third states. A row of sense amplifiers including amplifiers, and a pair of digit line pairs is selected by using an address signal as a column address when writing data in the first state. A column address decoder and Y that
Input data from the switch row and externally in the first state, and press Y
And a write drive circuit for transferring to the switch row, and in the first state, data input from the outside via the write drive circuit, the Y switch row and the sense amplifier row is connected to the word line shared by the memory cells. In the second state, the copy data stored in the cell row connected to the word line shared with the memory cell portion is read out and held in the sense amplifier column, and in the third state, the copy data is held in the sense amplifier column. The copy data is copied and written in the memory cell section cell row connected to the memory cell section word line.

The test data setting method according to the fourth aspect of the present invention corresponds to a plurality of memory cell section cell rows including memory cells provided corresponding to a plurality of digit line pairs and the plurality of digit line pairs. And a copy data storage cell row including copy data storage cells provided in a row and a sense amplifier column including a sense amplifier provided corresponding to the plurality of digit line pairs. The copy data storage cell row with copy data 1
A procedure for sequentially writing each cell, a procedure for simultaneously reading and holding the copy data stored in the copy data storage cell row to the sense amplifier column, and a procedure for writing the copy data held in the sense amplifier column to the cell row of the memory cell section. And a procedure for collectively writing in.

In the test data setting method of the fifth invention, a plurality of memory cell section cell rows including memory cells provided corresponding to a plurality of digit line pairs and a plurality of digit line pairs are provided. When a memory cell has a failure, a plurality of redundant cell section cell rows for replacing and repairing the memory cell section cell row including the defective cell, and a sense amplifier provided corresponding to the plurality of digit line pairs A method of setting test data for a memory device including a sense amplifier column including: a procedure for writing copy data sequentially for each cell with at least a part of a plurality of redundant cell section cell rows as cell rows for storing copy data. And a procedure for reading and holding the copy data from the redundant cell section cell row used as the cell row for storing the copy data to the sense amplifier column all at once, and holding it in the sense amplifier And a procedure for copying writing the copy data at once to the cell rows of the memory cell portion.

In the test data setting method of the sixth invention, a plurality of memory cell section cell rows including memory cells provided corresponding to a plurality of digit line pairs and the plurality of digit line pairs are provided. A test data setting method for a memory device including a sense amplifier column including a sense amplifier, wherein a part of a plurality of memory cell section cell rows is used as a cell row for storing copy data, and copy data is sequentially provided for each cell. The write procedure, the memory cell section used as the cell row for storing the copy data, the procedure for simultaneously reading and holding the copy data from the cell row to the sense amplifier column, and the copy data held in the sense amplifier in the memory cell section cell And a procedure of collectively writing in a row.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, a plurality of copy data storage cell rows having the same structure as one word of a memory cell portion are provided in a cell array, and a memory device is set to a first state in a test data setting mode. After writing the copy data for setting the test data to each of the copy data storage cell rows, the memory device is set to the second state and read from the copy data storage cell rows to the sense amplifiers all at once.
Further, the memory device is set to the third state, and the process of collectively writing to the plurality of first desired cell rows of the memory cell portion is sequentially performed.
Next, the memory device is set to the second state again and read simultaneously from the other copy data storage cell rows to the sense amplifiers, and the memory device is set to the third state to set a plurality of memory cells different from the first desired cell row. The process of collectively writing to the second desired cell row is sequentially performed. As a result, test data of various patterns can be set, and the writing of the test copy data to the copy data storage cell row is similar to the writing in the normal operation mode, which increases the load of the write drive circuit. It can be avoided and power consumption is reduced.

Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In the first embodiment of the present invention, in addition to the memory cell section and the redundant cell section, the copy data storage section is provided as a dedicated area for writing the copy source data when setting the test data. Next, the configuration of the first embodiment will be described. The memory device is a 4 × 4 dynamic RAM for simplification of the description as in the conventional example of FIG.

The entry circuit 110 receives the address signal A
0, A1, row address strobe RAS, column address strobe CAS, and write enable signal W
E is input, and it is detected that the test data setting mode has been entered based on the input order or the combination of signal levels, and the control signal CONT is output as a high level. There are various known techniques as a method of entering the test data setting mode from the normal operation mode, and one of them may be used.

The RAS / CAS circuit 106 includes a row address strobe RAS and a column address strobe CA.
S and the control signal terminal CONT are input, and the sense amplifier activation signal SE, the row / column switching signal RCS, and the word line deselection signal WNS are output. Control signal CON
In the normal operation mode in which T is low level, the row / column switching signal R is generated at the fall of the row address strobe RAS.
Set CS to high level and set the column address strobe CA
At the fall of S, the row / column switching signal RCS is set to low level. In addition, the sense amplifier activation signal SE is set to the active high level after a predetermined time delay from the fall of the row address strobe, and the sense amplifier activation signal SE is set to the low level at the rise of the row address strobe. In the test data setting mode in which the control signal CONT is at the high level, the row / column switching signal RCS is set to the high level of the first signal level at the fall of the row address strobe RAS, and the column address strobe CA is set.
At the fall of S, the row / column switching signal RCS is set to the low level of the second signal level. In addition, the sense amplifier activation signal SE is set to the active high level after a predetermined time delay from the fall of the row address strobe, and when the rise of the row address strobe is detected when the column address strobe CAS is low level, the sense amplifier activation signal SE is detected. Set SE to low level. Also, R
The AS / CAS circuit 106 uses the row / column switching signal RC
S is high level, control signal CONT is high level,
When the column address strobe CAS is at the low level of the first input level, the word line deselection signal WNS is set to the active level of high level and output.

The row address decoder 103 receives the address signals A0 and A1, the row / column switching signal RCS, the word line deselection signal WNS, and the defective memory cell row replacement signal NRS, and receives the row / column switching signal. When RCS is at high level, it becomes active and word line deselect signal W
When NS is low level, one of the memory cell word lines X0, X1, X2 and X3 is selected and set to high level based on the combination of the signal levels of the address signals A0 and A1. When the word line deselection signal WNS goes high, the row address decoder 103 goes into a non-selected state, and all the memory cell word lines X0, X1, X2, and X3 go low. Fault memory cell row replacement signal N
RS is a signal for prohibiting the use of a specific word line of the memory cell word lines X0, X1, X2, X3 or a memory cell connected to it when there is a failure, and thereby a redundant cell Part word line selection circuit 10
It avoids the occurrence of the competition of the operation with 4.

The redundant cell section word line selection circuit 104 includes address signals A0 and A1 and a row / column switching signal RCS.
And a defective memory cell row replacement signal NRS for prohibiting the use of a defective word line of the memory cell word lines connected to the row address decoder, and a redundant cell of the redundant cell part replaced by the defective word line. Redundant word selection signals PRX0 and PRX1 for selectively designating the partial word lines are output.

Copy data storage unit word line selection circuit 10
Reference numeral 5 receives the address signal A0, the control signal CONT, the row address strobe RAS, and the column address strobe CAS, and outputs the copy data storage word line selection signals PCX0 and PCX1. Control signal CONT
Is at a low level, it means that the copy data storage section word line selection signals PCX0 and PCX1 are both at a low level because it is a normal operation mode. When the control signal CONT is at the high level and in the test data setting mode, if the column address strobe CAS is at the low level at the fall of the row address strobe RAS, the address signal A0
Stored word selection signals PCX0, PC based on the level of
Select any one of X1 and set it to the high level.

The column address decoder 107 receives the address signals A0 and A1 and the row / column switching signal RCS, becomes active when the row / column switching signal RCS is at the low level, and outputs the signal levels of the address signals A0 and A1. Y switch selection signals Y0, Y based on the combination of
One of Y1, Y2 and Y3 is selected and output as a high level.

The write drive circuit 108 receives the input data Di
n and the write enable signal WE are input, the write enable signal WE is activated when the write enable signal WE is at the low level, the same data level of the input data Din is output to the positive side write data line D2T, and the inverted side write data line is output. The inverted signal level of the input data Din is output to D2N.

The redundant cell section word line drive circuit 111 receives the redundant word selection signals PRX0 and PRX1 and enhances the driving force through a buffer circuit whose input and output are in phase with each other, and redundant cell section word lines RX0 and RX1. Output to.

Copy data storage unit word line drive circuit 11
2 is a copy data storage section word line selection signal PCX0,
PCX1 is input, and the driving power is increased through the buffer circuits of which the input and the output are in phase, and output to the redundant cell section word lines CX0 and CX1.

The Y switch array 102 receives the Y switch selection signals Y0, Y1, Y2 and Y3, and outputs a pair of positive side Y switch output line D30T and inverted side Y switch output line D30N terminal, a positive side Y switch. Output line D31T and reverse side Y
Output line pair with switch output line D31N, output line pair with positive side Y switch output line D32T and reverse side Y switch output line D32N, or output line with positive side Y switch output line D33T and reverse side Y switch output line D33N One of the pair corresponding to the high-level Y switch selection signal is electrically connected to the data line pair of the positive side write data line D2T and the inverted side write data line D2N.

The sense amplifier row 101 is supplied with the sense amplifier activation signal SE, and the positive side Y switch output line D30T and the reverse side Y switch output line D are provided on the side of the Y switch row.
30N output line pair, positive side Y switch output line D31T and inverting side Y switch output line D31N output line pair, positive side Y
Switch output line D32T and reverse side Y switch output line D3
2N output line pair and positive side Y switch output line D33T
And an inversion side Y switch output line D33N connected to the output line pair, and a digit line pair of a positive digit line D40T and an inversion digit line D40N, a positive digit line D41T and an inversion digit line D41N on the cell array side. Digit line pair, positive digit line D42T and inverted digit line D42
It is connected to a digit line pair of N and a digit line pair of a positive digit line D43T and an inverted digit line D43N. The sense amplifier row 101 has a sense amplifier activation signal S
When E is high level, the internal sense amplifier is activated, and when data is written from the outside to the cell array 100, the signal level of each output line pair is transmitted to the corresponding digit line pair, and the cell array 100 is transmitted. At the time of reading data from the outside to the outside, the signal level difference of each digit line pair is amplified and transmitted to the corresponding output line pair.

The cell array 100 has memory cell word lines X0, X1, X2 and X3, redundant cell word lines RX0 and RX1 and a copy data storage word line CX on the row side.
0, CX1 are connected, and the digit line pair D40T on the column side
/ D40N, D41T / D41N, D42T / D42
N, D43T / D43N are connected.

FIG. 2 is a diagram showing a detailed configuration of the cell array 100, the sense amplifier array 101 and the Y switch array 102 of FIG. The sense amplifier array 101 is composed of a sense amplifier SA0, a sense amplifier SA1, a sense amplifier SA2, and a sense amplifier SA3. Activation / deactivation of each sense amplifier is controlled by a sense amplifier activation signal SE output from the RAS / CAS circuit 106.

On the other hand, the data input is complementary and independent for each sense amplifier. The positive side Y switch output line D30T and the reverse side Y switch output line D30N are connected to the sense amplifier SA0, and the positive side Y switch is connected. Output line D31
T and the inversion side Y switch output line D31N are connected to the sense amplifier SA1, and the positive side Y switch output line D32T and the inversion side Y switch output line D32N are connected to the sense amplifier SA2.
Connected to the positive side Y switch output line D33T and the reverse side Y
The switch output line D33N is connected to the sense amplifier SA3. The output is complementary like the input and independent for each sense amplifier. The sense amplifier SA0 is connected to the positive digit line D40T and the inverted digit line D40N, and the sense amplifier SA1 is inverted to the positive digit line D41T. Side digit line D41N terminal, the sense amplifier SA2 is connected to the positive side digit line D42T and the inversion side digit line D42N, and the sense amplifier SA3 is connected to the positive side digit line D43T and the inversion side digit line D43N. There is.

The cell array 100 includes memory cell section word lines X0, X1, X2 and X3 for four memory cell sections.
Redundant cell section word lines RX0, RX for two redundant cell sections
A total of eight word lines, one and two copy data storage word lines CX0 and CX1 for the copy data storage;
4 pairs of positive and reverse digit line pairs D40T / D40
N, D41T / D41N, D42T / D42N, D43
It is composed of T / D43N. Sixteen DRAM cells are arranged as memory cells in the memory cell section, eight cells are arranged as redundant cells for the redundant cell section, and eight cells are arranged as copy data storage cells for the copy data storage section.

In the memory cell section 200, a memory cell M00N is arranged so as to be connected to each of the intersections of the memory cell section word line X0 and the inversion digit line D40N, and the memory cell section word line X1 and the positive digit line D40T are arranged. The memory cells M10T are connected and arranged at the intersections of the memory cell word line X2 and the inversion digit line D4.
The memory cells M20N are connected and arranged at the intersections with 0N, and the memory cells M30T are arranged so as to be connected with the intersections between the memory cell part word line X3 and the positive digit line D40T. Further, memory cells M01T are connected to and arranged at the intersections of the memory cell word lines X0 and the positive digit lines D41T, and the memory cells M11N are arranged at the intersections of the memory cell word lines X1 and the inversion digit lines D41N. The memory cell portion word line X2 and the positive digit line D41 are connected to each other and arranged.
A memory cell M21T is connected to each other at an intersection with T, and a memory cell M31N is connected to each other at an intersection between the memory cell section word line X3 and the inversion digit line D41N. Further, memory cells M02N are connected and arranged at the intersections of the memory cell section word line X0 and the inversion digit line D42N, respectively, and the memory cell M12T is arranged at the intersection of the memory cell section word line X1 and the positive digit line D42T. The memory cell section word line X2 and the inversion side digit line D4 are connected to each other and arranged.
A memory cell M22N is connected to each other at an intersection with 2N, and a memory cell M32T is connected to each other at an intersection between the memory cell section word line X3 and the positive digit line D42T. Further, memory cells M03T are connected and arranged at the intersections of the memory cell word line X0 and the positive digit line D43T, and the memory cell M13N is provided at the intersection of the memory cell word line X1 and the inversion digit line D43N. The memory cell section word line X2 and the positive digit line D43 are connected to each other and arranged.
A memory cell M23T is connected to each other at an intersection with T, and a memory cell M33N is connected to each other at an intersection between the memory cell word line X3 and the inversion digit line D43N.

In the redundant cell section 201, redundant cells R00N are respectively connected and arranged at the intersections of the redundant cell section word line RX0 and the inversion digit line D40N, and the redundant cell section word line RX1 and the positive digit line D40T are arranged. Redundant cells R10T are respectively connected and arranged at the intersections of the redundant cell section word line RX0 and the positive side digit line D41T, and redundant cells R01T are respectively connected and arranged at the intersections of the redundant cell section word line RX1. Inversion digit line D4
Redundant cells R11N are connected and arranged at the intersections with 1N, and redundant cells R02N are connected and arranged at the intersections between the redundant cell section word line RX0 and the inversion digit line D42N, respectively. Redundant cells R12T are respectively connected and arranged at the intersections of RX1 and the positive digit line D42T, and redundant cell word line RX0 is provided.
At the intersection of the positive digit line D43T and the redundant cell R03T,
Redundant cell section word line RX1 and inversion side digit line D43N
Redundant cells R13N are respectively connected and arranged at the intersections with.

In the copy data storage unit 202, the copy data storage unit word line CX0 and the inversion side digit line D40N.
Copy data storage cells C00N are connected and arranged at the intersections with the copy data storage cell word lines CX.
1 and the positive digit line D40T, the copy data storage cells C10T are connected and arranged respectively, and the copy data storage word line CX0 and the positive digit line D41 are arranged.
Copy data storage cells C01T are connected and arranged at the intersections with T, respectively, and copy data storage word line C
Copy data storage cells C11N are arranged and connected to the intersections of X1 and the inversion digit line D41N,
Copy data storage cells C02N are respectively connected and arranged at the intersections of the copy data storage word line CX0 and the inversion digit line D42N, and the copy data are stored at the intersections of the copy data storage word line CX1 and the positive digit line D42T. The storage cells C12T are connected to each other and arranged, and the copy data storage cells C03T are connected to each other and arranged at the intersection of the copy data storage word line CX0 and the positive digit line D43T. The copy data storage cell C13N is arranged so as to be connected to each of the intersections of the and the inversion digit line D43N.

The Y switch row 102 is a Y switch YS0.
, Y switch YS1, Y switch YS2, and Y switch YS3. Since each switch handles complementary data, two switches function as one set. The column address decoder 10 turns on / off each Y switch.
7, the Y switch selection signal Y0, which is the output, becomes the input of the Y switch YS0, the Y switch selection signal Y1 becomes the input of the Y switch YS1, and the Y switch selection signal Y2 becomes the input of the Y switch YS2. The selection signal Y3 is input to the Y switch YS3.

On the other hand, the inputs relating to the data are complementary, and each Y
It is shared by the switches, and the positive side write data line D2T
And the inversion side write data line D2N are connected to the Y switch YS0.
, Y switch YS1, Y switch YS2, and Y switch YS3 are commonly connected. The output is also complementary like the input, but since the output destination is the sense amplifier row 101, each Y switch is connected to the corresponding sense amplifier. The correspondence between the input and output of each Y switch is that in the Y switch YS0, the positive side Y switch output line D30T is the output with respect to the input of the positive side write data line D2T, and the input of the reverse side write data line D2N is the input. On the other hand, the reverse side Y switch output line D
30N is the output. Similarly, in the Y switch YS1, the positive side Y switch output line D31T is an output with respect to the input of the positive side write data line D2T, and the reverse side write data line D2N is output.
The inversion side Y switch output line D31N is an output with respect to the input of. Similarly, in the Y switch YS2, the positive side Y switch output line D32T is input with respect to the input of the positive side write data line D2T.
Is an output, and the inversion side Y switch output line D32N is an output with respect to the input of the inversion side write data line D2N. Similarly, in the Y switch YS3, the positive side Y switch output line D33T is an output with respect to the input of the positive side write data line D2T, and the reverse side Y is with respect to the input of the reverse side write data line D2N.
The switch output line D33N is an output.

In FIG. 1, the entry circuit 110 and the RAS / C
The state control unit including the AS circuit 106 and the write enable signal WE sets the memory device to the copy data storage cell by the control signal CONT, the row / column switching signal RCS, the word line deselection signal WNS and the write enable signal WE. A first state for writing copy data to a row, a second state for simultaneously reading from the copy data storage cell row to the sense amplifiers, and a third state for sequentially performing a process of collectively writing to a plurality of desired cell rows Control.

Next, the operation of the first embodiment will be described. FIG. 3 is an operation timing chart when setting test data in the memory device of FIG. 1 according to the first embodiment of the present invention. The memory device is set to the first state during the period from time t1 to time t2 and the period from time t3 to time t4, and the period from time t5 to time t6 and time t11.
The second state is set during the period from time t12 to time t12, the period from time t7 to time t8, the time t9 to time t1.
The third state is set during the period from 0 and the period from time t13 to time t14.

First, the memory device enters the test data setting mode at time t0 in FIG. afterwards,
At time t1, all of the memory cell word lines X0 to X3 in FIG. 2 are set to the non-selected low level and the copy data storage word line CX0 or the copy data storage word line CX1 forming the copy data storage unit 202 is set. Select one. DRA for these signals
Since M cells are connected and the wiring capacity is large, control is performed using a dedicated drive circuit. Further, the copy data storage cell C00N is connected to the copy data storage word line CX0.
, A copy data storage cell C01T, a copy data storage cell C02N, and a copy data storage cell C03T are connected to each other, and these are connected to the first copy data storage cell row C.
It is called W0. Similarly, the copy data storage word line C
X1 includes a copy data storage cell C10T, a copy data storage cell C11N, and a copy data storage cell C12.
T is connected to the copy data storage cell C13N, which is referred to as a second copy data storage cell row CW1.

The copy data storage word line CX will be described below.
The selection procedure of 0 is shown. At time t1 in FIG. 3, when the row address strobe RAS transits from the high level to the low level and the column address strobe CAS is at the low level, the word line deselection signal WNS of the RAS / CAS circuit in FIG. 1 is at the high level. All the memory cell word lines X0 to X3 output from the row address decoder 103 become non-selected low level, and the memory device is set to the first state. The copy data storage word line selection circuit 105 determines the signal level of the address signal A0. If the signal level of the address signal A0 is low, the copy data storage word line selection signal PCX0 is output as a high level and the address signal If the signal level of A0 is high level, the copy data storage word line selection signal PCX1 is output as high level. Time t in FIG.
Since the address signal A0 is low level in 1
The copy data storage word line selection circuit 105 of FIG. 1 outputs the copy data storage word line selection signal PCX0 as a high level.

FIG. 4B is a circuit diagram of the copy data storage word line selection circuit 105. In the copy data storage word line selection circuit 105, the D-type flip-flop (D-FF) 313 holds the signal level of the column address strobe CAS when the row address strobe RAS transits from the high level to the low level.
A signal obtained by inverting the row address strobe RAS by the inverter circuit 312 is input to the trigger input terminal of the D-FF 313. The D-FF 313 holds the level of the data input terminal D when the clock terminal transits from the low level to the high level. Therefore, at time t in FIG.
In 1, the row address strobe RAS is transited from the high level to the low level, so an inverted high level is input to the trigger input terminal of the D-FF 313, and at this time, the data input terminal of the D-FF 313 is input. An inverted signal of the column address strobe CAS input to D, that is, a high level is a 3-input AND circuit 314 and 3
It is output to the input AND. Conversely, if the column address strobe CAS is at the high level when the row address strobe RAS transits from the high level to the low level, the low level is output to the 3-input AND circuit 314 and the 3-input AND circuit. In this state, even in the test data setting mode, the copy data storage word line selection signals PCX1 and 3 inputs A which are the outputs of the 3-input AND circuit 314 in the copy data storage word line selection circuit 105.
Since the copy data storage section word line selection signal PCX0 output from the ND circuit 315 is fixed to the low level, the copy data storage section 202 is not selected.
Therefore, when the copy data storage unit 202 is selected, when the row address strobe RAS transits from the high level to the low level, the column address strobe C
It is necessary that AS is at a low level.

On the other hand, since the control signal CONT enters the test data setting mode at the time t0 and is at the high level, the copy data storage section word line selection signal PCX1 which is the 3-input AND circuit 314 and the 3-input AND circuit 314.
The signal level of the copy data storage word line selection signal PCX0 output from the circuit 315 is determined by the signal level of the address signal A0. Since the address signal A0 is at low level at time t0, the 3-input AND circuit 31
4, the copy data storage section word line selection signal PCX1 is output as a low level. Further, the address signal A0
The copy data storage word line selection signal PCX0 is output as a high level from the 3-input AND circuit 315 to which the signal inverted by the inverter circuit 311 is input. Since the output signal of the copy data storage unit word line selection circuit 105 is intended to control the circuit operation, it is possible to directly drive the copy data storage unit word lines CX0 and CX1 of the copy data storage unit 202 in FIG. Can not. Therefore, the copy data storage word line drive circuit 112 having a buffer circuit enhances the load driving capability before the copy data storage word lines CX0, CX.
1 is being driven. At time t0, the copy data storage word line CX0 of the copy data storage word line drive circuit 112 is selected and becomes high level, so that the first copy data storage cell row CW0 is selected.

Next, the RAS / CAS circuit 106 will be described. FIG. 4A is a circuit diagram of the RAS / CAS circuit 106. One-shot pulse generation circuit 301, 3
02 and 305 generate a one-shot pulse when the input signal falls. SR-FF303 and SR-FF30
9 operates by receiving a one-shot pulse, and when the one-shot pulse is input to the set input terminal S, the output terminal Q
Becomes a high level output and holds the set state, and when a one-shot pulse is input to the reset end, the output end Q becomes a low level output and holds the reset state. At time t1 in FIG. 3, when the row address strobe RAS transits from the high level to the low level, the one-shot pulse generation circuit 301 outputs a one-shot pulse,
It is input to the set input terminal of the SR-FF 303. Also,
The one-shot pulse output from the one-shot pulse generation circuit 301 is delayed by the delay circuit 308 for a predetermined time and then input to the set input terminal of the SR-FF 309. As a result, the row / column switching signal RCS is output as a high level from the output terminal Q of the SR-FF 303, and the sense amplifier activation signal SE is output as a high level from the output terminal Q of the SR-FF 309 after a predetermined time delay. . Further, when the row address strobe RAS transits from the high level to the low level, the column address strobe C
Since AS is at the low level, the 3-input AND circuit 310
The word line deselection signal WNS, which is the output of, becomes high level. When the row / column switching signal RCS is at high level, the row address decoder 103 is active, and when it is at low level, the column address decoder 107 is active. However, after time t1, even if the row / column switching signal RCS is at the high level, the word line deselection signal WNS is at the high level, so that the output of the row address decoder 103 is in the non-selected state.

FIG. 4C shows the column address decoder 1
It is a figure which shows the structure of 07. Row / column switching signal RC
When S is at low level, the decode circuit is activated, and one of the Y switch selection signals Y0 to Y3 is selected and brought to high level based on the combination of the signal levels of the address signals A0 and A1. For example, when the address signals A0 and A1 are both low level, the Y switch selection signal Y0 is high level, when the address signal A0 is high level and the address signal A1 is low level, the Y switch selection signal Y1 is high level. When the signal A0 is at the low level and the address signal A1 is at the high level, the Y switch selection signal Y2 is at the high level and the address signal A
When both 0 and A1 are high level, the Y switch selection signal Y3 is high level.

The write enable signal WE is fixed to the low level between time t1 and time t2 in FIG. 3, and when the column address strobe CAS changes to the low level, the row / column selection signal RCS becomes the low level and the column address. The decoder is activated and the address signal A
The input data Din is written to the copy data storage cells of the first copy data storage row CW0 selected by the signal level of 0 sequentially by the column address.
When the memory device is provided with a page write function, the column address strobe is alternately changed between the high level and the low level and used as a clock signal without specifying the column address for each write. It is possible to sequentially select and write the switch selection signals Y0 to Y3. In the general page writing function, the memory cell portion is the target of page writing, but the present embodiment is characterized in that the target of page writing is the copy data storage portion. Between time t1 and time t2 and time t3 in FIG.
From time t4 to time t4, the case where the page write function is used is shown, but it goes without saying that writing may be repeated by designating a column address by an address signal for each copy data storage cell.

In the page write operation in the test data setting mode, the column address strobe CAS is clocked to capture the column address for designating the write destination and the input data serving as the copy data of the test data. At the fall of the column address strobe CAS during the page write operation, RAS / C of FIG.
The one-shot pulse generation circuit 302 of the AS circuit 106 outputs a one-shot pulse, which is input to the reset input terminal R of the SR-FF 303. As a result, SR-
From the output terminal Q of the FF303, the row / column switching signal RC
S is output as a low level. Since the row / column switching signal RCS is at low level, the column address decoder 107 is activated and the address signal A0 and the address signal A1 are used as column addresses. As the column address for designating the writing destination, one of the Y switch selection signals Y0 to Y3 is selected corresponding to the combination of the signal levels of the address signal A0 and the address signal A1. The non-selected state of the output of the row address decoder is maintained during the page writing.

On the other hand, the copy data is sequentially input data D
It is transmitted to the inside by the write drive circuit 108 in the active state as in, and the Y switch selection signals Y0, Y1, Y
2, Y3 are sequentially selected and held in the corresponding sense amplifiers. The page write operation is performed between time t1 and time t2 in FIG. 3, and the selection Y switches YS0, YS are selected.
1, YS2, YS3 are sequentially switched. For example, when the Y switch YS0 in FIG. 2 is selected,
It is held in the sense amplifier SA0. The data held by the sense amplifier SA0 is output to the positive digit line D40T and the inverted digit line D40N, and the copy data storage arranged at the intersection with the selected copy data storage word line CX0 is stored. Written to cell C00N. Y switch Y in FIG.
When S1 is selected, the copy data is as shown in FIG.
It is held in the sense amplifier SA1 in FIG. The data held by the sense amplifier SA1 is output to the positive digit line D41T and the inverted digit line D41N and stored in the copy data storage section word line CX0 in the selected state. Written to cell C01T. When the Y switch YS2 is selected, the copy data is the sense amplifier SA.
It is held at 2. The data held by the sense amplifier SA2 is output to the positive digit line D42T and the inverted digit line D42N, and the copy data storage arranged at the intersection with the selected copy data storage word line CX0 is stored. Written to cell C02N. When the Y switch YS3 is selected, the copy data is held in the sense amplifier SA3. The data held by the sense amplifier SA3 is
The data is output to the positive digit line D43T and the inverted digit line D43N and is written in the copy data storage cell C03T arranged at the intersection with the copy data storage word line CX0 in the selected state.

At time t2 in FIG. 3, since the writing of the copy data to the first copy data storage cell row CW0 in FIG. 2 is completed, the copy data to the first copy data storage cell row CW0 is written. In order to complete the writing, the row address strobe RAS is transited from the low level to the high level to bring the copy data storage word line CX0 in the selected state into the non-selected state. At this time, by setting the column address strobe CAS to the high level, the sense amplifier changes from the active state to the inactive state.

The operation will be described below. R in FIG. 4 (a)
The 2-input OR circuit 307 and 2-input AND circuit 304 used in the AS / CAS circuit 106 are the RAS of the conventional example.
This circuit is not included in the / CAS circuit 601 and is added in this embodiment. In the conventional RAS / CAS circuit 601, the one-shot pulse output from the one-shot pulse generation circuit 305 was directly input to the reset input terminal R of the SR-FF 309. In the conventional example of FIG. 11,
The sense amplifier is deactivated by changing the row address strobe RAS from the low level to the high level. In the present embodiment, the sense amplifier holds the data in the copy data storage unit and writes the data in the memory cell unit. In this case, since it is necessary to maintain the active state of the sense amplifier, the sense amplifier activation signal SE is set to the high level depending on the signal level of the column address strobe CAS when the row address strobe RAS is transited from the low level to the high level. Switching between maintaining and transitioning to low level.

At time t2 in FIG. 3, the column address strobe CAS is at low level and the control signal CONT is at high level. Therefore, RAS / in FIG.
The signal output from the 2-input AND circuit 306 of the CAS circuit 106 and input to one of the 2-input OR circuits 307 is at a low level. A one-shot pulse is input from the one-shot pulse generation circuit 305 to the other of the 2-input OR circuit 307. The one-shot pulse output from the one-shot pulse generation circuit 305 is a 2-input OR circuit 307.
Is output as it is, is input to the reset input terminal R of the SR-FF 309, and the sense amplifier activation signal SE output from the output terminal Q as a high level changes to a low level, and the SR-FF 309 holds the reset state. Since the sense amplifier activation signal SE becomes low level, the sense amplifiers SA0 to SA3 forming the sense amplifier column 101 in FIG. 2 are inactivated.

With the above, writing of the copy data to the first copy data storage cell row CW0 of FIG. 2 is completed.
Next, writing of the copy data to the second copy data storage cell row CW1 is performed between time t3 and time t4 in FIG. The basic operation is the first copy data storage cell row CW
Since the operation is the same as that described for 0, detailed description thereof will be omitted, and only the method of selecting the second copy data storage cell row CW1 will be described. The copy data storage word line selection circuit 105 of FIG. 1 determines the signal level of the address signal A0. Since the address signal A0 is at the high level at time t3 in FIG. 3, the copy data storage word line selection circuit 105 causes the copy data storage word line selection signal PCX.
1 is output. Copy data storage unit Word line drive circuit 1
The driving force is increased by 12 to drive the copy data storage word line CX1. At time t4 in FIG. 3, writing of the copy data to the first copy data storage cell row CW0 and the second copy data storage cell row CW1 is completed.

Next, the copy data stored in each copy data storage unit is read. The difference from the normal read operation is that the read source is not the memory cell section or the redundant cell section but the copy data storage section. After time t5 in FIG. 3, since the copy data is not written in the copy data storage unit 202, the write enable signal WE is set to the high level, the write drive circuit 108 in FIG. 1 is deactivated, and the data is input. Din is invalid. At time t5, the row address strobe R
The AS is transited from the high level to the low level, and the low level of the column address strobe CAS and the address signal A
The low level of 0 is detected by the copy data storage section word line selection circuit 105, and the first copy data storage cell row CW0 is selected. As a result, the copy data stored in the first copy data storage cell row CX0 of FIG. 2 is read. At this time, the word line deselection signal WN
Since S is at a high level, the memory cell word lines X0 to X0
X3 is all low level. RAS / in Figure 1
The sense amplifier activation signal SE output from the CAS circuit 106 changes from low level to high level, and all the sense amplifiers forming the sense amplifier row 101 in FIG. 2 are activated. Copy data storage cell C00N
Data is read out to the inversion side digit line D40N,
The potential difference from the positive digit line D40T, which is complementary to this, is amplified and held by the sense amplifier SA0.
The data stored in the copy data storage cell C01T, the copy data storage cell C02N, and the copy data storage cell C03T are also read by the same procedure, and the difference potential is amplified and held by the sense amplifier corresponding to each. Thus, the reading of the copy data stored in the first copy data storage cell row CW0 is completed.

Next, a procedure for writing the read copy data into the memory cell section will be described. At time t6 in FIG. 3, the first
The row address strobe RAS is changed from the low level to the high level in order to deselect the copy data storage cell row CW0. At this time, since it is necessary to maintain the data read from the first copy data storage cell row CW0 held by the sense amplifier, the column address strobe CAS is set to the high level to set the sense amplifier activation signal SE to the high level. Keep all sense amplifiers active. This is because the data of the first copy data storage cell row CW0 read at time t5 is used as copy data.

The procedure for holding the activated state of the sense amplifier will be described below. At time t6 in FIG. 3, the row address strobe RAS is changed from the low level to the high level, so that the inverter circuit 304 in the RAS / CAS circuit 106 in FIG.
The inverted signal of S is input to the one-shot pulse generation circuit 305. Since the one-shot pulse generation circuit 305 generates a one-shot pulse at the falling edge of the input signal, the one-shot pulse generation circuit 305 outputs the one-shot pulse at the rising edge of the row address strobe RAS.

On the other hand, since the output of the 2-input AND circuit 306 is at high level, the one-shot pulse generation circuit 30
Since the output of the 2-input OR circuit 307 remains at the high level regardless of the one-shot pulse output from 5, the reset operation of the SR-FF 309 is not performed. Therefore, the sense amplifier activation signal SE output from the SR-FF 309 maintains the high level, and the sense amplifier column 101 holds the data read from the first copy data storage cell row CW0. As described above, the re-reading of the copy data written in the first copy data storage cell row CW0 is completed.

Next, the procedure for writing the copy data into the memory cell section will be described. At time t7 in FIG. 3, the row address strobe RAS transits from the high level to the low level. At this time, the column address strobe C
By setting AS to the high level, the first copy data storage cell row CW0 and the second copy data storage cell row CW1 are prevented from being selected. Regarding the operation of the copy data storage section word line selection circuit 105,
Since it has been described above, it will be omitted. Here, the copy data storage unit is deselected in order to write the copy data held in the sense amplifier at time t6 into the memory cell for one word on the memory cell unit. Since the row address strobe RAS is transited from the high level to the low level at time t7 in FIG. 3, the RAS / CAS circuit 106 in FIG.
The row / column switching signal RCS output from the high level and the column address strobe being low level cause the word line deselection signal WNS to be low level. The memory cell word line X0 is selected in the row address decoder 103 in FIG. 1 because the memory cell word line is selected based on the above.

Since the sense amplifier column 101 holds the copy data read from the first copy data storage cell row CW0, the memory cell M00N connected to the currently selected memory cell section word line X0, Memory cell M01T, memory cell M02N, memory cell M03
Data is written in T from a sense amplifier connected to the same digit line pair as each memory cell. By the above operation, the copy writing of the copy data held in the first copy data storing cell row CW0 to the memory cell portion is completed. At time t9 in the figure, the memory cell section word line X2 of the memory cell section in FIG. 2 is selected and the copy data read from the first copy data storage cell row CW0 is written by the same procedure.

Of the pair of digit lines, the positive memory cell connected to the positive digit line (eg, M01T) and the inverted memory cell connected to the inverted digit line (eg, M00N) are always Information that is in an inverse relationship to each other is written. Therefore, a cell in which the input data from the data input Din and the data to be written in the memory cell match (positive side memory cell) and a cell in which the input data and the data to be written in the memory cell have an inversion relationship (inversion side memory cell)
Exists. The memory test pattern is required to be able to detect defects due to the influence of adjacent memory cells, and it is not the value of externally written data to the cell array, but the data actually held by the memory cells in the cell array. The value of is important.

Next, at time t10 in FIG. 3, the row address strobe RAS is transited from the low level to the high level, at this time, the column address strobe CAS.
The active state of the sense amplifier is released by keeping the low level. The reason for deactivating the sense amplifier is
This is to prevent the data held by the sense amplifier from being overwritten in the second copy data storage cell row CW1 when reading the copy data at time t11 in FIG. At time t11 in FIG. 3, the row address strobe RAS is changed from the high level to the low level to read the data of the second copy data storage cell row CW1. Subsequent operations are performed on the first copy data storage cell row CW.
Since the procedure is the same as that of 0, the description is omitted.

In the present embodiment, the data setting as the copy data can be freely selected for each selected Y switch and sense amplifier, and the restriction that one word is the same data in the conventional example can be avoided. . by this,
The first effect is that various test patterns can be realized so as to be suitable for detecting defective memory cells due to various failure causes. Further, although the test data setting mode is a mode peculiar to the present invention, the individual write operation and read operation use the general operation in the semiconductor memory,
Since no special write operation like the flash write in the conventional example of FIG. 1 is performed, only one Y switch is selected during the write operation, and the write drive circuit and the sense amplifier are selected. Since the same number is provided through the switch, it is possible to avoid the overload of the writing drive circuit that occurs in the flash write and reduce the power consumption, which is a second effect. Further, in the present embodiment, although the time required to first write the page to the copy data storage area is relatively long,
Since the copy data is temporarily stored in the copy data storage area, then read to the sense amplifier and then sequentially copied to desired cell rows of the memory cell portion, the entire set time of the test data can be shortened. In particular, the larger the number of memory cells forming one word is, the third effect is that the setting time of the test data can be significantly shortened as compared with the flash write in the conventional example.

In the first embodiment, the memory cell section 2
Although the memory device in which 00 is composed of 4 × 4 memory cells has been described as an example, the number of address signal lines is increased to make the number of digit line pairs 2 ^m (m is a positive integer of m ≧ 1) and the number of word lines 2 ⁿ (n is a positive integer of n ≧ 2) and the memory cell portion is 2 ^m ×
It is easy to expand to a configuration having 2 ⁿ memory cells. In addition, it is easy to increase the number of copy data storage cell rows included in the copy data storage unit. In the first embodiment, only the address A0 is input to the copy data storage unit word line selection circuit 105. Book (1 ≤ k
An address signal of <a positive integer of n) may be input to the copy data storage word line selection circuit to select one from 2 ^k copy data storage word lines.
Further, in FIG. 1, the memory device in which the input / output bit width of the data from the outside is 1 bit is taken as an example, but the invention can be applied to a memory device having a plurality of bit widths such as the input / output bit width of 8 bits without any trouble. You can

Next, a second embodiment of the present invention will be described with reference to FIGS. 5, 6 and 7. FIG. 5 is a block diagram of the second embodiment. In the first embodiment, a dedicated copy data storage unit is provided in the cell array, and a copy data storage unit word line drive circuit that drives the copy data storage unit is provided. However, in the second embodiment, the copy data storage unit in the cell array 400 is provided. At least a part of the redundant cell section is shared as a copy data storage section and driven by the redundant cell section word line drive circuit 401.
Since the basic configuration is the same as that of the first embodiment, only the changed portion will be described.

FIG. 6 is a diagram showing a detailed configuration of the cell array 400, the sense amplifier column 101, the row address decoder 103, and the redundant cell section word line drive circuit 401. The configurations and operations of the sense amplifier array 101 and the row address decoder 103 are the same as in the first embodiment.
The cell array 400 includes a memory cell section 200 and a redundant cell section 201. In the redundant cell section 201, the redundant cell section shared word lines RCX0, RX1 in place of the redundant cell section word lines RX0, RX1 in the first embodiment. RCX1 is connected. The redundant cell section word line drive circuit 401 enhances the drive capability of the buffer circuit as in the redundant cell section word line drive circuit 111 in the first embodiment, but the redundant word from the redundant cell section word line selection circuit 104 is used. In addition to the selection signals PRX0 and PRX1, the copy data storage unit word line selection signals PCX0 and PCX1 from the copy data storage unit word line selection circuit 105 are input, and the redundant word selection signal PRX0 and the copy data storage unit word line selection signal PCX0 are input. The logical sum is output to the redundant cell section shared word line RCX0, and the logical sum of the redundant word selection signal PRX1 and the copy data storage section word line selection signal PCX1 is output to the redundant cell section word line RCX1. In the second embodiment of FIG. 5, all cell rows of the redundant cell section 201 are shared as cell rows for storing copy data.

FIG. 7 is an operation timing chart when setting the test data in the second embodiment. The basic operation is the same as that of the first embodiment, but at time t1, the redundant cell section shared word line RCX0 is set to the high level, the copy data is written in the corresponding redundant word, and at time t3, the redundancy is performed. The cell part shared word line RCX1 is set to the high level and the copy data is written in the corresponding redundant word. Time t5
Then, the copy data is read from the redundant word corresponding to the redundant cell section shared word line RCX0 to the sense amplifier column 101, copy-written to the memory cell connected to the memory cell section word line X0 at time t7, and at time t9. Copy writing is performed to the memory cell connected to the word line X2 in the memory cell section. Read data for copying from the redundant word corresponding to the redundant cell section shared word line RCX1 to the sense amplifier column 101, copy write to the memory cell connected to the memory cell section word line X0, and write to the memory cell section word line X2. Copy writing to the connected memory cell is similarly performed.

In the second embodiment, the test data setting is limited to the test before the redundant cell portion is replaced with the defective memory cell and used as the original redundant cell, such as the initial defect selection test. Within that limit,
In addition to having the same effect as the first embodiment, there is a new effect that the occupied area of the cell array is small because there is no dedicated copy data storage section in the cell array.

In this embodiment as well, it is easy to increase the number of address signals to expand to a memory cell structure of 2 ^m × 2 ⁿ , as in the first embodiment. Also,
It is also easy to set the number of copy data storage cell rows in the redundant cell section 201 so that a part or all of the redundant cell section word lines are shared with the redundant cell section word lines. That is, the number of redundant cell word lines is set to j (j ≧ 2
If the number of address signals is k (a positive integer of 1 ≦ k ≦ log ₂ j), then one of the 2 ^k redundant cell section shared word lines can be selected by using ^k address signals. Good. Further, it can be applied to a memory device having a plurality of bit widths without any trouble.

Next, a third embodiment of the present invention will be described with reference to FIGS. 8, 9 and 10. FIG. 8 is a block diagram of the third embodiment. In the second embodiment, at least a part of the redundant cell section in the cell array is shared as the copy data storage section, but in the third embodiment, a part of the memory cell section in the cell array 400 is used as the copy data storage section. It is shared and driven by the row address decoder 501. Since the basic configuration is the same as that of the first and second embodiments, only the changed part will be described.

FIG. 9 is a diagram showing a detailed configuration of the cell array 400, the sense amplifier column 101, the row address decoder 501, and the redundant cell section word line drive circuit 111. The configurations and operations of the sense amplifier column 101 and the redundant cell section word line drive circuit 111 are the same as those in the first embodiment, and the cell array 400 is the same as that in the second embodiment and has a memory cell section 200 and a redundant cell section 201. is doing. In the redundant cell section 201, the redundant cell section word line drive circuit 111 to the redundant cell section word line RX0,
A part of the word line connected to the RX1 and connected from the row address decoder 501 to the memory cell section 200 in the cell array 400 is a memory that shares the original memory cell section word line X0 and the copy data storage section word line CX0. The word line XCX0 is changed to the cell section shared word line, and the original memory cell section word line X1 and copy data storage section word line CX1 are changed.
The word line XCX1 is shared with the memory cell shared word line XCX1. From the row address decoder 501, the logical sum of the selection signal of the memory cell section word line X0 from the decoding circuit and the copy data storage section word line selection signal PCX0 is output to the memory cell section common word line XCX0 and the decoding circuit outputs. The logical sum of the selection signal of the memory cell section word line X1 and the copy data storage section word line selection signal PCX1 is output to the memory cell section common word line X1 / CX01. In the third embodiment of FIG. 8, among the four cell rows of the memory cell unit 200, the memory cell unit shared word line XCX0
The cell row composed of the memory cells connected to the memory cell section and the cell row composed of the memory cells connected to the memory cell section common word line XCX1 are shared as a copy data storage section.

FIG. 10 is an operation timing chart of the third embodiment. The basic operation is similar to that of the first embodiment, but at time t1, the shared word line XCX0 of the memory cell section is set to the high level and the copy data is written in the cell row of the corresponding memory cell section, At t3, the word line XCX1 shared by the memory cell parts is set to the high level, and the copy data is written in the cell row of the corresponding memory cell part. At time t5, copy data is read from the cell row corresponding to the memory cell section shared word line XCX0 to the sense amplifier column 101, and at time t7, copy data is written to the cell row connected to the memory cell section word line X2. At time t9, copy data is read from the cell row corresponding to the memory cell section shared word line XCX1 to the sense amplifier column 101.
At 1, the data is written in the cell row connected to the memory cell word line X3.

In the third embodiment, it is necessary to pay attention to the designation of the copy destination address so as not to accidentally overwrite another cell row storing another copy data at the time of executing the copy writing. It has the same effect as that of the first embodiment,
In addition, since the dedicated copy data storage section is not included, the occupied area of the cell array is small, and since the redundant cell section is not used for the copy data storage section, the test data can be set even when the redundant cell is replaced with the defective cell. There is a new effect.

In this embodiment, the word line shared by the memory cells which shares the original word line and the copy data storage word line is designated by the address signal input to the copy data storage word line selection circuit 105. The number and position can be freely set within the range. That is, assuming that there are eight address signals A0 to A7, and the address signal A0 and the address signal A7 are input to the copy data storage cell row 105, (A7, A6, A
5, A4, A3, A2, A1, A0) = (0,0,0,
The word line corresponding to (0,0,0,0,0), (A7, A
6, A5, A4, A3, A2, A1, A0) = (0,
0,0,0,0,0,0,1) corresponding to the word line,
(A7, A6, A5, A4, A3, A2, A1, A0)
= (1,0,0,0,0,0,0,0) and the word line corresponding to (A7, A6, A5, A4, A3, A)
2, A1, A0) = (1,0,0,0,0,0,0,
Part or all of the four word lines corresponding to 1) can be used as the word line shared by the memory cells. The drive unit of the word lines corresponding to these addresses in the row address decoder is the row address decoder 501 of FIG.
Similarly, it is constituted by the logical sum of the word line selection signal from the decoding circuit and the selection signal from the copy data storage section word line selection circuit 105.

Also in this embodiment, it is easy to increase the number of address signals to expand to the configuration of 2 ^m × 2 ⁿ memory cells, as in the first and second embodiments. Further, it can be applied to a memory device having a plurality of bit widths without any trouble, as in the first and second embodiments.

[0078]

As described above, according to the present invention, one word can be collectively written in the test data setting mode, so that the test data setting time can be set similarly to the conventional memory device having the flash write function. It can be shortened. In addition to this, the present invention has three new effects.

The first point is that the data setting as copy data can be freely selected for each selected Y switch and sense amplifier, and the limitation that one word is the same data in the conventional example can be avoided. This makes it suitable for detecting defective memory cells due to various causes,
The point is that various test patterns can be realized.

The second point is that only one Y switch is selected during the write operation, and the same number of write drive circuits and sense amplifiers are provided via the selected Y switch. This is because it is possible to avoid overload of the embedded drive circuit and reduce power consumption.

The third point is that once the copy data is once stored in the copy data storage area, it is read out to the sense amplifier and then copied to the desired cell rows of the memory cell section one after another. The larger the number of memory cells that are configured, the more the set time of test data can be significantly shortened as compared with the conventional example having the flash write function.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration of a cell array, a sense amplifier row, and a Y switch row according to the first embodiment.

FIG. 3 is an operation timing chart when setting test data according to the first embodiment.

4A is a circuit diagram of a RAS / CAS circuit 106, FIG. 4B is a circuit diagram of a copy data storage word line selection circuit 105, and FIG. 4C is a column address decoder 107. It is a figure which shows a structure.

FIG. 5 is a block diagram of a second embodiment.

FIG. 6 is a diagram showing a detailed configuration of a cell array 400, a sense amplifier column 101, a row address decoder 103, and a redundant cell section word line drive circuit 401.

FIG. 7 is an operation timing chart when setting test data according to the second embodiment.

FIG. 8 is a block diagram of a third embodiment.

9 is a diagram showing a detailed configuration of a cell array 400, a sense amplifier column 101, a row address decoder 501 and a redundant cell section word line drive circuit 111. FIG.

FIG. 10 is an operation timing chart when setting test data according to the third embodiment.

FIG. 11 is a block diagram of a conventional memory device.

FIG. 12 is a diagram showing an internal configuration of a cell array 600 of a conventional example and connections between a peripheral row address decoder 103, a redundant cell section word line drive circuit 111 and a sense amplifier column 101.

13A is a diagram showing a configuration of a RAS / CAS circuit 601 in a conventional example, and FIG. 13B is a diagram showing a configuration of a column address decoder 602 in the conventional example.

FIG. 14 is an operation timing chart of a conventional flashlight.

[Explanation of symbols]

100,400 cell array 101 sense amplifier row 102 Y switch row 103,501 Row address decoder 104 redundant cell section word line selection circuit 105 copy data storage unit word line selection circuit 106 RAS / CAS circuit 107 column address decoder 108 Drive circuit for writing 110 entry circuit 111,401 Redundant cell section word line drive circuit 112 copy data storage unit word line drive circuit 200 memory cell section 201 redundant cell section 202 copy data storage A0, A1 address signal CAS column address strobe CONT control signal CX0, CX1 Copy data storage word line RAS row address strobe RCS row / column switching signal RX0, RX1 Redundant cell word line RCX0, RCX1 Redundant cell section shared word line SE sense amplifier activation signal WE write enable signal WNS Word line deselection signal X0, X1, X2, X3 Memory cell word line XCX0, XCX1 Shared word line for memory cells Y0, Y1, Y2, Y3 Y switch selection signal

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) G01R 31/28 V F Term (Reference) 2G132 AA08 AB01 AG01 AH01 AK07 AL09 AL12 5L106 AA01 CC02 CC11 CC17 CC21 CC32 DD06 GG05 GG07 5M024 AA04 AA90 BB20 BB30 BB40 CC22 CC82 CC96 MM04 MM12 MM15 PP01 PP02 PP03 PP07

Claims (12)

[Claims] 1. A state control section for setting first, second and third states of a test data setting mode based on an input signal from the outside, and a plurality of memory cell section word lines and a plurality of digit line pairs. Memory cell section including a plurality of selectively selectable memory cells, and in the first and second states, all the memory cell section word lines are unselected, and in the third state, the address signal is used as a row address for the memory cell section word lines. A row address decoder for selecting and driving one line; a copy data storage unit including a copy data storage cell which is selectively selectable by a copy data storage cell unit word line and the plurality of digit line pairs; In the second state, one of the copy data storage word lines is selected and driven based on a predetermined portion of the address signal, and in the third state, all the copy data are written. And copying the data storage unit word line selection drive circuit for a non-selected storage section word line, first provided corresponding to said plurality of digit line pairs, the second
And a sense amplifier row including a plurality of sense amplifiers that are in an operating state in the third state, and a column address decoder that selects one pair from the plurality of digit line pairs by using an address signal as a column address when writing data in the first state, It has a Y switch row and a write drive circuit that inputs data from the outside in the first state and transfers it to the Y switch row. In the first state, the write drive circuit, the Y switch row, and the sense amplifier row from the outside. The data input via the copy data storage unit is written in the copy data storage cell row connected to the word line, and in the second state, the copy data stored in the copy data storage cell row is read out and held in the sense amplifier column. However, in the third state, the copy data held in the sense amplifier row is transferred to the memory cell section cell connected to the memory cell section word line. Memory device, characterized in that the copy write to. 2. When the row / column switching signal is at the first signal level and the word line deselection signal is at the inactive level, the address signal is input as n (n ≧ 2 positive integer) row addresses. A row address decoder that selects and drives one of the 2 ⁿ memory cell word lines based on the above, and deselects all the memory cell word lines when the word line deselection signal is at an active level, It is provided corresponding to 2 ⁿ memory cell word lines
A memory cell portion having 2 ⁿ memory cell rows, each of which includes 2 ^m memory cells, one of which is selected based on (m ≧ 1 positive integer) column addresses, and test data. If the column address strobe is at the first input level when the row address strobe changes in a predetermined direction in the setting mode, a predetermined k (1 ≦ k <n positive integer) of n address signals If one of the 2 ^k copy data storage word lines is selected and driven based on the address signal and the row address strobe changes in a predetermined direction and the column address strobe is at the second input level, all Copy data storage word line selection drive circuit for deselecting the copy data storage word lines of the above, and m columns provided corresponding to 2 ^k copy data storage word lines 1 is selected based on the address 2
A copy data storage unit including 2 ^k rows of copy data storage cell rows each including ^m copy data storage cells in each cell row, and a sense amplifier activation signal provided corresponding to each of the 2 ^m column cell columns. A sense amplifier row including 2 ^m sense amplifiers that are in an active state when at an active level, and an address signal that is input as m column addresses when the row / column switching signal is at a second signal level. Based on the column address decoder and Y switch column that select one column from the 2 ^m columns based on this, and the column address strobe receives the first input when a change in the row address strobe in the predetermined direction is detected in the test data setting mode. If the level is set, the row / column switching signal is set to the first signal level and the word line deselection signal is set to the active level. If the column address strobe is at the second input level when a change in the row address strobe in the predetermined direction is detected after the sense amplifier activation signal is output as the active level after a predetermined time delay, the row / column The switching signal is set to the first signal level, the word line deselection signal is set to the inactive level, and after a predetermined time delay, the sense amplifier active signal is output as the active level to change the column address strobe in the predetermined direction. Has a RAS / CAS circuit that outputs the row / column switching signal as a second signal level when detecting, and a write drive circuit that transfers the input data to the Y switch train when the write enable signal is at the active level. However, when the row address strobe changes in the specified direction, the column add In the first state in which the rest strobe is at the first input level and the write enable signal is at the active level, the data input via the Y switch row and the sense amplifier row is written to the copy data storage cell row, and the row address strobe is set to a predetermined value. In the second state in which the column address strobe is at the first input level and the write enable signal is at the inactive level when changing in the direction of, the copy data stored in the copy data storage cell row is read to the sense amplifier row. When the row address strobe changes in a predetermined direction, the copy data held in the sense amplifier column is copied and written in the memory cell section cell row in the third state in which the column address strobe is at the second input level. A memory device characterized by the above. 3. The memory cell row of the memory cell section comprises:
A first memory cell connected to the positive digit line of the digit line pair, alternating with memory cells connected to the positive digit line of the digit line pair and memory cells connected to the inversion digit line; Memory cell row and the memory cell connected to the inversion side digit line of the digit line pair and the memory cell connected to the inversion side digit line of the digit line pair and the memory cell connected to the positive side digit line alternately. A second row of memory cells arranged, and the copy data storage cell row of the copy data storage section starts from the copy data storage cell connected to the positive digit line of the digit line pair, A first copy data storage cell in which copy data storage cells connected to the positive digit line and copy data storage cells connected to the inversion digit line are alternately arranged. And a copy data storage cell connected to the reverse digit line of the digit line pair and a copy data storage cell connected to the positive digit line of the digit line pair. 3. The memory device according to claim 2, further comprising alternating second copy data storage cell rows. 4. A state controller for setting the first, second and third states of the test data setting mode based on an input signal from the outside, and a plurality of memory cell section word lines and a plurality of digit line pairs. Memory cell section including a plurality of selectively selectable memory cells, and in the first and second states, all the memory cell section word lines are unselected, and in the third state, the address signal is used as a row address for the memory cell section word lines. A row address decoder that selects and drives one line, and a redundant cell section that includes a redundant cell section that can be selectively selected by a word line and a plurality of digit line pairs and that is used for replacement and repair when a memory cell fails And a redundant cell section word line selection circuit for selecting and outputting a redundant cell section word line which is replaced with the memory cell section word line of the defective cell when the memory cell fails, In the 1st and 2nd states, one of the redundant cell section word lines which is also shared as a word line for designating a cell column for storing copy data is selected based on a predetermined portion of the address signal. Of the copy data storage word line selection circuit that outputs all the redundant cell part shared word lines as non-selected in the third state, and the output of the redundancy cell part word line selection circuit and the copy data storage part word line selection circuit. A redundant cell section word line drive circuit for inputting the output and driving the redundant cell section common word line selected by the copy data storage section word line selection circuit; and a first provided for the plurality of digit line pairs. Second
And a sense amplifier row including a plurality of sense amplifiers that are in an operating state in the third state, and a column address decoder that selects one pair from the plurality of digit line pairs by using an address signal as a column address when writing data in the first state, It has a Y switch row and a write drive circuit that inputs data from the outside in the first state and transfers it to the Y switch row. In the first state, the write drive circuit, the Y switch row, and the sense amplifier row from the outside. The data input via the cell line connected to the word line shared by the redundant cell section is written into the cell row connected to the word line shared by the redundant cell section, and the copy data stored in the cell row connected to the word line shared by the redundant cell section is transferred to the sense amplifier column. In the third state, the copy data held in the sense amplifier column is read and stored in the memory cell section cell row connected to the memory cell section word line. Memory device, characterized in that the copy write. 5. An address signal is input as n (n.gtoreq.2 positive integer) row addresses when the row / column switching signal is at the first signal level and the word line deselection signal is at the inactive level. A row address decoder that selects and drives one of the 2 ⁿ memory cell word lines based on the above, and deselects all the memory cell word lines when the word line deselection signal is at an active level, It is provided corresponding to 2 ⁿ memory cell word lines
A memory cell portion having 2 ⁿ memory cell rows each including 2 ^m memory cells, one of which is selected based on (m ≧ 1 positive integer) column addresses, and j ( (a positive integer of j ≧ 2) redundant cell section word lines and a redundant cell section which is selectively selectable by the plurality of digit line pairs and includes a redundant cell for replacement and repair when a memory cell fails, and a memory cell When a row address strobe changes in a predetermined direction in the test data setting mode, and a redundant cell word line selection circuit that selects and outputs a redundant cell word line that replaces the memory cell word line of the defective cell at the time of the failure of If the column address strobe is at the first input level, 2 ^k (1 ≦ k ≦ l) which is also shared as a word line for designating a cell column for storing copy data among j redundant cell word lines (positive integer of og ₂ j) One redundant cell section shared word line is selected based on a predetermined k address signals out of n address signals from the redundant cell section shared word lines, and a row address strobe is predetermined. When the column address strobe is at the second input level when changing to the direction of, the copy data storage word line selection circuit that deselects all the copy data storage word lines and the redundant cell word line selection circuit 2 ^m column and a redundant cell section word line drive circuit for driving the redundant cell section shared word line selected by the copy data storage section word line selection circuit a sense amplifier comprising a 2 ^m-number of sense amplifiers in an operating state when the sense amplifier activation signal provided corresponding to each of the cell columns of the active level of When a column address decoder and Y switch array for selecting one column from cell column enter the address signal as the m column addresses 2 ^m columns on this basis when the row / column switch signal a second signal level And when the change in the row address strobe in the predetermined direction is detected in the test data setting mode and the column address strobe has the first input level, the row / column switching signal is set to the first signal level and the word line is set. The column address strobe receives the second input when the deselect signal is set to the active level and the sense amplifier activation signal is output as the active level after a predetermined time delay to detect a change in the row address strobe in the predetermined direction. If it is a level, the row / column switching signal is set to the first signal level and the word line is not selected. Of the row / column switching signal when the change of the column address strobe in a predetermined direction is detected by outputting the sense amplifier active signal as an active level after a predetermined time delay and a predetermined time delay. RAS / CAS circuit for outputting as a signal level of FF and a write drive circuit for transferring the input data to the Y switch row when the write enable signal is at the active level, and when the row address strobe changes in a predetermined direction. In the first state in which the column address strobe is at the first input level and the write enable signal is at the active level, the data input via the Y switch row and the sense amplifier row is used for the cell row connected to the redundant cell section shared word line. The row address strobe changes in the specified direction. In the second state in which the column address strobe is at the first input level and the write enable signal is at the inactive level, the copy data stored in the cell row connected to the word line shared by the redundant cell section is sent to the sense amplifier column. When the row address strobe is read and held, and the column address strobe is at the second input level when the row address strobe changes in the predetermined direction, the copy data held in the sense amplifier column is copied to the memory cell section cell row in the third state. A memory device for writing. 6. The memory cell row of the memory cell section comprises:
A first memory cell connected to the positive digit line of the digit line pair, alternating with memory cells connected to the positive digit line of the digit line pair and memory cells connected to the inversion digit line; Memory cell row and the memory cell connected to the inversion side digit line of the digit line pair and the memory cell connected to the inversion side digit line of the digit line pair and the memory cell connected to the positive side digit line alternately. The shared cell row including the arranged second memory cell row and connected to the redundant word line shared word line starts from the redundant cell connected to the positive digit line of the digit line pair and the digit line pair. A redundant cell connected to the positive digit line and a redundant cell connected to the inversion digit line of the first shared cell row and the inversion digit line of the digit line pair A second shared cell row in which redundant cells connected to the inversion digit line of the digit line pair and redundant cells connected to the positive digit line are arranged alternately, starting from a long cell; The memory device according to claim 5. 7. A state control section for setting the first, second and third states of the test data setting mode based on an input signal from the outside, and a plurality of memory cell section word lines and a plurality of digit line pairs. Memory cell section including a plurality of memory cells that can be selectively selected, and a memory cell section that is also shared as a word line that specifies a cell column for storing copy data among the word lines in the first and second states A copy data storage word line selection circuit that selects and outputs one of the shared word lines based on an address signal, and a memory cell part that corresponds to the output from the copy data storage word line selection circuit in the first and second states A row address decoder that selects and drives a word line and, in the third state, selects and drives one of the memory cell word lines using the address signal as a row address. , A first digit provided corresponding to the plurality of digit line pairs, a second digit
And a sense amplifier row including a plurality of sense amplifiers that are in an operating state in the third state, and a column address decoder that selects one pair from the plurality of digit line pairs by using an address signal as a column address when writing data in the first state, It has a Y switch row and a write drive circuit that inputs data from the outside in the first state and transfers it to the Y switch row. In the first state, the write drive circuit, the Y switch row, and the sense amplifier row from the outside. The data input via the memory cell section is written in the cell row connected to the word line shared by the memory cells,
In the state, the copy data stored in the cell row connected to the word line shared by the memory cell section is read and held in the sense amplifier column, and in the third state, the copy data held in the sense amplifier column is stored in the memory cell section word. A memory device characterized in that copy writing is performed in a memory cell section cell row connected to a line. 8. n (n ≧ 2 positive integer) row addresses
2 specified by ⁿIt corresponds to the word line of the memory cell section of the book
M (m ≧ 1 positive integer) column addresses
1 is selected based on 2^mMemory cells it
2 included in each cell rowⁿMemo with row memory cell row
The re-cell part, The row address strobe is located in the test data setting mode.
When changing to a fixed direction, the column address strobe
If it is the first input level, of the memory cell word lines
As a word line that specifies a cell column for storing copy data
Address one of the shared word lines of the memory cell section that is also shared
Selection of copy data storage word line selection based on
Optional drive circuit, When the row / column switching signal is at the first signal level, the word line
The address signal is sent when the selection signal is at the inactive level.
No. is input as n row addresses and based on this, 2ⁿ
Before selecting and driving one of the memory cell word lines
When the word line deselection signal is at active level,
Output from the word line selection circuit
The lower row that selects and drives the shared word line of the memory cell
Dress decoder, Two^mA sense array is provided for each cell row.
Operation is activated when the pump activation signal is at the active level.
2^mA sense amplifier array including individual sense amplifiers, In the row address strobe in the test data setting mode
When a change in the fixed direction is detected, the column address
If the lobe is the first input level, the row / column disconnection
The exchange signal is set to the first signal level and the word line deselection signal
Signal to the active level and
After that, set the sense amplifier activation signal to the active level.
Outputs the change in the row address strobe in the specified direction.
The column address strobe is the second input when detected
If it is a level, the row / column switching signal is the first signal.
Set to level and inactivate the word line deselection signal
Set the level and after a certain time delay, sense
Output the pump activation signal as an active level
When a change in the dress strobe in the specified direction is detected
The row / column switching signal as a second signal level
RAS / CAS circuit for output, Input when the write enable signal is active level
Write drive circuit that transfers the force data to the Y switch string.
Then When the row address strobe changes in the specified direction
The column address strobe is at the first input level and
The first state where the write enable signal is active level
Is input via the Y switch row and the sense amplifier row.
Connected data to the shared word line cell of the memory cell section.
Cell row and write the row address strobe
Column address strobe is first when changing direction
Input level and the write enable signal is
In the second state of the active level, the word shared by the memory cells
The copy data stored in the cell row connected to the line is saved.
Read out and hold it in the row of sense amplifiers, and
Column address strobe when the
In the third state, where the lobe is at the second input level, the sense amplifier is
Copy data stored in the memory cell column
A memory device characterized by copying and writing to a row. 9. The memory cell row of the memory cell portion comprises:
A first memory cell connected to the positive digit line of the digit line pair, alternating with memory cells connected to the positive digit line of the digit line pair and memory cells connected to the inversion digit line; Memory cell row and the memory cell connected to the inversion side digit line of the digit line pair and the memory cell connected to the inversion side digit line of the digit line pair and the memory cell connected to the positive side digit line alternately. A second memory cell row arranged, and the shared cell row connected to the shared word line of the memory cell section starts from a memory cell connected to the positive digit line of the digit line pair, and a digit line pair Connected to the first shared cell row in which the memory cells connected to the positive digit line and the memory cells connected to the inverted digit line are alternately arranged and the inverted digit line of the digit line pair. A second shared cell row in which the memory cells connected to the inversion side digit line of the digit line pair and the memory cells connected to the positive side digit line are alternately arranged. 9. The memory device according to claim 8, wherein the memory device is a memory device. 10. A copy including a plurality of memory cell section cell rows including memory cells provided corresponding to a plurality of digit line pairs, and a copy data storage cell provided corresponding to the plurality of digit line pairs. A test data setting method for a memory device comprising a data storage cell row and a sense amplifier column including a sense amplifier provided corresponding to the plurality of digit line pairs, wherein copy data is stored in a copy data storage cell row. A procedure for sequentially writing cell by cell, a procedure for simultaneously reading and holding the copy data stored in the copy data storage cell row in the sense amplifier column, and a procedure for writing the copy data held in the sense amplifier column to the cells of the memory cell section A method of setting test data, which comprises a step of collectively writing in a row. 11. A plurality of memory cell section cell rows including memory cells provided corresponding to a plurality of digit line pairs, and when a memory cell provided corresponding to the plurality of digit line pairs has a failure. Memory including a plurality of redundant cell section cell rows for replacing and repairing a memory cell section cell row including a defective cell, and a sense amplifier column including sense amplifiers provided corresponding to the plurality of digit line pairs A method for setting test data of an apparatus, wherein at least a part of a plurality of redundant cell section cell rows is used as a cell row for storing copy data, copy data is sequentially written for each cell, and a cell row for storing copy data. Redundant cell section used as a procedure to read and hold the copy data from the cell row to the sense amplifier column all at once, and the copy data held in the sense amplifier to the memory cell. Test data setting method characterized by having a step of copying write collectively in a cell line of. 12. A plurality of memory cell section cell rows including memory cells provided corresponding to a plurality of digit line pairs, and a sense amplifier column including sense amplifiers provided corresponding to the plurality of digit line pairs. A method for setting test data of a memory device comprising: a step of sequentially writing copy data for each cell by using a part of a plurality of memory cell section cell rows as a cell row for storing copy data; and storing the copy data. Memory cell section used as a cell row Procedure for simultaneously reading out and holding copy data from the cell row to the sense amplifier column, and copying and writing collectively the copy data held in the sense amplifier to the memory cell section cell row A test data setting method, comprising: