JP2003036183A5 - - Google Patents

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Publication number
JP2003036183A5
JP2003036183A5 JP2002139368A JP2002139368A JP2003036183A5 JP 2003036183 A5 JP2003036183 A5 JP 2003036183A5 JP 2002139368 A JP2002139368 A JP 2002139368A JP 2002139368 A JP2002139368 A JP 2002139368A JP 2003036183 A5 JP2003036183 A5 JP 2003036183A5
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JP
Japan
Prior art keywords
vector
circuit
test
combined
input vector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002139368A
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English (en)
Japanese (ja)
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JP2003036183A (ja
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Publication date
Priority claimed from US09/873,874 external-priority patent/US6718498B2/en
Application filed filed Critical
Publication of JP2003036183A publication Critical patent/JP2003036183A/ja
Publication of JP2003036183A5 publication Critical patent/JP2003036183A5/ja
Withdrawn legal-status Critical Current

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JP2002139368A 2001-06-04 2002-05-15 統合デバッグ回路を利用する集積回路の試験方法 Withdrawn JP2003036183A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/873,874 2001-06-04
US09/873,874 US6718498B2 (en) 2001-06-04 2001-06-04 Method and apparatus for the real time manipulation of a test vector to access the microprocessor state machine information using the integrated debug trigger

Publications (2)

Publication Number Publication Date
JP2003036183A JP2003036183A (ja) 2003-02-07
JP2003036183A5 true JP2003036183A5 (https=) 2005-09-15

Family

ID=25362502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002139368A Withdrawn JP2003036183A (ja) 2001-06-04 2002-05-15 統合デバッグ回路を利用する集積回路の試験方法

Country Status (2)

Country Link
US (1) US6718498B2 (https=)
JP (1) JP2003036183A (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7111199B2 (en) * 2002-07-08 2006-09-19 Lsi Logic Corporation Built-in debug feature for complex VLSI chip
US7127649B2 (en) * 2003-06-09 2006-10-24 Stmicroelectronics, Inc. Smartcard test system and related methods
TWI369652B (en) * 2008-04-25 2012-08-01 Novatek Microelectronics Corp Data transformation method and related device for a testing system
US8219947B2 (en) * 2008-09-15 2012-07-10 Synopsys, Inc. Method and apparatus for merging EDA coverage logs of coverage data
JP5412667B2 (ja) * 2008-12-26 2014-02-12 独立行政法人産業技術総合研究所 積層ｌｓｉチップのシステム検査のための方法および検査システム
US8729981B2 (en) * 2011-05-12 2014-05-20 Colby Instruments, Inc. Precision delay line instrument
US8543953B2 (en) * 2012-01-04 2013-09-24 Apple Inc. Automated stimulus steering during simulation of an integrated circuit design

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3927371A (en) * 1974-02-19 1975-12-16 Ibm Test system for large scale integrated circuits
US5745501A (en) * 1995-10-20 1998-04-28 Motorola, Inc. Apparatus and method for generating integrated circuit test patterns
US5859962A (en) * 1995-12-21 1999-01-12 Ncr Corporation Automated verification of digital design
JP2921502B2 (ja) * 1996-08-19 1999-07-19 日本電気株式会社 順序回路の故障箇所推定方法
US5867644A (en) 1996-09-10 1999-02-02 Hewlett Packard Company System and method for on-chip debug support and performance monitoring in a microprocessor
US5818850A (en) 1996-12-20 1998-10-06 Hewlett-Packard Company Speed coverage tool and method
US6269319B1 (en) * 1999-01-29 2001-07-31 The Mcdonnell Douglas Corporation Reconfigurable integration test station

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