JP2003032234A - Frame synchronization system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frame synchronization system, capable of regenerating normal information, when a line recovers from a trouble. SOLUTION: The frame synchronization system comprises a first unit (31), having a scramble circuit (3114 ) for scrambling reference information (a1) transmitted from outside to transmit the scrambled reference information (a1) and a second unit (32), having a descramble circuit (3215 ) for descrambling the scrambled reference information (a1) from the first unit (31), to transmit the descrambled reference information (a1). The first unit (31) constructs the scrambled reference information (a1) to form frames and transmits them. The second unit (32) detects a line trouble, based on the synchronizing condition of the transmitted frames, and controls the first unit (31), so as to transmit the reference information (a1) transmitted from outside after recovery of the line from trouble. Thus this frame synchronization system can regenerate the reference information (a1) transmitted from outside, when the line recovers from the trouble.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is currently T1X1.5.
Is a frame format aimed at standardization in G
generic Framing Procedure
(GFP), and more particularly to a frame synchronization method.

[0002]

2. Description of the Related Art GFP is an SDL (Simple Da
ta Link), UDL (Universal Da)
ta Link), HDT (Hybrid Data)
It is one of the Layer2 encapsulation techniques like Transport) and provides a common frame format for efficiently allocating various Layer2 payloads.

As shown in FIG. 8A, a GFP frame has a core header, a payload, and optionally an FCS (Frame Check Sequence).
e) and. For frame synchronization, HEC (Header Error) contained in the core header is used.
information (packet), which is established by r Control) and is contained in the payload. The payload is scrambled and transferred to ensure security.

[0004] For GFP frame detection, G of FIG.
As shown in the FP frame detection state transition diagram, when synchronization is lost, the Hunt state is set and Bit-by-Bit is set.
To find the HEC position. If the HEC positions match, Pr
e-Sync state transition to Frame-by-Frame
The check at e is done. Therefore, HE consecutively N times
When C is detected, the state becomes Sync. In the frame synchronization method based on GFP, when synchronization is lost, synchronization is achieved using HEC of GFP (contained in the core header) as shown in the state transition diagram of FIG. In the frame synchronization method based on GFP, after a synchronization state is reached, a break for each frame is determined, and if the payload and FCS are defined, the FCS is also extracted and descrambled.

However, in the conventional frame synchronization system using GFP, when a line break occurs during transmission and the line is restored later, the scramble of GFP must be closed for each frame as shown in FIG. 8 (a). However, since it is a method of transmitting by scrambling continuously from the previous frame, the GFP frame that arrives first and carries valid information cannot be descrambled normally, and an error always occurs. There is.

As a main cause of this problem, as shown in FIG. 8B, a frame (called an idle frame) flowing when information is not transferred has only a core header. This is because the descrambles cannot be synchronized.

Such a problematic phenomenon occurs when the line is restored from the disconnected state. Here, as shown in FIG. 8C, the information transfer 1 is externally sent to the transmission side between points P0 and P3, and the information transfer 2 is externally sent to the transmission side between points P7 and P10. It is point P16
It is assumed that the information transfer 3 is sent from the outside to the sending side during −P19. Information transfer 1, information transfer 2, and information transfer 3 are
Corresponds to transmission information (packet). FIG. 8D is a timing chart showing information transmission on the receiving side. Figure 8
(E) is a timing chart showing the synchronization state of the GFP frame. At point P4 ′, a line failure occurs after the receiving side transfers the information transfer 1 to the outside,
At point P12 ′, it is assumed that the line failure is recovered before the information transfer 3 is sent from the outside to the transmission side.

First, the line is disconnected at point P4 ', and the GFP (with information) is transmitted from the transmission side to the reception side.
If the frame cannot be transmitted during that time (point P4 '
The information at point P12 ') (information transfer 2) is discarded. After that, when the line is restored (point P12 '),
Normal information (information transfer 3) is transmitted from the sending side to the receiving side, but since the descramble condition is not satisfied at the receiving side, the information (information transfer 1) received immediately before is used as the basis. Since it is descrambled, the information of the first frame (information transfer 3) cannot be reproduced. After the line is restored, information (information transfer 3) is not transmitted for a while, and only idle frames continue to flow (point P13 to point P16), and valid information is sent to the transmitting side at point P16. Even if it comes, the receiving side cannot always reproduce the information of the first frame (information transfer 3). Even if there is a time lag between the recovery time and the transmission time, the problem phenomenon occurs. Even if the line looks normal, there is a phenomenon that information cannot be sent properly. Therefore, there is a demand for a frame synchronization method capable of reproducing normal information when the line failure is restored.

Further, Japanese Laid-Open Patent Publication No. 63-226145 discloses a scrambled binary type transmission system which scrambles and transmits a signal obtained by adding a data signal sequence to a frame synchronization signal. In this scrambled binary type transmission system, the device on the transmission side is provided with means for resetting the scrambling circuit each time a signal is transmitted by adding a data signal sequence to the frame synchronization signal,
The device on the receiving side is provided with a sync detection pattern output circuit that outputs the same frame sync detection pattern as the transmitted scrambled sync signal and a register that temporarily stores the received signal, and these outputs match. It is characterized in that a means for resetting the descrambling circuit for judging whether or not to perform the determination and, when they match, reset the signal output from the register is provided.

Further, Japanese Patent Laid-Open No. 62-136937 discloses a descramble circuit in a demodulator of a PCM communication system. The descrambling circuit includes a PN sequence generator that generates the same PN sequence signal as the PN sequence signal used when performing the exclusive OR operation when scrambling the scramble signal input from the outside, and P.
A gate circuit that detects a specific state of the shift register train constituting the N-series generator and outputs a positive logic frame detection signal, and an OR operation of a positive logic frame synchronization signal input from the outside and the output of the gate circuit And an exclusive OR gate for performing an exclusive OR operation of the scramble signal input from the outside and the PN series signal output from the PN series generator. It is characterized by that.

Further, in Japanese Patent Laid-Open No. 13146/1990,
The intermediate relay system uses an output obtained through a self-synchronizing scramble circuit for an intermediate relay station auxiliary signal or a receiving terminal station auxiliary signal to a subsequent frame-configured subsequent station, and a frame configured subsequent signal. A means for selecting and outputting the main signal to be transmitted from the transmitting end station to the receiving end station by multiplexing the auxiliary signal for the intermediate relay station or the auxiliary signal for the receiving end station to the receiving end station is provided by the control of the frame synchronizing circuit of the main signal. , The receiving end station is provided with an auxiliary signal separated from the main signal received by the control of the frame synchronization circuit of the received main signal, and an output obtained by passing the received main signal through the self-synchronous descramble circuit. A digital signal transmission system is disclosed in which a means for reproducing the auxiliary signal for the receiving end station is provided after selecting the received main signal by controlling the frame synchronizing circuit.

According to this digital signal transmission method, when signal transmission between certain stations is interrupted, an intermediate relay station located after this station transmits an auxiliary signal for intermediate relay station to a subsequent frame-configured intermediate relay station or After scrambling the receiving end station auxiliary signal at the main signal transmission speed, it is output to the main signal route under the control of the frame synchronization circuit, and the main signal received at the receiving end station is descrambled at the main signal transmission speed. It is characterized in that the signal is converted into a signal, and the descrambled signal is selected by the control of the frame synchronization circuit and input to the auxiliary signal reproduction circuit.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame synchronization system capable of reproducing normal information when a line fault is restored.

Another object of the present invention is to provide a frame synchronization system capable of initializing the descramble arithmetic circuit on the receiving side and the scramble arithmetic circuit on the transmitting side when a line failure occurs. To do.

Still another object of the present invention is to provide a frame capable of canceling the initialization of the descramble arithmetic circuit on the receiving side and canceling the initialization of the scramble arithmetic circuit on the transmitting side when the line fault is restored. It is to provide a synchronization method.

[0016]

[Means for Solving the Problems] Means for solving the problems will be described below with reference to the numbers and symbols used in the embodiments of the present invention. These numbers and signs are added to clarify the correspondence between the description in [Claims] and the description in [Embodiment of the Invention], but in [Claims] It should not be used to interpret the technical scope of the described invention.

The frame synchronization system of the present invention includes a first device (31) and a second device (32). First device (3
1) includes a scramble circuit (31 ₁₄ ) for scrambling the reference information (a1) transmitted from the outside, and transmits the scrambled reference information (a1). The second device (32) includes a descramble circuit (32 ₁₅ ) that descrambles the scrambled reference information (a1) from the first device (31), and the descramble circuit (32).
₁₅ ) The reference information (a1) descrambled by (1) is transmitted. The first device (31) constructs and transmits the scrambled reference information (a1) in a frame. The second device (32) detects the line abnormality based on the synchronization state of the transmitted frame and transmits the reference information (a1) transmitted from the outside after the line abnormality is recovered. Control (31). Thus, the frame synchronization method of the present invention can reproduce the reference information (a1) transmitted from the outside when the line failure (line abnormality) is recovered.

When the line is abnormal, the second device (32) initializes the descramble circuit (32 ₁₅ ) and notifies the first device (31) of the line abnormality. First device (31)
Initializes the scramble circuit _{(31 14)} on the basis of the line abnormality notification from the second device (32).

The second device (32) cancels the initialization of the descramble circuit (32 ₁₅ ) at the time of restoration, and the first device (32)
Notify the device (31) of the restoration. The first device (31) is
To release the initialization of the scrambling circuit (31 ₁₄₎ based on the restoration of the notification from the second device (32).

The frame is a GFP frame. Second
When the line is abnormal, the device (32) initializes the descramble circuit (32 ₁₅ ), generates a GFP frame including an OAM message indicating the error, and then the first device (3).
Notify line abnormality to 1). The first device (31) is the second
Analyze the contents of the OAM message from the device (32),
As a result of the analysis, if the contents of the OAM message is abnormal, to initialize the scrambling circuit _{(31 14).} Further, the second device (32) cancels the initialization of the descramble circuit (32 ₁₅ ) at the time of restoration, and indicates O as the restoration.
First, a GFP frame including an AM message is generated, and
Notify the device (31) of the restoration. The first device (31) is
The content of the OAM message from the second device (32) is analyzed, and as a result of the analysis, if the content of the OAM message is restored, the initialization of the scramble circuit (31 ₁₄ ) is released.

The frame is a SONET frame.
When the line is abnormal, the second device (32) initializes the descrambling circuit (32 ₁₅ ) and stores the alarm transfer indicating the abnormality in the SONET frame, and the first device (3)
Notify line abnormality to 1). The first device (31) is the second
It initializes the scramble circuit (31 ₁₄₎ on the basis of the alarm forwarding indicating an abnormality from the device (32). The second device (32) has a descrambling circuit (32) at the time of restoration.
₁₅ ) The initialization is canceled and the alarm transfer indicating the recovery is accommodated in the SONET frame, and the first device (31)
Notify the recovery. The first device (31) is connected to the second device (3
To release the initialization of the scrambling circuit (31 ₁₄₎ on the basis of the alarm forwarding illustrating restoration from 2).

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A frame synchronization system based on GFP will be described below as an embodiment of the frame synchronization system of the present invention.
A description will be given with reference to the drawings.

The GFP frame shown in FIG. 1 has a core header, a payload, and an optional FCS.
(Frame Check Sequence). The frame synchronization is performed by the HEC (Header Error Con) contained in the core header.
information (packet) established in the payload and stored in the payload. The payload is scrambled and transferred to ensure security. Since the scramble is calculated based on the information immediately before, the continuity is maintained and the scramble is transferred.

Further, the payload has a mechanism that not only allows information to be entered but also allows the frame to be hierarchized. As shown in FIG. 1, there is a mechanism for accommodating a payload header for more detailed management. To simplify
The P frame format will be described as being transferred with the configuration of the core header, payload (information only), and FCS. Here, the core header is a PLI (PDU Length Indicator) indicating the frame length.
And cHEC (Core Header Error C
It is assumed that the FCS contains a CRC and the FCS contains a CRC.

In the conventional frame synchronization system using GFP, once the line is disconnected and resynchronization is performed, the first frame cannot be reproduced because the continuity is maintained and scrambling is performed, and information is transmitted. When not,
Since a frame including only the core header as shown in FIG. 2 is flowing, scrambling cannot be resynchronized in the idle state.

Therefore, in the frame synchronization system by GFP of the present invention, the receiving side judges that the line is disconnected (line abnormality), and the receiving side initializes the descramble arithmetic circuit and carries out the alarm transfer to the transmitting side. , The sending side initializes the scramble arithmetic circuit by alarm transfer. In the frame synchronization system by GFP of the present invention, the alarm is released by the receiving side after the line abnormality is recovered, the descrambling arithmetic circuit on the receiving side and the scramble arithmetic circuit on the transmitting side are deinitialized in this order, and This is a method in which normal information can be transferred from a frame containing valid information that is transmitted first by starting scrambling from a state of being restored from a failure.

(Embodiment 1) FIG. 3 is a block diagram showing a configuration of a frame synchronization system by GFP according to Embodiment 1.

As shown in FIG. 3, the frame synchronization system using GFP according to the first embodiment includes a first device 31, a second device 32, and transmission lines 33 and 34. The first device 31, a transmitting circuit 31 ₁ and the receiver circuit 31 _2. The second device 32 includes a transmitter circuit 32 ₂ and a receiver circuit 32.
_It consists of ₁ . The transmission circuit 31 ₁ of the first device 31 and the reception circuit 32 ₁ of the second device 32 are connected via a transmission line 33. The transmission circuit 32 ₂ of the second device 32 and the reception circuit 31 ₂ of the first device 31 are connected via a transmission path 34. The first device 31 and the second device 32 have the same configuration. Transmission circuit ₃₁ 1, 32 _2, and framing information into GFP, performs a process of mounting transmitted to SONET / SDH frame. The GFP frame synchronization method of the present invention is applied to a system in which two lines are provided for bidirectional communication.

Transmitting circuit 31 of the first device 31₁Is the flare
Length measurement circuit 31₁₁And the CRC calculation circuit 31₁₂When,
HEC operation circuit 31_ThirteenAnd the scramble arithmetic circuit 31
₁₄And the idle frame generation circuit 31₁₅And the control
Frame generation circuit for message 31₁₆And the GFP frame
Circuit 31₁₇And SONET framing circuit 31
₁₈And the SONET frame ALM transfer circuit 31₁₉When
Is equipped with.

Receiving circuit 31 of the first device 31_TwoIs SON
ET frame synchronization circuit 31₂₁And SONET frame
ALM detection circuit 31₂₂And GFP frame synchronization circuit 3
1_{Two Three}And the GFP frame ALM detection circuit 31₂₄When,
Descramble arithmetic circuit 31 ₂₅And the error by FCS
Correction circuit 31₂₆And the selection circuit 31₂₇And the control messe
Image determination circuit 31₂₈It has and.

Transmitting circuit 32 of the second device 32_TwoIs the flare
Length measuring circuit 32₂₁And the CRC calculation circuit 32₂₂When,
HEC operation circuit 32₂₃And the scramble arithmetic circuit 32
₂₄And the idle frame generation circuit 32₂₅And the control
Frame generation circuit for message 32₂₆And the GFP frame
Circuit 32₂₇And SONET framing circuit 32
₂₈And the SONET frame ALM transfer circuit 32₂₉When
Is equipped with.

Receiving circuit 32 of the second device 32₁Is SON
ET frame synchronization circuit 32₁₁And SONET frame
ALM detection circuit 32₁₂And GFP frame synchronization circuit 3
Two_{1 Three}And the GFP frame ALM detection circuit 32₁₄When,
Descramble arithmetic circuit 32 ₁₅And the error by FCS
Correction circuit 32₁₆And the selection circuit 32₁₇And the control messe
Image determination circuit 32₁₈It has and.

First, the transmission circuits 31 ₁ and 32 ₂ corresponding to the transmission sides of the first device 31 and the second device 32 will be described. Transmission circuit 31 _1, the transmission circuit 32 _2, receives the information a1, a3 from outside as input information. Further, the transmission circuit 31 ₁ of the first apparatus 31, when FCS is valid, receiving the information a1 simultaneously FCS effective setting b1 externally. The transmission circuit 32 of the _second device 32, if the FCS is valid, information a3 simultaneously FCS valid setting b2
And are received from the outside.

The received information a1 and a3 are frame length meters.
Measuring circuit 31₁₁, 32₂₁And CRC calculation circuit 31₁₂,
32₂₂And scramble arithmetic circuit 31₁₄, 32₂₄When
Entered in. In addition, the frame length measuring circuit 31₁₁Three
Two₂₁And CRC calculation circuit 31 ₁₂, 32₂₂And selection circuit
31₂₇, 32₁₇FCS valid settings b1 and b3
I will be forced.

Frame length measuring circuits 31 ₁₁ and 32
₂₁ inputs information a1 and a3 from the outside, and when the FCS is valid, calculates the frame length of the information a1 and a3 based on the input of the FCS valid settings b1 and b2. The frame length is the entire length sandwiched between the core header and FCS and is displayed in octet units. This value is 0-
In the range of 65535, 0 to 3 are reserved to mean special frames. The frame length is calculated by PLI (PDU Length Indicatto) in GFP.
It means that r) has been obtained (calculated). Frame length measuring circuit ₃₁ 11, _{32 21,} calculated information a
Outputs 1, a3 frame length (including PLI) to HEC calculation circuit ₃₁ 13, _{32 23.}

The HEC arithmetic circuit ₃₁ 13, _{32 23,} (performs HEC calculation) to calculate the value of the cHEC from PLI included in the frame length calculated by the frame length measurement circuit ₃₁ 11, _{32 2 1,} 1 Build the core header in the indicated GFP frame format. H
Generating polynomial of HEC operations performed by EC arithmetic circuit ₃₁ 13, _{32 23} is ^{X 16 + X 12 + X 5} +1, PLI core header accommodates cHEC, to accommodate the value of CRC16 for PLI. HEC operation circuit 3
1 _{13, 32 23,} the core header constructed GFP
And outputs the framing circuit _{31 1} 7, _{32 27.}

The CRC calculation circuits 31 ₁₂ and 32 ₂₂ input the information a1 and a3 from the outside, and when the FCS is valid, perform the CRC calculation of the information a1 and a3 based on the input of the FCS valid setting b1 and b2. To do. This CRC calculation circuit 3
1 ₁₂ and 32 ₂₂ perform the operation of CRC-32 accommodated in the FCS in the GFP frame format shown in FIG. Since the addition of the FCS area is optional, the CRC calculation circuits 31 ₁₂ and 32 ₂₂ are
It is possible to select valid / invalid by the valid settings b1 and b2. The CRC calculation circuits 31 ₁₂ and 32 ₂₂ are CRC-3.
2 (CRC32) operation result scramble operation circuit 3
Output to 1 ₁₄ and 32 ₂₄ .

The scrambling operation circuit ₃₁ 14, _{32 24}
Is the information a1 and a3 from the outside and the CRC calculation circuit 31.
₁₂ and 32 ₂₂ and CRC-32 (CRC32) operation results are input, scrambled (scrambling operation is performed) to ensure security, and the payload and F in the GFP frame format shown in FIG.
Build CS and. Scramble arithmetic circuit 31 ₁₄ , 3
The generator polynomial for the scrambling operation performed at 2 ₂₄ is X
⁴³ + 1, the payload contains the information a1 and a3, and the FCS contains the calculation results of the CRC calculation circuits 31 ₁₂ and 32 ₂₂ . Scrambling arithmetic circuit ₃₁ 14, 32
₂₄ outputs a payload and FCS built GFP framing circuit ₃₁ 17, _{32 27.}

The GFP framing circuit ₃₁ 17, _{32 27}
If there is valid information (information a1 and a3) to be transmitted, the HE is used as a process for transmitting the valid information.
A core header constructed by C arithmetic circuit ₃₁ 13, _{32 23,} the scrambling operation circuit ₃₁ 14, ₃₂ payload built at _24, based on the FCS, information a
Construct a frame as a GFP for transfer of 1 and a3 (G
FP is framed) and the constructed GFP is SON
And outputs the ET framing circuit ₃₁ 18, _{32 28.}

Idle frame generation circuits 31 ₁₅ and 32
₂₅ is effective information for transmission (information a1, a3)
In the absence, GFP framing circuit ₃₁ 17, 32
Called from _27, GFP framing circuit ₃₁ 17 generates an idle frame of GFP shown in Figure 2, 3
And outputs it to the 2 _27. Idle frame generation circuit 3
Idle frames sent from 1 ₁₅ and 32 ₂₅ are
As described above, the frame is a core header-only frame composed only of PLI and cHEC. The GFP framing circuits 31 ₁₇ and 32 ₂₇ process the idle frame generation circuits 31 ₁₅ and 32 ₂₅ as a process of packing / inserting the idle information in the empty area when there is no valid information (information a1 and a3) for transmission. Based on the idle frame from, the frame is constructed as the GFP for idle (frame conversion of GFP is performed), and the constructed GFP is S
And outputs the ONET framing circuit ₃₁ 18, _{32 28.}

Control message frame generation circuit 31
₁₆ and 32 ₂₆ are notifications of line anomalies such as transmission line anomalies from the other end (abnormalities of GFP frame synchronization of the receiving circuits 31 ₂ and 32 ₁ corresponding to the receiving sides of the first device 31 and the second device 32). From the receiving circuits 31 ₂ and 32 ₁ and notifies the other party (the receiving circuits 32 ₁ and 31 ₂ corresponding to the receiving side of the second device 32 and the first device 31) of the abnormality of the receiving circuits 31 ₂ and 32 _1. It generates a control message frame to be output to the GFP framing circuit ₃₁ 17, _{32 27.}
Control message frame generation circuits 31 ₁₆ , 32 ₂₆
The control message frame generated by
When the PLI of the header is 1, the frame is only the core header composed of PLI, cHEC, and undefined (reserved) (FIG. 4A), and when the PLI is 2 and 3, P
LI, cHEC, and message (OAM (Operati
on Administration and Mai
The frame is composed of a core header and is composed of a CRC 16) (FIG. 4).
(B), (c)). GFP framing circuit 31 ₁₇ , 3
2 _{2 7} is a control message frame generation circuit 31 ₁₆ 3 as a process of inserting alarm information when a line is abnormal.
Based on the control message frame from 2 _26, O
Building a frame as GFP for AM (performs framing of GFP), and outputs the GFP built SONET framing circuit ₃₁ 18, _{32 28.} Here, the message (OAM message) is the destination (second device 3
2, the receiving circuit 32 ₁ corresponding to the receiving side of the first device 31,
31 ₂ ) is used to notify the abnormality of the receiving circuits 32 ₁ and 31 ₂ .

In this way, the GFP framing circuit 31
₁₇ and 32 ₂₇ are HEC operation circuits 31 ₁₃ and 3
2 ₂₃ , scramble operation circuits 31 ₁₄ and 32 ₂₄ , idle frame generation circuits 31 ₁₅ and 32 ₂₅ , and control message frame generation circuits 31 ₁₆ and 32 ₂₆ output GFP for transfer of information a 1 and a 3 and idle. Of the GFP and the GFP for OAM are determined to determine the timing of transmission.

GFP framing circuit 31 ₁₇ , 32 ₂₇
The GFP (GFP frame) constructed by the above is installed in a SONET frame (SONET frame) and transmitted when being transmitted through the transmission paths 33 and 34. SO
NET framing circuit _{31 1} 8 _{32 28} inputs the GFP frame from GFP framing circuit ₃₁ 17, _{32 27,} the GFP frame to accommodate transferred / transmitted in the payload of the SONET frame, SONET framing (Encapsulate in SONET frame). The SONET framing circuits 31 ₁₈ , 32 ₂₈ are
The SONET frame is transferred / transmitted to the transmission lines 33 and 34.

SONET frame ALM transfer circuit 31
_{19, 32} 29, by using the alarm transfer line disconnection in SONET frames, and outputs the SONET framing circuit _{31 1} 8 _{32 28.} The SONET frame ALM forwarding circuit ₃₁ 19, _{32 29,} line abnormality such as line failure from the opposite destination (second device 32, SONET in the transmission circuit ₃₂ 2, 31 ₁ corresponding to the transmitting side of the first device 31 Reception circuit 3 for notification of (frame synchronization error)
1 ₂ 3 _{2 1} for notifying the destination (the second device 32, the receiving circuit 32 ₁ , 31 ₂ corresponding to the receiving side of the first device 31 of the receiving device 32 ₁ , 31 ₂ ) of the abnormality of the receiving circuit 31 ₂ , 32 ₁ . and it generates an alarm transfer indicating abnormality and outputs the SONET framing circuit ₃₁ 18, _{32 28.} Also, SONET frame ALM forwarding circuit ₃₁ 19, _{32 29,} line abnormality recovery from the opposite destination (second device 32, SONE in the transmission circuit ₃₂ 2, 31 ₁ corresponding to the transmitting side of the first device 31
Receiving a notification of T frame synchronization resumption) circuit ₃₁ 2, 32
₁ to generate an alarm transfer indicating recovery for notifying the opposite side (the receiving circuit 32 ₁ , 31 ₂ corresponding to the receiving side of the second device 32, the receiving side of the first device 31) of the transmitting side and generating S
And outputs the ONET framing circuit ₃₁ 18, _{32 28.} SONET framing circuit ₃₁ 18, _{32 2 8,}
SONET frame ALM transfer circuit 31 ₁₉ , 32 ₂₉
If the alarm transfer is input from the
It is accommodated in the NET frame, and the transmission circuit 32 ₂ , 3 corresponding to the transmission side of the opposite device (the second device 32, the first device 31)
1 ₁ ) is transferred / transmitted to the transmission lines 33 and 34 in order to notify it.

Next, the receiving circuits 32 ₁ and 31 ₂ corresponding to the receiving sides of the second device 32 and the first device 31 will be described. Receiving circuit 32 _1, the receiving circuit 31 ₂ sends as output information the information a2, a4 to the outside.

SONET framing circuit 31 ₁₈ , 32
_The SONET frame output from ₂₈ is transmitted through the transmission line 33.
Through, opposite destination (second device 32, the receiving circuit ₃₂ 1 corresponding to the receiving side of the first device 31, 31 ₂₎ to be transferred / transmitted is input to a SONET frame synchronizing circuit ₃₂ 11, _{31 21.} This SONET frame synchronization circuit 3
2 _{1 1, 31} 21, it synchronizes the SONET frames, and outputs the GFP frame synchronization circuit ₃₂ 13, _{31 23.}

SONET frame ALM detection circuit 32
_{12, 31} 22, terminates the SONET frame. S
ONET frame synchronization circuits 32 ₁₁ and 31 ₂₁ are SON
At the same time synchronizing the ET frame, SONET frame ALM detecting circuit _{32 12, 31} 22 monitors the synchronization status of the SONET frame SONET frame synchronizing circuit ₃₂ 11, _{31 21} do, detects a SONET frame synchronization abnormality when (if it is not possible to synchronize the SONET frame), which indicates that it is line abnormal SONET frame ALM forwarding circuit ₃₂ 29, _{31 19.} In addition, the SONET frame ALM detection circuits 32 ₁₂ and 31
_22, (if the SONET frame synchronization can not be taken) when it detects a SONET frame synchronization abnormality initializes the descrambling operation circuit ₃₂ 15, _{31 25.}

SONET frame ALM transfer circuit 32
₂₉, 31₁₉The notification transferred to is a line error notification.
One time, as described above, SONET frame ALM transfer
Sending circuit 32₂₉, 31₁₉Alarm transfer indicating an abnormality
To generate the SONET framing circuit 32₂₈, 31
₁₈To the SONET framing circuit 32₂₈Three
1 ₁₈Is a SONET frame ALM transfer circuit 3
Two₂₉, 31₁₉Alarm transmission indicating an abnormality from the SO
It is accommodated in the NET frame and is transmitted via the transmission lines 34 and 33.
SONET frame synchronization circuit 31₂₁, 32₁₁Transferred to
/ Transmit. SONET frame ALM detection circuit 31
₂₂, 32₁₂Is a SONET frame synchronization circuit 31
₂₁, 32₁₁Housed in a SONET frame from
If an alarm transfer indicating an abnormality is detected, scramble
Arithmetic circuit 31₁₄, 32₂₄Is initialized.

[0049] When the line abnormality is restored, and at the same time synchronizing the SONET frame synchronizing circuit ₃₂ 11, _{31 21} again SONET frame, SONET frame ALM detecting circuit _{32 12, 31} 22, SONET frame synchronization circuit ₃₂ 11, _{31 21} Monitoring the state of SONET frame synchronization performed by the device, and when recovery from an abnormal SONET frame synchronization is detected (when SONET frames can be synchronized), SONET frame A indicates that the line is recovered.
Notifying the LM transfer circuit ₃₂ 29, _{31 19.} Also, S
ONET frame ALM detection circuit 32 ₁₂ , 31
No. ₂₂ detects the recovery from the abnormality of SONET frame synchronization (when the SONET frame can be synchronized),
Releasing the initialization of the descramble operation circuit ₃₂ 15, _{31 25.}

SONET frame ALM transfer circuit 32
_{29, 31 19} is forwarded to the notification, when a notification of the line abnormality restoration, as described above, SONET frame A
LM transfer circuit ₃₂ 29, _{31 19,} SONET framing circuit _{32 28} generates an alarm transfer illustrating restoration,
Output to 31 _18, SONET framing circuit 3
2 _{28, 31} 18, the SONET frame synchronization circuit ₃₁ 21, _{32 11} via the transmission path 34 and 33 to accommodate the alarm transfer in a SONET frame indicating the recovery from the SONET frame ALM forwarding circuit ₃₂ 29, _{31 19} Transfer / Transmit. SONET frame ALM detection circuit 3
1 ₂₂ and 32 ₁₂ are SONET frame synchronization circuits 31
_{When the} alarm transfer indicating the recovery accommodated in the SONET frame is detected from ₂₁ and 32 ₁₁ , the initialization of the scramble arithmetic circuits 31 ₁₄ and 32 ₂₄ is released.

SONET frame synchronization circuit 32 ₁₁ , 3
If successful synchronization of the SONET frame are taken at 1 _21, GFP frame synchronization circuit ₃₂ 13, 31
₂₃ is a SONET frame synchronization circuit 32 ₁₁ , 31
GF by decapsulating the SONET frame from _21.
In order to detect the P frame and find the frame boundary point, the frame position is calculated from the cHEC of the core header and the GFP frame is synchronized.

GFP frame synchronization circuit 32_Thirteen, 31
₂₃Synchronizes the GFP frame and
Lame ALM detection circuit 32₁₄, 31₂₄Is the GFP
Lame synchronization circuit 32_Thirteen, 31₂₃GFP Flare
Monitor the synchronization status of the system and check for GFP frame synchronization abnormalities.
When detected (if the GFP frame cannot be synchronized)
If the line is abnormal, the control message frame
Generation circuit 32₂₆, 31₁₆To notify. Where control
Message frame generation circuit 32₂₆, 31₁₆Is
GFP frame ALM detection circuit 32₁₄, 31₂₄From
As described above, the destination (the first device 31,
The receiving circuit 31 corresponding to the receiving side of the second device 32 _Two, 32
₁) To receiving circuit 32₁, 31_TwoFor notification of abnormalities
G is generated by generating the control message frame shown in FIG.
FP framing circuit 32₂₇, 31₁₇Output to. G
FP framing circuit 32₂₇, 31₁₇Is the control messe
Frame generating circuit 32₂₆, 31₁₆Control from
Based on the message frame, GFP for OAM and
To build a frame (frame GFP),
SONET framing circuit 3 for the constructed GFP
Two₂₈, 31₁₈Output to. In addition, GFP frame A
LM detection circuit 32₁₄, 31₂₄Is the same as the GFP frame
Phase abnormality is detected (GFP frame can be synchronized)
If not), the descramble arithmetic circuit 32₁₅, 31
₂₅Is initialized.

GFP frame synchronization circuit 32_Thirteen, 31
₂₃If the GFP frame is normally synchronized in
Descrambling arithmetic circuit 32₁₅, 31₂₅Is a biography
The sent information a1, a3, FCS, OAM message
Unscramble information containing (descramble performance
Calculate). This descramble arithmetic circuit 32₁₅Three
1 ₂₅When FCS is added (accommodated in FCS
CRC calculation circuit 31₁₂, 32₂₂Calculation result of
Result), the information a1 and a3 contained in the payload,
CRC calculation circuit 31 housed in the FCS₁₂, 32
₂₂And the OAM message (control message
Frame generation circuit 31₁₆, 32₂₆Generated by
Error correction circuit 32 by FCS₁₆Three
1₂₆Output to. FCS error correction circuit 3
Two₁₆, 31₂₆Is the descramble arithmetic circuit 3
Two₁₅, 31₂₅Enter the information from the
CRC calculation circuit 31₁₂, 32₂₂Result of
Error detection and correction (correction of FCS error
Correct) and the information a1, a contained in the payload
3 and OAM message selection circuit 32₁₇, 31
₂₇Output to. CRC calculation times stored in FCS
Road 31₁₂, 32₂₂The calculation result of is incorrect due to FCS
Correction circuit 32₁₆, 31₂₆Due to an FCS error
After correcting the error, it is discarded.

In addition, the descrambling operation circuit 32 ₁₅ ,
31 _25, FCS or may not be added (the operation result of the CRC calculation circuit ₃₁ 12, _{32 22} FCS is not accommodated), directly, the information a1, a3 which is housed in the payload, the OAM message Selection circuit 3
Output to 2 _{17, 31 27.}

[0055] Selection circuit ₃₂ 17, _{31 27} is to select in accordance with the presence or absence of FCS, when FCS is valid, based on the input of the FCS effective setting b2, b1, external information a2, a4 as output information And sends the OAM message to the control message determination circuits 32 ₁₈ , 31 _28.
Output to.

Control message determination circuit 32₁₈, 31
₂₈Is the selection circuit 32₁₇, 31₂₇OAM message from
Sage (control message frame generation circuit 31₁₆,
32_{Two 6}By inputting the message generated in
Decrypt M message and receive GFP abnormally (Reception circuit 3
Two₁, 31_TwoError) is determined. As a result of judgment, OAM
When a message is input (GFP reception error), control
Message determination circuit 32 ₁₈, 31₂₈Scramble
Operation circuit 32₂₄, 31₁₄Is initialized. on the other hand,
If there is no OAM message input as a result of the determination (GF
P synchronization is normal), control message determination circuit 32₁₈,
31₂₈Is a scramble arithmetic circuit 32_{Two Four}, 31₁₄
Cancel the initialization of.

The GFP-based frame synchronization method according to the first embodiment is configured as described above, and when the line failure occurs, the descramble operation circuit 32 on the receiving side (reception circuits 32 ₁ and 31 ₂ ). _{15, 31 25} and initialize the sender (transmitter circuit ₃₁ 1, 32 ₂₎ the scrambling operation circuit ₃₁ 14, _{32 24} initializes the, when a line failure is restored, the receiving side (receiving circuit ₃₂ 1, 31 ₂ de descrambled arithmetic circuit ₃₂ 15, _{31 25} initialization of), by releasing the initialization of scrambling arithmetic circuit ₃₁ 14, _{32 24} of the transmission side (transmission circuit ₃₁ 1, 32 _2), the line failure Normal information a1, a when restored
3 can be played.

Next, the operation of the frame synchronization system by GFP according to the first embodiment will be described. Regarding the operation of the frame synchronization method by GFP according to the first embodiment,
It is divided into (A) normal operation and (B) line failure (line abnormality) operation.

First, (A) normal operation will be described with reference to FIGS.

Here, FIG. 5A is a timing chart showing the transmission information sent from the outside to the transmission side (first device 31). As shown in FIG. 5A, as the transmission information (packet), the information transfer 1 is sent from the outside to the first device 31 between the points P0 and P3, and the point P7 is transmitted.
It is assumed that the information transfer 2 is sent from the outside to the first device 31 during −P10, and the information transfer 3 is sent from the outside to the first device 31 between points P16 and P19. Information transfer 1,
The information transfer 2 and the information transfer 3 correspond to the above-mentioned information a1.

[0061] As shown in FIG. 3, the first device 31, a frame length measuring circuit _{31 11,} information from outside a
When 1 is input and FCS is valid, the frame length of the information a1 is calculated based on the input of the FCS valid setting b1, and the calculated frame length of the information a1 (including PLI)
The output to the HEC calculation circuit _{31 13.} HEC arithmetic circuit _{31 13,} to build a core header by calculating the value of the cHEC from PLI included in the frame length calculated by the frame length measurement circuit _{31 11,} and outputs the GFP framing circuit _{31 17.}

[0062] CRC calculation circuit _{31 12} receives the information a1 from the outside, if the FCS is valid, based on the input of the FCS effective setting b1, information a1 CRC calculation (FC
Performs the operation) of CRC32 be accommodated in S, and outputs the calculation result of the CRC32 to scramble arithmetic circuit _{31 14.}
Scrambling arithmetic circuit _{31 14,} information from the external a1
When inputs the calculation result from the CRC calculation circuit _{31 12} CRC32, houses the information a1 in the payload, and store computation results of the CRC calculation circuit _{31 12} to FCS, a payload and FCS scrambles Construction And GFP
And outputs the framing circuit _{31 17.}

[0063] If there is valid information for transmitting (information a1), GFP framing circuit _{31 17,} as a process for transmitting useful information, HEC calculation circuit 31
A core header constructed by _13, payload constructed by scrambling arithmetic circuit _{31 14,} based on the FCS, to build a frame as GFP for the transfer of information a1, SONET framing GFP built Circuit 3
And outputs it to the 1 _18. SONET framing circuit _{31 18}
Receives the GFP frame from GFP framing circuit _{31 17,} the point of the SONET framing performed (encapsulated in SONET frames), and transfers / transmits the SONET frame to the transmission line 33 (FIGS. 5 (a) P
GFP frame for information transfer 1 shown in 0-P3, GFP frame for information transfer 2 shown in points P7-P10, and information transfer 3 shown in points P16-P19
GFP frame).

On the other hand, effective information for transmission (information a
1) does not exist (points P3 to P7 in FIG. 5A,
Points P10-P16), GFP framing circuit 31
_17, the idle frame generating circuit ₃₁ 15, _{32 25}
And idle frame generation circuits 31 ₁₅ and 32
_The frame is constructed as a GFP for idle based on the idle frame from ₂₅ , and the constructed GFP is S
And outputs the ONET framing circuit _{31 18.} SONE
T framing circuit _{31 18,} GFP framing circuit 3
Enter the GFP frame from 1 ₁₇ performs SONET framing (encapsulated in SONET frames), shown at point P3-P7 of transferring / transmitting SONET frames to the transmission line 33 (FIGS. 5 (a) Idle GFP frame, idle GFP frame shown at points P10-P16).

In this way, the information a1 transferred / transmitted from the first device 31 is transferred to the second device 32 via the transmission path 33.

In the second device 32, the SONET frame synchronization circuit 32 ₁₁ is connected to the SONET from the first device 31.
The GFP frame synchronization circuit 32 synchronizes the frames.
It outputs to ₁₃ . SONET frame synchronization circuit 32 ₁₁
If the SONET frame is normally synchronized with, the GFP frame synchronization circuit 32 ₁₃ decapsulates the SONET frame from the SONET frame synchronization circuit 32 ₁₁ to detect the GFP frame, and detects the frame from cHEC of the core header. The position is calculated and the GFP frame is synchronized (points P0-P19 in FIG. 5A: GFP frame for information transfer 1 shown at points P0-P3, GF for idle shown at points P3-P7).
P frame, GFP frame for information transfer 2 shown at points P7-P10, GFP frame for idle shown at points P10-P16, point P16-P
GFP frame for information transfer 3 shown in 19).

The GFP frame synchronization circuit 32 ₁₃
If successful synchronization of P-frame is taken, the descrambling operation circuit _{32 15,} transmitted information a1, FCS
Unscramble information containing. When the FCS is added (the calculation result of the CRC calculation circuit 31 ₁₂ contained in the FCS), the descramble calculation circuit 32 ₁₅ includes the information a1 contained in the payload and the F
The calculation result of the CRC calculation circuit 31 ₁₂ stored in the CS and the error correction circuit 32 ₁₆ by FCS are output.
Error correction circuit _{32 16} by FCS receives the information from the descramble operation circuit _{32 1 5,} based on the calculation result of the CRC calculation circuit _{31 12} is housed in the FCS, during error detection and correction (FCS Error The error is corrected) and the information a1 contained in the payload is output to the selection circuit 32 ₁₇ . The calculation result of the CRC calculation circuit 31 ₁₂ accommodated in the FCS is discarded after the error at the FCS error is corrected by the FCS error correction circuit 32 ₁₆ .

Further, the descramble arithmetic circuit 32
₁₅If FCS is not added (CR is added to FCS
C arithmetic circuit 31₁₂Is not stored),
The selection circuit directly selects the information a1 contained in the payload.
32₁₇Output to. Selection circuit 32 ₁₇Has FCS
If it is valid, the information a2 is transmitted as output information to the outside.
(The information transfer shown at points P0-P3 in FIG.
GFP frame for transmission 1, shown at points P7-P10
GFP frame for information transfer 2 that was saved, point P16-
GFP frame for information transfer 3 shown in P19).

In this way, the information transfer 1, the information transfer 2, and the information transfer 3 corresponding to the information a1 are sent from the outside to the first device 31, and the first device 31 receives the information a1 (the information transfer 1, the information transfer 2). , A frame is constructed as a GFP for transfer of information transfer 3) (GFP frame), and SONET is framed based on the GFP frame (SONET frame), and the second device 32 transfers / transmits from the first device 31. The received information a1 (SONET frame, GFP frame) is received in synchronization with the information and transferred to the outside.

Next, the operation of (B) line failure (line abnormality) will be described with reference to FIGS. 3 and 5. A feature of the present invention is that when the line failure is recovered, the GFP information that arrives first can be normally transferred.
(B) For the operation of line failure (line abnormality), refer to (B
1) Abnormal operation of SONET frame synchronization and (B2) G
It is divided into an abnormal operation of FP frame synchronization. Also,
The operation of (B) line failure (line abnormality) will be described only when there is a line failure, and the same description as (A) normal operation will be omitted.

Here, similarly to the above, as shown in FIG. 5A, the information transfer 1 is sent from the outside to the first device 31 between the points P0 and P3, and the outside between the points P7 and P10. Information transfer 2 from the outside to the first device 31, and information transfer 3 from the outside between the points P16 and P19 to the first device 31. Information transfer 1, information transfer 2,
The information transfer 3 corresponds to the above-mentioned information a1 as transmission information (packet). FIG. 5B shows the transmitting side (first device 3
It is a timing chart which shows the information transmission of 1). Figure 5
(C) is a timing chart showing information transmission on the receiving side (second device 32). FIG. 5D is a timing chart showing the synchronization state of the GFP frame.

At the point P4 ', the second device 32
After transferring the information transfer 1 to the outside, a line failure occurs, and at the point P12 ', the information transfer 3 is transferred from the outside to the first position.
It is assumed that the line failure is recovered before being sent to the device 31.

First, (B1) abnormal operation of SONET frame synchronization will be described.

As shown in FIG. 3, external information a1
The information transfer 1 corresponding to is sent to the first device 31 (see FIG. 5).
Information transfer 1) indicated by points P0-P3 in (a),
The first device 31 constructs a frame as a GFP for transfer of the information a1 (information transfer 1) based on the information a1 (information transfer 1) (GFP frame), and creates a SONET frame based on the GFP frame (SONET frame). ) And transfer it to the second device 32 (point P in FIG. 5B).
0-GFP frame for information transfer 1 shown in P3).
The second device 32 receives in synchronization with the information a1 (SONET frame, GFP frame) transferred / transmitted from the first device 31 and transfers it to the outside (point P in FIG. 5C).
GFP frame for information transfer 1 indicated by 0-P3, points P0-P3 in FIG. 5D).

When there is no valid information (information a1) for transmission (points P3 to P4 in FIG. 5A), the first device 31 transfers the idle frame to the second device 32. In the transfer of the idle frame by the first device 31, a frame is constructed as a GFP for idle (GFP frame), a SONET frame is formed based on the GFP frame (SONET frame), and transferred to the second device 32 (Fig. GFP frame for idle shown in points P3 to P4 of 5 (b)). The second device 32 uses the idle frame (SON) transferred / transmitted from the first device 31.
ET frame, GFP frame) (GFP frame for idle shown at points P3 to P4 in FIG. 5C, point P3 to P in FIG. 5D)
4). Similarly, valid information for transmission (information a
1) does not exist (points P4 to P5 in FIG. 5A),
The first device 31 transfers the idle frame to the second device 32 (the idle GFP frame shown at points P4 to P5 in FIG. 5B).

If a failure occurs in the transmission line 33,
2 SONET frame synchronization circuit 32 of device 32₁₁Is
SONET frame transferred / transmitted from the first device 31
Will be out of sync. Here, the GFP frame synchronization time
Road 32_ThirteenIs a SONET frame synchronization circuit 32₁₁To
Therefore, the GFP frame cannot be synchronized (FIG. 5 (d)).
Point P4 '). SONET frame ALM detection times
Road 32₁₂Is a SONET frame synchronization circuit 32₁₁But
Line failure due to the inability to synchronize SONET frames
Detects damage (line abnormality) and informs that it is a line abnormality.
ET frame ALM transfer circuit 32₂₉To notify. SO
NET frame ALM transfer circuit 32₂₉Indicates an abnormality
SONET framing circuit 32 for generating alarm transfers
₂₈To the SONET framing circuit 32₂₈Is
SONET frame ALM transfer circuit 32₂₉Anomalies from
Accommodating the alarm transfer indicating
SONET frame of the first device 31 via the transmission path 34
Synchronization circuit 31₂₁Transfer / transmit. In the first device 31
The SONET frame ALM detection circuit 31₂₂Is
SONET frame synchronization circuit 31₂₁From SONET
Detected an alarm transfer indicating anomalies contained within the ram
When a failure occurs, the failure is judged and based on the judgment of the failure occurrence
Rumble arithmetic circuit 31₁₄Is initialized (Fig. 5 (b))
Point P4 '). In the second device 32, S
ONET frame ALM detection circuit 32 ₁₂Is SONE
When T-frame synchronization error is detected, descramble
Arithmetic circuit 32₁₅Is initialized (point of FIG. 5C)
P4 ').

In the state where the fault remains on the transmission line 33 (line disconnection state) (point P4 'in FIG. 5C)
-P12 '), in the first device 31, the information transfer 2 corresponding to the information a1 is transmitted from the outside (information transfer 2 shown at points P7 to P10 in FIG. 5A), but in the line disconnection state. since there line abnormality is not restored, while performing the initialization of scrambling arithmetic circuit 31 ₁₄ is illustrated continue forwarding an idle frame to the second device 32 (the point P5-P13 shown in FIG. 5 (b) Idol GFP frame).

If the failure of the transmission path 33 shown in FIG. 3 is recovered before the information transfer 3 is sent from the outside to the first device 31, the SONET frame synchronization circuit 32 of the second device 32 is recovered.
₁₁ is a SONET transferred / transmitted from the first device 31.
Frames can be synchronized. The SONET frame ALM detection circuit 32 ₁₂ detects that the SONET frame synchronization circuit 32 ₁₁ has recovered the line failure (line abnormality) due to the synchronization of the SONET frame, and indicates that the SONET frame has been recovered (line restoration). A
Notifying the LM transfer circuit _{32 29.} SONET frame ALM forwarding circuit _{32 29} outputs the SONET framing circuit _{32 2 8} generates an alarm transfer illustrating restoration,
The SONET frame conversion circuit 32 ₂₈ accommodates the alarm transfer indicating the recovery from the SONET frame ALM transfer circuit 32 _{29 in} the SONET frame and the SONET frame synchronization circuit 31 of the first device 31 via the transmission path 34.
₂₁ transfer / transmission. In the first device 31, the SON
ET frame ALM detection circuit ₃₁ 22, to the alarm transfer illustrating restoration accommodated from the SONET frame synchronization circuit _{31 21} in the SONET frame, and determines a fault recovery, scrambling based on the determination of the fault recovery operation circuit 31 The initialization of ₁₄ is canceled (point P12 ′ in FIG. 5B). In the second device 32, the SONE
When the T-frame ALM detection circuit 32 ₁₂ detects the restoration of the SONET frame synchronization, the T-frame ALM detection circuit 32 ₁₂ cancels the initialization of the descramble calculation circuit 32 ₁₅ (point P12 ′ in FIG. 5C).

For GFP frame detection, G of FIG.
As shown in the FP frame detection state transition diagram, when synchronization is lost, the Hunt state is set and Bit-by-Bit is set.
To find the HEC position. If the HEC positions match, Pr
e-Sync state transition to Frame-by-Frame
The check at e is done. Therefore, HE consecutively N times
When C is detected, the state becomes Sync. GFP of the present invention
In the frame synchronization method by, N = 3. During this period, the first device 31 transmits the idle frame to the second device 32.
(The idle GFP frame shown at points P13 to P17 in FIG. 5B), and the second device 32
When recovering from the line abnormality, a synchronous state is detected in which three idle frames are detected, and recovery is achieved and synchronization can be taken from the fourth idle frame (point P13-P in FIG. 5C).
GFP frame for idle shown in FIG. 17, FIG.
(D) after point P16).

That is, after recovering from a line failure (line abnormality) such as a line disconnection state, the information transfer 3 is sent from the outside to the first device 31 (points P16-P19 in FIG. 5A).
Information transfer 3) shown in FIG.
Construct a frame as a GFP for transfer of information a1 (information transfer 3) based on (information transfer 3) (GFP frame)
Then, the SONET is framed based on the GFP frame (SONET frame) and transferred to the second device 32 (the GFP frame for information transfer 3 shown at points P16 to P19 in FIG. 5B). The second device 32 is the first
When the information a1 (SONET frame, GFP frame) transferred / transmitted from the device 31 is received, it is restored to 4
The third idle frame is synchronized and transferred to the outside (the GFP frame for information transfer 3 shown at points P17 to P20 in FIG. 5C, point P in FIG. 5D).
17-P20).

Here, after recovery from the line abnormality, the first device 31
Information transfer 3 transmitted to the scramble arithmetic circuit 31
Since ₁₄ is the information sent only after the release of the reset / initialization, the scrambling operation circuit 31 _14, the scrambling operation carried out only after the initialization. On the other hand, the information transfer 3 transmitted from the first device 31 to the second device 32 is the information sent only after the descrambling operation circuit 32 ₁₅ is initialized / de-initialized after the line abnormality is recovered. , descrambling operation circuit 32 _15, the descrambling operations carried out only after the initialization. As described above, in the frame synchronization method by GFP of the present invention, correct calculation can be performed, and by exchanging and controlling the information of the line failure, correct reproduction can be performed from the first received GFP frame after the line failure is recovered. it can.

Next, (B2) abnormal operation of GFP frame synchronization will be described. As this abnormality, SONET
Although the frame is normal, there may be a problem that only the frame synchronization of the GFP mounted on the SONET frame cannot be achieved. In this case, the same processing can be performed.

In FIG. 3, when the GFP frame synchronization circuit 32 ₁₃ of the second device 32 cannot synchronize the GFP,
The GFP frame ALM detection circuit 32 ₁₄ detects the loss of GFP frame synchronization (abnormal GFP frame synchronization), and at the same time, initializes the descrambling operation circuit 32 ₁₅ . The GFP frame ALM detection circuit 32 ₁₄ notifies the result (abnormal) to the control message frame generation circuit 32 ₂₆ . In the second device 32, the control message frame generator circuit _{32 26,} a control message frame of GFP shown in Figure 4 OA
Using the GFP frame for M message (the GFP frame for OAM including the OAM message), GFP
Loss of frame synchronization is notified to the opposite party (first device 31). In the case of this example, a GFP frame with PLI = 2 is used. OAM sent (indicating abnormal)
GFP frame for messages, are detected by the control message judging circuit _{31 28} of the first apparatus 31, the control message determining circuit _{31 28} analyzes the contents of the OAM message, the result of the analysis, if the contents of the OAM message is abnormal initializes the scramble arithmetic circuit _{31 14.}

At the time of recovery from the loss of GFP frame synchronization, the GFP frame synchronization circuit 32 ₁₃ of the second device 32 causes the GFP frame synchronization.
, The GFP frame ALM detection circuit 32 ₁₄ detects the recovery from the loss of GFP frame synchronization and, at the same time, cancels the initialization of the descramble calculation circuit 32 ₁₅ . GFP frame ALM detection circuit 32
_14, the result (that is restored), and notifies the control message frame generator circuit _{32 26.} Second device 3
In 2, controlled by the message frame generator circuit _{32 26,} using the GFP frame for OAM messages,
Restoration of loss of GFP frame out-of-sync (first device 3
Notify 1). This is also notified using the GFP frame for OAM message. GFP frame for transmitted (indicating a recovery) OAM message is detected by the control message judging circuit _{31 28} of the first device 31,
Control message judging circuit _{31 28} analyzes the contents of the OAM message, the result of the analysis, if the contents of the OAM message is restored to release the initialization of scrambling arithmetic circuit _{31 14.} In this way, in the frame synchronization method by GFP of the present invention, S
It can be dealt with in the same way as when the ONET frame is abnormal.

As a result, according to the frame synchronization method by GFP according to the first embodiment, it is possible to reproduce normal information when the line fault is restored.

(Embodiment 2) FIG. 6 is a block diagram showing a configuration of a frame synchronization system by GFP according to Embodiment 2. In FIG.

As shown in FIG. 6, in the frame synchronization system by GFP according to the second embodiment, in the transmission circuit 31 ₁ of the first device 31, the SONET framing circuit 31 _{18 is used.}
And the SONET frame ALM forwarding circuit _{31 19} is removed, GFP framing circuit _{31 17} is connected to the transmission line 33. Further, in the receiving circuit 31 ₂ of the first device 31, SONET frame sync circuit _{31 21} and the SONET
A frame ALM detection circuit _{31 22} is removed, GFP frame synchronization circuit _{31 23} is connected to the transmission line 34. Further, in the transmission circuit 32 of the _second device 32, SON
ET frame conversion circuit 32 ₂₈ and SONET frame AL
The M transfer circuit 32 ₂₉ is removed and the GFP framing circuit 32 ₂₇ is connected to the transmission path 34. Further, in the reception circuit 32 ₁ of the second device 32, the SONET frame synchronization circuit 32 ₁₁ and the SONET frame ALM detection circuit 32
_12, and the GFP frame synchronization circuit 32 ₁₃ is connected to the transmission line 33.

The operation and effects of the frame synchronization system using GFP according to the second embodiment are the same as those of the first embodiment. In this case, GFP framing circuit ₃₁ 17, 32
₂₇ does not encapsulate the constructed GFP with another frame, but uses the GFP frame synchronization circuit 32 via the transmission line 33.
_{13, 31} and output / transmitted to _23, GFP frame synchronization circuit ₃₂ 13, _{31 23,} GFP framing circuit 31
₁₇ and 32 ₂₇ synchronize the GFP.

As described above, the GFP frame synchronization method of the present invention transfers the SONET alarm transfer and the GFP frame out-of-sync information to add control to the scramble arithmetic circuit and the descramble arithmetic circuit. At the time of recovery from a line failure in information transmission using GFP, it is possible to normally reproduce from the information of the GFP frame that arrived first.

According to the frame synchronization method by GFP of the present invention, when transmitting using GFP, it is roughly divided into two.
The street method is possible. One is a case where GFP is further encapsulated in another frame as described in the first embodiment, and a case where the GFP is encapsulated in a SONET frame and transferred in the first embodiment. This is particularly advantageous when the relay device uses the SONET frame for transfer, and has the advantage of being easily incorporated into the system.

The second method is a case where the GFP is not encapsulated in another frame and is sent as it is, as described in the second embodiment. Also in this case, as in the first embodiment, there is an advantage that it can be easily incorporated into the system.

For example, when a line failure occurs, communication on the transmission line is disabled first. At this time, in a system where scrambled data is transmitted, and if scramble is not closed for each frame and scrambled across frames, once a line failure occurs, and a disconnection occurs, The scramble cannot be reproduced and the information a1 and a3 (the GFP frame carrying the information) cannot be transmitted even after the line failure is recovered. Also, in a system that scrambles even idle frames for transmission, resynchronization can be performed using idle frames, but only frames that transmit valid information a1 and a3, such as GFP, are scrambled. if they are, the valid information a1, a3 (receiving circuit ₃₂ 1, 31 ₂
Since the descramble processing is not executed unless it is received, the valid information a1 and a3 sent after the line failure is recovered.
The GFP frame on which is put cannot be descrambled normally, and an error always occurs.

In the frame synchronization system by GFP of the present invention
According to this, if a line failure (line abnormality) occurs, the receiving side
(Reception circuit 32₁, 31_Two) Detects out of sync. This
When, the receiving side (reception circuit 32₁, 31_Two) Descramble
Bull arithmetic circuit 32₁₅, 31 ₂₅To initialize. Bidirectional
Using the lines (transmission lines 33, 34) that can be transmitted by communication,
Alarm transfer (Alarm transfer indicating line abnormality, OAM message)
Error) and recognize the reception error on the opposite station side. alarm
Is active (alarm transfer indicating line error,
During transmission of the OAM message, the transmitting side (transmitting circuit 31)
₁, 32_Two) Scramble operation circuit 31₁₄, 32
₂₄To initialize. After the line error is recovered, the receiving side (receiving
Communication circuit 32₁, 31_Two) To release the alarm (recovery of line error)
Alarm transfer indicating the old, OAM message)
Receiving side (reception circuit 32₁, 31_Two) Descramble operation
Circuit 32₁₅, 31₂₅, Transmitting side (transmitting circuit 31₁Three
Two_Two) Scramble operation circuit 31₁₄, 32₂₄Order of
Is initialized. Therefore, after line failure recovery
Transmission side (transmission circuit 31₁, 32_Two) Is the first time after initialization
GF on which the information a1 and a3 scrambled for the first time are added
The P frame is transmitted, and the reception side (reception circuit 32₁Three
1_Two) But the scrambled GFP frame after initialization
Is descrambled, so descramble from the initial value
Can be applied, and normal information a1 and a3 can be reproduced.
It becomes Noh.

Frame synchronization by GFP of the present invention
According to the scheme, it is encapsulated by multiple frames
Alarm transmission corresponding to each frame even if
(Alarm transfer indicating line abnormality, OAM message)
Receiving side (receiving circuit 32₁, 31_Two) Descramble
Arithmetic circuit 32₁₅, 31₂₅, Transmitting side (transmitting circuit 3
1 ₁, 32_Two) Scramble operation circuit 31₁₄, 32
₂₄It can be realized by initializing. GF of the present invention
Line failure by applying the frame synchronization method by P
Receives the first scrambled information a1 and a3 after restoration
Descrambling can be performed normally from the time of believing.

From the above description, according to the frame synchronization method by GFP of the present invention, the second device 32 (or the first device 31) transmits the frame (transmitted from the first device 31 (or the second device 32) ( A line fault is detected based on the synchronization state of the GFP frame and SONET frame, and information a1 (or a) transmitted from the outside after the line fault is recovered.
Since the first device 31 (or the second device 32) is controlled so as to transmit 3) to the second device 32 (or the first device 31), normal information can be reproduced when the line fault is restored. it can.

Further, according to the frame synchronization method by GFP of the present invention, the descramble arithmetic circuit on the receiving side can be initialized and the scramble arithmetic circuit on the transmitting side can be initialized when a line fault occurs. it can.

Further, according to the frame synchronization system by GFP of the present invention, the initialization of the descramble arithmetic circuit on the receiving side is canceled and the initialization of the scramble arithmetic circuit on the transmitting side is canceled when the line fault is recovered. can do.

[0098]

According to the frame synchronization system by GFP of the present invention, normal information can be reproduced when the line fault is restored.

[Brief description of drawings]

FIG. 1 is a diagram showing a frame format of GFP.

FIG. 2 is a diagram showing an idle frame of GFP.

FIG. 3 is a block diagram showing a configuration of a frame synchronization method by GFP according to the first embodiment.

FIG. 4 is a diagram showing a frame for a GFP control message.

5 (a) is a timing chart showing transmission information sent from the outside to a transmission side, FIG. 5 (b) is a timing chart showing information transmission on the transmission side, and FIG.
Timing chart showing information transmission on the receiving side, FIG.
(D) is a timing chart showing the synchronization state of the GFP frame.

FIG. 6 is a block diagram showing a configuration of a frame synchronization method based on GFP according to the second embodiment.

FIG. 7 is a state transition diagram showing frame detection of GFP.

8A is a diagram showing a frame format of GFP, FIG. 8B is a diagram showing an idle frame of GFP, and FIG. 8C is transmission information sent from the outside to a transmission side. 8 (d) is a timing chart showing information transmission on the receiving side, and FIG. 8 (e) is
It is a timing chart which shows the synchronization state of a GFP frame.

[Explanation of symbols]

31 1st device 32 2nd device 31 ₁ , 32 ₂ Transmission circuit 31 ₁₁ , 32 ₂₁ Frame length measurement circuit 31 ₁₂ , 32 ₂₂ CRC calculation circuit 31 ₁₃ , 32 ₂₃ HEC calculation circuit 31 ₁₄ , 32 ₂₄ Scramble calculation circuit 31 ₁₅ , 32 ₂₅ idle frame generation circuit 31 ₁₆ , 32 ₂₆ control message frame generation circuit 31 ₁₇ , 32 ₂₇ GFP framing circuit 31 ₁₈ , 32 ₂₈ SONET framing circuit 31 ₁₉ , 32 ₂₉ SONET frame ALM transfer circuit 31 ₂ , 32 ₁ receiver circuit _{31 21,} 32 11 SONET frame synchronizing circuit _{31 22,} 32 12 SONET frames ALM detecting circuit _{31 23, 32} 13 GFP frame sync circuit _{31 24, 32} 14 GFP frame ALM detection circuit ₃₁ 25, _{32 15} Scrambling arithmetic circuit _{31 26, 32} 16 errors due FCS correction circuit ₃₁ 27, _{32 17} selecting circuits ₃₁ 28, _{32 18} control message judging circuit 33 transmission path a1, a3 information a2, a4 information b1, b2 FCS validity setting

Claims (5)

[Claims] 1. A first device for transmitting scrambled reference information, comprising a scramble circuit for scrambling reference information transmitted from the outside, and descrambles the scrambled reference information from the first device. A second device having a descrambling circuit and transmitting the reference information descrambled by the descramble circuit, wherein the first device constructs and transmits the scrambled reference information in a frame; The second device detects the line abnormality based on the synchronization state of the transmitted frame, and controls the first device to transmit the reference information transmitted from outside after the line abnormality is recovered. Frame synchronization method. 2. The frame synchronization method according to claim 1, wherein the second device initializes the descramble circuit when the line is abnormal, and notifies the first device of the line abnormal, The frame synchronization method in which the first device initializes the scramble circuit based on the notification of the line abnormality from the second device. 3. The frame synchronization method according to claim 2, wherein the second device cancels the initialization of the descrambling circuit at the time of the restoration, and notifies the first device of the restoration, The frame synchronization method in which the first device cancels the initialization of the scramble circuit based on the notification of the restoration from the second device. 4. The frame synchronization method according to claim 1, wherein the frame is a GFP frame. 5. The frame synchronization method according to claim 1, wherein the frame is a SONET frame.