JP2003031861A - Power supply line circuit - Google Patents

Power supply line circuit

Info

Publication number
JP2003031861A
JP2003031861A JP2001214709A JP2001214709A JP2003031861A JP 2003031861 A JP2003031861 A JP 2003031861A JP 2001214709 A JP2001214709 A JP 2001214709A JP 2001214709 A JP2001214709 A JP 2001214709A JP 2003031861 A JP2003031861 A JP 2003031861A
Authority
JP
Japan
Prior art keywords
circuit
power supply
line
superconducting
supply line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001214709A
Other languages
Japanese (ja)
Inventor
Yoshinobu Taruya
良信 樽谷
Keiichi Tanabe
圭一 田辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Superconductivity Technology Center
Hitachi Ltd
Original Assignee
International Superconductivity Technology Center
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Superconductivity Technology Center, Hitachi Ltd filed Critical International Superconductivity Technology Center
Priority to JP2001214709A priority Critical patent/JP2003031861A/en
Publication of JP2003031861A publication Critical patent/JP2003031861A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a structure and system for power supply line circuit that can reduce its power consumption, can secure the operating areas of logic circuits, can reduce the occupying areas of the logic circuits, and is suitable for the higher integration of a digital circuit. SOLUTION: The superconducting digital circuit is composed of logic circuits, such as an arithmetic circuit, a storage circuit, etc., which process digital signals and a power supply line 48 circuit which supplies a direct bias current or a bias DC voltage to the logic circuits. Each branch line 44 to the constituent element of each logic circuit is constituted of a resistor 43 and superconducting lines 401 and 402 . In addition, impedance discontinuity is imparted to the branch line 44.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、高速で高周波のデ
ジタルデータ処理装置、さらには超電導性を有すること
により特有の性能を発揮する超電導デジタルデータ処理
回路の分野に関わり、とくに超高速性能を発揮するデー
タ処理回路に必須の要素となる電源回路の構成とその動
作に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field of a high-speed and high-frequency digital data processing device, and further, a superconducting digital data processing circuit that exhibits superconducting properties to exhibit unique performance. The present invention relates to the configuration and operation of a power supply circuit, which is an essential element of the data processing circuit.

【0002】[0002]

【従来の技術】デジタル論理回路を駆動する電源回路に
要求される性能は(1)論理回路を構成する各ゲートあ
るいは要素素子にそれぞれの動作に適した電圧、あるい
は電流を供給すること、(2)特定のゲートあるいは要
素素子がスイッチしても、スイッチングにともなう素子
抵抗の一時的な変動によって、隣接するゲートあるいは
要素素子に供給される電源電流あるいは電圧が変動しな
いこと、および(3)電源線回路での消費電力を抑える
こと、等である。
2. Description of the Related Art The performance required of a power supply circuit for driving a digital logic circuit is (1) supplying a voltage or current suitable for each operation to each gate or element element forming the logic circuit, (2) ) Even if a specific gate or element element is switched, the power supply current or voltage supplied to an adjacent gate or element element does not change due to a temporary change in element resistance due to switching, and (3) power line That is, to reduce power consumption in the circuit.

【0003】従来用いられている電源線回路の等価回路
を図2に示した。図2は論理回路が複数の要素素子によ
り構成され、各要素素子には各要素素子の動作を安定に
するためのバイアス電流を供給するために、抵抗12、
12’を介して電源10が接続されていることを模式的
に示す。要求性能(1)を満足させるために、電源線か
ら各要素素子に分岐する配線8に抵抗12、12’を接
続し、抵抗値によって電源10の電流を分割し、望まし
い値の電流を各要素素子に分配する方法が用いられてい
る。
FIG. 2 shows an equivalent circuit of a conventional power supply line circuit. In FIG. 2, a logic circuit is composed of a plurality of element elements, and each element element has a resistor 12 for supplying a bias current for stabilizing the operation of each element element.
It is shown schematically that the power supply 10 is connected via 12 '. In order to satisfy the required performance (1), the resistors 12 and 12 'are connected to the wiring 8 that branches from the power supply line to each element element, the current of the power supply 10 is divided by the resistance value, and the desired value of current is supplied to each element. A method of distributing to elements is used.

【0004】要求性能(2)を満足させるために、スイ
ッチングにともなう各要素素子の抵抗の変動値より十分
大きい抵抗12’を電源線より分岐する配線に接続す
る。たとえばスイッチングにともなう要素素子の抵抗の
変動幅が10オームであるとすると、電源線につながる
抵抗の値を100オームとすれば、スイッチングにとも
なう電流の再配分割合は10%以下に抑えられる。この
ような電源線回路の構成法はとくに電流によって駆動さ
れる超電導回路において通常よく用いられている。この
電源線回路の構成法はM.Currie等Transactions on Appl
ied Superconductivity, 9巻、2号3531頁(1999年)他多数
の例に記載されている。
In order to satisfy the required performance (2), a resistor 12 'which is sufficiently larger than the variation value of the resistance of each element element due to switching is connected to the wiring branched from the power supply line. For example, if the variation width of the resistance of the element element due to switching is 10 ohms, the redistribution ratio of the current associated with switching can be suppressed to 10% or less if the value of the resistance connected to the power supply line is 100 ohms. Such a method of constructing a power supply line circuit is usually often used especially in a superconducting circuit driven by an electric current. This power line circuit is constructed by Transactions on Appl by M. Currie et al.
ied Superconductivity, Vol. 9, No. 2, page 3531 (1999) and many other examples.

【0005】これらの電源線回路の例では、おしなべて
論理回路のゲートあるいは要素素子の電圧状態における
抵抗値より、十分大きい電源線抵抗が用いられているこ
とは言うまでもない。さらに要求性能(3)を満足させ
るため、すなわち、電源線回路での消費電力を抑えるた
めに、電源線から各ゲートあるいは要素素子に分岐する
配線の抵抗値を低くし、要素素子のスイッチングにとも
なう供給電流の変動を抑えるために、分岐のインダクタ
ンスと抵抗の比を十分大きくする方法が提案されてい
る。この電源線回路の特性はN. Yoshikawa等、Extended
Abstract of the1999 International Superconductivit
y Electronics Conference,339頁(1999年)に示されてい
る。
It goes without saying that in these examples of power supply line circuits, power supply line resistances which are generally sufficiently larger than the resistance values in the voltage states of the gates of logic circuits or element elements are used. Further, in order to satisfy the required performance (3), that is, in order to suppress the power consumption in the power supply line circuit, the resistance value of the wiring branched from the power supply line to each gate or the element element is lowered, and the element element is switched. In order to suppress the fluctuation of the supply current, a method has been proposed in which the ratio of the inductance and the resistance of the branch is made sufficiently large. The characteristics of this power line circuit are extended by N. Yoshikawa et al.
Abstract of the1999 International Superconductivit
y Electronics Conference, p. 339 (1999).

【0006】[0006]

【発明が解決しようとする課題】デジタル回路の電源線
回路に要求される性能としては、従来の技術で述べた項
目を満足させる以外に、高集積で高性能のデジタル回路
を得るために、以下に述べる課題を解決する必要があ
る。
As the performance required for the power supply line circuit of the digital circuit, in order to obtain a highly integrated and high performance digital circuit, in addition to satisfying the items described in the prior art, It is necessary to solve the problem described in.

【0007】すなわち、高集積回路を実現するには電源
線回路での消費電力が論理回路の消費電力と同等以下で
あるだけでなく、回路全体に占める電源線回路の面積割
合が小さいことが必要である。
That is, in order to realize a highly integrated circuit, not only the power consumption of the power supply line circuit is equal to or less than that of the logic circuit, but also the area ratio of the power supply line circuit to the entire circuit is required to be small. Is.

【0008】しかるに電源線回路の消費電力を小さくた
めに抵抗値を低くし、かつ要素素子のスイッチングにと
もなう供給電流の変動を抑えるためには分岐線のインダ
クタンスを増大させることが必要であり、そのために
は、各分岐線の長さを伸ばす必要があった。この結果電
源線回路の占有面積が増大する結果となっていた。たと
えば抵抗値を5オーム、インダクタンスを100ピコヘ
ンリーとすると、1ミクロン幅の配線でも、配線長は約
100ミクロンとなる。1ミクロン幅の配線を用いれ
ば、磁束量子回路の超電導ループの大きさは10ミクロ
ン程度以内であるから、回路全体に占める電源線回路の
割合がかなり増大することは言うまでもない。
However, in order to reduce the power consumption of the power supply line circuit, it is necessary to lower the resistance value and to increase the inductance of the branch line in order to suppress the fluctuation of the supply current due to the switching of the element elements. It was necessary to extend the length of each branch line. As a result, the area occupied by the power supply line circuit is increased. For example, if the resistance value is 5 ohms and the inductance is 100 picohenries, the wiring length is about 100 microns even if the wiring has a width of 1 micron. Needless to say, if the wiring of 1 μm width is used, the size of the superconducting loop of the magnetic flux quantum circuit is within about 10 μm, so that the ratio of the power supply line circuit to the entire circuit is considerably increased.

【0009】そこで本発明が解決しようとする課題は、
さきに述べたごとく、消費電力を論理回路部での値より
十分低く抑えることができるとともに、論理回路の動作
領域を高い値に確保でき、かつ占有面積割合増大させな
い、デジタル回路の電源回路構成を提供することにあ
る。
Therefore, the problem to be solved by the present invention is as follows.
As mentioned earlier, a power supply circuit configuration of a digital circuit that can keep the power consumption sufficiently lower than the value in the logic circuit section, can secure the operation area of the logic circuit at a high value, and does not increase the occupied area ratio. To provide.

【0010】[0010]

【課題を解決するための手段】演算回路、記憶回路等、
デジタル信号を処理する論理回路部分と、論理回路に直
流のバイアス電流、あるいは直流のバイアス電圧を供給
する電源線回路からなるデジタル回路において、各論理
回路の要素素子に至る電源線回路の分岐部分を抵抗と超
電導線路によって構成し、かつ分岐部分にインピーダン
スの不連続性を形成する。すなわち、本発明では、電源
線回路の分岐部分に形成したインピーダンスの不連続部
分により、見かけ上の分岐線のインダクタンスを増大さ
せることにより、電源線回路の分岐部分を長くしたのと
同等の結果を得ることを可能にする。電源線回路の各分
岐の長さは、要素素子の発生する信号の波長に対応する
長さの4分の1以上とする。これは各分岐で、要素素子
の発生する信号が電磁波であるとみなせるために必要で
ある。
[Means for Solving the Problems] arithmetic circuit, memory circuit, etc.
In a digital circuit consisting of a logic circuit part that processes a digital signal and a power supply line circuit that supplies a DC bias current or a DC bias voltage to the logic circuit, the branch part of the power supply line circuit that reaches the element element of each logic circuit It is composed of a resistance and a superconducting line, and forms an impedance discontinuity at the branch. That is, in the present invention, the impedance equivalent to the apparent branch line inductance is increased by the impedance discontinuity formed in the branch portion of the power supply line circuit, and the same result as when the branch portion of the power supply line circuit is lengthened is obtained. Make it possible to get. The length of each branch of the power supply line circuit is one fourth or more of the length corresponding to the wavelength of the signal generated by the element element. This is necessary in each branch so that the signal generated by the element element can be regarded as an electromagnetic wave.

【0011】[0011]

【発明の実施の形態】本発明に係る電源線回路の等価回
路を図1に示した。図1において、5、6は超電導線
路、8は電源分岐線、10は電源、12は抵抗である。
ここで、論理回路の各要素素子に至る電源分岐線8を構
成する配線の主要部分を、インピーダンスの異なる超電
導線路5,6の直列回路と抵抗12の直列接続とし、か
つ抵抗12の抵抗値が論理回路の要素素子の固有抵抗と
同等であるか、あるいは固有抵抗より小さい値とする。
固有抵抗とは,たとえば超電導回路の場合、超電導素子
が電圧状態にスイッチした場合の抵抗値である。
FIG. 1 shows an equivalent circuit of a power supply line circuit according to the present invention. In FIG. 1, 5 and 6 are superconducting lines, 8 is a power supply branch line, 10 is a power supply, and 12 is a resistor.
Here, the main part of the wiring forming the power supply branch line 8 leading to each element element of the logic circuit is a series circuit of superconducting lines 5 and 6 having different impedances and a resistor 12 connected in series, and the resistance value of the resistor 12 is The value is equal to or smaller than the specific resistance of the element element of the logic circuit.
For example, in the case of a superconducting circuit, the specific resistance is a resistance value when the superconducting element is switched to a voltage state.

【0012】超電導線路5,6で、インピーダンスを違
えた値とする具体的な方法として、配線の単位面積当り
の容量を不連続に変化させる、あるいは、配線の幅を不
連続に変化させる、等の回路構造を用いる。たとえば、
電源線回路および各要素素子ともに絶縁膜を介して超電
導性の接地膜を配し、各分岐線の全体あるいは各分岐線
の一部と接地膜との間で構成される単位面積当りの容量
値を、要素素子の配線と接地膜との間で構成される単位
面積当りの容量値より大きい値とする。より具体的に
は、電源線回路の各分岐線の途中、あるいは要素素子と
の境界部で、各分岐線に重なる絶縁膜を比誘電率の異な
る絶縁膜に置き換えた構成とする。この結果、電源線回
路の各分岐線の途中の比誘電率の異なる絶縁膜の異なる
両側では、インピーダンスが異なることになる。
As a concrete method for changing the impedances of the superconducting lines 5 and 6, the capacitance per unit area of the wiring is discontinuously changed, or the width of the wiring is discontinuously changed. The circuit structure of is used. For example,
Capacitance value per unit area that is composed of the whole or a part of each branch line and the ground film by arranging the superconducting ground film through the insulating film in both the power line circuit and each element Is larger than the capacitance value per unit area formed between the wiring of the element element and the ground film. More specifically, the insulating film overlapping each branch line is replaced with an insulating film having a different relative permittivity in the middle of each branch line of the power line circuit or at the boundary with the element element. As a result, impedances are different on both sides of the insulating films having different relative permittivities in the middle of each branch line of the power supply line circuit.

【0013】さらにはこのような電源線回路において、
比誘電率の異なる2種類以上の絶縁膜を用いる。電源線
回路の各分岐線に重なる絶縁膜の全部あるいは一部には
比誘電率の高い絶縁物を用いる。要素素子の配線に重な
る絶縁膜、あるいは要素素子の配線と電源線回路の分岐
線の一部に重なる絶縁膜には、比誘電率の高い絶縁膜と
比誘電率の低い絶縁膜の層状構造として、実効的に低い
単位面積あたり容量を実現する。容量を構成する絶縁膜
の例として、チタン酸ストロンチウムをはじめとする高
誘電率の絶縁材料を用いる。
Furthermore, in such a power line circuit,
Two or more types of insulating films having different relative dielectric constants are used. An insulator having a high relative dielectric constant is used for all or part of the insulating film that overlaps each branch line of the power supply line circuit. The insulating film that overlaps with the wiring of the element element, or the insulating film that overlaps with the wiring of the element element and a part of the branch line of the power line circuit has a layered structure of an insulating film with a high relative dielectric constant and an insulating film with a low relative dielectric constant. , Effectively realizing a low capacity per unit area. As an example of the insulating film forming the capacitor, an insulating material having a high dielectric constant such as strontium titanate is used.

【0014】かかる電源線回路において、電源線回路の
給電するべき論理回路は超電導配線と超電導素子、すな
わち超電導接合と超電導インダクタを主要な回路要素と
して構成し、超電導接合を含む超電導配線の閉ループの
組合わせによって構成される超電導回路とする。超電導
回路では、超電導接合が要素素子としての役割を有す
る。このような超電導回路を伝搬する論理信号の担体は
磁束量子であり、磁束量子の移動によって信号を伝搬さ
せるものとする。すなわち超電導回路を伝搬する論理信
号は2個の状態間をスイッチするレベル信号ではなく、
信号が伝搬したあとは論理ゲートがもとの状態に戻るパ
ルス信号とする。
In such a power supply line circuit, a logic circuit to be fed by the power supply line circuit comprises a superconducting wire and a superconducting element, that is, a superconducting junction and a superconducting inductor as main circuit elements, and a closed loop set of superconducting wires including the superconducting junction. It will be a superconducting circuit composed by combining. In the superconducting circuit, the superconducting junction serves as an element element. The carrier of the logic signal propagating in such a superconducting circuit is a magnetic flux quantum, and the signal is propagated by the movement of the magnetic flux quantum. That is, the logic signal propagating in the superconducting circuit is not a level signal that switches between two states,
The pulse signal is used to return the logic gate to the original state after the signal propagates.

【0015】以下本発明を以下に述べる実施例にもとづ
いて説明する。 (実施例1)図1に示される構成の電源線回路を用い
て、ジョセフソン伝送路を構成した。図3、図4に電源
線回路を含むジョセフソン伝送路の一部の構成を模式的
に示した。図3は、後述する図7に示すフリップフロッ
プ回路のジョセフソン伝送路にあたる部分とこれにバイ
アス電流を供給する電源線の部分とを示す平面図を模式
的に示す図である。図4は、図3におけるA−A位置で
の断面を矢印方向に見た断面図である。
The present invention will be described below based on the following embodiments. (Embodiment 1) A Josephson transmission line was constructed using the power supply line circuit having the construction shown in FIG. 3 and 4 schematically show the configuration of part of the Josephson transmission line including the power supply line circuit. FIG. 3 is a diagram schematically showing a plan view showing a portion corresponding to the Josephson transmission line of the flip-flop circuit shown in FIG. 7, which will be described later, and a portion of a power supply line for supplying a bias current thereto. FIG. 4 is a cross-sectional view of the cross section at the AA position in FIG. 3 as seen in the arrow direction.

【0016】図3において、401は超電導線であり、
その中間部に超電導接合42が形成されている。超電導
線401の一端は超電導接続46を介して超電導性の接
地膜52に接続される。41はインダクタであり、超電
導線401の他端を順次接続する。超電導線401と超電
導接合42の直列回路が、インダクタ41で順次接続さ
れることでジョセフソン伝送路が形成される。402
超電導線であり、その一部に抵抗43が形成されてい
る。抵抗43が形成された超電導線402は電源分岐線
44として機能するものとなり、その一端は超電導線4
1とインダクタ41との接続点に接続され、他端は電
源線48に接続される。ここで、53,54は、高誘電
率層間絶縁膜、低誘電率層間絶縁膜の領域を示す。すな
わち、電源分岐線44は、高誘電率層間絶縁膜53の領
域と低誘電率層間絶縁膜54の領域が交差する位置でイ
ンピーダンスが変化する。
In FIG. 3, reference numeral 40 1 is a superconducting wire,
A superconducting junction 42 is formed in the middle part thereof. One end of the superconducting wire 40 1 is connected to a superconducting ground film 52 via a superconducting connection 46. Reference numeral 41 is an inductor, which sequentially connects the other ends of the superconducting wires 40 1 . A series circuit of the superconducting wire 40 1 and the superconducting junction 42 is sequentially connected by the inductor 41 to form a Josephson transmission line. 40 2 is a superconducting wire, and a resistor 43 is formed on a part of it. The superconducting wire 40 2 on which the resistor 43 is formed functions as a power supply branch line 44, and one end of the superconducting wire 40 2 is connected to the superconducting wire 4 2.
0 1 and the inductor 41 are connected to each other, and the other end is connected to the power supply line 48. Here, reference numerals 53 and 54 denote regions of the high dielectric constant interlayer insulating film and the low dielectric constant interlayer insulating film. That is, the impedance of the power supply branch line 44 changes at the position where the region of the high dielectric constant interlayer insulating film 53 and the region of the low dielectric constant interlayer insulating film 54 intersect.

【0017】回路は酸化物系の高温超電導薄膜を用いて
作製した。図4に示す断面図において、51は基板、5
2は超電導性の接地膜、53は高誘電率層間絶縁膜、5
4は低誘電率層間絶縁膜、55は超電導電極膜、56は
層間絶縁膜、57は超電導接合、58は超電導電極膜、
59は抵抗膜である。図4に示す構成要素と図3におけ
るそれとの関係は、超電導接合57が超電導接合42
に、超電導電極膜55が超電導線401に、超電導電極
膜58が電源分岐線44および電源線48に、抵抗膜5
9が抵抗43に、それぞれ、対応する。
The circuit was manufactured using an oxide-based high temperature superconducting thin film. In the cross-sectional view shown in FIG.
2 is a superconducting ground film, 53 is a high dielectric constant interlayer insulating film, 5
4 is a low dielectric constant interlayer insulating film, 55 is a superconducting electrode film, 56 is an interlayer insulating film, 57 is a superconducting junction, 58 is a superconducting electrode film,
Reference numeral 59 is a resistance film. The relationship between the components shown in FIG. 4 and that in FIG. 3 is that the superconducting junction 57 is
In addition, the superconducting electrode film 55 is provided on the superconducting wire 40 1 , the superconducting electrode film 58 is provided on the power supply branch line 44 and the power supply line 48, and the resistance film 5 is formed.
9 corresponds to the resistor 43, respectively.

【0018】層間絶縁膜53および54には高比誘電率
および低比誘電率の2種類の絶縁材料を用いた。ジョセ
フソン伝送路の全体と、電源線回路の分岐線44がジョ
セフソン伝送路に繋がる部分には、低誘電率の層間絶縁
膜を用いた。さらに電源線回路の分岐線の大部分には高
誘電率の層間絶縁膜を用いた。
Two kinds of insulating materials having a high relative dielectric constant and a low relative dielectric constant are used for the interlayer insulating films 53 and 54. An interlayer insulating film having a low dielectric constant was used for the entire Josephson transmission line and the portion where the branch line 44 of the power supply line circuit is connected to the Josephson transmission line. Furthermore, a high dielectric constant interlayer insulating film is used for most of the branch lines of the power line circuit.

【0019】基板51にはランタン・ストロンチウム・
アルミニウム・タンタル酸化物(LSAT)単結晶を用
いた。超電導電極、配線膜および超電導接地膜にはイッ
トリウム・バリウム・銅酸化物(YBCO)膜を用い
た。抵抗にはAu膜を用いた。低誘電率の層間絶縁膜に
はセリウム酸化物(CeO)を、高誘電率の層間絶縁膜
にはチタン酸ストロンチウム(SrTiO)を用いた。
超電導接合は下部電極膜の端部にイオンビームを照射し
て損傷を与え、これを障壁層とし、この上に上部電極膜
を形成する構成とした。YBCO膜、Au膜、CeO膜
およびSrTiO膜等は酸素雰囲気中のレーザ蒸着法に
よって形成した。
The substrate 51 has lanthanum, strontium, and
Aluminum tantalum oxide (LSAT) single crystal was used. An yttrium-barium-copper oxide (YBCO) film was used for the superconducting electrode, the wiring film, and the superconducting ground film. An Au film was used for the resistance. Cerium oxide (CeO) was used for the low dielectric constant interlayer insulating film, and strontium titanate (SrTiO) was used for the high dielectric constant interlayer insulating film.
In the superconducting junction, the edge of the lower electrode film is irradiated with an ion beam to damage it, and this is used as a barrier layer, and the upper electrode film is formed thereon. The YBCO film, Au film, CeO film, SrTiO film, etc. were formed by a laser deposition method in an oxygen atmosphere.

【0020】層間絶縁CeO膜およびSrTiO膜の膜
厚は300nmであった。容量の測定結果によれば、C
eO膜の比誘電率は20であり、SrTiO膜の比誘電
率はほぼ500であった。作製された超電導接合の温度
20Kでの臨界電流は0.2mA、電圧状態での抵抗は
5オーム、接合性能の指標であるこれらの値の積は1m
Vであった。分岐線を構成する抵抗の値は5オームとし
た。ジョセフソン伝送路および、電源線回路の分岐線の
線幅は1ミクロンとした。また分岐線が1本に繋がる配
線幅も1ミクロンとした。各分岐線のジョセフソン伝送
路までの長さは15ミクロンとした。この分岐線の長さ
は周波数200ギガヘルツの高周波信号が伝搬する場合
の波長の1/4倍より長い。
The film thickness of the interlayer insulating CeO film and the SrTiO film was 300 nm. According to the capacity measurement result, C
The relative dielectric constant of the eO film was 20, and the relative dielectric constant of the SrTiO film was approximately 500. The produced superconducting junction has a critical current of 0.2 mA at a temperature of 20 K, a resistance in a voltage state of 5 ohms, and a product of these values, which is an index of junction performance, is 1 m.
It was V. The resistance value of the branch line was 5 ohms. The line width of the Josephson transmission line and the branch line of the power supply line circuit was 1 micron. Also, the width of the wiring that connects one branch line is set to 1 micron. The length of each branch line to the Josephson transmission line was set to 15 microns. The length of this branch line is longer than ¼ times the wavelength when a high-frequency signal with a frequency of 200 GHz propagates.

【0021】このような構成になるジョセフソン伝送路
を伝搬する磁束量子信号の、超電導接合間伝搬時間の電
源電流に対する依存性は以下のような結果になった。す
なわち図5に、本発明に係る電源線回路を用いた場合に
おけるジョセフソン伝送路の超電導接合間での伝搬遅延
時間を参照符号64で、従来の抵抗のみの電源分岐線を
用いたジョセフソン伝送路の伝搬遅延時間を参照符号6
5で、それぞれ臨界電流に対する電源電流の割合を横軸
にとって示した。
The dependence of the magnetic flux quantum signal propagating through the Josephson transmission line having such a structure on the power supply current of the propagation time between superconducting junctions has resulted in the following result. That is, referring to FIG. 5, reference numeral 64 denotes a propagation delay time between superconducting junctions of a Josephson transmission line when the power supply line circuit according to the present invention is used, and the Josephson transmission using a conventional power supply branch line having only resistance. Reference numeral 6 for the propagation delay time of the path
5 shows the ratio of the power supply current to the critical current on the horizontal axis.

【0022】本実施例のジョセフソン伝送路では電源電
流に対する動作領域も、臨界電流に近い電源電流側で拡
がっていることがわかった。また本発明の構成になるジ
ョセフソン伝送路の電源電流に対する周波数特性は各電
源分岐線44を独立にし、個別に直流電流を供給した場
合と同様の特性であった。また電源分岐線44の1本当
りの消費電力は0.13マイクロワットであり、超電導
接合が電圧状態に遷移している場合の消費電力とほぼ等
しい。電源分岐線の占有面積は1ミクロンx15ミクロ
ンであり、配線の微細化によってさらに縮小できる。
It was found that in the Josephson transmission line of this embodiment, the operating region for the power supply current also widens on the power supply current side near the critical current. Further, the frequency characteristic of the Josephson transmission line having the configuration of the present invention with respect to the power supply current was the same as that when the power supply branch lines 44 were made independent and the direct current was supplied individually. The power consumption of each power supply branch line 44 is 0.13 microwatts, which is almost the same as the power consumption when the superconducting junction is in the voltage state. The area occupied by the power supply branch line is 1 micron × 15 micron, and can be further reduced by miniaturizing the wiring.

【0023】このように本発明に係るジョセフソン伝送
路の動作領域が拡がり、かつ周波数性能が向上したのは
以下の理由によるものである。本実施例で掲げた磁束量
子を信号の担体とする超電導回路で、動作領域を狭くし
ている要因は磁束量子が超電導接合を通過するときに、
超電導接合から発生する電流パルスが必ずしもジョセフ
ソン伝送路のみを伝搬しないことにある。
The reason why the operation area of the Josephson transmission line according to the present invention is widened and the frequency performance is improved is as follows. In the superconducting circuit using the magnetic flux quantum as a signal carrier in the present embodiment, the reason for narrowing the operation region is that the magnetic flux quantum passes through the superconducting junction.
This is because the current pulse generated from the superconducting junction does not necessarily propagate only in the Josephson transmission line.

【0024】すなわち磁束量子の伝搬にともなって、ジ
ョセフソン伝送路を電流パルスが伝わるだけでなく、電
流パルスの一部は電源分岐線44にも伝わる。この電流
パルスは隣接する電源分岐線44を伝わって、隣接する
超電導接合の電源電流に加算される。このために、この
ような現象の存在しない場合と比較して、動作可能な電
源電流の上限が低下する。
That is, along with the propagation of the magnetic flux quantum, not only the current pulse is transmitted through the Josephson transmission line, but also a part of the current pulse is transmitted to the power supply branch line 44. This current pulse propagates through the adjacent power supply branch line 44 and is added to the power supply current of the adjacent superconducting junction. Therefore, the upper limit of the operable power supply current is reduced as compared with the case where such a phenomenon does not exist.

【0025】磁束量子信号は数百ギガヘルツの高周波パ
ルス信号である。この周波数成分は超電導接合の臨界電
流と電圧状態での抵抗の積に比例し、この積が1mVの
場合、300−500ギガヘルツまで達する。このよう
な高い周波数のパルスの伝搬を制御するには分布定数回
路として電源線回路を設計することによって可能とな
る。すなわち、電源分岐線44の長さが磁束量子パルス
信号の波長と同等か、これより長ければ、単なる抵抗の
大きさや、インダクタンスと抵抗の比で信号振幅を減衰
させる集中定数に基づいた設計ではなく、磁束量子パル
ス信号を波として処理する必要がある。
The magnetic flux quantum signal is a high frequency pulse signal of several hundred gigahertz. This frequency component is proportional to the product of the critical current of the superconducting junction and the resistance in the voltage state, and when the product is 1 mV, it reaches 300 to 500 GHz. It is possible to control the propagation of such a high frequency pulse by designing a power supply line circuit as a distributed constant circuit. That is, if the length of the power supply branch line 44 is equal to or longer than the wavelength of the magnetic flux quantum pulse signal, the design is not based on the mere resistance size or the lumped constant that attenuates the signal amplitude by the ratio of the inductance and the resistance. , It is necessary to process the magnetic flux quantum pulse signal as a wave.

【0026】すなわち本実施例の電源分岐線44では、
接地面との間の層間絶縁膜が比誘電率20のCeO膜か
ら、比誘電率500のSrTiO膜に不連続に移り変わ
る。ここでインピーダンスや磁束量子パルス信号の伝搬
速度に5倍以上のずれが生じる。したがって電源分岐線
44に漏れた磁束量子パルス信号成分はこの不連続部分
で反射され、元に戻る。電源分岐線44を伝搬して、隣
接する電源分岐線44を伝わり、磁束量子によって遷移
しようとする超電導接合に達することはない。
That is, in the power supply branch line 44 of this embodiment,
The interlayer insulating film between the ground plane and the CeO film having a relative permittivity of 20 changes discontinuously to the SrTiO film having a relative permittivity of 500. Here, the impedance and the propagation velocity of the magnetic flux quantum pulse signal are deviated five times or more. Therefore, the magnetic flux quantum pulse signal component leaked to the power supply branch line 44 is reflected at this discontinuous portion and returns to the original state. It does not propagate through the power supply branch line 44, propagate through the adjacent power supply branch line 44, and reach the superconducting junction which is about to transit due to the flux quantum.

【0027】このような様子は図6に示されるSパラメ
ータの周波数依存性によっても明らかである。図6
(A)は、図3の回路構成で、ジョセフソン伝送路を除
いて、電源線回路のみを残し、一つの電源分岐線に着目
して、これを伝搬して、隣接する電源分岐線に達する信
号のSパラメータを示した。ここで、本発明に係る電源
分岐線における反射信号強度を62に、本発明に係る電
源分岐線における伝搬信号強度を63に示した。図から
明らかなように、50ギガヘルツ以上の周波数領域では
隣接する電源分岐線に達する信号成分は10%以下であ
り、大部分は信号を発生した電源分岐線に戻る。なお、
図の特性は、計算した回路の構造に依存するものであ
り、この種の回路に共通する特性と言うわけではない
が、本発明のように、電源分岐線にインピーダンスの不
連続性を持たせた結果として、電源分岐線を介しての信
号伝播を効果的に抑制できるものとできることを示すも
のである。電流分布の周波数依存性でも、図示しなかっ
たが、50ギガヘルツ以上の周波数領域において、隣接
する電源分岐線の低誘電率側に流れ込む電流密度が十分
低くなることが分かった。このような現象は高周波信号
の誘電率の不連続に変化する部分、すなわち、インピー
ダンスの不連続に変化する部分での反射によるものであ
る。SrTiOのような高誘電率の絶縁材料を用いるこ
とは、インピーダンスの不連続を生じることと、電源分
岐線の線路長を短くできる効果がある。
Such a situation is apparent from the frequency dependence of the S parameter shown in FIG. Figure 6
(A) is the circuit configuration of FIG. 3, except for the Josephson transmission line, leaving only the power supply line circuit, focusing on one power supply branch line, propagating this, and reaching the adjacent power supply branch line. The S-parameters of the signal are shown. Here, the reflected signal strength at the power supply branch line according to the present invention is shown at 62, and the propagation signal strength at the power supply branch line according to the present invention is shown at 63. As is clear from the figure, in the frequency region of 50 GHz or higher, the signal components reaching the adjacent power supply branch lines are 10% or less, and most of them return to the power supply branch line which generated the signal. In addition,
The characteristics shown in the figure depend on the calculated circuit structure, and are not common characteristics of this type of circuit. However, as in the present invention, the power supply branch line has impedance discontinuity. As a result, it is shown that signal propagation through the power supply branch line can be effectively suppressed. Although not shown in the figure, the frequency dependence of the current distribution revealed that the current density flowing into the low dielectric constant side of the adjacent power supply branch line was sufficiently low in the frequency region of 50 GHz or higher. Such a phenomenon is due to reflection at a portion where the permittivity of the high frequency signal changes discontinuously, that is, a portion where the impedance changes discontinuously. Using an insulating material having a high dielectric constant such as SrTiO has the effects of causing impedance discontinuity and shortening the line length of the power supply branch line.

【0028】CeO酸化物のみを層間絶縁膜として電源
線回路を構成した場合、すなわち電源分岐線にインピー
ダンスの不連続が無い状態での電源分岐線のSパラメー
タを、比較のために、図6(B)に示した。電源分岐線
における反射信号強度を62’に、電源分岐線における
伝搬信号強度を63’に示した。周波数100GHzま
では隣接する電源分岐線に伝搬する信号強度の方が強
い。これ以上の周波数でも、信号を発した分岐線に戻る
信号強度の方が強いが、その隣接する電源分岐線に伝搬
する信号強度との差は僅かである。
For comparison, the S parameter of the power supply branch line in the case where the power supply line circuit is formed by using only CeO oxide as the interlayer insulating film, that is, in the state where there is no impedance discontinuity in the power supply branch line, is shown in FIG. It is shown in B). The reflected signal strength at the power supply branch line is shown at 62 ', and the propagation signal strength at the power supply branch line is shown at 63'. The signal strength propagating to the adjacent power supply branch line is stronger up to the frequency of 100 GHz. At frequencies higher than this, the signal strength returning to the branch line that has generated the signal is stronger, but the difference from the signal strength propagating to the adjacent power supply branch line is small.

【0029】以上述べたごとく、本発明に係る電源線回
路によれば、論理回路の動作領域の拡大、電源線回路の
消費電力の低減、および電源線回路を中心とした論理ゲ
ート占有面積の縮小と、論理回路の高密度化を図ること
ができ、デジタル回路の高集積化と高機能化を可能にす
るものである。 (実施例2)本電源線回路を用いてセット・リセット・
フリップフロップ回路(フリップフロップと略称)を作
製した。作製したフリップフロップの等価回路を図7に
示した。図7において、100はフリップフロップであ
る。311はセット信号発生回路、312はリセット信号
発生回路である。これらの信号発生回路は信号源14と
抵抗15およびインダクタ16の直列回路と超電導接合
17からなり、信号源14のレベル信号を磁束量子信号
へ変換して出力する回路である。セット信号発生回路3
1、リセット信号発生回路312から発生された信号
は、実施例1で説明したインダクタ16と超電導接合1
7とからなるジョセフソン伝送路32を介してフリップ
フロップ100のセット端子101、リセット端子10
2に加えられる。この実施例のフリップフロップ100
では、セット端子101にセット信号が加えられると、
このことがインダクタ16の周回電流の形で保存され
る。インダクタ16に周回電流があるときにリセット端
子102にリセット信号が加えられると出力端子104
に出力信号が出力される。インダクタ16に周回電流が
無いときにリセット端子102にリセット信号が加えら
れても出力端子104に出力信号が出力されることは無
い。出力端子104の出力信号はインダクタ16と超電
導接合17とからなるジョセフソン伝送路32を介して
出力インタフェイスである磁束量子信号からレベル信号
への変換回路33に伝送される。
As described above, according to the power supply line circuit of the present invention, the operating area of the logic circuit is expanded, the power consumption of the power supply line circuit is reduced, and the area occupied by the logic gate centering on the power supply line circuit is reduced. With this, it is possible to increase the density of the logic circuit, and to achieve high integration and high functionality of the digital circuit. (Example 2) Set / reset by using this power line circuit
A flip-flop circuit (abbreviated as flip-flop) was manufactured. An equivalent circuit of the produced flip-flop is shown in FIG. In FIG. 7, 100 is a flip-flop. Reference numeral 31 1 is a set signal generation circuit, and 31 2 is a reset signal generation circuit. These signal generating circuits consist of a signal source 14, a series circuit of a resistor 15 and an inductor 16 and a superconducting junction 17, and are circuits for converting the level signal of the signal source 14 into a magnetic flux quantum signal and outputting it. Set signal generation circuit 3
1 1 , the signal generated from the reset signal generation circuit 31 2 is the inductor 16 and the superconducting junction 1 described in the first embodiment.
And a reset terminal 10 of the flip-flop 100 via a Josephson transmission line 32 composed of
Added to 2. Flip-flop 100 of this embodiment
Then, when a set signal is applied to the set terminal 101,
This is stored in the form of a circulating current in the inductor 16. When a reset signal is applied to the reset terminal 102 when the inductor 16 has a circulating current, the output terminal 104
The output signal is output to. Even if a reset signal is applied to the reset terminal 102 when the inductor 16 has no circulating current, no output signal is output to the output terminal 104. The output signal of the output terminal 104 is transmitted to the conversion circuit 33 for converting a magnetic flux quantum signal into a level signal, which is an output interface, through the Josephson transmission line 32 including the inductor 16 and the superconducting junction 17.

【0030】これらのフリップフロップ100およびジ
ョセフソン伝送路32には、前述したようにバイアス電
流を供給するための電源が必要である。本実施例でも、
図1に示される構成の電源線回路を用いてバイアス電流
を供給する。10は電源であり、11は超電導線路であ
る。ここで、超電導線路11は、図1における超電導線
路5、6の直列回路と同じ構成であるが、図を簡略化す
るために図のような表示とした。本実施例の超電導回路
における要素素子は超電導接合である。超電導接合を含
む超電導閉ループを基本として超電導回路を構成し、磁
束量子を信号の担体とする回路動作方式とした。
The flip-flop 100 and the Josephson transmission line 32 require a power supply for supplying a bias current as described above. Also in this embodiment,
A bias current is supplied using the power supply line circuit having the configuration shown in FIG. Reference numeral 10 is a power source, and 11 is a superconducting line. Here, the superconducting line 11 has the same configuration as the series circuit of the superconducting lines 5 and 6 in FIG. 1, but the display is as shown in the figure in order to simplify the figure. The element element in the superconducting circuit of this embodiment is a superconducting junction. A superconducting circuit is constructed based on a superconducting closed loop including a superconducting junction, and a circuit operation method is used in which magnetic flux quantum is used as a signal carrier.

【0031】図に示すように、各要素素子としての超電
導接合に対して、1本の電源分岐線を接続した。電源分
岐線は抵抗12と超電導線11の直列接続とした。各電
源分岐線は1本に纏め、チップ外部の電源10に接続し
た。
As shown in the figure, one power supply branch line was connected to the superconducting junction as each element element. The power supply branch line was a series connection of a resistor 12 and a superconducting wire 11. Each power supply branch line was bundled into one and connected to the power supply 10 outside the chip.

【0032】このような超電導フリップフロップ回路の
1部の断面構造例を図8に示した。図8は、図3に示す
A−A位置に対応する部分の断面図である。図8におい
て、51は基板、52は接地面、53は高誘電率層間絶
縁膜、54は低誘電率層間絶縁膜、55は超電導電極
膜、56は層間絶縁膜、57は超電導接合、58は超電
導電極膜、59は抵抗膜である。基板51はLSAT単
結晶とした。超電導接合57はランプエッジ型で、下部
電極端面にアルゴンイオンを照射して形成した損傷層を
障壁層とし、YBCO膜を電極55,58として構成し
た。接地膜52はYBCO膜とし、接地膜と超電導接合
の電極間、あるいは接地膜と配線膜間の絶縁にはSTO
膜を用いた。フリップフロップ回路本体では接地膜に被
覆する層間絶縁膜をSTO膜とCeO膜の積層構造5
3,54とし、電源分岐線を含めた電源線回路部では接
地膜に被覆する層間絶縁膜をSTO膜の単層53とし
た。超電導接合の電圧状態での抵抗値は5オームから1
0オームの範囲にあった。抵抗59には金膜を用いた。
An example of a sectional structure of a part of such a superconducting flip-flop circuit is shown in FIG. FIG. 8 is a sectional view of a portion corresponding to the position AA shown in FIG. In FIG. 8, 51 is a substrate, 52 is a ground plane, 53 is a high dielectric constant interlayer insulating film, 54 is a low dielectric constant interlayer insulating film, 55 is a superconducting electrode film, 56 is an interlayer insulating film, 57 is a superconducting junction, and 58 is The superconducting electrode film and 59 are resistance films. The substrate 51 was an LSAT single crystal. The superconducting junction 57 was a lamp edge type, and the damaged layer formed by irradiating the end face of the lower electrode with argon ions was used as the barrier layer, and the YBCO film was used as the electrodes 55 and 58. The ground film 52 is a YBCO film, and STO is used for insulation between the ground film and the electrodes of the superconducting junction or between the ground film and the wiring film.
A membrane was used. In the flip-flop circuit body, the interlayer insulating film covering the ground film is a laminated structure of STO film and CeO film 5
In the power supply line circuit portion including the power supply branch line, the interlayer insulating film covering the ground film is a single layer 53 of the STO film. The resistance value of the superconducting junction in the voltage state is 5 ohms to 1
It was in the 0 ohm range. A gold film was used for the resistor 59.

【0033】図8に例示した構造と前述した図4とで
は、図を対比して分かるように、本質的な差異はなく、
高誘電率層間絶縁膜53および低誘電率層間絶縁膜54
の積層構造が異なるのみである。
There is no essential difference between the structure illustrated in FIG. 8 and the above-described FIG.
High dielectric constant interlayer insulating film 53 and low dielectric constant interlayer insulating film 54
The only difference is the laminated structure of.

【0034】あらかじめ数値シミュレーションによっ
て、各超電導接合に供給するべき電流の最適値を計算し
た。これらの電流に反比例する値として、電源分岐線4
4の抵抗値を算出した。抵抗12の平均的な値は3オー
ムとした。これに対して電源分岐線44の配線長は20
ミクロンとした。
The optimum value of the current to be supplied to each superconducting junction was calculated in advance by numerical simulation. As a value inversely proportional to these currents, the power supply branch line 4
The resistance value of 4 was calculated. The average value of the resistance 12 was 3 ohms. On the other hand, the wiring length of the power supply branch line 44 is 20
Micron was used.

【0035】図9に実施例2によるフリップフロップ回
路の動作波形を示す。先にも述べたように、セット信号
21が入力された状態で、リセット信号22が入力され
た場合、出力信号が得られ、磁束量子信号からレベル信
号への変換回路33で出力信号23が検出される。一
方、セット信号21の入力のない状態で、リセット信号
22が入力された場合、出力信号は得られず、磁束量子
信号からレベル信号への変換回路では出力信号が検出さ
れない。実施例2による回路の動作波形を測定したとこ
ろ、フリップフロップとしての動作が確認された。
FIG. 9 shows operation waveforms of the flip-flop circuit according to the second embodiment. As described above, when the reset signal 22 is input while the set signal 21 is input, an output signal is obtained, and the output signal 23 is detected by the conversion circuit 33 from the magnetic flux quantum signal to the level signal. To be done. On the other hand, if the reset signal 22 is input without the input of the set signal 21, no output signal is obtained, and the output signal is not detected by the conversion circuit from the magnetic flux quantum signal to the level signal. When the operation waveform of the circuit according to Example 2 was measured, the operation as a flip-flop was confirmed.

【0036】図10に、実施例2によるフリップフロッ
プ回路で電源電流を変えて、フリップフロップ動作可能
な電源電流の領域を示した。回路全体で、CeO膜を接
地面上の層間絶縁層として用いた場合を含めて、60が
本発明に係る電源分岐線による電源電流の動作領域を示
し、61が従来の抵抗のみの電源分岐線による電源電流
の動作領域を示す。図から明らかなように、本実施例で
は電源電流の動作領域が拡大した。このように動作領域
が広がることにより、集積度を高めて、超電導臨界電流
等、要素素子特性の不均一性が拡大した場合でも、回路
の動作が可能となった。
FIG. 10 shows a region of the power supply current in which the flip-flop circuit according to the second embodiment can change the power supply current and perform the flip-flop operation. In the entire circuit, including the case where the CeO film is used as the interlayer insulating layer on the ground plane, 60 indicates the operating region of the power supply current by the power supply branch line according to the present invention, and 61 is the conventional power supply branch line with only resistance. Shows the operating region of the power supply current by. As is clear from the figure, the operating region of the power supply current is expanded in this embodiment. By expanding the operating region in this way, it is possible to increase the degree of integration and operate the circuit even when the nonuniformity of the element element characteristics such as the superconducting critical current is expanded.

【0037】本実施例での超電導接合1個当りの平均的
な通電電流は0.15mAである。したがって超電導接
合1個当りの、電流供給線の平均的な消費電力は75ナ
ノワットである。一方、従来構造の電源分岐線を用いた
場合、平均的な消費電力は抵抗値に比例して増大する。
フリップフロップ動作を安定化させるために抵抗値を超
電導接合抵抗の10倍とした場合、消費電力は1.1マ
イクロワットとなる。このように、本発明に係る電源線
回路構造は従来構造と比較して広い動作領域のみでな
く、低い消費電力性能を示す。
The average energizing current per superconducting junction in this example is 0.15 mA. Therefore, the average power consumption of the current supply line per superconducting junction is 75 nanowatts. On the other hand, when the power supply branch line having the conventional structure is used, the average power consumption increases in proportion to the resistance value.
When the resistance value is set to 10 times the superconducting junction resistance in order to stabilize the flip-flop operation, the power consumption becomes 1.1 microwatt. As described above, the power supply line circuit structure according to the present invention exhibits not only a wide operating area but also low power consumption performance as compared with the conventional structure.

【0038】本実施例に示されるごとく、本発明に係る
電源線回路を用いることによって、動作領域が広がり、
消費電力を低減できるとともに、回路面積を縮小でき
た。したがって、回路の高密度化と高集積化が可能であ
る。 (実施例3)図1に示される構成の電源線回路を用い
て、4段シフトレジスタ回路を作製した。作製したシフ
トレジスタの等価回路を図11に示した。本実施例の4
段シフトレジスタ回路は、超電導接合線路JTLおよび
分岐回路SPがカスケードに接続されたクロック信号線
回路34と、超電導接合線路JTLおよびセット・リセ
ット・フリップフロップrs−FFがカスケードに接続
されたデータ信号線回路36およびそれぞれの対となる
分岐回路SPとセット・リセット・フリップフロップr
s−FFとを超電導接合線路JTLによって結合した分
岐回路35による構成とした。最終段は分岐回路SPは
無い。クロック信号線回路34の第1段の超電導接合線
路121には、図7で説明したセットあるいはリセット
信号発生回路31と同様に磁束量子信号が加えられる。
超電導接合線路121から出力される磁束量子信号は分
岐回路122で2個の磁束量子信号に分割されてそれぞ
れの後段に設けられた超電導接合線路123、124に
加えられる。超電導接合線路124の出力段にはセット
・リセット・フリップフロップrs−FF126が設け
られる。セット・リセット・フリップフロップrs−F
F126には、もう一つの超電導接合線路125の出力
が加えられる。超電導接合線路125には、データ入力
信号が加えられている。セット・リセット・フリップフ
ロップrs−FF126は超電導接合線路125を介し
て加えられたデータ入力信号を保持しているが、超電導
接合線路124からクロック信号が出力されるとこれを
超電導接合線路127を介してセット・リセット・フリ
ップフロップrs−FF128に送る。このような分岐
回路SPとセット・リセット・フリップフロップrs−
FFを4個カスケードに配列して4ビットのシフトレジ
スタとしたものである。
As shown in this embodiment, by using the power supply line circuit according to the present invention, the operating region is expanded,
The power consumption can be reduced and the circuit area can be reduced. Therefore, higher density and higher integration of the circuit are possible. (Example 3) A four-stage shift register circuit was manufactured using the power supply line circuit having the configuration shown in FIG. An equivalent circuit of the manufactured shift register is shown in FIG. 4 of this embodiment
The stage shift register circuit includes a clock signal line circuit 34 in which a superconducting junction line JTL and a branch circuit SP are connected in a cascade, and a data signal line in which a superconducting junction line JTL and a set / reset flip-flop rs-FF are connected in a cascade. Circuit 36 and branch circuits SP and set / reset flip-flops r that form a pair
The s-FF and the s-FF are connected by a superconducting junction line JTL to form a branch circuit 35. There is no branch circuit SP at the final stage. A magnetic flux quantum signal is applied to the first-stage superconducting junction line 121 of the clock signal line circuit 34 similarly to the set or reset signal generation circuit 31 described with reference to FIG.
The magnetic flux quantum signal output from the superconducting junction line 121 is divided into two magnetic flux quantum signals by the branch circuit 122 and added to the superconducting junction lines 123 and 124 provided in the subsequent stages. A set / reset flip-flop rs-FF 126 is provided at the output stage of the superconducting junction line 124. Set / reset flip-flop rs-F
The output of another superconducting junction line 125 is applied to F126. A data input signal is applied to the superconducting junction line 125. The set / reset flip-flop rs-FF 126 holds the data input signal applied via the superconducting junction line 125. To the set / reset flip-flop rs-FF128. Such a branch circuit SP and a set / reset flip-flop rs-
This is a 4-bit shift register in which four FFs are arranged in a cascade.

【0039】本実施例の4ビットのシフトレジスタも、
それぞれの要素素子は、当然電源が必要であり、図1に
示される構成の電源線回路を用いて、電源電流を供給す
るものとした。10は電源、11は超電導線路、12は
抵抗である。図では、セット・リセット・フリップフロ
ップrs−FF、超電導接合線路JTLおよび分岐回路
SPのそれぞれに、1つの電源分岐線で電源を供給する
形で示したが、たとえば、図3および図7で説明したよ
うに、超電導接合線路JTLが複数の要素素子から成っ
ているときはそでぞれに電源分岐線を設けて電源を供給
することが必要であることは言うまでもない。各超電導
接合に対して、電源10から分岐した抵抗11と超電導
線12の直列接続よりなる電源分岐線で電源を供給す
る。シフトレジスタの各要素素子に至る電源分岐線は1
本に纏め、チップ外部の電源10に接続した。抵抗12
の値は2オームとした。
The 4-bit shift register of this embodiment is also
Each element element naturally needs a power supply, and the power supply line circuit configured as shown in FIG. 1 is used to supply a power supply current. Reference numeral 10 is a power source, 11 is a superconducting line, and 12 is a resistor. In the figure, the set / reset flip-flop rs-FF, the superconducting junction line JTL, and the branch circuit SP are shown to be supplied with power by a single power supply branch line. As described above, it goes without saying that when the superconducting junction line JTL is composed of a plurality of element elements, it is necessary to provide a power supply branch line for each of them to supply power. Power is supplied to each superconducting junction by a power branch line formed by a series connection of a resistor 11 and a superconducting wire 12 branched from a power source 10. The power branch line to each element of the shift register is 1
It was put together in a book and connected to a power source 10 outside the chip. Resistance 12
The value of was 2 ohms.

【0040】シフトレジスタ回路の一部の構造図を図1
2に示した。図12において、40は超電導線、41は
インダクタ、42は超電導接合、43は抵抗、44は電
源分岐線、54は接地面、46は超電導接続、48は電
源線である。実施例1における電源線回路とは異なり、
電源分岐線を纏める配線48の線幅を電源分岐線の幅の
5倍とした。電源分岐線を纏める配線48の線幅が5倍
とされたことを除けば、図3で説明した構造図と本質的
に異なることはない。シフトレジスタ回路はYBCO超
電導薄膜を用いて作製した。基板はLSAT単結晶とし
た。超電導接合はランプエッジ型で下部電極端面にアル
ゴンイオンを照射して形成した損傷層を障壁層とし、Y
BCO膜を電極として構成した。接地膜はYBCO膜と
し、接地膜と超電導接合の電極間、あるいは接地膜と配
線膜間の絶縁にはSTO膜を用いた。フリップフロップ
回路本体では接地膜に被覆する層間絶縁膜をSTO膜と
CeO膜の積層構造とし、電源分岐線を含めた電源線回
路部では接地膜に被覆する層間絶縁膜をSTO膜の単層
とした。超電導接合の電圧状態での抵抗値は5オームか
ら10オームの範囲にあった。抵抗には金膜を用いた。
FIG. 1 is a structural diagram of a part of the shift register circuit.
Shown in 2. In FIG. 12, 40 is a superconducting wire, 41 is an inductor, 42 is a superconducting junction, 43 is a resistance, 44 is a power supply branch line, 54 is a ground plane, 46 is a superconducting connection, and 48 is a power supply line. Unlike the power line circuit in the first embodiment,
The line width of the wiring 48 that bundles the power supply branch lines is set to 5 times the width of the power supply branch lines. Except that the line width of the wiring 48 for collecting the power supply branch lines is five times, there is essentially no difference from the structural diagram described in FIG. The shift register circuit was manufactured using a YBCO superconducting thin film. The substrate was LSAT single crystal. The superconducting junction is a lamp edge type, and the damage layer formed by irradiating the lower electrode end face with argon ions is used as a barrier layer.
The BCO film was used as an electrode. The ground film was a YBCO film, and the STO film was used for insulation between the ground film and the electrodes of the superconducting junction or between the ground film and the wiring film. In the flip-flop circuit body, the interlayer insulating film covering the ground film has a laminated structure of STO film and CeO film, and in the power line circuit section including the power supply branch line, the interlayer insulating film covering the ground film is a single layer of the STO film. did. The resistance value of the superconducting junction in the voltage state was in the range of 5 to 10 ohms. A gold film was used for the resistance.

【0041】図13に示されるごとく、クロック信号2
4にタイミングを合わせて、入力データの信号列25と
同様のビット列の出力信号列26が得られ、シフトレジ
スタとしての動作が実現していることが分かった。電源
電流に対する動作可能な領域はプラス・マイナス25%
であった。この値は電源分岐線の、抵抗の値を16オー
ムとし、超電導接合の電圧状態の抵抗値より十分大きく
した場合の動作可能な領域よりプラス・マイナス3%広
い値であった。
As shown in FIG. 13, the clock signal 2
It was found that an output signal train 26 of a bit train similar to the signal train 25 of the input data was obtained in synchronism with 4 and the operation as the shift register was realized. The operable area for the power supply current is plus or minus 25%
Met. This value was plus or minus 3% wider than the operable area when the resistance value of the power supply branch line was set to 16 ohms and was made sufficiently higher than the resistance value in the voltage state of the superconducting junction.

【0042】このように本発明に係る電源線回路を用い
てシフトレジスタを用いた場合、動作領域が広がったの
は電源線回路の寄与によるものであり、その機構は実施
例1で述べたとおりである。また本実施例での超電導接
合1個当りの、電流供給線の平均的な消費電力は50ナ
ノワットであり、従来構造の電流供給線を用いた場合の
約1/8であった。
As described above, when the shift register is used by using the power supply line circuit according to the present invention, the operation area is widened due to the contribution of the power supply line circuit, and its mechanism is as described in the first embodiment. Is. Further, the average power consumption of the current supply line per superconducting junction in this example was 50 nanowatts, which was about ⅛ that when the current supply line having the conventional structure was used.

【0043】本電源線回路を用いることによる動作領域
の拡大と、電源線回路の消費電力の低減、および占有面
積の縮小はフリップフロップやシフトレジスタだけでな
く、コンフルエンスバッファ、AND、OR、インバー
タゲート等他の回路でも当てはまる。さらにこれらの回
路を組合わせて構成された機能回路でも、回路全体とし
ての動作領域は拡大し、電源線回路の消費電力、および
占有面積を低減することができる。
The expansion of the operating region, the reduction of the power consumption of the power supply line circuit, and the reduction of the occupied area by using this power supply line circuit are not limited to the flip-flops and shift registers, but also confluence buffers, AND, OR, and inverter gates. The same applies to other circuits. Furthermore, even with a functional circuit configured by combining these circuits, the operating area of the entire circuit can be expanded, and the power consumption and occupied area of the power supply line circuit can be reduced.

【0044】[0044]

【発明の効果】以上、発明の実施の形態の項で述べたご
とく、本発明に係わる電源線回路は以下の効果を有す
る。 (1)電源線回路より電流供給する論理回路の動作領域
を拡大し、論理動作の実行を容易にする。 (2)電源線回路の消費電力を低減でき、回路全体の消
費電力を、信号の伝搬に必然的にともなう電力消費のレ
ベルまで低減することができる。 (3)電源線回路の占有面積を縮小でき、高密度化を可
能にする。 (4)デジタル回路の高集積化と高機能化を可能にす
る。
As described above in the embodiments of the invention, the power supply line circuit according to the present invention has the following effects. (1) The operation area of the logic circuit which supplies the current from the power supply line circuit is expanded to facilitate the execution of the logic operation. (2) The power consumption of the power supply line circuit can be reduced, and the power consumption of the entire circuit can be reduced to the level of power consumption that is inevitably involved in signal propagation. (3) The area occupied by the power supply line circuit can be reduced, and high density can be achieved. (4) It enables high integration and high functionality of digital circuits.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る電源線回路の等価回路。FIG. 1 is an equivalent circuit of a power supply line circuit according to the present invention.

【図2】従来用いられている電源線回路の等価回路。FIG. 2 is an equivalent circuit of a conventional power supply line circuit.

【図3】本発明に係る電源線回路を含むジョセフソン伝
送路の一部の構成例を模式的に示す図。
FIG. 3 is a diagram schematically showing a partial configuration example of a Josephson transmission line including a power supply line circuit according to the present invention.

【図4】図3のジョセフソン伝送路の一部の断面を示す
図。
FIG. 4 is a diagram showing a partial cross section of the Josephson transmission line of FIG. 3;

【図5】ジョセフソン伝送路の伝搬遅延時間のバイアス
電流割合に対する依存性を示す図。
FIG. 5 is a diagram showing the dependence of the propagation delay time of the Josephson transmission line on the bias current ratio.

【図6】本発明に係るジョセフソン伝送路のインピーダ
ンスの不連続性を有する電源分岐線のSパラメータの周
波数依存性を示す図。
FIG. 6 is a diagram showing the frequency dependence of the S parameter of the power supply branch line having the impedance discontinuity of the Josephson transmission line according to the present invention.

【図7】本発明に係る電源線回路を採用した超電導フリ
ップフロップの等価回路を示す図。
FIG. 7 is a diagram showing an equivalent circuit of a superconducting flip-flop adopting the power supply line circuit according to the present invention.

【図8】本発明に係る超電導フリップフロップ回路の1
部の断面構造例を、図3に示すA−A位置に対応する部
分の断面図として示す図。
FIG. 8: 1 of a superconducting flip-flop circuit according to the present invention
The figure which shows the cross-section example of a part as a cross-sectional view of the part corresponding to the AA position shown in FIG.

【図9】図7に示す超電導フリップフロップの動作波形
を示す図。
9 is a diagram showing operation waveforms of the superconducting flip-flop shown in FIG.

【図10】図7に示す超電導フリップフロップの動作可
能な電源電流の領域を示す図。
10 is a diagram showing an operable power supply current region of the superconducting flip-flop shown in FIG.

【図11】本発明に係る超電導シフトレジスタ回路の等
価回路を示す図。
FIG. 11 is a diagram showing an equivalent circuit of a superconducting shift register circuit according to the present invention.

【図12】本発明に係る電源線回路を採用した超電導シ
フトレジスタ回路の構造を示す図。
FIG. 12 is a diagram showing a structure of a superconducting shift register circuit adopting a power supply line circuit according to the present invention.

【図13】図12に示す超電導シフトレジスタ回路の動
作波形を示す図。
13 is a diagram showing operation waveforms of the superconducting shift register circuit shown in FIG.

【符号の説明】[Explanation of symbols]

5:超電導線路、6:超電導線路、8:電源分岐線、1
0:電源、11:超電導線路、12:抵抗、13:超電
導接合、14:信号源、15:抵抗、16:インダク
タ、17:超電導接合、21:セット信号、22:リセ
ット信号、23:磁束量子−レベル信号変換部出力信
号、24:クロック信号、25:入力データの信号列、
26:出力信号、31:セット、リセット信号発生回
路、32:ジョセフソン伝送路、33:磁束量子信号か
らレベル信号への変換回路、34:クロック信号線、3
5:分岐、36:データ信号線、40:超電導線、4
1:インダクタ、42:超電導接合、43:抵抗、4
4:電源分岐線、46:超電導接続、48:電源線、5
1:基板、52:接地面、53:高誘電率層間絶縁膜、
54:低誘電率層間絶縁膜、55:超電導電極膜、5
6:層間絶縁膜、57:超電導接合、58:超電導電極
膜、59:抵抗、60:本発明に係る電源分岐線を用い
たフリップフロップ回路の動作可能な電源電流領域、6
1:抵抗のみの電源分岐線を用いたフリップフロップ回
路の動作可能な電源電流領域、62:本発明に係る電源
分岐線における反射信号強度、63:本発明に係る電源
分岐線における伝搬信号強度、64:本発明に係る電源
分岐線を用いたジョセフソン伝送路の伝搬遅延時間、6
5:抵抗のみの電源分岐線を用いたジョセフソン伝送路
の伝搬遅延時間、100:フリップフロップ回路、10
1:フリップフロップ回路のセット端子、102:フリ
ップフロップ回路のリセット端子、JTL,121,1
23,125,127:超電導接合線路、rs−FF,
126,128:セット・リセット・フリップフロッ
プ、SP,122:分岐回路。
5: superconducting line, 6: superconducting line, 8: power supply branch line, 1
0: power supply, 11: superconducting line, 12: resistor, 13: superconducting junction, 14: signal source, 15: resistor, 16: inductor, 17: superconducting junction, 21: set signal, 22: reset signal, 23: magnetic flux quantum -Level signal converter output signal, 24: clock signal, 25: input data signal string,
26: output signal, 31: set, reset signal generation circuit, 32: Josephson transmission line, 33: magnetic flux quantum signal to level signal conversion circuit, 34: clock signal line, 3
5: branch, 36: data signal line, 40: superconducting line, 4
1: inductor, 42: superconducting junction, 43: resistance, 4
4: Power supply branch line, 46: Superconducting connection, 48: Power supply line, 5
1: substrate, 52: ground plane, 53: high dielectric constant interlayer insulating film,
54: low dielectric constant interlayer insulating film, 55: superconducting electrode film, 5
6: Interlayer insulating film, 57: Superconducting junction, 58: Superconducting electrode film, 59: Resistor, 60: Operable power supply current region of the flip-flop circuit using the power supply branch line according to the present invention, 6
1: Power supply current region in which a flip-flop circuit using a power supply branch line having only a resistor is operable, 62: Reflected signal strength in the power supply branch line according to the present invention, 63: Propagation signal strength in the power supply branch line according to the present invention, 64: Propagation delay time of Josephson transmission line using power supply branch line according to the present invention, 6
5: Propagation delay time of Josephson transmission line using power supply branch line with only resistance, 100: Flip-flop circuit, 10
1: Set terminal of flip-flop circuit, 102: Reset terminal of flip-flop circuit, JTL, 121, 1
23, 125, 127: superconducting junction line, rs-FF,
126 and 128: set / reset flip-flops, SP and 122: branch circuits.

フロントページの続き (72)発明者 田辺 圭一 東京都江東区東雲一丁目14番3 財団法人 国際超電導産業技術研究センター内 Fターム(参考) 4M113 AA06 AA16 AA25 AC33 AD23 AD36 AD42 AD67 AD68 BB07 BC08 CA34 5J042 AA01 5J056 AA00 BB17 BB57 DD53 KK02Continued front page    (72) Inventor Keiichi Tanabe             1-14-3 Shinonome, Koto-ku, Tokyo Foundation               International Superconductivity Industrial Technology Research Center F term (reference) 4M113 AA06 AA16 AA25 AC33 AD23                       AD36 AD42 AD67 AD68 BB07                       BC08 CA34                 5J042 AA01                 5J056 AA00 BB17 BB57 DD53 KK02

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】演算回路、記憶回路等、デジタル信号を処
理する論理回路部分と、論理回路に直流のバイアス電
流、あるいは直流のバイアス電圧を供給する電源線回路
からなるデジタル回路に適用され、各論理回路の要素素
子に至る該電源線回路の分岐線が抵抗と超電導線路によ
って構成され、かつ分岐線がインピーダンスの不連続性
を有することを特徴とする電源線回路。
1. A digital circuit including a logic circuit portion for processing a digital signal, such as an arithmetic circuit and a memory circuit, and a power supply line circuit for supplying a DC bias current or a DC bias voltage to the logic circuit. A power line circuit, wherein a branch line of the power line circuit reaching an element element of a logic circuit is composed of a resistance and a superconducting line, and the branch line has impedance discontinuity.
【請求項2】前記電源線回路の各分岐線の長さが、要素
素子の発生する信号の波長に対応する長さの4分の1以
上である請求項1に記載の電源線回路。
2. The power supply line circuit according to claim 1, wherein the length of each branch line of the power supply line circuit is not less than ¼ of the length corresponding to the wavelength of a signal generated by an element element.
【請求項3】前記電源線回路の各分岐線を構成する配線
の主要部分が超電導線路と抵抗の直列接続によって得ら
れ、かつ抵抗膜の抵抗値が論理回路の要素素子の固有抵
抗と同等であるか、あるいは固有抵抗より小さい値であ
る請求項1に記載の電源線回路。
3. A main portion of wiring constituting each branch line of the power supply line circuit is obtained by connecting a superconducting line and a resistor in series, and a resistance value of a resistance film is equal to a specific resistance of an element element of a logic circuit. The power supply line circuit according to claim 1, wherein the power supply line circuit has a value which is smaller than or equal to the specific resistance.
【請求項4】前記電源線回路の各分岐線を構成する配線
内部、あるいは各分岐線を構成する配線とこれらの分岐
線を束ねる配線間の接続部、あるいは各分岐線を構成す
る配線と要素素子を構成する配線間の接続部でインピー
ダンスを違える請求項1に記載の電源線回路。
4. The inside of the wiring forming each branch line of the power supply line circuit, or the connection portion between the wiring forming each branch line and the wiring that bundles these branch lines, or the wiring and the elements forming each branch line. The power supply line circuit according to claim 1, wherein impedances are different at a connection portion between wirings forming the element.
【請求項5】前記電源線回路および要素素子ともに絶縁
膜を介して超電導性の接地膜を配し、分岐線の全体ある
いは分岐線の一部と接地膜との間で構成される単位面積
当りの容量値が、要素素子の配線と接地膜との間で構成
される単位面積当りの容量値より大きい請求項1または
請求項4に記載の電源線回路。
5. A unit area formed by arranging a superconducting ground film through an insulating film in both the power line circuit and the element element, and forming the entire branch line or a part of the branch line and the ground film. The power supply line circuit according to claim 1 or 4, wherein the capacitance value of is larger than the capacitance value per unit area formed between the wiring of the element element and the ground film.
【請求項6】前記電源線回路の各分岐線に重なる絶縁膜
が配線の端部あるいは途中で比誘電率の異なる絶縁膜に
置き換えられて成る請求項1、請求項4および請求項5
のいずれかに記載の電源線回路。
6. The insulating film which overlaps with each branch line of the power supply line circuit is replaced with an insulating film having a different relative dielectric constant at an end or in the middle of the wiring.
The power line circuit according to any one of 1.
【請求項7】前記比誘電率の異なる2種類の絶縁膜を用
い、該電源線回路の各分岐線に重なる絶縁膜の全部ある
いは一部には比誘電率の高い絶縁物を用い、要素素子の
配線に重なる絶縁膜、あるいは要素素子の配線と電源線
回路の分岐線の一部に重なる絶縁膜には比誘電率の高い
絶縁膜と比誘電率の低い絶縁膜の層状構造とする請求項
1、請求項4および請求項5のいずれかに記載の電源線
回路。
7. An element element, wherein two types of insulating films having different relative dielectric constants are used, and an insulating film having a high relative dielectric constant is used for all or part of an insulating film overlapping with each branch line of the power line circuit. The insulating film that overlaps with the wiring, or the insulating film that overlaps with the wiring of the element element and a part of the branch line of the power supply line circuit has a layered structure of an insulating film having a high relative dielectric constant and an insulating film having a low relative dielectric constant. The power supply line circuit according to claim 1, claim 4, or claim 5.
【請求項8】チタン酸ストロンチウムをはじめとする高
誘電率の絶縁材料を容量を構成する絶縁膜の一部として
用いる請求項1、請求項5、請求項6、および請求項7
のいずれかに記載の電源線回路。
8. An insulating material having a high dielectric constant, such as strontium titanate, is used as a part of an insulating film constituting a capacitor, claim 5, claim 6, and claim 7.
The power line circuit according to any one of 1.
【請求項9】電源線回路の給電するべき論理回路が超電
導配線と超電導素子によって構成される超電導回路であ
り、さらには超電導回路を伝搬する論理信号の担体が磁
束量子である請求項1に記載の電源線回路。
9. The logic circuit to be fed by the power line circuit is a superconducting circuit composed of superconducting wiring and a superconducting element, and a carrier of a logic signal propagating through the superconducting circuit is a flux quantum. Power line circuit.
【請求項10】演算回路、記憶回路等、デジタル信号を
処理する論理回路部分と、該論理回路の要素素子に直流
のバイアス電流、あるいは直流のバイアス電圧を供給す
る電源線回路からなるデジタル回路であって、各論理回
路の要素素子に至る該電源線回路の分岐線が抵抗と超電
導線路によって構成され、かつ分岐線がインピーダンス
の不連続性を有することを特徴とするデジタル回路。
10. A digital circuit comprising a logic circuit portion for processing a digital signal, such as an arithmetic circuit and a memory circuit, and a power supply line circuit for supplying a DC bias current or a DC bias voltage to the element elements of the logic circuit. A digital circuit characterized in that a branch line of the power supply line circuit reaching the element element of each logic circuit is constituted by a resistance and a superconducting line, and the branch line has impedance discontinuity.
JP2001214709A 2001-07-16 2001-07-16 Power supply line circuit Pending JP2003031861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001214709A JP2003031861A (en) 2001-07-16 2001-07-16 Power supply line circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001214709A JP2003031861A (en) 2001-07-16 2001-07-16 Power supply line circuit

Publications (1)

Publication Number Publication Date
JP2003031861A true JP2003031861A (en) 2003-01-31

Family

ID=19049478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001214709A Pending JP2003031861A (en) 2001-07-16 2001-07-16 Power supply line circuit

Country Status (1)

Country Link
JP (1) JP2003031861A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7429196B2 (en) 2004-11-05 2008-09-30 Ddk Ltd. Card connector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7429196B2 (en) 2004-11-05 2008-09-30 Ddk Ltd. Card connector

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