JP2003030992A - Memory cell and semiconductor integrated circuit device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, in which increment of layout area can be suppressed for a CAM cell, in which data is written in a plurality of memory cells, at the same time. SOLUTION: A memory cell CAMC1 is provided with a first transistor TA1 which is controlled by a first word line TWL, and which couples a first bit line ASL1 and a first internal node n1, a second transistor ZWTr controlled by a second word line WLa and coupling the first internal node n1 and a second internal node n2, an inverter INV2 for coupling the first node n1 and an input node, an inverter INV1 for coupling an output of the inverter INV2 and the input node, third and fourth transistors T11, T12 and fifth and sixth transistors T13, T14 which are connected in series respectively between a coincidence detection line MHL and a ground potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to the structure of a semiconductor integrated circuit device including a circuit portion capable of storing data.

[0002]

2. Description of the Related Art Conventionally, a so-called associative memory has been used as a structure of a semiconductor memory device for detecting a match or a mismatch between prestored data and comparison data to be input later to search and collate the data. Cell (Content Addressabl
e Memory cell: Hereinafter, a semiconductor memory device having a "CAM cell" is known.

In a memory device having such a CAM cell, a match detection line is provided corresponding to each memory cell row in a CAM cell array sharing a bit line and a word line.

The coincidence detection line is precharged to the internal power supply potential in advance, for example, prior to the comparison operation. Then, when a potential level corresponding to the comparison data is applied to the bit line pair, if the data stored in the CAM cell and the data applied to the bit line pair match, a match detection is performed. The line level is maintained at the internal power supply potential. On the other hand, when the two do not match, the match detection line is discharged and the potential level thereof is lowered. In such a configuration, by simply monitoring the level of the match detection line, the data stored in the associative memory cell array,
The result of comparison with the data applied to the bit line can be read from the outside.

Japanese Patent Laid-Open No. 2001-6387 discloses a configuration in which such a CAM cell array is used to store a row address or a column address of a defective memory cell in a redundancy analysis of a semiconductor memory device, for example. There is.

The CAM cell array in such a redundancy analysis will be described below. FIG. 11 is a schematic block diagram showing an example of the configuration of a redundant circuit provided for the memory array unit 8010 of the semiconductor memory device.

One memory cell in the memory array section 8010 has a row address signal RA0- inputted from the outside.
13, selected by the column address signal CA0-8. The data applied to the data input / output terminal DQ (not shown) is written to the selected one memory cell in the write operation, and the data input / output is performed in the read operation. Read data from memory array section 8010 is output to terminal DQ.

Row decoder 8020 selects one row (row) of memory cells to be read or written according to the input row address. Further, the column decoder 8030 selects one column (column) by the input column address, and further selects one memory cell from the memory cells for one row selected by the row address.

In the structure shown in FIG. 11, two spare rows SR1 and SR2 are used as spare memory cells.
And two spare columns SC1 and SC2, respectively. Spare row SR1 includes memory cells SRM1 for one row and spare row decoder SRD1.
The spare row SR2 is a memory cell SRM2 for one row.
And a spare row decoder SRD2.

The spare column SC1 is composed of one column of memory cells SCM1 and a spare column decoder SCD1. The spare column SC2 is a memory cell SC for one column.
It consists of M2 and a spare column decoder SCD2.

Spare row decoders SRD1 and SRD
2 has a row address with a defective memory cell previously recorded therein, compares the input row address with the row address with the defective memory cell, and if they match, responds to each other. The spare memory cell SRM1 or SRM2 is selected. When spare row memory cell SRM1 or SRM2 is selected, spare row decoders SRD1 and SRD2 control row decoder 8020 to prevent the memory cells of the regular memory array from being selected. The same applies to spare column decoders SCD1 and SCD2.

Here, for example, as shown in FIG.
Defective memory cells DBM1 to DBM8 in the memory array
Consider the case.

At this time, the defective memory cells DBM2 to DBM
It is assumed that M4 corresponds to the same row address RF2, and defective memory cells DBM3 and DBM5 to DBM7 correspond to the same column address CF3.

In the test for finding defective memory cells, the defective memory cells DBM1 are sequentially changed while changing the row address and the column address.
~ When detecting the DBM8, the defective memory cell DBM
The existence of defective memory cells will be detected in the order of 1 to DBM8.

At this time, in the case where the replacement processing of the defective address corresponding to these defective memory cells is performed in the two spare rows SR1 and SR2 and the two spare columns SC1 and SC2, the spare rows and the spare columns are arranged in any order. Depending on whether the normal memory cell row or the normal memory cell column corresponding to the defective memory cell is replaced, there are cases where all the defective memory cells are relieved and cases where they are not.

For example, defective memory cell DBM1 (row address RF1, column address CF1) is replaced with spare row memory cell SRM1, and defective memory cells DBM2 to DBM2.
BM4 (row address is common to RF2, column addresses are CF2, CF3, and CF4, respectively) is replaced with a second spare row memory cell SRM2, and a defective memory cell DBM5.
~ DBM7 (column address is common to CF5, row addresses are RF3, RF4, and RF5, respectively) is replaced by the first spare column memory cell SCM1, and defective memory cell DBM8 (row address RF8, column address CF8) is replaced by
When replaced with the second spare column memory cell SCM2, all the defective memory cells DBM1 to DBM8 are replaced by
It is possible to replace with two spare rows SR1 and SR2 and two spare columns SC1 and SC2. However, if the replacement is performed in a different order, there may be a case where the repair cannot be performed.

Here, when there are two spare rows and two spare columns, each replacement is performed according to the order in which the defective memory cells that are sequentially detected are replaced with the spare row and the spare column. There are the following six combinations depending on which step in one step the spare row or spare column is replaced with.

In the following, the case of replacement with a spare row is represented by R, and the case of replacement with a spare column is represented by C.

Case 1: R → R → C → C Case 2: R → C → R → C Case 3: R → C → C → R Case 4: C → R → R → C Case 5: C → R → C → R Case 6: C → C → R → R FIG. 12 is a schematic block diagram for explaining the configuration of a conventional address replacement determination unit 8000 for determining such a repairable replacement order. Such a replacement determiner 8000 is provided, for example, in a built-in self-test circuit for performing a self-test on a defective memory cell in a semiconductor memory device including a memory array section 8010.

The address replacement decision unit 80 shown in FIG.
In 00, parallel processing is performed on six systems so that the six cases of replacement by two spare rows and two spare columns as described above can be determined in parallel. ing.

Referring to FIG. 12, address replacement determining unit 8
000 corresponds to each of Cases 1 to 6 described above, and when the defective address replacement processing is performed, the first to sixth determinations are made to determine whether the defective addresses can be relieved by replacement. Replacement determination unit 8100.1
With 8100.6.

The address replacement decision unit 8000 further includes
First replacement determining unit 8100.1 to sixth replacement determining unit 8
Corresponding to 100.6, a row address storage unit R for storing row addresses each of which is to be replaced with two spare rows
A column address storage unit C for storing M1 to RM6 and a column address to be replaced with two column addresses
Equipped with M1 to CM6.

For example, in the case 1 described above, that is, the first replacement determination unit 8100 provided corresponding to the processing in which the replacement processing by the spare row is performed twice in succession and the replacement processing by the spare column is performed twice in succession. .. 1 is provided with a row address storage unit RM1 and a column address storage unit CM1.

The row address storage unit RM1 stores a memory cell column MCR11 for storing a row address to be replaced by the first spare row SR1 and a row address to be replaced by the second spare row SR2. The memory cell column MCR12 is included.

On the other hand, the column address storage unit CM1 stores a memory cell column MCC11 for storing a column address to be replaced by the first spare column SC1 and a column address to be replaced by the second spare column SC2. A memory cell column MCC12 for storing is included.

Since the first replacement determination unit 8100.1 corresponds to the case 1 as described above, the corresponding storage cell column in the row address storage unit RM1 and column address storage unit CM1 is A memory cell column MCR11, a memory cell column MCR12, a memory cell column MCC11, and a memory cell column MCC12 are sequentially passed, and a pass / fail signal P / F indicating the pass / fail of the test result of the memory cells is sequentially tested.
Each time is activated, it is determined whether or not the internal address signal at that time is written in the memory cell column.

Memory cell columns MCR11, MCR12, M
Precharge circuit C corresponding to CC11 and MCC12
PR11, CPR12, CPC11, and CPC12 are provided, respectively. Precharge circuits CPR11 to C
Each of the PCs 12 has a corresponding memory cell column MCR11.
~ Matching judgment line MHL provided for MCC12
Is precharged to the "H" level according to the signal φ.

Memory cell columns MCR11 and MCR12
Are provided corresponding to 14 groups of internal row address signals RA0, / RA0 to signals RA13, / RA13, respectively, and include associative memory cells for storing the levels of these signals. .

Similarly, the memory cell columns MCC11 and MCC12 have internal column address signals CA0 and CA0, respectively.
A pair of / CA0 to a pair of signals CA8 and / CA8 are provided respectively, and an associative memory type cell for storing these signal levels is included.

In the associative memory type cells in the row address storage unit RM1 and the column address storage unit CM1, the level of the write activation line TWL is activated in response to an instruction from the corresponding first replacement determination unit 8100.1. Level (“H” level)
Accordingly, the level of the corresponding internal row address signal or internal column address signal is stored.

On the other hand, the level of the match determination line MHL which is precharged to the "H" level in advance is given to the address signal level already stored in the memory cell column and the address replacement determination unit 8000 at that time. Internal address signals RA0, / RA0 to RA13, / RA13 or internal column address signals CA0, / CA0 to CA8, / CA.
If the level of 8 matches, the "H" level is maintained. On the other hand, if they do not match, the matching determination line M
The HL level becomes the “L” level.

Further, memory cell columns MCR11, MCR1
2, corresponding to MCC11 and MCC12, flip-flop circuits SFR11, SFR12, SFC11, S
Each FC 12 is provided. The levels of the flip-flop circuits SFR11 to SFC12 are reset by the reset signal RST before the test operation is started, and the write select line TWL of the corresponding memory cell column is activated (“H”). Is set according to.

The second replacement determining unit 8100.2 corresponds to case 2, and the third to sixth replacement determining units 8100.3-
Regarding 8100.6 as well, each differs only in the corresponding memory cell column and the order in which writing to the memory cell column is performed, depending on cases 3 to 6, and other configurations are the same as those of the replacement determination unit 8100.1. The configuration is the same.

In the configuration as described above, the replacement judging section 8
The outline of the operation of 100.1 is as follows.

That is, for example, when the pass / fail signal P / F becomes active, the first replacement determination unit 8
100.1 is a write select line TW of the memory cell column MCR11.
L is activated. In response to this, the memory cell column MCR
The level of the flip-flop circuit SFR11 corresponding to 11 is set, and the fact that the address signal has already been written to this memory cell column MCR11 is held as data.

Then, when the pass / fail signal P / F is activated again, the internal row address signal held in the memory cell column MCR11 and the level of the internal row address signal at this time are shown. Of the memory cell column MCR1 according to the comparison result.
The level of the match detection line MHL of 1 is driven. In response to this, the first replacement determination unit 8100.1 determines that the internal row address already held in the memory cell column MCR11 matches the internal row address corresponding to the newly detected defective memory cell. If so, the memory cell column MCR12 is not activated.

On the other hand, if the internal row address already stored in memory cell column MCR11 and the internal row address corresponding to the newly found defective memory cell do not match, the first The replacement determination unit 8100.1 is 2
The write select line TWL of the memory cell column MCR12 to be activated next is activated.

Then, the second memory cell column MCR12
The internal row address corresponding to the newly found defective memory cell is written into the memory cell column MCR12.
The level of the flip-flop circuit SFR12 corresponding to is set.

In the same manner, each time a defective memory cell is sequentially detected, the internal row address or internal column address already held in the memory cell column and the internal corresponding to the newly detected defective memory cell are detected. If the row address or the internal column address do not match, the memory cell column is activated according to the corresponding order of case 1 of the first replacement determination unit 8100.1.

On the other hand, when the internal row address or internal column address already stored in the memory cell column matches the internal row address or internal column address corresponding to the newly detected defective memory cell, The first replacement determining unit 8100.1 does not activate the memory cell column corresponding to the next order.

Finally, when the normal memory cells are inspected during the built-in self-test, the internal row addresses and internal column addresses of all the defective memory cells which are sequentially detected are the row address storage unit MR1 and the column address. If the internal row address or the internal column address already stored in the address storage unit CM1 matches, the defective memory cell is replaced with the spare row or the spare column in the order corresponding to the first replacement determination unit 8100.1. By doing so, it is determined that all defective memory cells can be replaced and repaired. The result of the determination is output from the address replacement determiner 8000 to the outside as a repair fail signal RF.

As described above, the first replacement judging section 810.
0.1 and row address storage unit RM1 corresponding thereto
Also, a configuration similar to that corresponding to the column address storage unit CM1 is provided corresponding to the second replacement determination unit 8100.2 to the sixth replacement determination unit 8100.6. Moreover, each of the second replacement determination unit 8100.2 to the sixth replacement determination unit 8100.6 is
In accordance with the corresponding order, each replacement determining unit activates the storage cell column of the row address storage unit and the storage cell column of the column address storage unit in the corresponding order.

Therefore, as shown in FIG. 11, if the defective memory cells in the normal memory cell array 100R can be relieved by the two spare rows and the two spare columns, the first replacement determination unit 8100. The repair fail signal RF from at least one of the first to sixth replacement determining units 8100.6 is in the inactive state (“L” level) even when the last defective memory cell is detected.
Will be maintained.

A plurality of memory cell columns for storing such internal row addresses constitute one CAM cell array as a whole. Similarly, a plurality of storage cell columns for storing internal column addresses are also combined into one CAM as a whole.
Configure a cell array.

[0045]

FIG. 13 is a circuit diagram showing an extracted configuration of CAM cells CAMC1 and CAMC2 corresponding to one bit line pair in such a CAM cell array. Here, this bit line pair has internal column address signals CAn and / CAn (n: natural number,
n = 0 to 8) shall be transmitted.

Referring to FIG. 13, CAM cell CAMC1
Is an inverter INV whose input is coupled to the storage node n2
1 and the storage node n1 and an input I coupled to the inverter I
With NV2. The output node of the inverter INV1 is
The output node of the inverter INV2 is coupled to the input node of the inverter INV2, and the output node of the inverter INV1 is coupled to the bistable storage element.

Inverter INV1 includes P-channel MOS transistor TP1 and N-channel MOS transistor T connected in series between the power supply potential Vcc and the ground potential.
Including N1. The inverter INV2 includes a P-channel MOS transistor TP2 and an N-channel MOS transistor T connected in series between the power supply potential Vcc and the ground potential.
Including N2.

The CAM cell CAMC1 further includes a bit line (hereinafter, referred to as a bit line) for transmitting the internal column address signal CAn.
An address signal line ASL1 and a storage node n1 are connected to each other according to the level of the word line TWL, and an N-channel access transistor TA1 and an address signal CAn.
And a storage node n2 for transmitting an internal address signal / CAn complementary to the N-channel access transistor TA2 for connecting the bit line ASL2 and the storage node n2 according to the level of the word line TWL, and a match detection line. It includes N-channel transistors T11 and T12 connected in series between MHL and the ground potential, and transistors T13 and T14 connected in series between match detection line MHL and the ground potential.

The gate of the transistor T11 is connected to the address signal line ASL1 and the gate of the transistor T12 is connected to the storage node n2. Transistor T1
The gate of the transistor T14 is connected to the storage node n1, and the gate of the transistor T14 is connected to the address signal line ASL2.

That is, the bistable storage element is connected to address signal lines ASL1 and ASL2 in response to activation of word line TWL. On the other hand, the data held in the bistable storage element and the address signal lines ASL1 and AS
When the internal address signal on L2 does not match, the match detection line MHL is connected to the ground potential and discharged via either the path of the transistors T11 and T12 or the path of the transistors T13 and T14. Become.

The configuration of the CAM cell CAMC2 is also C
The configuration is similar to that of the AM cell CAMC1.

Next, the data writing to the CAM cell array having such a configuration will be described. In writing data, bit line driver circuit BLDRV drives the levels of address signal lines ASL1 and ASL2.

When the CAM cell array having the structure as shown in FIG. 13 is used for the address replacement judging unit 8000 shown in FIG. 12, a plurality of CAM cell arrays sharing an address signal line (bit line) and a word line are simultaneously operated. It is necessary to activate the word line and simultaneously write the data of the bit line into a plurality of memory cells.

Therefore, the bit line driver circuit BLDR
V is a plurality of CAMs in which data opposite to the write data is stored
Occasionally, data is written to a cell.

For example, in FIG. 13, it is assumed that both CAM cells CAMC1 and CAMC2 are held at "L" level in storage node n1 before the write operation. Further, in the write operation, the level of the address signal line ASL1 changes to the bit line driver circuit BLDRV.
Is driven to "H" level. When the word line TWL is activated, the CAM cells CAMC1 and CAMC
Transistor TN1 in both inverters INV1
Current flows from the bit line driver circuit BLDRV to the ground potential via the address signal line ASL1.

Therefore, in order to cope with the case where data is simultaneously written in such a plurality of memory cells, the bit line driver needs to flow a current against the current of the CAM cell. Therefore, it is necessary to increase the size of the bit line driver, which increases the layout area and
Moreover, there is a problem that the current consumption is large.

The present invention has been made in order to solve such a problem, and its object is to enable a plurality of word lines in a CAM array sharing a bit line and a word line to enable bit lines. It is an object of the present invention to provide a semiconductor integrated circuit device capable of suppressing current consumption while suppressing an increase in layout area for a CAM cell which simultaneously writes line data in a plurality of memory cells.

[0058]

A memory cell according to claim 1, which is controlled by a first word line, has a first bit line for transmitting read data and write data, and a first internal node. A first transistor that couples
A second transistor controlled by the second word line to couple the first internal node to the second internal node; a first inverter coupling the first node to the input node; and a first inverter A second inverter having an output node coupled to an input node and an output node coupled to a second internal node.

In addition to the structure of the memory cell according to claim 1, the memory cell according to claim 2 is matched with the third and fourth transistors connected in series between the match detection line and a predetermined potential. The third transistor further includes fifth and sixth transistors connected in series between the detection line and the predetermined potential, and the third transistor is turned on according to the output level of the second inverter, and the fourth transistor is turned on. Is conductive according to the level of the first bit line, the fifth transistor is conductive according to the level of the first internal node, and the sixth transistor is connected to the level of the second bit line. Accordingly, it becomes conductive.

A semiconductor integrated circuit device according to a third aspect of the present invention includes a memory cell array in which a plurality of memory cells are arranged in rows and columns, and each memory cell is controlled by a first word line to provide read data and write data. For coupling a first bit line for transmitting a first internal node and a first internal node
The second transistor, the second transistor controlled by the second word line to couple the first internal node and the second internal node, and the first inverter having the first node coupled to the input node. A second inverter having an output node of the first inverter coupled to the input node and an output node coupled to the second internal node; and
A row selection circuit that selectively drives the first and second word line levels, and an address signal and write data
And a column selection circuit for selectively driving the first bit line level.

According to a fourth aspect of the semiconductor integrated circuit device of the present invention, in addition to the configuration of the third aspect of the semiconductor integrated circuit device of the third aspect, in the write operation, the row selection circuit sets the second transistor after turning off the second transistor. The first transistor is selectively turned on.

A semiconductor integrated circuit device according to a fifth aspect of the present invention includes a memory cell array in which a plurality of memory cells each for holding stored data are arranged in a matrix, and the memory cell array includes a plurality of normal memory cells. At least a memory cell row and a memory cell column that include a normal memory cell array and a spare memory cell array including a plurality of spare memory cells and are common to the normal memory cell arrays of the first and second sub memory cell arrays in accordance with an address signal. A normal memory cell selection circuit for selecting one of the memory cells, and a common memory cell row or memory cell column to be selected by the normal memory cell selection circuit when there is a defective memory cell in the normal memory cell array. Select either memory cell row or memory cell column in the spare memory cell array And a self-test circuit for performing a test for detecting a defective memory cell in a normal memory cell and determining which spare memory cell is to be replaced. The test circuit includes an associative memory cell array having a plurality of associative memory cells arranged in a matrix for obtaining a comparison result between a defective address already detected and a newly detected defective address. Each of the cells is controlled by a first word line to couple a first bit line for transmitting the detected defective address to a first internal node, and a second word. A second transistor controlled by a line to couple the first internal node and the second internal node, and a first inverter having the first node coupled to the input node , A second inverter in which the output of the first inverter is coupled to the input node and the output node is coupled to the second internal node, and in series between the coincidence detection line for transmitting the comparison result and the predetermined potential. It further comprises third and fourth transistors connected to each other, and fifth and sixth transistors connected in series between the coincidence detection line and the predetermined potential, wherein the third transistor is connected to the second inverter. The fourth transistor is turned on according to the output level, the fourth transistor is turned on according to the level of the first bit line, and the fifth transistor is turned on according to the first bit line.
Becomes conductive according to the level of the internal node, and the sixth transistor becomes conductive according to the level of the second bit line.

According to a sixth aspect of the semiconductor integrated circuit device, in addition to the configuration of the semiconductor integrated circuit device according to the fifth aspect, in the associative memory cell, the second transistor is turned off in a write operation, The first transistor is selectively turned on.

[0064]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a schematic block diagram showing an overall structure of a dynamic semiconductor memory device (hereinafter referred to as DRAM) 1000 according to a first embodiment of the present invention.

As will be apparent from the following description,
The CAM cell array according to the present invention is not limited to being used in the built-in self-test circuit mounted in the DRAM 1000 shown in FIG. 1, but is more generally mounted in a semiconductor integrated circuit device. It can be applied to a circuit for data storage.

Particularly, the memory cell according to the present invention is effective when it is necessary to simultaneously enable a plurality of word lines and simultaneously write data to a plurality of memory cells corresponding to the plurality of word lines. It is something.

Referring to FIG. 1, DRAM 1000 includes row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE, chip enable signal / CE, clock enable signal CKE.
, A control signal input terminal group 11 for receiving control signals, an address input terminal group 13 for receiving address signals A0 to Ai (i: natural number), a data input / output terminal group 15 for inputting / outputting data, and an external unit. Vc receiving power supply potential Vcc
c terminal 18 and Vss terminal 19 for receiving ground potential Vss
With.

Here, the signal CKE applied to the control signal input terminal group 11 is a signal for instructing that the control signal can be input to the chip.

DRAM 1000 further includes a control circuit 26 for generating an internal control signal for controlling the operation of DRAM 1000 as a whole according to a control signal, an internal control signal bus 72 for transmitting the internal control signal, and an address input terminal group 13. An address buffer 30 for receiving an external address signal from an external address signal is generated, and a memory cell array 100 having a plurality of memory cells MC arranged in a matrix.

The internal address signals are complementary internal row address signals RA0-RAi and / RA0-R generated from external row address signals RA0-RAi, for example.
Internal column address signals CA0 to CAj and / C which are generated from Ai and the external column address signal CAj and which are complementary to each other.
It means A0 to CAj.

Memory cell MC is composed of a capacitor for holding data and an access transistor GM having a gate connected to word line WL corresponding to each row.

In memory cell array 100, word line WL is provided for each row of memory cells, and bit lines BL, / BL are provided for each column of memory cells.

Further, the memory cell array 10 shown in FIG.
0 includes a regular memory cell array 100R, a spare row SR and a spare column SC.

Also in memory cell array 100, two spare rows SR1 and S are used as spare rows SR.
R2 is provided, and one spare column SC1 is provided as the spare column SC.

The DRAM 1000 further includes the DRAM 1
A built-in self-test circuit (hereinafter referred to as a BIST circuit) 2000 for detecting a defective memory cell of 000 and replacing it with a spare row SR or a spare column SC.

BIST circuit 200 is controlled by control circuit 26, and in normal operation, internal row address signal and internal column address signal from address buffer 30 are directly applied to row decoder 40, spare row decoder 42, and column decoder. 50 and spare column decoder 52, respectively. Furthermore, the BIST circuit 2
000 is a data input / output terminal group 1 in normal operation.
5, the buffer data is buffered by the input / output buffer 85, and the write data output from the write driver circuit 80 is received and directly output to the column selection gate 200.

On the other hand, the BIST circuit 2000 is
In the test operation, not the internal address signal from address buffer 30 but the internal address signal generated inside BIST circuit 2000 is applied to row decoder 40, spare row decoder 42, column decoder 50 and spare column decoder 52, respectively. Further, not the data given from the write driver 80 but the BIST circuit 20
The test write data TD generated in 00 is applied to the column selection gate 200 to write the test data in the memory cell array 100. The test write data T
D may be configured to be provided from outside the DRAM 1000.

After the write operation in the test operation is completed, BIST circuit 2000 again generates an internal address signal to sequentially read the written data. The BIST circuit 2000 sequentially detects defective memory cell positions in the normal memory cell array 100R according to the result of comparison between the read data and the expected value data ED, and responds to such a plurality of defective memory cells. The combination of the spare row SR and the spare column SC for the plurality of defective row addresses and defective column addresses to be replaced is determined. Again, the expected value data E
D may be provided from the outside of DRAM 1000.

FIG. 2 shows the BIST circuit 200 shown in FIG.
It is a schematic block diagram for demonstrating the structure of 0.

The BIST circuit 2000 is controlled by the BIST control unit 2010 for controlling the built-in test operation and the BIST control unit 2010 according to the control from the control circuit 26, and the internal row address signal is supplied during the built-in test operation. RA0-RAi, / RA0- / RAi
And internal column address signals CA0 to CAj, / CA0.
/ CAj, test write data TD and expected value data E
A test signal generator 2020 for generating D respectively, and B
The internal row address signals RA0 to RAi, / R from the address buffer 30 are controlled by the IST control unit 2010.
Receiving A0 to / RAi and the internal row address signal from the test signal generator, either row decoder 40 or spare row decoder 4 is selectively selected according to the operation mode.
2 and the internal column address signals CA0 to CAj and / CA0 to / C from the address buffer 30 under the control of the multiplexer 2030 and the BIST control unit 2010.
A multiplexer 2040 which receives Aj and the internal column address signal from the test signal generator 2020 and outputs either one to the column decoder 50 and the spare column decoder 52 in accordance with the operation mode, and the BIST control unit 201.
0 controlled to receive the write data WD from the write driver 80 and the test write data TD from the test signal generator 2020, and one of them is given to the select gate 200 depending on the operation mode.
And the read data RD from the column selection circuit 200 and the expected value data ED from the test signal generator 2020 in the read operation in the built-in test mode, and pass / fail in response to the match / mismatch of the comparison results. In response to the comparator 2060 which outputs the signal P / F and the internal row address signal and the internal column address signal which are output from the test signal generator during the built-in test mode, the pass / fail signal P / from the comparator 2060 is received. In response to activation of F (when data ED and data RD do not match), a defective address in normal memory cell array 100R is stored and a defect to be replaced by spare row SR and spare column SC. And an address replacement determining unit 3000 that determines an address.

When the spare row decoder 42 and the spare column decoder 52 have electrically rewritable non-volatile storage elements according to the determination result of the address replacement determination unit 3000, the BIST control unit 2010 stores these non-volatile storage elements. Program the bad address to be replaced in the device. Alternatively, the BIST control unit 2010 outputs the defective address to be replaced to the outside from the input / output terminal group 15 via the read amplifier 80 and the input / output buffer according to the determination result of the address replacement determination unit 3000.

FIG. 3 is a schematic block diagram for illustrating the configuration of address replacement determination unit 3000 shown in FIG.

Before describing the configuration of address replacement determination circuit 3000, the processing procedure for replacing a defective address in memory cell array 100 in FIG. 1 with spare rows SR1 and SR2 and spare column SCI will be briefly summarized.

Here, as described above, since the memory cell array 100 has two spare rows and one spare column, defective memory cells to be sequentially detected are treated as a spare row and a spare column in any order. There are the following three combinations for replacement, depending on which step in the three steps of each replacement is to replace with the spare row or the spare column.

In the following, the replacement with the spare row is represented by R, and the replacement with the spare column is represented by C.

Case 1: R➝R➝C Case 2: R➝C➝R Case 3: C➝R➝R In other words, which step among the three steps is the replacement with the spare column? Once decided
Such combinations are determined, and the total number of such combinations is 3 (total of 2 spare rows + 1 spare column).
_{(2 + 1)} C ₁ = (2 + 1)! / {2!・ 1! } = There are only 3 ways. Here, for a natural number k, k! Represents the factorial of a natural number k.

More generally, when there are m spare rows and n spare columns, the number of such combinations is
_{(m + n)} C _n = _{(m + n)} C _m = (m + n)! There are only / (m! × n!) Streets.

When all the defective memory cells can be finally replaced and repaired by the two spare rows and one spare column, the spare row can always be repaired in the above-described three ways. There will be an order of replacement processing with the spare column.

Address replacement determination circuit 30 shown in FIG.
In 00, parallel processing is performed for three systems so that the above three cases can be determined in parallel.

Referring to FIG. 3, address replacement determination circuit 3
000 indicates that when defective address replacement processing is performed in each of Cases 1 to 3 described above,
First to third replacement determination units 3100.1 for respectively determining whether or not the defective addresses can be relieved.
˜3100.3.

Address replacement determining circuit 3000 further stores row addresses to be replaced with two spare rows, corresponding to first replacement determining section 3100.1 to third replacement determining section 3100.3. Row address storage units RM1 to RM3 and column address storage units CM1 to CM3 for storing a column address to be replaced with one column address.

For example, in case 1 described above, that is, the first replacement determination unit 3100.1 provided corresponding to the process of performing replacement by the spare column once after performing the replacement process by the spare row twice in succession. A row address storage unit RM1 and a column address storage unit CM1 are provided corresponding to the above.

The row address storage unit RM1 stores a memory cell column MCR11 for storing a row address to be replaced by the first spare row SR1 and a row address to be replaced by the second spare row SR2. The memory cell column MCR12 is included.

On the other hand, the column address storage unit CM1 includes a storage cell column MCC11 for storing the column address to be replaced by the first spare column SC1.

Transmission of the address signal to the memory cell column is carried out by driving the level of the address signal line (CAM cell bit line) by driver circuit 3002.1 or 3002.2.

Since the first replacement determination section 3100.1 corresponds to the case 1 as described above, it stores the corresponding storage cell row of the row address storage section RM1 and the column address storage section CM1. Every time the pass / fail signal P / F is activated in the order of the cell column MCR11, the memory cell column MCR12, and the memory cell column MCC11, it is determined whether or not the internal address signal at that time point is taken into the memory cell column. To do.

Precharge circuit CPR1 corresponding to memory cell columns MCR11, MCR12 and MCC11.
1, CPR12 and CPC11 are provided respectively. The precharge circuits CPR11 to CPC11 precharge the match determination lines MHL provided corresponding to the corresponding memory cell columns MCR11 to MCC11 to “H” level according to the signal φ from the BIST control unit 2010. To do.

Memory cell columns MCR11 and MCR12
Are provided corresponding to the groups of internal row address signals RA0, / RA0 to the groups of signals RAi, / RAi, respectively, and include associative memory cells for storing the levels of these signals. A word line TWL and a write word line WLa are provided for this associative memory cell, as will be described later.

Similarly, memory cell column MCC11 has a set of internal column address signals CA0 and / CA0 to signal CAj ,.
/ CAj is provided corresponding to and includes an associative memory cell for storing these signal levels.

The associative memory cells in the row address storage unit RM1 and the column address storage unit CM1 are first written by the write / read drive circuit 3200 in response to an instruction from the corresponding first replacement determination unit 3100.1. Word line W
The level of La is set to "L", and after a predetermined time has elapsed, CAM
In response to the activation of the level of cell word line TWL (“H” level), the level of the corresponding internal row address signal or internal address signal is stored.

On the other hand, the level of the match determination line MHL precharged to the "H" level is the level of the address signal already stored in the memory cell column and the address replacement determination circuit 3000.1 at that time. The applied internal address signals RA0, / RA0-RA0i, / RAi or internal column address signals CA0, / CA0-CAj, /
When the level of CAj matches, the "H" level is maintained. On the other hand, when they do not match, the level of the match determination line MHL becomes the “L” level.

Further, memory cell columns MCR11, MCR1
Flip-flop circuits SFR11, SFR12 and SFC11 are provided corresponding to 2 and MCC11, respectively. Flip-flop circuits SFR11 to SF
The level of C11 is reset by the reset signal RST before the test operation is started. The levels of the flip-flop circuits SFR11 to SFC11 are set in response to the activation (“H” level) of the CAM word line TWL of the corresponding memory cell column.

Second replacement determining unit 3100.2 corresponds to case 2, and corresponds to the row address storing unit RM2 and the column address corresponding to the spare row replacement process and the spare column replacement process. Memory C
M2 is provided for each. Second replacement determination unit 31
Reference numeral 00.2 indicates the pass / fail signal P for the memory cell columns in the corresponding row address memory unit RM2 and column address memory unit CM2 in the order of memory cell column MCR21, memory cell column MCC21, and memory cell column MCR22. Each time / F is activated, it is determined whether or not the internal address signal at that time is written in the memory cell column. Other configurations are similar to those of the first replacement determination unit 3100.1.

With respect to the third replacement determining unit 3100.3 as well, according to Case 3, only the corresponding memory cell column and the order of writing to the memory cell column are different, and other configurations are similar to the replacement determining unit 3100. Since the configuration is the same as that of No. 1, the description thereof will not be repeated.

Further, in the above configuration, the operation of the replacement determining unit 3100.1 during the determination is the same except for the driving method of the word line TWL and the write word line WLa at the time of writing data to the associative memory cell. Since it is similar to that described in FIG. 12, description thereof will not be repeated.

In the operation of reading data from the associative memory cell, the level of the signal line SRL is activated ("H" level) and the write word line WLa is activated, which will be described later. As described above, the word line TWL is also activated under the control of the BIST control unit 2010.

FIG. 4 is a circuit diagram showing a structure of the associative memory cell shown in FIG. 3 and a structure for writing data to the associative memory cell.

Also in FIG. 4, the structure of the associative memory cells CAMC1 and CAMC2 corresponding to one bit line pair in the associative memory cell array shown in FIG. 3 is extracted and shown. Here, this bit line pair has, for example, internal column address signals CAn and / CAn (n: natural number).
Shall be transmitted.

Referring to FIG. 4, associative memory cell CAM
C1 is an inverter INV whose input is coupled to the node n1
2 and an inverter INV1 having an input coupled to the output node of the inverter INV2. Inverter INV1
Between the output node n2 and the node n1 of the N channel MO whose gate potential is controlled by the write word line WLa.
An S transistor ZWTr is provided. Inverter IN
V1 and the inverter INV2 make the transistor ZWTr
In the ON state, a bistable memory element is formed.

Inverter INV1 includes P-channel MOS transistor TP1 and N-channel MOS transistor T connected in series between power supply potential Vcc and ground potential.
Including N1. The inverter INV2 includes a P-channel MOS transistor TP2 and an N-channel MOS transistor T connected in series between the power supply potential Vcc and the ground potential.
Including N2.

The associative memory cell CAMC1 further includes
A bit line (hereinafter, address signal line) ASL1 for transmitting the internal column address signal CAn and a node n1 are connected to each other.
An N-channel access transistor TA1 for connection according to the level of the word line TWL, and a match detection line MH
N-channel transistors T11 and T12 connected in series between L1 and the ground potential, and the match detection line MHL1
Transistor T1 connected in series between the ground and the ground potential
3 and T14.

The gate of the transistor T11 is connected to the address signal line ASL1, and the gate of the transistor T12 is connected to the output node of the inverter INV2.
The gate of the transistor T13 is connected to the node n1,
The gate of the transistor T14 is the address signal line ASL2.
Connected with.

That is, in the data write operation, the inverter I is activated in response to the activation of the word line TWL1.
The input node of NV2 is connected to the address signal line ASL1. In the data read operation, the word line TW
Depending on the activation of L1 and the write word line WLa1,
The output node of the inverter INV1 is the address signal line A
It is connected to SL1.

On the other hand, in the comparison operation, the data held in the bistable storage element and the address signal line ASL1
And the internal address signal on ASL2 does not match, the match detection line MHL is connected to the path of the transistors T11 and T12 or the transistors T13 and T14.
It will be connected to the ground potential and discharged through any of the paths.

The structure of the associative memory cell CAMC2 is similar to that of the associative memory cell CAMC1.

That is, in the structure of the associative memory cell shown in FIG. 4, in addition to the structure shown in FIG. 13, a write word line WLa is further provided, and a transistor ZWTr which is turned on / off by the write word line WLa is provided as a storage element. Are provided between the two inverters and the bit line (address signal line) ASL1. Also, one of the access transistors TA
Delete 2. At the time of writing data, the word line WLa is lowered before the word line TWL is raised, and the transistor Z is turned off.
Turn off WTr.

The bit line (address signal line) AS is connected via the output node of the inverter INV1 of the associative memory cell.
Since the current flowing from L1 to the ground potential can be cut, the size of the bit line driver BLDRV can be reduced.

At the time of holding / determining data and reading data, the newly inserted transistor ZWTr is turned on.

With this structure, the bit line driver BLDRV does not need to flow a large current,
Since the size can be reduced, the current during the write operation can be reduced.

Further, although the number of word lines is increased as compared with the conventional structure, since the number of transistors is the same as the conventional structure, it is possible to suppress an increase in array area. Therefore, by reducing the size of the bit line driver, it is possible to reduce the layout area of the CAM cell array and its writing circuit as a whole.

FIG. 5 is a diagram for explaining the temporal changes in the potential levels of word line TWL1 and write word line WLa1 in the write operation, data holding / determining operation and read operation for the associative memory cell shown in FIG. It is a timing chart.

For example, if the data write operation is started from time t1, the potential level of write word line WLa1 is inactive (set to "L" level) at time t1. After that, the access transistor TA
The word line TWL controlling 1 is activated, data is written from the bit line driver BLDRV, and the write operation is completed at time t2.

In the data holding operation or the match determining operation, word line TWL1 is maintained in the inactive state. On the other hand, the write word line WLa1 maintains the active state,
The transistor ZWTr remains conductive.

At time t3, when the read operation is started, word line TWL is activated to connect bit line ASL1 to corresponding node n1. Further, the write word line WLa1 also maintains the active state (“H”) level.

FIG. 6 shows a write / read drive circuit 3 shown in FIG.
2 is a circuit diagram showing a configuration of 200. FIG. In FIG. 6, only the configuration corresponding to the memory cell column MCR11 is extracted and shown.

Referring to FIG. 6, write / read drive circuit 320.
0 is an inverter INV32 that receives a signal from the node WEa of the replacement determination unit 3100.1 and inverts it, and one input is coupled to the signal line SRL and the other input is the inverter INV.
An inverter INV3 that receives an output from an inverter INV32 and an OR circuit GOR10 that is coupled to the output of the inverter 32 and applies an inverted signal to the word line TWL of the associative memory cell.
4 and one input is connected to the coincidence detection line MHL and the other input is connected to the output of the flip-flop circuit SFR11, and the result of the logical product operation is set to the node MH of the replacement determination unit 3100.1.
and an AND circuit GAD10 given to a.

In the data holding operation or the match determination operation, the level of node WEa is at "L" level and the level of write word line WLa is maintained at "H". On the other hand, also in the read operation, the level of the signal line SRL becomes “H”, so that the level of the write word line WLa is maintained at “H”.

On the other hand, in the write operation, when the level of the node WEa becomes "H" level, the level of the write word line WLa becomes "L". After that, delaying by the signal transmission delay time of the inverter INV34,
The level of the word line TWL becomes "H".

FIG. 7 shows the first replacement judging section 3 shown in FIG.
10 is a schematic block diagram for explaining the configuration of 100.1.

The second replacement determination section 3100.2 to the third replacement determination section 3100.3 have the same basic configuration except that the connected memory cell columns are different.

The first replacement determination section 3100.1 has an AND circuit in which the match detection line MHL of the memory cell column MCR11 and the output of the flip-flop circuit SFR11 are connected to the input node.
The output from the circuit GAD10, the output from the AND circuit GAD10 in which the output of the match detection line MHL of the storage cell column MCR12 and the flip-flop circuit SFR12 are connected to the input node, and the output of the match detection line MHL of the storage cell column MCC11.
And the output of flip-flop circuit SFC11 and the output of AND circuit GAD10 connected to the input node, and includes 3-input NOR circuit 3110 for outputting signal MS.

In the first replacement judging section 3100.1,
The nodes connected to the output nodes of the AND circuit GAD10 of the memory cell columns MCR11, MCR12 and MCC11 are represented by nodes MHa, MHb and MHc, respectively, and the input nodes connected to the outputs of the flip-flop circuits SFR11 to SFC11 are nodes MVa, MVb and MVc. Will be represented by.

The first substitution judging section 3100.1 further receives the signal MS and the pass / fail signal P / F, and outputs an AND of these signals, and an AND circuit 3120.
An inverted signal of the level of the node MVa, an inverted signal of the level of the node MVb, an inverted signal of the level of the node MVc, and
A logic gate 3300 that receives the output of the ND circuit 3120 and outputs a logical product of these signals, and a logic gate 33.
00, an OR circuit 3302 that receives the signal Ew1 that is activated from the BIST control unit 2010 at the time of data reading after the end of the test operation, an activation signal WLE that is applied from the BIST control unit 2010, and an OR circuit 3302. AND circuit 3304 for receiving the output of
Inverter 3306 that inverts the output of D circuit 3304
And an inverter 3308 which inverts the output of the inverter 3306 and outputs a selection signal WEa to be applied to the CAM cell word line TWL of the memory cell column MCR11.

The first replacement determining section 3100.1 further receives the signal of the level of the node MVa, the inverted signal of the level of the node MVb, the inverted signal of the level of the node MVc, and A
A logic gate 3310 which receives the output of the ND circuit 3120 and outputs a logical product of these signals, and a logic gate 33.
10 and the signal Ew2 supplied from the BIST control unit 2010, an OR circuit 3312, an AND circuit 3314 receiving the activation signal WLE supplied from the BIST control unit 2010 and the output of the OR circuit 3312, and A
Inverter 3316 that inverts the output of ND circuit 3314
And an inverter 3318 that inverts the output of the inverter 3316 and outputs a selection signal WEb to be applied to the CAM cell word line TWL of the memory cell column MCR12.

The first replacement determining section 3100.1 further ANDs the signal of the level of the node MVa, the signal of the level of the node MVb, and the inverted signal of the level of the node MVc.
A logic gate 3320 which receives the output of the circuit 3120 and outputs a logical product of these signals;
OR circuit 3322 that receives the output of the BIST control unit 2010 and the signal Ew3 supplied from the BIST control unit 2010, and the activation signal WLE supplied from the BIST control unit 2010 and the OR circuit 3
AND circuit 3312 which receives the output of 322 and AND
An inverter 3326 that inverts the output of the circuit 3324;
The output of the inverter 3326 is inverted, and the memory cell column MC
An inverter 3328 that outputs a selection signal WEc to be applied to the CAM cell word line TWL of C11.

The first permutation inversion unit 3100.1 further receives the level of the node MVa, the level of the node MVb, the level of the node MVc, and the output of the AND circuit 3120, and outputs a logical product of these, and is a 4-input AND. Circuit 333
0, reset in response to the reset signal RST,
Case 1 set according to the output of D circuit 3330
Flip-flop circuit 3340 for outputting a repair fail signal CS1-RF for

Therefore, the repair fail signal CS1-
RF is within the range of two spare rows and one spare column, if the defective memory cells in the corresponding sub memory cell array 100. 1 can be replaced and repaired in the replacement order of R → R → C. , And “L” level, it becomes “H” level when replacement is impossible.

The activation signal WLE is a signal which is set to the "H" level in the write operation and the read operation.

With the above structure, the memory cell array 10 is self-tested while suppressing the area occupied by the write driver circuit for the associative memory cell array.
It is possible to perform redundant relief for relieving the defective memory cell in 0.

[Second Embodiment] In the first embodiment, the associative memory cell array has been described. However, in the second embodiment, a configuration similar to that of the first embodiment is applied to a static random access memory (hereinafter referred to as SRAM). Call)
The configuration applied to the above will be described.

FIG. 8 shows SRAM 4000 of the second embodiment.
Only the circuit for selecting the memory cell array 100 and the memory cell is extracted and shown.

In the memory cell array 100, memory cells MC described later are arranged in a matrix. A word line TWL and a write W corresponding to each memory cell row
La is provided. On the other hand, bit lines BL1 to BL are provided corresponding to the memory cell columns.

Row decoder 40 selects signal W for the selected memory cell row in response to address signal ADD.
Output E. The selection signal WE is the inverter INV32
Is inverted by the inverter INV34 and further transmitted to the word line TWL of the selected memory cell row.

On the other hand, OR circuit GOR10 receiving the output of inverter INV32 at one input receives signal R / W at the other input which attains "H" level in the read operation and "L" level in the write operation. OR circuit GO
The output of R10 is applied to the write word line WLa.

On the other hand, the column decoder 50 outputs the address signal A
A memory cell column is selected according to DD, and the potential level of the bit line of the selected memory cell column is driven according to write data DQ.

FIG. 9 is a circuit diagram showing a structure of memory cell MC shown in FIG. Referring to FIG. 9, the memory cell M
C is an inverter INV2 whose input is coupled to the node n1
And an inverter INV1 having an input coupled to the output node of the inverter INV2. An N channel MOS whose gate potential is controlled by the write word line WLa is provided between the output node n2 and the node n1 of the inverter INV1.
A transistor ZWTr is provided. Inverter INV
1 and the inverter INV2 form a bistable storage element when the transistor ZWTr is in the ON state.

The memory cell MC further includes a bit line BL
1 and the node n1 according to the level of the word line TWL, an N-channel type access transistor TA.
Including 1.

That is, in the data write operation, the word line WLa is lowered before the word line TWL is raised to turn off the transistor ZWTr. Therefore, when writing data, the input node of inverter INV2 is connected to bit line BL1 in response to activation of word line TWL.

In the data read operation, in response to activation of word line TWL and write word line WLa,
The output node of the inverter INV1 is connected to the bit line BL1. During the data holding operation and the data reading, the transistor ZWTr is turned on.

With such a configuration, the bit line driver (not shown) in column decoder 50 does not need to flow a large current, and its size can be reduced, so that the current during the write operation is reduced. Can be made smaller.

FIG. 10 is a timing chart for explaining the time change of the potential levels of word line TWL and write word line WLa in the write operation, data holding operation and read operation for memory cell MC shown in FIG. is there.

For example, if the data write operation is started from time t1, signal R is read at this time t1.
/ W is set to "L" level, and the potential level of write word line WLa is inactive (set to "L" level). After that, the word line T for controlling the access transistor TA1 of the memory cell row selected by the address signal ADD
WL is activated, data is written from the bit line driver, and the write operation ends at time t2.

In the data holding operation, the word line TW
L is kept in the inactive state. On the other hand, the write word line W
La remains active and transistor ZWTr remains conductive. At this time, since the signal WE is at "L" level, the signal R / W may be at "L" or "H" level.

At time t3, when the read operation is started, word line TWL is activated and bit line BL1 is connected to corresponding node n1. Further, the write word line WLa also maintains the active state (“H”) level.

With this structure, the SRAM 4
In 000, even when it is necessary to simultaneously enable a plurality of word lines and simultaneously write data to a plurality of memory cells corresponding to the plurality of word lines, the circuit scale of the bit line driver circuit is suppressed, In addition, the power consumption at the time of writing data can be reduced.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0157]

According to the memory cell of the first and second aspects,
Even when writing the reverse data to the already stored data at the time of writing the data, the current flowing from the first bit line through the first inverter can be suppressed, so that the current consumption at the time of writing can be reduced. Moreover, it is possible to make the driver circuit for writing small.

According to another aspect of the semiconductor integrated circuit device of the present invention, when a plurality of word lines are simultaneously activated at the time of data writing and the already stored data and reverse data are written to a plurality of memory cells. However, since the current flowing from the first bit line through the memory cell can be suppressed,
The current consumption during writing can be reduced. Moreover, it is possible to make the driver circuit for writing small.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a dynamic semiconductor memory device 1000 according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram for explaining the configuration of a BIST circuit 2000 shown in FIG.

FIG. 3 is a schematic block diagram for explaining a configuration of address replacement determiner 3000 shown in FIG.

FIG. 4 is a circuit diagram showing a structure of the associative memory cell shown in FIG. 3 and a structure for writing data to the associative memory cell.

FIG. 5 is a timing chart for explaining a time change of a signal in a writing operation, a data holding / determining operation, and a reading operation for an associative memory cell.

6 is a circuit diagram showing a configuration of a write / read drive circuit 3200 shown in FIG.

7 is a diagram illustrating a first replacement determination unit 3100.1 shown in FIG.
3 is a schematic block diagram for explaining the configuration of FIG.

FIG. 8 is a circuit diagram showing only a configuration for selecting a memory cell array 100 and a memory cell out of the configuration of SRAM 4000 of the second embodiment.

9 is a circuit diagram showing a configuration of a memory cell MC shown in FIG.

FIG. 10 is a timing chart for explaining changes over time in potential levels of word line TWL and write word line WLa in a write operation, a data holding operation, and a read operation with respect to memory cell MC.

FIG. 11 is a memory array portion 8010 of the semiconductor memory device.
FIG. 3 is a schematic block diagram showing an example of the configuration of a redundant circuit provided for the.

FIG. 12 is a schematic block diagram for explaining a configuration of a conventional address replacement determination unit 8000 for determining a repairable replacement order.

FIG. 13 is a CAM cell C corresponding to one bit line pair.
It is a circuit diagram which extracts and shows the structure of AMC1 and CAMC2.

[Explanation of symbols]

11 control signal input terminal group, 13 address signal input terminal group, 15 data input / output terminal group, 18 external power supply terminal, 19 external ground terminal, 26 control circuit, 3
0 address buffer, 40 row decoder, 42 spare row decoder, 50 column decoder, 52 spare column decoder, 70 internal potential generation circuit, 72 internal control signal bus, 80 read amplifier / write driver, 85 input / output buffer, 100 memory cell array , 200 column selection / sense amplifier circuit, 1000 DARM, 200
0,2002 BIST circuit, 3000 address replacement determination circuit, 3100.1 to 3100.3 replacement determination unit,
RM1 to RM3 Row address storage unit, CM1 to CM
3 Column address storage section.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 29/00 671 G01R 31/28 B V

Claims (6)

[Claims] 1. A first transistor coupled to a first bit line and a first internal node for transmitting read data and write data under the control of a first word line, and a second word. A second transistor controlled by a line to connect the first internal node and the second internal node, a first inverter connecting the first node to the input node, and a first inverter A second inverter having an output coupled to the input node, the output node coupled to the second internal node. 2. A third and a fourth transistor connected in series between the coincidence detection line and a predetermined potential, and a fifth and a fifth transistor connected in series between the coincidence detection line and the predetermined potential. The third transistor is rendered conductive in accordance with the output level of the second inverter, and the fourth transistor is rendered conductive in accordance with the level of the first bit line. 2. The fifth transistor is rendered conductive in accordance with the level of the first internal node, and the sixth transistor is rendered conductive in accordance with the level of the second bit line. Memory cells. 3. A memory cell array having a plurality of memory cells arranged in a matrix, each memory cell being controlled by a first word line, a first data line for transmitting read data and write data. A first transistor connecting the bit line and the first internal node; a second transistor connected by the second word line to connect the first internal node and the second internal node; A first inverter having a first node and an input node coupled to each other; a second inverter having an output and an input node of the first inverter coupled to each other and an output node coupled to the second internal node; A row selection circuit that selectively drives the first and second word line levels according to an address signal, and the first selection circuit according to the address signal and write data.
And a column selection circuit for selectively driving the bit line level of the semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 3, wherein the row selection circuit selectively turns on the first transistor after turning off the second transistor in a write operation. . 5. A memory cell array in which a plurality of memory cells each for holding storage data are arranged in a matrix, wherein the memory cell array includes a normal memory cell array including a plurality of normal memory cells and a plurality of spares. A spare memory cell array including memory cells, and for selecting at least one of a memory cell row and a memory cell column common to the normal memory cell arrays of the first and second sub-memory cell arrays according to an address signal. A normal memory cell selection circuit, and in the case where there is a defective memory cell in the normal memory cell array, the normal memory cell selection circuit, instead of one of the common memory cell row and memory cell column to be selected by the normal memory cell selection circuit, Select either memory cell row or memory cell column in the spare memory cell array Further comprising a spare memory cell selection circuit for detecting the defective memory cell in the normal memory cell, and a self-test circuit for performing a test for determining which spare memory cell is to be replaced. The self-test circuit includes an associative memory cell array having a plurality of associative memory cells arranged in a matrix to obtain a comparison result of the previously detected defective address and a newly detected defective address, Each of the associative memory cells is controlled by a first word line to couple a first bit line for transmitting a detected defective address to a first internal node, and a first transistor. A second transistor controlled by a second word line to couple the first internal node and the second internal node; and the first node and the input node. And a second inverter having an output node of the first inverter coupled to an input node and an output node coupled to the second internal node, and a match for transmitting the comparison result. Third and fourth transistors connected in series between the detection line and the predetermined potential, and fifth and sixth transistors connected in series between the coincidence detection line and the predetermined potential are further included. The third transistor is rendered conductive in accordance with the output level of the second inverter, the fourth transistor is rendered conductive in accordance with the level of the first bit line, and the fifth transistor is The transistor is conductive according to the level of the first internal node, and the sixth transistor is conductive according to the level of the second bit line. Apparatus. 6. The semiconductor integrated circuit according to claim 5, wherein the associative memory cell selectively turns on the first transistor after turning off the second transistor in a write operation. apparatus.