JP2003030051A - Data processor and data access method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress reduce data processing speed due to erroneous cache by excluding probabilistic elements from behaviors of a cache memory. SOLUTION: A computer 10 is provided with a CPU 11 to carry out a given instruction and main storage memory 16 to be defined as an accessing object of the CPU 11. In addition, the computer 10 is provided with the cache memory 13 to act for write and/or read of data to be performed between the CPU 11 and the main storage memory 16 and a cache memory control part 15 to lock a cache line to write and/or read data by accessing the cache memory 13 by the CPU 11 based on the instruction given to the CPU 11 and to unlock the cache line according to access to an address of the locked cache line by the CPU 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to writing and / or writing data to be performed between a processor and a main memory.
Also, the present invention relates to a data processing device and a data access method for accessing data held in a cache memory that performs read-out.

[0002]

2. Description of the Related Art A general operating system (op
In the erating system, a thread or a process exists as one unit of data processing. An operating system executes a so-called context switch (thread) in order to perform a plurality of data processings simultaneously on a computer such as a workstation having limited resources.
ing) operation is performed by switching to realize a multi-task system.

In the context switching operation, a process of saving the contents of a plurality of register files provided in the computer to the main memory and a process of restoring the contents of the main memory to the register file are performed.
Therefore, in the process of saving or restoring the contents of the register file to a plurality of CPUs, the CPU (Central Processi)
ng Unit), the frequency of access to the main memory, which has a slower operating speed than the operating speed, will increase the overhead of data processing.

Therefore, in the computer, a so-called cache memory is provided as a buffer memory interposed between the CPU and the main storage memory on the memory hierarchy. That is, in the computer, paying attention to the fact that the CPU reuses the data most recently accessed in time, or refers to the data placed near the most recently accessed data in time, Data to be saved between the CPU and main memory when a process of saving or restoring the contents of the register file secures a copy of part of the data on the main memory in the cache memory with a high operation speed. By substituting the writing and / or reading of the above, the access time to the main memory is hidden. Even in the context switching operation, the data processing can be performed at high speed by using the cache memory.

[0005]

The capacity of the cache memory described above is very small compared to the capacity of the main memory. Therefore, when the CPU accesses the cache memory, the required data may not exist, resulting in a so-called cache miss. At this point, the operation of the cache memory is
I had to say that it was stochastic. Therefore, it is difficult for the computer to speed up the data processing by the cache memory in all cases of the generated context switching operation.

[0006] On the other hand, the cache memory brings about a speeding up of data processing, but on the other hand, it causes a difference in data processing speed at the time of so-called cache hit and cache miss. Therefore, in the service call of the operating system including the context switching operation that requires frequent access to the main memory, even if the same processing is performed, the processing time greatly varies. In a computer, it is important to minimize variations in processing time without impairing the maximum data processing speed from the standpoint of designing a system that efficiently uses resources.

As a measure for avoiding such a stochastic operation of the cache memory, there is one called a cache lock mechanism. This cache lock mechanism is realized by a cache lock instruction for fixing the contents of the register file in the cache memory. As a result, in the computer, the contents of the locked cache line are not changed without permission, and when accessing this cache line, there is a risk that a hit will always occur and a cache miss will occur.

However, the computer may not be able to hold the necessary data in the cache memory due to unnecessary cache lock, and as a result,
The frequency of access to the main memory is increased, which may cause a decrease in data processing speed. Moreover, in the computer, in order to unlock the cache line locked by the cache lock instruction, it is necessary to give a cache unlock instruction again.

As an existing device for the purpose of speeding up the context switching operation, there is a device provided with a register file different from the register file normally used in a computer. In this computer, when a context switching operation occurs, the contents of the register file are saved in another separately prepared register file. In this way, this computer suppresses the overhead caused by the increase in the frequency of access to the main memory by performing the data transfer between the register files connected by the high-speed internal bus.

However, this computer has a problem that the manufacturing cost of the hardware increases because it is necessary to separately provide a register file in addition to the normally used register file.

Further, as another existing device for the purpose of speeding up the context switching operation, Japanese Patent Laid-Open No.
As described in Japanese Patent Application Laid-Open No. 0-242505, by limiting the number of register files that can be used in a thread during program execution in advance, the number of register files to be saved can be reduced during context switching operation. , There is one that aims to shorten the data processing time.

However, in this computer, there is a possibility that the data processing speed may be lowered by limiting the number of register files. Further, this computer has a problem that a special compiler is required to limit the number of register files. Furthermore, this computer had to be provided with special hardware for notifying the operating system of the register file to be saved.

The present invention has been made in view of the above circumstances, and it is possible to unlock a locked cache line without using a cache unlock instruction, and it is probabilistic from the operation behavior of the cache memory. An object of the present invention is to provide a data processing device and a data access method capable of suppressing the decrease in data processing speed due to a cache miss by eliminating elements.

[0014]

A data processing apparatus according to the present invention that achieves the above-mentioned object writes a processor that executes a given instruction and data to be accessed by the processor and supplied from the processor. And / or a main memory from which data stored by the processor is read and a processor and a main memory that hold data to be written to the main memory by the processor and / or data to be read from the main memory by the processor Between the cache memory that performs the writing and / or reading of data to be performed between the cache memory and the cache line in which the processor accesses the cache memory and writes and / or reads the data based on the instruction given to the processor. Locked and locked Depending on the processor to access the address of Yasshurain, it is characterized in that a control means for unlocking the cache line.

In the data processing apparatus according to the present invention as described above, the cache line is temporarily locked under the control of the control means, and thereafter, the processor access to the address of the main memory corresponding to the cache line is possible. Lock the cache line until a certain time.

Further, in the data access method according to the present invention which achieves the above-mentioned object, writing and / or reading can be performed between a processor executing a given instruction and a main memory to be accessed by this processor. Write and / or read of data to be performed between the processor and the main memory, holding data to be written to the main memory by the processor and / or data to be read from the main memory by the processor A data access method for accessing data held in a cache memory on behalf of a processor, wherein the processor accesses the cache memory based on an instruction given to the processor to write and / or write data.
Alternatively, it is characterized in that the read cache line is locked and the cache line is unlocked when the processor accesses the address of the locked cache line.

In such a data access method according to the present invention, the cache line is temporarily locked, and thereafter, the cache line is locked until the processor accesses the address of the main memory corresponding to the cache line.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments to which the present invention is applied will be described in detail below with reference to the drawings.

As shown in FIG. 1, this embodiment is a computer 10 such as a workstation, which is provided with a so-called cache memory 13, and in particular unlocks a cache line locked without using a cache unlock instruction. It is provided with a mechanism that can be locked. That is, the computer 10 is effective during so-called context switching operation, and the contents of the register file are temporarily locked in the cache memory 13 so that the operation behavior of the cache memory 13 can be estimated. It is possible to suppress the reduction of the data processing speed due to a so-called cache miss by eliminating the essential element. More specifically, the computer 10 temporarily locks a cache line, and thereafter, until there is a predetermined number of so-called cache hits caused by an access request to the address of the main memory 16 corresponding to this cache line, the register file of the register file is deleted. Contents of cache memory 13
It is equipped with a mechanism that locks up. In the following, after the computer 10 locks the cache line,
The cache line is unlocked by the first cache hit, and this mechanism is called a one-time cache lock mechanism.

As shown in FIG. 1, the computer 10 physically stores a CPU (Central Processing Unit) 11 having various units necessary for executing instructions in the computer 10 and a virtual address VAD of the main memory 106 to be accessed. An address conversion unit 12 for converting to an address PAD,
A cache memory 13 as a buffer memory interposed between the CPU 101 and the main memory 106, and a comparator 14 for comparing the physical address PAD supplied from the address conversion unit 12 and the tag information TG supplied from the cache memory 13. And a cache memory control unit 15 that is a control unit that controls the cache memory 13, and a main memory 16 that is an access target of the CPU 11.

The CPU 11 has an instruction fetch unit for reading instructions, an instruction dispatch unit for the operating system to control the allocation of operations, and an arithmetic unit for performing various operations. , And an execution control unit for controlling the execution of the instructions, and various units necessary for executing the instructions in the computer 10. CPU1
When No. 1 is given a store (STORE) command, which is a write command, 1 writes data DT to the main memory 16. At this time, the CPU 11 also writes the data DT to the cache memory 13. Also, C
The PU 11 reads the data DT from the main memory 16 when a load (LOAD) instruction is given. At this time, the CPU 11 reads the corresponding data DT from the cache memory 13 without accessing the main memory 16 at the time of a cache hit. The CPU 11 has a main memory 16 to be accessed with respect to the address conversion unit 12 and the cache memory 13.
Of the virtual address VAD. Here, the virtual address VAD is a predetermined number of higher bits of the physical address PAD of the main memory 16. Further, when the CPU 11 is given a later-described instruction with a one-time cache lock mechanism for performing the one-time cache lock mechanism, the CPU 11 outputs a one-time lock bit request signal OTLR for requesting an operation of the one-time cache lock mechanism. This is generated and the one-time lock bit request signal OTLR is supplied to the cache memory control unit 15.

The address conversion unit 12 converts the virtual address VAD of the main memory 106 to be accessed supplied from the CPU 11 into a physical address PAD. The address conversion unit 12 uses the converted physical address PAD as the comparator 1.
4 and the main storage memory 16.

As shown in FIG. 2, the cache memory 13 has a plurality of cache lines C represented by a fixed length.
It has L ₁ , CL ₂ , CL ₃ , CL ₄ , ... Cash lines CL ₁ , CL ₂ , CL ₃ , CL ₄ , ...
Are the data fields that store the data,
It is composed of a tag field that stores a tag that is an identifier expressed by a physical address for identifying this data.

More specifically, the cache lines CL ₁ ,
As shown in FIG. 3, the tag fields in CL ₂ , CL ₃ , CL ₄ , ... Each include a tag part for storing the above-mentioned tag and a valid bit indicating the validity of the cache line. A valid bit part to store, a lock bit part to store the lock bit (lock bit) indicating whether the mode is the existing cache lock mechanism, and a one indicating whether the mode is the one-time cache lock mechanism. Time lock bit (onetime lock
bit), and has a one-time lock bit unit.

In the valid bit part, when both the information stored in the tag field and the data stored in the data field in the cache line are valid, "1" is set as a flag indicating that they are valid. When "" is added and any of the information and data stored in the tag field is invalid, "0" is added.

"1" is added to the lock bit portion as a flag indicating that the data stored in the data field is locked, and "0" is added when it indicates that the data is not locked. To be done.

Like the lock bit part, the one-time lock bit part is provided with "1" as a flag indicating that the data stored in the data field is locked, indicating that it is not locked. in case of,
“0” is added.

In the computer 10, cashier
In CL₁, CL_Two, CL_Three, CL _FourThat's ...
Between the lock bit and the one-time lock bit
If both are assigned "1", the normal cap
The shrock mechanism shall be executed preferentially.

Also, the cache lines CL ₁ , CL ₂ ,
The data fields in CL ₃ , CL ₄ , ...
Each of them is composed of four data parts for storing data A, B, C, D so that a plurality of pieces of information are handled as one, and each data is stored in each data part.

A plurality of such cache lines C
L₁, CL_Two, CL_Three, CL_FourCaps with ...
In the cache memory 13, the cache memory control unit 1
Based on the lock bit control signal LBC supplied from
Each cache line CL₁, CL_Two, CL_Three, C
L_FourLocks to be added to the lock bit part in
Qubit value is controlled and cache memory
One-time lock bit control supplied from the control unit 15
Each cache line CL based on the signal OTLBC₁，
CL_Two, CL_Three, CL_Four, ...
Value of one-time lock bit given to the qubit part
Is controlled. Is the cache memory 13 a CPU 11?
When the virtual address VAD is supplied from the
Select the cache line associated with the VAD
It For example, the cache memory 13 is shown in the shaded area in FIG.
Based on the virtual address VAD, the cache
Line CL _ThreeSelect. At this time, cache memory
13, as described above, the tag is expressed by the physical address.
Therefore, it is similar to the address conversion unit 12 described above.
The virtual address VAD provided to
Inside the memory 13, the physical address corresponding to the physical address PAD
Convert to a dress. Then, the cache memory 13
The tag stored in the tag part of the selected cache line
Is supplied to the comparator 14 as tag information TG.

Further, the cache memory 13 outputs the valid bit stored in the valid bit portion of the selected cache line as a signal necessary for controlling the operation of the cache memory 13 together with the output of the tag information TG. As the valid bit signal VB, the lock bit stored in the lock bit portion of the selected cache line is used as the lock bit signal LB, and the one-time lock bit stored in the one-time lock bit portion of the selected cache line is used for one time. As the lock bit signal OTLB, the cache memory control unit 15
Supply to. Under the control of the cache memory control unit 15, the cache memory 13 holds data DT to be written in the main memory 16 by the CPU 11 and / or data to be read from the main memory 16 by the CPU 11 at the time of a cache hit. Hold DT.

In the computer 10, the conversion of the virtual address VAD to the physical address PAD is performed inside the cache memory 13 in addition to the address conversion unit 12 by performing two independent processes in parallel. It is intended to be

The comparator 14 is provided to determine a cache hit or a cache miss in the cache memory 13 using the tag information TG. That is, the comparator 14 compares the physical address PAD supplied from the address conversion unit 12 with the tag information TG supplied from the cache memory 13. Then, the comparator 14
Supplies the comparison result as a hit / miss signal H / M to the cache memory control unit 15.

The cache memory control unit 15 controls the cache memory 13. Specifically, the cache memory control unit 15 determines the cache hit of the cache memory 13 based on the valid bit signal VB supplied from the cache memory 13 and the hit / miss signal H / M supplied from the comparator 14. Alternatively, the CPU 11 and the cache memory 13 are grasped by grasping the state of the cache miss.
Controls writing and / or reading of the data DT between and. That is, when the valid bit signal VB indicates that the data is valid and the hit / miss signal H / M indicates that the addresses match, the cache memory control unit 15 determines the cache hit. It is determined that In addition, the cache memory control unit 15
Grasps the lock state of the cache memory 13 based on the lock bit signal LB and the one-time lock bit signal OTLB supplied from the cache memory 13.

Further, the cache memory control unit 15 is
When the cache lock instruction is given to the CPU 11, the lock bit control signal LBC is supplied to the cache memory 13 so that the cache memory 13
In each cache line CL ₁ , CL ₂ , CL ₃ ,
Operate the lock bit part of CL ₄ , ...
Lock the cache. Cache memory control unit 15
When a cache unlock command is given to the CPU 11, the cache memory 13 supplies a control signal (not shown) for unlocking the cache-locked cache line. Furthermore, the cache memory control unit 15 receives a command with a one-time cache lock, which will be described later, from the CPU 11.
One-time lock bit request signal O supplied from 11
One-time cache lock is performed on the cache memory 13 based on the TLR. That is, the cache memory control unit 15 supplies the one-time lock bit control signal OTLBC to the cache memory 13 based on the instruction with the one-time cache lock given to the CPU 11, so that the CPU 11 causes the cache memory to operate. Each cache line CL ₁ , CL ₂ , CL ₃ , C in the cache memory 13 that accessed 13 to write and / or read data
The one-time lock bit portion of L ₄ , ... Is operated to perform one-time cache lock. As will be described later, the cache memory control unit 15 sends to the cache memory 13 a control signal for unlocking the cache line in response to the CPU 11 accessing the address of the cache line locked by the one-time cache lock. Supply.

The main memory 16 has an address conversion unit 1
The data DT supplied from the CPU 11 is written to the address represented by the physical address PAD supplied from 2. Further, the data DT stored in the address represented by the physical address PAD supplied from the address conversion unit 12 from the main memory 16 is stored in the CPU 1
Read by 1.

Such a computer 10 is a one-time cache.
A shlock mechanism is realized. Specifically, the computer 10
Is each cache line in the cache memory 13.
CL ₁, CL_Two, CL_Three, CL_Four, ...
One-time lock bit to control the bit part
Provided an instruction to operate the cache lock mechanism
It The computer 10 issues the above-mentioned store instruction as this instruction.
A new version of the decree and load instructions will be installed. Ingredient
Physically, the computer 10 uses this command as a main memory memo.
When writing the data DT to the memory 16,
The data DT to be written in the cache memory 13
It is a write command with a lock for shredding.
Store with o one-time cash lock
ne time cache lock) instruction "STORE.fmt.otcl"
When reading the data DT from the storage memory 16,
Data DT to be written in the cache memory 13
It is a read instruction with a lock for cache lock.
Load with one-time cash lock (load with
One time cache lock) instruction "LOAD.fmt.otcl"
To do.

The store instruction with one-time cache lock is a one-time cache lock for the cache line associated with the accessed address of the main memory 16 after the CPU 11 writes the data to the main memory 16. . The cache line locked by the store instruction with the one-time cache lock is unlocked by the access to the main memory 16 by the hit by the CPU 11. On the other hand, the load instruction with one-time cache lock is a one-time cache lock for the cache line associated with the accessed address of the main memory 16 after the CPU 11 reads the data from the main memory 16. The cache line locked by the load instruction with the one-time cache lock is also unlocked by the access to the main memory 16 accompanied by the hit by the CPU 11. Note that “fmt” in “STORE.fmt.otcl” and “LOAD.fmt.otcl” is an abbreviation of the format, and is the type of data that is the target of access to the main memory 16. Is a field indicating. In addition, “STORE.
"otcl" in fmt.otcl "and" LOAD.fmt.otcl "
Is a field for indicating to the CPU 11 that the instruction is an instruction with a one-time cache lock.

When such an instruction with a one-time cache lock is issued, the computer 10 decodes the instruction with a one-time cache lock by the CPU 11 and executes it. The computer 10 causes the CPU 11 to convert the virtual address VAD to be accessed to the main memory 16 into the address conversion unit 12 and the cache memory 13.
And a one-time lock bit request signal OTLR to the cache memory controller 15 to make a one-time cache lock request for the cache line in the cache memory 13 associated with the virtual address VAD, and The one-time lock bit part is locked by adding a flag. Then, the computer 10 unlocks the cache line by the first cache hit caused by the subsequent access request to the address of the main memory 16 corresponding to this cache line. As a result, in the computer 10, after the cache line is locked by the instruction with the one-time cache lock, it is guaranteed that the cache hit will occur only in the next first access.

Specifically, when the one-time cache lock instruction is issued, the computer 10 locks the cache line for one time cache through a series of steps shown in FIG.

First, the computer 10, as shown in FIG.
In step S1, the CPU 11 supplies the one-time lock bit request signal OTLR to the cache memory 15.

Subsequently, in step S2, the computer 10 causes the cache memory control unit 15 to perform a cache hit of the cache memory 13 based on the hit / miss signal H / M supplied from the comparator 14 to the cache memory control unit 15. Alternatively, a cache miss is determined to determine whether or not there is a cache hit.

If it is determined that there is a cache hit, the computer 10 shifts the processing to step S3, and the one-time lock bit signal OTL supplied from the cache memory 13 to the cache memory control unit 15 is executed.
Based on B, the cache memory control unit 15 reads the value of the one-time lock bit of the corresponding cache line.

Subsequently, the computer 10 determines in step S4 that the value of the read one-time lock bit is "0".
Or not, that is, whether or not the corresponding cache line is not one-time cache locked.

Here, if the value of the one-time lock bit is "1", it means that the corresponding cache line is already one-time cache locked. Therefore, the computer 10 directly performs a series of processes. To finish.

On the other hand, if the value of the one-time lock bit is "0", it means that the corresponding cache line is not one-time cache-locked. The lock bit control signal OTLBC is supplied to the cache memory 13, "1" is added to the one-time lock bit part in the cache line, the cache line is cache locked for one time, and the series of processes is completed.

If the computer 10 determines that there is a cache miss in step S2, the process proceeds to step S5, and the CPU 11 accesses the main storage memory 16. That is, when the issued instruction is a store instruction with one-time cache lock, the computer 10 causes the CPU 11 to access the main memory 16 and write the data DT. Further, when the issued instruction is a load instruction with one-time cache lock, the computer 10 accesses the main memory 16 by the CPU 11 and reads the data DT.

Further, in step S6, the computer 10 accesses the cache memory 13 by the CPU 11 and writes the data DT written in the main memory 16 or the data DT read from the main memory 16 into a new cache line.

Then, in step S7, the computer 10 supplies the one-time lock bit control signal OTLBC to the cache memory 13 and sets the one-time lock bit portion in the cache line in which the data DT is written to "1", as described above. Is added, the cache line is locked for one time, and a series of processing is completed.

By passing through such a series of steps, the computer 10 can lock the cache line for one time in response to the issuance of the instruction with the one-time cache lock.

On the other hand, the computer 10 unlocks the one-time cache-locked cache line by going through a series of steps as shown in FIG. On this occasion,
The computer 10 has a main memory 1 with a cache enabled.
The cache line is unlocked by issuing a normal store instruction or load instruction for accessing 6. That is, the computer 10 starts the following processing when an instruction other than the one-time cache lock instruction is issued.

First, the computer 10, as shown in FIG.
In step S11, the CPU 11 makes an access request to the main memory 16. In other words, the computer 10 generates the virtual address VAD to be accessed by the CPU 11, supplies it to the address conversion unit 12 and the cache memory 13, and when the issued instruction is a normal store instruction, The CPU 11 accesses the main memory 16 and tries to write new data DT. If the issued instruction is a normal load instruction, the computer 10 tries to access the main memory 16 by the CPU 11 and read the data DT.

Subsequently, in step S12, the computer 10 causes the cache memory control unit 15 to cache hit the cache memory 13 based on the hit / miss signal H / M supplied from the comparator 14 to the cache memory control unit 15. Alternatively, a cache miss is determined to determine whether or not there is a cache hit.

If it is determined that there is a cache hit, the computer 10 shifts the processing to step S13, and the one-time lock bit signal OT supplied from the cache memory 13 to the cache memory controller 15
Based on the LB, the cache memory control unit 15 reads the value of the one-time lock bit of the corresponding cache line.

Subsequently, the computer 10 determines in step S14 whether the value of the read one-time lock bit is "1", that is, whether the corresponding cache line is one-time cache locked. Determine whether or not.

Here, if the value of the one-time lock bit is "0", it means that the corresponding cache line is not one-time cache locked. Therefore, the computer 10 directly performs a series of processes. finish.

On the other hand, if the value of the one-time lock bit is "1", it means that the corresponding cache line is one-time cache-locked. The lock bit control signal OTLBC is supplied to the cache memory 13, "0" is added to the one-time lock bit portion in the cache line, the cache line is unlocked, and the series of processes is completed.

If the computer 10 determines that there is a cache miss in step S12, the process proceeds to step S16, and the CPU 11 accesses the main storage memory 16. That is, the computer 10
If the issued instruction is a normal store instruction,
The CPU 11 accesses the main memory 16 and writes the data DT. In addition, the computer 10 executes the CPU 11 when the issued instruction is a normal load instruction.
To access the main memory 16 to read the data DT.

Then, in step S17, the computer 10 accesses the cache memory 13 by the CPU 11 and accesses the data DT written in the main memory 16 or the data DT read from the main memory 16 to the main memory 16. The corresponding cache line associated with the address is written, and the series of processes is completed.

By going through such a series of steps, the computer 10 responds to the issuance of a normal instruction requesting access to the main memory 16 corresponding to the cache line locked by the one-time cache lock. Then, the cache line can be unlocked.

As described above, the computer 10 can guarantee the cache hit at the next access to the same address by locking the cache line using the one-time cache lock instruction. Therefore, the computer 10 saves the contents of the register file by the instruction with the one-time cache lock when performing the context switching operation, for example, without affecting the stochastic element of the operation of the cache memory 13. It is possible to restore the contents of the file. That is, the one-time cache lock mechanism is effective when performing data processing or the like accompanied by temporary saving or restoring processing to the main memory 16.

Now, as an example of specific data processing using such a one-time cache lock mechanism, a case of applying to context switching processing will be described below.

The computer 10 performs a context switching process in which a thread or process is switched by interrupt or scheduling to perform a plurality of data processes at the same time. The computer 10 performs a series of steps as shown in FIG. 6 by the operating system to perform context switching processing using the one-time cache lock mechanism.

That is, the operating system in the computer 10 is, as shown in FIG.
In step S22, when a context switching process occurs, such as when the first process is switched to another second process, in step S22, a one-time cache-locked store instruction is given to the CPU 11, and the process shown in FIG. The series of processing shown is performed, and the contents of the register file relating to the first processing that is currently being performed are saved in the main storage memory 16 as data DT.

Then, in step S23, the operating system identifies at least the saved process such as the process number of the saved process in order to hold the address of the cache line locked by the one-time cache lock, as will be described later in detail. The information about the context consisting of the context identifier of the above and the head address of the saved main memory 16 is registered in the cache lock table managed by the operating system. Further, the operating system can also register the priority of the context, which will be described later, in the cache lock table as the information regarding the context, if necessary.

The cache lock table is shown in FIG.
, For example, n context identifiers I
_{D 1, ID 2, ···,} ID n and these context identifiers _{ID 1, ID 2, ···,} n -number of main memory 16 the contents of the register file is saved corresponding to each ID _n Head address HAD ₁ , HAD ₂ , ...
.., HAD _n and context identifiers ID ₁ , I
D _2, · · ·, priority _{PR 1,} PR 2 of n context corresponding to the respective ID _n, · · ·, it is composed of a PR _n, as shown in the concept in Figure 8, the operating system It is stored in a memory (not shown) that is managed. Actually, the cache lock table is held in the main memory 16.

Subsequently, the operating system sends a normal load instruction to the CPU 11 in step S24.
Then, the series of processing shown in FIG. 5 is performed to restore the contents of the register file regarding the second processing which is the context of the switching destination. At this time, in the computer 10, the cache line in which the restored data that had been locked by the one-time cache was stored is unlocked.

Then, in step S25, the operating system deletes the information regarding the context of the switching destination registered in the cache lock table, and ends the series of processes.

The computer 10 performs such processing each time the context switching processing occurs. Here, the purpose of using the cache lock table described above is as follows.

In the computer 10, if a one-time cache lock mechanism is used when a large number of processes are switched by the context switching process, there is a possibility that all areas of the cache memory 13 are locked. That is, the computer 10 may be in a state equivalent to a state in which the cache memory 13 does not exist. In the computer 10, when such a state occurs, only the main memory 16 can be accessed, the processing efficiency decreases and the overhead increases. Therefore, in the computer 10,
By using the cache lock table and limiting the number of processes for performing the context switching operation, the number of cache lines locked in the cache memory 13 can be limited.

As described above, the computer 10 manages the context switching process using the cache lock table and performs the series of processes described above, thereby reducing the processing efficiency of the context switching process using the one-time cache lock mechanism. Can be done without inviting.

Further, in the computer 10, when a large number of processes are switched by the context switching process using the one-time cache lock mechanism, the performance of the cache memory 13 is deteriorated due to a decrease in the number of unlocked cache lines. To avoid this, when the cache lock table entry becomes full, the one-time cache lock of the cache line that holds the contents of the register file of the context already registered in the cache lock table is released voluntarily. You can also do it. At this time, the computer 10 sets the one-time cache lock to be released, for example, from the context having the lowest priority among the contexts registered in the cache lock table. That is,
The computer 10 sets priorities for the contexts, and determines the target for releasing the one-time cache lock based on the priorities indicating the priorities. Specifically, the computer 10
Performs a series of steps as shown in FIG. 9 by the operating system to release the one-time cache lock.

First, in the computer 10, the operating system refers to the cache lock table and selects the context having the lowest priority in step S31 as shown in FIG.

Subsequently, the operating system unlocks the cache line in which the selected context is held in step S32. That is, the operating system issues a normal store instruction or load instruction to perform the series of processes shown in FIG. 5, and from the top address of the main memory 16 relating to the selected context to this start address. Then, the cache line corresponding to the address of the main memory 16 obtained by adding the size of the context is unlocked.

Then, in step S33, the operating system deletes the information on the context for which the one-time cache lock is released from the cache lock table, and ends the series of processes.

The computer 10 voluntarily unlocks the one-time cache-locked cache line in order to perform a context with a low priority by performing such a series of processing in a system idle time or the like. It is possible to hide the processing overhead due to the reduction in the number of unlocked cache lines.

As described above, the computer 10 is provided with the one-time cache lock mechanism, so that the locked cache line can be unlocked without using the cache unlock instruction, and the operation of the cache memory 13 can be prevented. By eliminating the stochastic element, it is possible to suppress a decrease in data processing speed due to a cache miss. Therefore, the computer 10 is particularly effective when performing data processing that involves temporary saving processing or restoring processing to the main memory 16 such as context switching operation.

Further, the computer 10 uses the main memory 16 as a cache memory area in which the stochastic operation element is excluded by explicitly describing the one-time cache lock instruction in the data processing program. Will also be possible. As a result, the computer 10
Data processing can be performed at high speed.

Furthermore, the computer 10 limits the number of cache lines locked in the cache memory 13 by using the cache lock table, and when the cache lock table entry becomes full, the cache lock table is already stored. By releasing the one-time cache lock of the cache line holding the register file contents of the registered context, it is possible to reduce the processing overhead due to the decrease in the number of unlocked cache lines. .

As described above, the computer 10 reduces variations in processing time, which is important for performing real-time software processing, and is effective for processing that frequently calls data such as a real-time operating system. Further, it can be used in applications and the like, and it is possible to provide high convenience to the user.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, for convenience of description, it is described that the cache line is unlocked by the first cache hit after the cache line is locked for a one-time cache, but the present invention uses multiple cache hits. The cache line may be unlocked.

Further, in the above-mentioned embodiment, the context registered in the cache lock table has been described as one in which the one-time cache lock is released, for example, from the one having the lowest priority. The present invention may unlock a plurality of low-priority contexts at once, or may use a predetermined criterion other than the priority as a criterion for determining a cancellation target.

Further, in the above-described embodiment, the one-time cache lock is released when the cache lock table entry becomes full, but in the present invention, the remaining number of entries in the cache lock table is The one-time cache lock may be released when the number exceeds the predetermined number. That is, in the present invention, the one-time cache lock may be released when the ratio of the cache lines locked in the one-time cache to all the cache lines in the cache memory 13 exceeds a predetermined value.

As described above, it goes without saying that the present invention can be appropriately modified without departing from the spirit of the present invention.

[0085]

As described in detail above, the data processing apparatus according to the present invention is a processor that executes a given instruction, and an access target of this processor, in which data supplied from the processor is written. Between the processor and the main storage memory, the main storage memory from which the data stored by the processor is read, and the data to be written into the main storage memory by the processor and / or the data to be read from the main storage memory by the processor are held. And a cache line that performs writing and / or reading of data to be performed by the processor, and a cache line in which the processor accesses the cache memory and writes and / or reads data based on an instruction given to the processor. And locked cache Depending on the processor to access the in-address, and a control means for unlocking the cache line.

Therefore, the data processing device according to the present invention temporarily locks the cache line under the control of the control means, and thereafter, the processor accesses the address of the main memory corresponding to this cache line. By locking the cache line up to, it is possible to unlock the locked cache line without using the cache unlock instruction,
By eliminating the stochastic element of the operation of the cache memory, it is possible to suppress a decrease in data processing speed due to a cache miss.

Further, the data access method according to the present invention is data which is written and / or read between a processor executing a given instruction and a main memory to be accessed by this processor. A cache memory that holds data to be written to the main memory by the processor and / or data to be read from the main memory by the processor, and that writes and / or reads the data to be performed between the processor and the main memory. A data access method for accessing held data, wherein a processor accesses a cache memory and locks a cache line in which data is written and / or read based on an instruction given to the processor, To the address of the locked cache line Processor in response to access, to unlock the cache line.

Therefore, the data access method according to the present invention temporarily locks the cache line, and thereafter locks the cache line until the processor accesses the address of the main memory corresponding to this cache line. , It becomes possible to unlock the locked cache line without using the cache unlock instruction, eliminate the stochastic element of the operation of the cache memory, and suppress the decrease in data processing speed due to cache miss. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a computer shown as an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a cache memory included in the computer.

FIG. 3 is a diagram illustrating a configuration of a cache line included in the cache memory.

FIG. 4 is a flow chart illustrating a series of processes when a cache line is locked for a one-time cache in the computer.

FIG. 5 is a flow chart illustrating a series of processing when unlocking a cache line locked by one-time cache lock in the computer.

FIG. 6 is a flowchart illustrating a series of processes performed by the operating system when a context switching process using the one-time cache lock mechanism is performed in the computer.

FIG. 7 is a diagram illustrating a configuration of a cache lock table.

FIG. 8 is a diagram conceptually illustrating how a cache lock table is managed by an operating system.

FIG. 9 is a flowchart illustrating a series of processing by the operating system when releasing the one-time cache lock of a cache line that holds the contents of the register file of the context already registered in the cache lock table in the computer. is there.

[Explanation of symbols]

10 computer, 11 CPU, 12 address conversion unit, 13 cache memory, 14 comparator, 1
5 cache memory control unit, 16 main memory

Claims (30)

[Claims] 1. A processor that executes a given instruction, and a main memory that is an access target of the processor and into which data supplied from the processor is written and / or data stored by the processor is read out. And / or writing and / or writing of data to be performed between the processor and the main memory by holding data to be written in the main memory by the processor and / or data to be read from the main memory by the processor.
Alternatively, based on an instruction given to the processor and a cache memory acting on behalf of the read, the processor accesses the cache memory to lock the cache line in which the data is written and / or read, and is locked. A data processing apparatus, comprising: a control unit that unlocks the cache line in response to the processor accessing the address of the cache line. 2. The data processing device according to claim 1, wherein the control means unlocks the cache line by locking the cache line and then performing a predetermined number of cache hits to the address of the cache line. . 3. The data processing apparatus according to claim 2, wherein the control means unlocks the cache line by locking the cache line and then by a first cache hit to an address of the cache line. 4. The instruction is a write instruction with lock that locks the cache line associated with the accessed address of the main memory after writing data to the main memory by the processor. The data processing device according to claim 1, wherein 5. The instruction is a locked read instruction that locks the cache line associated with an accessed address of the main memory after reading data from the main memory by the processor. The data processing device according to claim 1. 6. The control means, when a write command for writing data to the main memory is given to the processor, unlocks the cache line locked by the command. The data processing device according to claim 1. 7. The control means unlocks the cache line locked by the instruction when a read instruction for reading data from the main memory is given to the processor. 1. The data processing device according to 1. 8. The processor is provided with the instruction when saving the contents of a register file in the main memory during a switching process of a plurality of processes, and the control means is provided with the instruction given to the processor. 2. The data processing device according to claim 1, wherein the processor locks a cache line in the cache memory where the processor accesses the cache memory to write and / or read data on the basis of the cache line. 9. The data processing apparatus according to claim 8, wherein the processor is given the instruction when the contents of the register file are saved in the main memory during thread or process switching processing. . 10. A table in which information including at least an identifier for identifying the saved processing and a start address of the main memory in which the contents of the register file corresponding to the identifier is saved is stored. 9. The data processing device according to claim 8, further comprising storage means for performing the processing. 11. The data processing device according to claim 10, wherein the storage means is the main storage memory. 12. The information on the switching destination process registered in the table is deleted from the table when the contents of the register file relating to the switching destination process are restored. Data processing equipment. 13. The control means sets a predetermined criterion among the processes registered in the table when the ratio of locked cache lines to all cache lines in the cache memory exceeds a predetermined value. 11. The data processing device according to claim 10, wherein the cache line holding the contents of the register file relating to the process selected based on is unlocked. 14. The information registered in the table has a priority indicating the priority of the process corresponding to the identifier, and the control means is a register related to the process having the lowest priority as the reference. 14. The data processing device according to claim 13, wherein the cache line holding the contents of the file is unlocked. 15. The data processing apparatus according to claim 13, wherein the information related to the unlocked process registered in the table is deleted from the table. 16. Data to be written and / or read between a processor executing a given instruction and a main memory to be accessed by the processor, the data being written in the main memory by the processor. Data and / or data to be read from the main memory by the processor, and is stored in a cache memory acting on behalf of writing and / or reading of data to be performed between the processor and the main memory. A data access method for accessing data, wherein, based on an instruction given to the processor, the processor accesses the cache memory to lock a cache line in which data is written and / or read, Address of the above cache line locked In response to said processor accesses data access method characterized in that unlock the cache line. 17. The data access method according to claim 16, wherein after the cache line is locked, the cache line is unlocked by a predetermined number of cache hits to the address of the cache line. 18. The data access method according to claim 17, wherein after the cache line is locked, the cache line is unlocked by the first cache hit to the address of the cache line. 19. The instruction is a locked write instruction for locking the cache line associated with an accessed address of the main memory after writing data to the main memory by the processor. The data access method according to claim 16, wherein 20. The instruction is a locked read instruction that locks the cache line associated with an accessed address of the main memory after reading data from the main memory by the processor. The data access method according to claim 16. 21. When a write command for writing data to the main memory is given to the processor, the cache line locked by the command is unlocked. Data access method. 22. The data access according to claim 16, wherein when a read instruction for reading data from the main memory is given to the processor, the cache line locked by the instruction is unlocked. Method. 23. The processor is provided with the instruction when saving the contents of a register file in the main memory during a switching process of a plurality of processes, and the processor is based on the instruction given to the processor. 18. The data access method according to claim 16, further comprising: locking a cache line in the cache memory that has accessed the cache memory to write and / or read data. 24. The data access method according to claim 23, wherein the processor is given the instruction when the contents of the register file are saved in the main memory during a thread or process switching process. . 25. A table is stored in which at least information including an identifier for identifying the saved processing and a head address of the main memory in which the contents of the register file corresponding to the identifier is saved is stored. 24. The data access method according to claim 23, characterized in that the data is stored in the means. 26. The data access method according to claim 25, wherein the main storage memory is used as the storage means. 27. The information regarding the switching destination process registered in the table is deleted from the table when the contents of the register file regarding the switching destination process are restored. Data access method. 28. When the ratio of locked cache lines to all cache lines in the cache memory exceeds a predetermined value, the process registered in the table is selected based on a predetermined criterion. 26. The data access method according to claim 25, wherein the cache line holding the contents of the register file relating to the processing is unlocked. 29. The information registered in the table has a priority indicating the priority of the process corresponding to the identifier, and holds the contents of the register file regarding the process having the lowest priority as the reference. 29. The data access method according to claim 28, wherein the cache line being locked is unlocked. 30. The data access method according to claim 28, wherein the information about the unlocked process registered in the table is deleted from the table.