JP2000353146A - Input/output control device and method for prefetching data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an I/O control device capable of efficiently prefetching data and a method for prefetching data. SOLUTION: The I/O control device is constituted of a data buffer for prefetching data from a main storage device 1 and storing the prefetched data, a prefetch address register 54 for storing a prefetch address in the data buffer, a prefetch count register 60 for storing the transfer length of data to be prefetched at present, a succeeding prefetch address register 51 for storing a prefetch address next to the prefetch address stored in the register 60, and a succeeding prefetch count register 57 for storing count length next to the transfer length stored in the register 60. Since an address to be prefetched next is previously set up, prefetch can be quickly started from the succeeding prefetch address at the time of detecting a page-over state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device and a data prefetching method, and more particularly to an input / output control device for prefetching data from a main storage device in preparation for a DMA / direct memory access transfer. The present invention relates to an output control device and a data prefetch method.

[0002]

2. Description of the Related Art Today, many information processing apparatuses employ a paging method. In the paging method, a physical address space is managed in a page unit, and each page in the physical address space is allocated to a logical address space. Therefore, even when consecutive addresses are accessed in the logical address space, they are not always continuous in the physical address space. For this reason, when accessing across the pages in the main memory access, this event is detected as page over or page over, and various controls are activated using this as an opportunity.

On the other hand, an input / output control device (IOP) connects the main storage device and the input / output device, and controls data transfer between them according to a program for controlling input / output operations called a channel program. . The channel program includes a command, a transfer address, a data length, and the like, and a logical address may be used in the channel program.

[0004] The input / output control device that has received the channel program analyzes the command, converts a logical address to a physical address, and issues a command to a peripheral device. When a data transfer request (transfer from the main storage device to the input / output device) is received from the input / output device (also referred to as a peripheral device), the input / output control device reads data from the designated area of the main storage device and inputs the data. Transfer the data to the output device. As described above, when performing data transfer from the main storage device to the input / output device, the input / output control device transfers data in the main storage device in accordance with a request from the input / output device.

However, if the main storage device is accessed at the time of a data transfer request from the input / output device, the input / output device is made to wait between accesses to the main storage device, and the throughput of the input / output operation is reduced. descend. for that reason,
By pre-reading data that the input / output device will request from the main storage device and storing it in the input / output control device, data prefetching can be performed quickly in response to a data transfer request from the input / output device. Technology is used.
Such a conventional input / output control device is used for the purpose of improving the efficiency of prefetching data when a data chain occurs.

[0006] A channel program is composed of several CCEs (channel command entries).
For example, in Conventional Example 1, one CCE is composed of an address +
One indicated by count + control information and one indicated by a plurality of addresses + count + control information (data chain CC
E). When performing data transfer from a main storage device to a peripheral device, an IOP (input / output processor / input / output processing mechanism) needs to transfer data in the main storage device in response to a request from the peripheral device.

However, if the main storage device is accessed when a data transfer request is issued from the peripheral device, it is necessary to make the peripheral device wait while accessing the main storage device.
Therefore, also in this case, the throughput of the input / output operation is reduced.

[0008] As a prior art example corresponding to this problem,
By reading in advance the main memory data that will be requested by the peripheral device in the IOP and buffering the data in the IOP, the data can be transferred to the peripheral device as soon as there is a data transfer request from the peripheral device. This is a so-called data prefetching method.

FIG. 9 is a block diagram of a data transfer section 10 of the second prior art to which the above-described data prefetching method is applied. The data transfer unit 10 of the conventional example includes a main storage device 1, an input / output control device 20, and a processor 3. The input / output control device 20 is further subdivided into a main memory access control unit 4, a DMA control unit 6 having a main memory read data buffer 61 and a main memory write data buffer 62, and a prefetch control unit 50.

FIG. 10 is a block diagram showing a more detailed configuration example of the prefetch control unit 50 in the second conventional example. FIG.
At 0, the prefetch control unit 50 of the conventional example includes a prefetch address register 54, a prefetch count register 60, selectors 53, 55, 59, 65, an adder 56, and a subtractor 6.
6. It has a data chain detector 67.

In the data transfer section 10 of the second conventional example, the input / output control device 2 existing between the processor 3 and the main storage device 1
Control the data transfer between the network controller and the channel controller.

As a third conventional example similar to the present invention in the technical field, there is an "input / output processing device" disclosed in Japanese Patent Application No. 5-143512. The purpose of the third conventional example is to prefetch the next data transfer address and count by using a microprogram while performing data transfer, to speed up interrupt processing to the microprogram, and to shorten the time during which data transfer is interrupted.

[0013]

However, as described above, if an address specified by a channel program is a logical address and a page is crossed (page over), the physical address beyond that is re-added to the logical address. I do not know unless I calculate. Therefore, when page over occurs, prefetching of data is stopped. And
The stoppage due to page over is notified to the microprogram, and the prefetching is restarted by having the host processor set the next address to prefetch.

In the above conventional example 2, the count specified by the channel program is exhausted, that is, "0", and in the case of a data chain instruction, prefetch cannot be continued unless the next address and count length are set. . Therefore, when the data chain occurs, the prefetching of data is stopped. Further, at the time of stop, there is a problem that it is necessary to notify the microprogram to restart the prefetching and to have the processor set the address and the count length to be prefetched next.

Incidentally, in the input / output processing device of the conventional example 3, a page over / data chain occurs according to the transfer.

An object of the present invention is to provide an input / output control device which makes data prefetching more efficient and a data prefetching method. More specifically, an object of the present invention is to set an address to be prefetched next in advance so that prefetching can be started immediately from the next prefetch address when a page over is detected, or data prefetching when a data chain occurs. To provide an input / output control device and a method for prefetching data of the input / output control device in which the efficiency is improved.

[0017]

According to the present invention, there is provided an input / output control apparatus comprising: a data buffer for prefetching and holding data from a main storage;
A prefetch address register that holds a prefetch address for prefetching in this data buffer, a prefetch count register that holds a transfer length of data to be prefetched at present, and a prefetch address next to the prefetch address held in the prefetch address register. A next prefetch address register to be held;
And a next prefetch count register for holding a count length next to the transfer length stored in the prefetch count register.

The prefetch address held by the prefetch address and the next prefetch address held by the next prefetch address register may be physical addresses.

The above-mentioned input / output control device is preferably installed between predetermined devices to improve the efficiency of data prefetching when a data chain occurs.

Further, the above-mentioned next prefetch address register,
The next prefetch count register, the prefetch address register and the prefetch count register preferably have the number of channel programs that can be activated simultaneously.

Further, the above-mentioned prefetch address register and prefetch count register are constituted by a group of registers.
The input / output control device further includes a selector for selecting input / output of data held by the register group. The input / output control device is connected to a predetermined processor for controlling the operation, and the processor inputs a physical address to the next prefetch address register. The transfer count length is set by the processor in the next prefetch count register, and a flag indicating each valid / invalid and a flag indicating the presence / absence of a data chain instruction are set in the next prefetch count register. Has a flag indicating the validity / invalidity of the selector, and has a flag indicating the validity / invalidity. The prefetch count register has a flag indicating the validity / invalidity of the selector, and a flag indicating the presence / absence of a data chain instruction. Good.

According to a sixth aspect of the present invention, there is provided a data prefetch method for prefetching and holding data from a main storage device, and a prefetch address register step for holding a prefetch address prefetched in the data buffer process. A prefetch count register for holding a transfer length of data to be prefetched, a prefetch address register for holding a prefetch address next to the prefetch address held in the prefetch address register, and a prefetch count register And a next prefetch count register step for holding a count length next to the transfer length to be transferred.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the input / output control device of the present invention will be described in detail with reference to the drawings.

(First Embodiment) Referring to FIG. 1, an information processing system applied to a first embodiment of the present invention includes a processing device 10 connected by a system bus 400.
0 and the main storage device 200. The input / output control device 300 is further connected to the system bus 400. A channel control device 500 is connected to the input / output control device 300,
Under the channel control device 500, an input / output device such as a disk control device 700 for the disk device 800 and a local area network (LAN) processor 900 is connected via a channel card 600. Various other devices such as a magnetic tape and a front-end processor may be applicable to the input / output device.

Therefore, the input / output control device 300 is located between the main storage device 200 and the processing device group, and controls data transfer between them. The control of this data transfer is, for example,
The processing is started by the processing device 100 issuing an input / output instruction, and is realized by the input / output control device 300 executing the channel program held in the main storage device 200.

Referring to FIG. 2, input / output control device 300
Is a data buffer 310, a prefetch management circuit 320,
It includes a data transfer control circuit 330 and a main memory access control circuit 340.

The data buffer 310 includes a read data buffer 311 and a write data buffer 312, and holds read data from the main storage device 200 or write data to the main storage device 200, respectively. The configuration of the data buffer 310 can be basically the same as that of the cache memory. However, since the data held in the data buffer 310 is assumed to be continuous data, it is desirable that the line size be larger than that of a normal cache memory.

The data transfer control circuit 330 executes the channel program held on the main storage device 200,
This is a circuit for controlling data transfer between the main storage device 200 and the input / output device. Specifically, the channel control device 50
In addition to issuing a direct memory access (DMA) transfer instruction to 0, a prefetch address to the read data buffer 311 and a next prefetch address are prepared. This specific operation will be described later.

The main memory access control circuit 340 issues a write request from the data buffer 310 to the main memory 200,
In addition, it arbitrates for a prefetch request from the prefetch management circuit 320, and controls read or write processing to the main storage device 200.

The prefetch management circuit 320 is a circuit for managing a prefetch process for the read data buffer 311. FIG.
, The prefetch management circuit 320 includes a next prefetch address register 321, a prefetch address disk 324, an adder 326, a page over detector 327, and a selector 3
22, 323, and 325.

The prefetch address register 324 holds the physical address of data to be prefetched in the read data buffer 311. Also, the next prefetch address register 321
Holds the physical address of the data to be prefetched in the read data buffer 311 next. A plurality of prefetch address registers 324 and next prefetch address registers 321 can be provided. The number may be, for example, the number of simultaneously executable channel programs or the number of subordinate channel cards 600. In this case, the correspondence with each register needs to be separately managed. In the case of "number of subordinate channel cards 600", it can be managed by a channel number. In the case of “the number of channel programs that can be executed simultaneously”, it can be managed by dynamically assigning an identification number to each channel program.

Each of the prefetch address register 334 and the next prefetch address register 321 has a one-to-one correspondence, and when the use of a certain prefetch address register 324 is finished, the contents of the corresponding next prefetch address register 321 are changed to the prefetch address register 324. Will be held. Further, each of the prefetch address register 324 and the next prefetch address register 321 holds a validity flag in addition to the address itself. If the validity flag indicates "invalid", the corresponding address does not indicate a significant value, and if it indicates "valid", it means that a significant address is held.

The selector 325 is a prefetch address register 3
24 is selected and output. Selector 3
Reference numeral 22 selects and outputs any one of the contents of the next prefetch address register 321. The selector 325 is the selector 32
3, the output of the adder 326, and the processing device 100
Output one of the addresses.

The adder 326 transfers the output of the selector 325, that is, the prefetch address held in one of the prefetch address registers 324, to the main memory 200 sent from the main memory access control circuit 340 to the main memory 200. Add the amount.

The page-over detector 327 includes the adder 32
The occurrence of page over for the prefetched address is detected from the result of addition of 6, and the occurrence of page over is notified to the data transfer control circuit 330 and the processing device 100.

Next, the operation of the above embodiment will be described.

Referring to FIGS. 1 and 4, prior to execution of an input / output instruction, an operating system (OS) operating on the processing device 100 prepares a channel program on the main storage device 200 (step S401). .
When the preparation of the channel program is completed, the operating system issues an input / output command to the input / output control device 300 (step S402). In response to the input / output command, the input / output control device 300 causes the main storage device 200
The upper channel program is read (step S40).
3) Execute (Step S404). When a DMA transfer read instruction is present in the channel program, the input / output control device 300 performs a data transfer process in the following procedure.

Referring to FIGS. 1 to 3 and 5, the data transfer control circuit 330 in the input / output control device 300 issues a DMA transfer command to the channel control device 500 (step S501). The DMA transfer command includes a transfer start address, a transfer data amount, a transfer direction (whether reading from the main storage device 200 or writing to the main storage device 200), and a channel number (channel card 60).
0) is designated. At this time, the data transfer control circuit 330 in the input / output control device 300
If the address related to the DMA transfer request is specified by a virtual address, it is converted to a physical address.
If the transfer direction of the DMA transfer command indicates that “read data from the main storage device is transferred to the I / O device”, then, for example, the subordinate disk device 800 Requesting a transfer.

Prior to receiving a DMA transfer from the subordinate input / output device, the data transfer control circuit 330 prepares a prefetch address in the prefetch address register 324 in the prefetch management circuit 320 (step S502). In particular,
The selector 322 selects a physical address from the data transfer control circuit 330, and sets this physical address in the prefetch address register 324 corresponding to the input / output device (the disk device 800 in the above example). At this time, the validity flag in the prefetch address register 324 is set to “valid”.
Set to state.

When the preparation of the next prefetch address is completed, the data transfer control circuit 330 uses the address held in the prefetch address register 324 to read the data in the read data buffer 31.
In step S503, a prefetch process is started. The contents of the prefetch process will be described later with reference to FIG.

Following the setting of the prefetch address, the data transfer control circuit 330 prepares the next prefetch address in the next prefetch address register 321 in the prefetch management circuit 320 (step S504). Specifically, the physical address from the data transfer control circuit 330 is set in the next prefetch address register 321 corresponding to the input / output device. At this time, the validity flag in the next prefetch address register 321 is set to the “valid” state.

The prefetching process started in step S503 is sequentially performed until the read data buffer 311 becomes full or a page over occurs. When a page over occurs (step S505), the corresponding prefetch address register 324 is invalidated, and the value stored in the corresponding prefetch address register 321 is newly stored in the prefetch address register 324 (step S505). S506). Then, the prefetch processing is started again by the new prefetch address (step S503). The next prefetch address is set in the next prefetch address register 321 (step S504).

Referring to FIGS. 1 to 3 and FIG. 6, the prefetch processing to the read data buffer 311 is performed while the read data buffer 311 has a free space (step S60).
1), which is performed continuously (step S602). If the data buffer 311 is full, the prefetching process is interrupted, and resumes if there is free space. This read data buffer 31
The prefetching to 1 is performed in units of a predetermined data amount. At the time of access for prefetching, the main memory access control circuit 340 selects the selector 325 of the prefetch management circuit 320.
A main memory read request is issued to the main storage device 200 using the prefetch address output from the
The transfer data amount and the channel number related to the read request issued at 00 are output to the prefetch management circuit 320. According to the output channel number, the prefetch address register 324
Is selected by the selector 325, the transfer data amount is added by the adder 326, and the corresponding prefetch address register 324 is updated via the selector 323 (step S603).

As a result of the addition, when occurrence of page over in the prefetching process is detected (step S604),
From the page over detector 327 to the data transfer control circuit 33
It is output that page over has occurred to 0 (step S605). In response to the occurrence of the page-over, the data transfer control circuit 330 moves the value held in the next prefetch address register 321 to the corresponding prefetch address register 324 as described above (step S50).
6).

As described above, according to the embodiment of the present invention, by providing the next prefetch address register 321 for holding the “next prefetch address” following the prefetch address held in the prefetch address register 324, Even if page over occurs during processing, the next prefetch can be continued.

(Second Embodiment) Next, a second embodiment of the input / output control device and its data prefetching method according to the present invention will be described.
The embodiment will be described in detail. Referring to FIGS. 7 and 8, there is shown an embodiment of the input / output control device and the data prefetching method according to the present embodiment.

Referring to FIG. 7, (DMA)
Data) Data transfer unit 10 to which the prefetch control unit 5 is applied
Is shown in FIG.

Referring to FIG. 7, the data transfer unit 10 includes a main storage device 1, an input / output control device 2, and a processor 3. The input / output control device 2 is further subdivided into a main memory access control unit 4, a DMA control unit 6 having a main memory read data buffer 61 and a main memory write data buffer 62, and a prefetch control unit 5. .

In FIG. 7 showing an example of the configuration of the data transfer unit 10, the input / output control unit 2 existing between the processor 3 and the main storage unit 1 transmits the data from the main storage unit 1 to the channel control unit in accordance with an instruction from the processor 3. Controls data transfer between

The processor 3 analyzes the channel program on the main storage device 1 and converts a virtual address into a physical address if the request is a DMA transfer request. The physical address, its count length, the presence or absence of a data chain instruction, and the data A transfer direction (whether data is written to or read from the main storage device 1) and a channel number are instructed to the input / output control device 2. When a notification of the occurrence of a data chain is received from the input / output control device 2, the next prefetch address and its count length are passed to the input / output control device 2.

The input / output control device 2 comprises a prefetch control unit 5, a main memory access control unit 4, and a DMA control unit 6.

When the request from the channel controller is a main memory read, the DMA controller 6 transfers data from the read data buffer of the main memory 1 to the channel controller. When the request from the channel control unit is a main memory write, the data from the channel control unit is written into a write data buffer for the main storage device 1 and a main memory data write request is issued to the main memory access control unit 4. . Further, it notifies the prefetch control unit 5 whether or not there is a free space in the read data buffer.

The prefetch control unit 5 receives the D from the processor 3
When the MA transfer instruction is a data read from the main storage device 1, a data read (prefetch) request from the main storage device 1 is sent to the main storage access control unit 4 based on the physical address and the count length specified by the processor 3. put out. The prefetching stops when the read data buffer of the DMA control unit 6 is full or a data chain is detected and there is no physical address and count length to be read next.

The main memory access control section 4 arbitrates a main memory data write request from the DMA control section 6 and a prefetch request from the prefetch control section 5, and performs a read / write operation to the main storage device 1.

FIG. 8 is a block diagram showing a more detailed configuration example of the prefetch control unit 5 in the embodiment of the present invention.
In FIG. 8, the prefetch control unit 5 of the present embodiment includes a next prefetch address register 51, a prefetch address register 5
4, next prefetch count register 57, prefetch count register 60, selectors 52, 53, 55, 58, 59,
65, adder 56, subtractor 66, data chain detector 67
Is configured.

The next prefetch address register 51 is a group of registers for holding the physical address of the next page of the physical address stored in the prefetch address register 54, and the physical address is set by the processor 3. It also has flags indicating valid / invalid.

The next prefetch count register 57 is a group of registers for holding the count length next to the transfer length stored in the prefetch count register 60, and the transfer count length is set by the processor 3. Further, each flag has a flag indicating validity / invalidity and a flag indicating presence / absence of a data chain instruction.

The prefetch address register 54 is a group of registers for holding a physical address to be prefetched at present, and stores the result of the selection by the selector 53. It also has flags indicating valid / invalid.

The prefetch count register 60 is a group of registers for holding the transfer length to be prefetched at the present time.
9 are stored. Further, each flag has a flag indicating validity / invalidity and a flag indicating presence / absence of a data chain instruction.

The next prefetch address register 51, the next prefetch count register 57, the prefetch address register 54, and the prefetch count register 60 have the number of channel programs that can be started simultaneously. In the present embodiment, a channel program can be started for each channel, and the same number of registers as the number of channels are provided.

The prefetch arbitration unit is a functional unit (not shown) included in the prefetch control unit 5. The prefetch arbitration unit controls write to the next prefetch address register 51, the selector 52,
53, 55 select control, prefetch address register 5
4 is performed. Further, it performs write control to the next prefetch count register 57, select control of the selectors 58, 59, 65, and write control of the prefetch count register 60. Further, a data chain detection signal from the data chain detector is received.

The preemption arbitration unit sends the next prefetch address register 51 and the next prefetch count register 5 from the processor 3.
7. A setting instruction of the prefetch address register 54 and the prefetch count register 60, and a signal from the DMA control unit 6 indicating whether or not the main memory read data buffer 61 has a free space.

The prefetch arbitration unit determines which channel's prefetch address is valid from the valid / invalid flags of the prefetch address register 54, the prefetch count register 60, the next prefetch address register 51, and the next prefetch count register 57. Furthermore, if prefetching is necessary for a plurality of channels, arbitration is performed and a prefetch request is made to the main memory access control unit 4.

The selectors 52 and 58 select the next prefetch address register 51 and the next prefetch count register 57 based on the control signal (channel number) from the prefetch arbitration unit.

The selectors 53 and 59 select and output the output from the adder / subtractor, the prefetch address register 54 or the next prefetch count register 57 specified by the processor 3 in accordance with an instruction from the prefetch arbitration unit.

The selectors 55 and 65 select the prefetch address register 54 or the prefetch count register 60 based on the control signal (channel number) from the prefetch arbitration unit.

The adder 56 adds the data transfer amount to the main memory 1 sent from the main memory access controller 4 to the prefetch address.

The subtractor 66 subtracts the data transfer amount sent from the main memory access control unit 4 to the main memory 1 to the prefetch count.

The data chain detector 67 determines that the result of subtracting the data transfer amount to the main storage device 1 from the prefetch count is “0”.
And when there is a data chain instruction in the prefetch count register, the data chain is detected. When the data chain occurs, the occurrence is notified to the prefetch arbitration unit and also notified to the processor 3.

An operation example of the embodiment will be described with reference to FIG. If the result of analyzing the channel program is a main storage read DMA transfer, the processor 3 sends the channel number and the physical address of the main storage device 1 to the prefetch control unit 5.
The transfer length and the presence or absence of a data chain are notified, and writing to the prefetch address register 54 and the prefetch count register 60 is instructed. In the case of data chain instruction,
Notify the prefetch control unit 5 of the channel number and the physical address of the next main storage device 1, the transfer length, and the presence or absence of a data chain,
Writing to the next prefetch address register 51 and the next prefetch count register 57 is also instructed.

When the prefetch arbitration unit receives a write instruction from the processor 3 to the prefetch address register 54, the prefetch arbitration unit causes the selector 53 to select the physical address sent from the processor 3, and the channel number sent from the processor 3 Is selected from the prefetch address register 54 corresponding to the prefetch address register 54, the physical address is written, and the valid display of the prefetch address register corresponding to the channel number sent from the processor 3 is performed.

When receiving a write instruction from the processor 3 to the next prefetch address register 51, the prefetch address validity display corresponding to the channel number sent from the processor 3 is referred to. One of 51 is selected, the physical address is written, and the next prefetch address register valid display corresponding to the channel number sent from the processor 3 is performed.

On the other hand, if the address is invalid, the selector 53 selects the physical address sent from the processor 3 and selects one of the prefetch address registers 54 corresponding to the channel number sent from the processor 3. At the same time, a physical address is written and a prefetch address register valid display corresponding to the channel number sent from the processor 3 is performed.

Similarly, when the prefetch arbitration unit receives a write instruction to the prefetch count register 60 with respect to counting, it causes the selector 59 to select the count length sent from the processor 3, and receives the count length sent from the processor 3. Count register 6 corresponding to the channel number
Select one from 0 and write the count length. At the same time, the valid display of the prefetch count register 60 corresponding to the channel number sent from the processor 3 is performed.

When a data chain instruction is involved, the data chain display in the prefetch count register 60 is set to "with data chain". When the processor 3 receives a write instruction from the processor 3 to the next prefetch count register 57, it refers to the prefetch count validity display corresponding to the channel number sent from the processor 3, and if it is valid, stores 1 in the next prefetch count register 57. One is selected, the count length is written, and the next prefetch count register valid display corresponding to the channel number sent from the processor 3 is performed.

When a data chain instruction is accompanied, the data chain display in the next prefetch count register 57 is set to "with data chain". Conversely, if the prefetch count valid display is invalid, the selector 59 is caused to select the count length sent from the processor 3 and one of the prefetch count registers 60 corresponding to the channel number sent from the processor 3 is selected. Is selected, the count length is written, and a prefetch count register valid display corresponding to the channel number sent from the processor 3 is performed. If a data chain is involved, the data chain display in the prefetch count register 60 is set to "with data chain".

The prefetch arbitration unit selects one of the channels if both the prefetch address register 54 and the prefetch count register 60 indicate valid display, and sends the channel number to the main memory access control unit 4. At the same time, a main memory read request is issued. However, when the main memory read data buffer 61 of the DMA control unit 6 is full and there is no room for writing, the main memory read request to the main memory access control unit 4 is suppressed.

When the main memory access control unit 4 receives the main memory read request from the prefetch arbitration unit, it selects the selector 55 using the channel number passed from the prefetch arbitration unit, reads the prefetch address, and sends the main memory read request to the main memory. Apparatus 1
The transfer amount and the channel number of the read request sent to the main storage device 1 and the channel number are sent to the prefetch control unit 5, and the result of adding the prefetch address and the transfer amount is instructed to be written into the prefetch address register 54 according to the channel number. .

Similarly, the selector 65 is selected by the channel number, the prefetch count is read, and the result of subtracting the prefetch count and the transfer amount is written to the prefetch count register 60 according to the channel number.

The data chain detecting section 62 detects "0" as a result of subtraction of the prefetch count and the transfer amount, and detects the data chain if the data chain in the prefetch count register is valid. The chain detection is reported to the preemption arbitration unit, and the data chain detection is reported to the processor 3 together with the channel number.

The prefetch arbitration unit notified of the data chain detection invalidates the prefetch address register and the prefetch count valid display corresponding to the channel number in which the data chain was detected, and the next prefetch corresponding to the channel in which the data chain was detected. The valid display of the address register 51 and the next prefetch count register 57 is searched.

If both the next prefetch address register 51 and the next prefetch count register 57 are valid, the selector 52 and the selector 58 are selected by the channel on which the data chain has been detected, and the next prefetch address register 51 is stored in the selector 53. And the selector 58 selects the next prefetch count register 57.

The value of the next prefetch address register 51 is loaded into the prefetch address register 54 corresponding to the channel in which the data chain has been detected, and the value of the next prefetch count register 57 is similarly stored in the prefetch count register 60 including the data chain display. To load. At the same time, the valid display of the prefetch address register 54 and the prefetch count register 60 is made valid.

Processor 3 reported data chain detection
If the next address and count are necessary for the transfer to the reported channel control unit, the prefetch control unit 5 is notified of the channel number, the physical address of the main storage device 1, the count length, and the presence or absence of a data chain. Instructs writing to the address register 51 and the next prefetch count register 57.

(Modification) In the above embodiment, the prefetch address register 54, the prefetch address register valid display bit, the next prefetch address register 51, and the next prefetch address register valid display bit correspond to the channels. However, it makes sense to have the number (n) of channel programs that can be activated at the same time. Therefore, even if the channel program is not supported, the numbers 1 to n are assigned when the channel program is activated, and the register and the valid display bit are assigned by that number. You may choose.

According to the above embodiment, an address to be prefetched and its count length, and an address to be prefetched next and its count length can be set in the data prefetch mechanism in the input / output control device. Thus, upon detecting a data chain (the count length is “0” and a data chain instruction is present), prefetching can be immediately started according to the next channel program entry.

In FIG. 8, prefetch address register 5
The read operation from the main storage device 1 is performed at the address stored in the main storage device 4. The prefetch address register 54 and the count length are updated in accordance with the amount of data read from the main storage device 1. When a data chain occurs, values are loaded from the next prefetch address register 51 and the count length and prefetching is continued. At the same time, the microprogram is requested to set the next prefetch address and the count length. The microprogram performs address conversion to set the next prefetch address and the count length.

Therefore, by setting the address to be prefetched next and the count length in the register in advance in the register, prefetching can be started from the next prefetched address when a page over is detected, thereby improving the throughput of the input / output operation. Can be achieved.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0090]

As apparent from the above description, the input / output control device and the data prefetching method of the present invention hold a physical address to be prefetched, hold a transfer length to be prefetched, and hold. The physical address of the page next to the stored physical address is held, and the count length next to the stored transfer length is held. Thus, when a data chain occurs, prefetching can be performed efficiently by loading the next address and continuing prefetching.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an information processing system to which the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of an input / output control device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a prefetch management circuit in the first embodiment of the input / output control device of the present invention.

FIG. 4 is a diagram illustrating an operation of an input / output instruction issuance process according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating an operation of a data transfer process according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation of a prefetch process according to the first embodiment of the present invention;

FIG. 7 is a block diagram showing a data transfer unit to which an input / output control device according to a second embodiment of the present invention is applied;

FIG. 8 is a block diagram illustrating a more detailed configuration example of a prefetch control unit according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a data transfer unit according to a conventional example.

FIG. 10 is a block diagram showing a more detailed configuration example of a prefetch control unit in a conventional example.

[Explanation of symbols]

 1, 200 main storage device 2, 300 input / output control device 3 processor 4 main storage access control unit 5 prefetch control unit 6 DMA control unit 10 data transfer unit 51 secondary prefetch address register 52, 53, 55, 58, 59, 65 selector 54 Prefetch address register 56 Adder 57 Next prefetch count register 60 Prefetch count register 61 Main storage read data buffer 62 Main storage write data buffer 66 Subtractor 67 Data chain detector 100 Processing unit 400 System bus 500 Channel control unit 800 Channel card 700 Disk control device 800 Disk device 900 LAN processor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/08 G06F 12/08 X G 13/12 340 13/12 340D F-term (Reference) 5B005 JJ12 KK15 LL11 MM23 NN01 NN43 5B013 AA20 5B014 EA03 GC22 GC23 GD24 5B033 AA04 BC06 DB06 DC02 5B061 BA03 DD01 DD06 DD09 DD11 PP01

Claims (6)

[Claims] 1. A data buffer for prefetching and holding data from a main storage device, a prefetch address register for holding a prefetch address for prefetching data in the data buffer, and a transfer length of data to be prefetched at present. A prefetch count register; a next prefetch address register that holds a prefetch address next to the prefetch address held in the prefetch address register; and a next prefetch count that holds a count length next to the transfer length stored in the prefetch count register. An input / output control device, comprising: a register; 2. The input / output control device according to claim 1, wherein the prefetch address held by the prefetch address and the next prefetch address held by the next prefetch address register are physical addresses. 3. The input / output control device according to claim 2, wherein the input / output control device is installed between predetermined devices, and the efficiency of data prefetching can be improved when the data chain occurs. . 4. The prefetch address register, the next prefetch count register, the prefetch address register, and the prefetch count register have the number of channel programs that can be activated at the same time. 2. The input / output control device according to item 1. 5. The prefetch address register and the prefetch count register are constituted by a group of registers, and the input / output control device further includes a selector for selecting input / output of data held by the group of registers. The device is connected to a predetermined processor for controlling the operation, has a physical address set in the next prefetch address register by the processor and has a flag indicating valid / invalid, and a transfer count length by the processor to the next prefetch count register. Is set, a flag indicating each valid / invalid state and a flag indicating the presence / absence of a data chain instruction are stored. The select result of the selector is stored in the prefetch address register, and a flag indicating each valid / invalid state is provided. The selection result of the selector is stored in the count register. The input / output control device according to any one of claims 2 to 4, wherein the input / output control device has a flag indicating the validity / invalidity and a flag indicating presence / absence of a data chain instruction. 6. A data buffer process for prefetching and holding data from a main storage device, a prefetch address register process for holding a prefetch address prefetched in the data buffer process, and holding a transfer length of data to be prefetched at present. A prefetch count register step, a next prefetch address register step of holding a prefetch address next to the prefetch address held in the prefetch address register step, and a next count length of the transfer length stored in the prefetch count register step. A prefetching method for data, comprising: holding a next prefetching count register.