JP2003022616A - Data reproducing circuit for disk reproducer, and data reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data reproducing circuit for disk reproducer, which promptly and easily demodulate target data when failing in the detection of a target ID sink and a data sink, and to provide a method for reproducing the data. SOLUTION: The data reproducing circuit 10 demodulates a bit steam Bs by using a decoder 1. In parallel, a serial/parallel conversion device 7 converts the bit steam Bs into a sample signal SMP. A memory control part 2 stores the sample signal SMP into a RAM 3. When the decoder 1 fails in the detection of the target data sink and carries out retry, an N bit shifter 8 inputs the sample signal SMP on the RAM 3 into the decoder 1 by shifting it by only a prescribed number of bits. The decoder 1 demodulates the target data from the sample signal SMP on the RAM 3.

Description

Detailed Description of the Invention

[0001]

The present invention relates to reproducing data from a disk-shaped recording medium such as a flexible disk (FD), hard disk (HD), optical disk (CD, DVD), and magneto-optical disk (MO). Disc reproducing apparatus. In particular, the present invention relates to a data reproducing circuit for converting a serial signal read from a disc-shaped recording medium into a parallel signal, arranging the parallel signal in a memory, and detecting and correcting a code error of the parallel signal.

[0002]

2. Description of the Related Art A conventional disk reproducing apparatus is, for example, an F
D drive (FDD), HD drive (HDD), CD-R
Personal computer (PC) peripheral equipment such as OM drive, DVD-ROM drive and MO drive, and audio / audio equipment such as CD player and DVD player
Includes video (AV) equipment. In those disc reproducing apparatuses, first, the head reproduces a serial signal from the disc-shaped recording medium. Further, the data reproducing circuit converts the serial signal into a parallel signal and demodulates the parallel signal into original data. Demodulated data generally contains code errors. The data reproduction circuit detects and corrects a code error in the data. On top of that, data without code error,
Also, the data whose code error has been corrected is transferred to the host. Here, the host corresponds to, for example, a PC, a display, and a speaker.

The data reproduction circuit uses a FM (Frequency Modulat) as a data demodulation method in, for example, FD and HD.
ion), MFM (Modified FM), and 1-7 RLL (Run
Length Limited) Modulation and demodulation methods, etc.
The modulation / demodulation method and the 8-16 modulation / demodulation method are adopted respectively. The data reproduction circuit uses an error correction method, for example,
Reed-Solomon code is used. The error correction method using the Reed-Solomon code has good correction efficiency and correction capability, and further, various code lengths can be selected. At the time of error correction by the Reed-Solomon code, the data reproducing circuit reads the data read from the disk-shaped recording medium into the SRAM.
And a predetermined format on a memory such as a DRAM.

A conventional data reproducing circuit will be briefly described below. As a conventional data reproducing circuit, for example,
The one disclosed in Japanese Patent Laid-Open No. 4-89665 is known. FIG. 20 is a block diagram of a conventional disc reproducing apparatus. The reading unit R includes a head Hd. The head Hd reproduces data as an analog signal from a disk-shaped recording medium (hereinafter referred to as a disk) D. The reading unit R performs analog / digital conversion on the analog signal and outputs it as a bit stream Bs which is a serial digital signal.
Further, the reading unit R generates the read clock RCK with substantially the same frequency as the bit stream Bs. The phase of the read clock RCK is adjusted by, for example, a PLL so as to be synchronized with the bit stream Bs.

The data reproduction circuit 100 uses the bit stream Bs
Are demodulated and transferred to the host Hs as follows: First, the decoder 101 inputs the bit stream Bs in synchronization with the read clock RCK. Decoder 101 is a bitstream Bs
Target data from among the error correction code (parity code)
It is also extracted and converted into a parallel signal for demodulation. The memory control unit 2 uses the data demodulated by the decoder 101 as R
Arrange on AM3. The error detection unit 4B detects a code error in the data output from the decoder 101. When the error detection unit 4B detects a code error in the data, the memory control unit 2 causes the RA
The array on M3 is output to the error correction unit 5. The error correction unit 5 corrects the code error of the data based on the input array.
The memory control unit 2 rearranges the error-corrected data on the RAM 3 again. After the above processing, the memory control unit 2
The data arranged above is output to the host interface 6. The host interface 6 transfers the input data to the host Hs.

<Physical Format of Disc D> FIG. 1 is a schematic diagram showing a track T recorded on the disc D.
On the disc D, there are multiple tracks T and the center C of the disc D.
Are recorded concentrically around. Each track T is a positive integer N sectors S1, S2, ..., S (N−1), SN,
It is divided into N gaps G1, G2, ..., G (N−1), GN, alternately. Each sector is an area for recording the same amount of data, and has the same length. That is, data is recorded in the sector at a constant linear recording density. The number of sectors per track T is N tracks
Different for each T. The head of the first sector S1 on each track T is set on a predetermined radius O of the disk D.
The head of the disk reproducing device reads data one sector at a time. The gap is an area for distinguishing adjacent sectors on one track T. A specific code is recorded on the gap to distinguish it from the data. 1st gap G1 to (N-1) th gap G
It has the same length up to (N-1). On the other hand, the Nth gap G
N has a different length for each track T.

FIG. 2 is a diagram showing a physical format of one track T on the disc D. Figure 2 (a) shows a truck T
Shows the overall physical format. FIG. 2B shows the physical format of each sector. As shown in FIG. 2B, each sector includes an ID field Id, a pad P, and a data field Da in order from the beginning. I
The D field Id is an area in which sector identification information is recorded. The data field Da is an area in which data is recorded. Pad P has ID field Id and data field Da
This is an area for distinguishing between and. The ID field Id and the data field Da include an ID sync Id2 and a data sync Da2 as respective synchronization signals, next to the respective preambles Id1 and Da1. That is, the physical format of the disk D includes two sync signals per sector, namely, ID sync Id2 and data sync Da2.

<Demodulation of Data by Decoder> FIG. 21 is a block diagram of the decoder 101 in the conventional data reproducing circuit 100. The decoder 101 extracts and demodulates target data as follows based on the physical formats shown in FIGS. 1 and 2. The preamble detection unit 11A detects the head preamble Id1 of the ID field Id from the bitstream Bs. When the detection of the preamble Id1 is successful, the preamble detection unit 11A outputs the activation signal Wi to the ID sync detection unit 12A. The activation signal Wi is an on / off binary signal. This activation signal Wi is called an ID sync detection window. When the ID sync detection window Wi is on, I
The D sync detector 12A operates. On the other hand, when the ID sync detection window Wi is off, the ID sync detection unit 12A stops. When the preamble detection unit 11A succeeds in detecting the preamble Id1 of the ID field Id, the preamble detection window 11A detects the ID sync detection window W
Turn on i for a predetermined time.

The ID sync detector 12A has an ID sync detection window W
The ID sync Id2 is detected only during the ON period of i. Thereby, the probability of false detection of the ID sync Id2 is reduced.
When the ID sync detector 12A succeeds in detecting the ID sync Id2, it outputs the ID sync detection signal SYi to the serial / parallel converter 14 and the sector coincidence detector 16B. Cereal/
The parallel conversion unit 14 is activated by the ID sync detection signal SYi, and converts the bit stream (serial signal) Bs input to the decoder 101 subsequently to the detected ID sync Id2 into the parallel signal Bp0 for a predetermined time. Where parallel signal B
p0 is, for example, 8 bits (=
1 byte each) is parallelized. The demodulation unit 15 demodulates the sector identification information (ID) Id3 in the ID field Id from the parallel signal Bp0.

The sector coincidence detector 16B is activated by the ID sync detection signal SYi and detects a code error in the demodulated IDId3. Further, when no code error is detected, the sector specified by the demodulated IDId3 is compared with the target sector 17. In the comparison, the sector number in IDId3 is generally used. When a match between the sector identified by IDId3 and the target sector 17 is detected, the sector match detection unit 16
B is the first load signal to the data sync down counter 18B
Output Td. As a result, the count value of the data sync down counter 18B becomes the data sync input estimated time ΔT0.
Is preset to. Here, the data sync input prediction time ΔT0 is shorter than the prediction time from the output of the first load signal Td by the sector coincidence detection unit 16B to the input of the data sync Da2 of the target sector 17 to the decoder 101 by a predetermined length. It's time. The data sync input predicted time ΔT0 is represented by, for example, the number of clocks of a write clock WCK described later.
The sector coincidence detection unit 16B determines the data sync input prediction time ΔT0.
Is determined based on the above physical format.

The data sync down counter 18B is a down counter and decrements the count value by 1 bit at each rising edge of each pulse of the write clock WCK. Here, the write clock WCK is, for example, by a synthesizer,
It is generated independently of the read clock RCK. The frequency of the write clock WCK is equal to the frequency of the operation clock when writing data to the disk D, and the track T
It is kept constant every time. The write clock WCK is generated so as to be synchronized with the bit stream Bs with reference to the time when the ID sync Id2 is successfully detected, for example. Furthermore,
The data sync down counter 18B outputs a start signal Wd to the data sync detector 13A when the count value reaches 0. The activation signal Wd is an on / off binary signal. This activation signal Wd is called a data sync detection window. When the data sync detection window Wd is on, the data sync detection unit
13A works. On the other hand, when the data sync detection window Wd is off, the data sync detection unit 13A stops. The data sync down counter 18 turns on the data sync detection window Wd for a predetermined number of clocks.

The data sync detector 13A detects the data sync Da2 only during the ON period of the data sync detection window Wd. As a result, the probability of false detection of the data sync Da2 is reduced. The data sync detector 13A has a data sync D
When the detection of a2 is successful, the data sync detection signal SYd is output to the serial / parallel conversion unit 14. The serial / parallel converter 14 is activated by the data sync detection signal SYd, and converts the bit stream Bs input following the data sync Da2 into the parallel signal Bp0 by a predetermined number of bits. The demodulation unit 15 demodulates the data Da3 in the data field Da from the parallel signal Bp0. Further, by the above serial / parallel conversion, the memory control unit 2 arranges the demodulated data Da3 on the RAM3 one word (one byte, for example).

FIG. 22 shows a bit stream Bs input to the decoder 101 during reproduction by the conventional data reproducing circuit 100.
It is a timing chart of ID sync detection window Wi, ID sync detection signal SYi, first load signal Td, data sync detection window Wd, and data sync detection signal SYd. The bit stream Bs in FIG. 22 corresponds to the serial signal read from the positive integer kth sector Sk, the kth gap Gk, and the (k + 1) th sector S (k + 1).

First, the target sector is set to the kth sector Sk. The preamble detection unit 11A detects the preamble Id1 of the ID field of the kth sector Sk. When the detection of the preamble Id1 is successful, the preamble detection unit 11A turns on the ID sync detection window Wi. The ID sync detector 12A detects the ID sync Id2 of the kth sector Sk during the ON period of the ID sync detection window Wi. The ID sink Id2
When the ID sync detection section 12A succeeds in detecting the ID sync detection signal SYi, the ID sync detection section 12A outputs the ID sync detection signal SYi. As a result, the serial / parallel conversion unit 14 and the sector coincidence detection unit 16B are activated, and the IDId3 of the kth sector Sk is demodulated. The sector coincidence detection unit 16B compares the sector numbers of the sector specified by IDId3 and the target sector. Since both sector numbers belong to the kth sector Sk, the sector coincidence detection unit 16B outputs the first load signal Td. Then I
The time Δt from the output of the D-sync detection signal SYi to the output of the first load signal Td is substantially constant. The data sync down counter 18B shows the estimated data sync input time ΔT0
The count value is reduced in synchronization with the write clock WCK from the completion of preset of. When the count value reaches 0, the data sync down counter 18B turns on the data sync detection window Wd. The data sync detection unit 13A has a data sync detection window W
The data sync Da2 of the kth sector Sk is detected during the on period of d. When the data sync Da2 is successfully detected,
The data sync detection unit 13A outputs a data sync detection signal SYd. As a result, the serial / parallel conversion unit 14 is activated, and the data Da3 and parity code of the kth sector Sk
Da4 is demodulated.

Thus, the decoder 101 has the kth sector Sk
With regard to (3), both the ID sync Id2 and the data sync Da2 are successfully detected, and the data Da3 and the parity code Da4 are demodulated. Next, the target sector is the (k + 1) th sector S (k + 1)
Is set, and the process from the detection of the preamble Id1 to the turning on of the data sync detection window Wd is performed in the same manner as above. In the example shown in FIG. 22, the data sync Da2 of the (k + 1) th sector S (k + 1) is missing from the bitstream Bs. Causes of loss of the data sink Da2 include data loss due to scratches and magnetic deterioration on the disk D, or a read error of the head Hd due to vibration and shock. Thus, when the data sync Da2 is lost, the data sync detection unit 13A cannot detect the data sync Da2. In that case,
The decoder 101 uses the data Da3 of the (k + 1) th sector S (k + 1)
The demodulation of is tried as follows.

When the data sync detection unit 13A cannot detect the data sync Da2 during the ON period of the data sync detection window Wd, the decoder 101 selects the next target sector as the sector including the data sync Da2, that is, (k + 1). ) Th sector S (k + 1). Further, the disc reproducing apparatus temporarily stops the reproducing operation of the data reproducing circuit 100 and rotates the disc D once. Thereby, the data reproducing circuit 100 tries again to reproduce the data from the target sector. This replay operation is called a retry.

FIG. 23 is a timing chart of the same signals as in FIG. 22 during the above-mentioned retry. At the time of retry, the operation from the preamble detection unit 11A to the sector coincidence detection unit 16B is the same as that before the above retry. Regarding the k-th sector Sk, the sector number is different between IDId3 and the target sector.
Therefore, the sector coincidence detection unit 16B outputs neither the first load signal Td nor the second load signal Tp. On the other hand, (k
For the (+1) th sector S (k + 1), the sector number is the same in IDId3 and the target sector. Therefore, the sector coincidence detection unit 16B detects the coincidence of the sector numbers of IDId3 and the target sector, and outputs both the first load signal Td and the second load signal Tp at the same time. As a result, the count value of the data sync down counter 18B is preset to the data sync input predicted time ΔT0, and the count value of the pseudo data sync down counter 19B is preset to the pseudo data sync generation time ΔT1. Here, the pseudo data sync Sp is a signal for instructing the data sync detection unit 13A to output the data sync detection signal SYd regardless of the detection of the data sync Da2. The pseudo data sync generation time ΔT1 is calculated from the output of the second load signal Tp by the sector coincidence detection unit 16B,
It is the estimated time until the target data sink Da2 is input to the decoder 101. In the example shown in FIG. 23, the target data sync Da2 corresponds to that of the (k + 1) th sector S (k + 1). That is, the pseudo data sync generation time ΔT1 is longer than the data sync input prediction time ΔT0 and shorter than the data sync input prediction time ΔT0 plus the ON period of the data sync detection window Wd. The pseudo data sync generation time ΔT1 is the same as the data sync input prediction time ΔT0, and the write clock WC
Expressed in K clocks. The sector coincidence detection unit 16B determines the pseudo data sync generation time ΔT1 based on the above physical format.

The data sync down counter 18B starts counting the data sync input prediction time ΔT0 from the completion of presetting of the data sync input prediction time ΔT0. At the end of the count, the data sync down counter 18B turns on the data sync detection window Wd. The pseudo data sync down counter 19B is at the same time as the data sync down counter 18B.
Start counting the pseudo data sync generation time ΔT1. The count by the pseudo data sync down counter 19B is the same as that of the data sync down counter 18B. When the data sync detector 13A does not detect the data sync Da2 by the end of the counting of the pseudo data sync down counter 19B, the pseudo data sync down counter 19B outputs the pseudo data sync Sp. As a result, the data sync detector
13A outputs the data sync detection signal SYd in the same manner as when detecting the data sync Da2.

The serial / parallel converter 14 converts the bit stream Bs into a parallel signal Bp0 for a predetermined time after the input of the data sync detection signal SYd. The demodulation unit 15 regards the parallel signal Bp0 as the data Da3 and the parity code Da4 and demodulates it. The error detector 4B detects a code error in the demodulated parallel signal Bp. Further, the error correction unit 5 attempts to correct the code error. When the code error is not detected and can be corrected, the demodulated parallel signal Bp is (k +
1) Data Da3 and parity code of the 1st sector S (k + 1)
It can be regarded as equivalent to Da4. Therefore, the host interface 6 transfers the demodulated parallel signal Bp to the host Hs. On the other hand, when the error detection unit 4B detects a large number of code errors that cannot be corrected, and when the error correction unit 5 fails to correct the code errors, the disk reproducing device retries again and repeats the above reproducing operation. .

In this way, the decoder 101 has the ID sync Id2
Of the sector S (k + 1) for which the detection of the data sync Da2 has succeeded and the detection of the data sync Da2 has failed, the data Da3 and the parity code Da4 are demodulated. Further, when the decoder 101 fails to detect the ID sync Id2 of the target sector, it attempts to demodulate the data Da3 and the parity code Da4 of the target sector as follows.

In the example described below, the (k + 1) th sector
The ID sync Id2 of S (k + 1) is missing from the bitstream Bs. The cause of losing the ID sync Id2 is a loss of data due to scratches on the disk D and magnetic deterioration, or a read error of the head Hd due to vibration and shock. In this way, when the ID sync Id2 is lost, the ID sync detection unit 12A cannot detect the ID sync Id2. In that case, the conventional disc reproducing apparatus determines the target sector under the following conditions: 1) The target sector is located before the sector in which the ID sync Id2 has failed to be detected, preferably one before. 2) The target sector contains a detectable ID sync Id2. In the following example, the k-th sector Sk is set as the target sector.

Next, the conventional data reproducing circuit temporarily stops the reproducing operation of the data reproducing circuit 100 and retries the target sector. FIG. 24 is a timing chart of the same signals as in FIG. 22 during the retry. At the time of retry, the operation from the preamble detection unit 11A to the sector coincidence detection unit 16B is the same as that before the above retry. In particular, the kth sector Sk
As for the sector match detection unit 16B, the sector number match between IDId3 and the target sector is detected. At that time, the sector coincidence detection unit 16B outputs the first load signal Td. However, unlike before the retry, the data sync down counter 18B
The count value of is preset to the target data sync input predicted time ΔT2. Here, the target data sync input predicted time ΔT2 is from the output of the first load signal Td by the sector coincidence detection unit 16B to the input to the decoder 101 of the data sync Da2 of the (k + 1) th sector S (k + 1). Is the estimated time. The target data sync input prediction time ΔT2 is represented by the number of write clocks WCK, like the data sync input prediction time ΔT0. The sector coincidence detection unit 16B determines the target data sync input prediction time ΔT2 based on the above physical format.

The data sync down counter 18B starts counting from the completion of presetting of the target data sync input predicted time ΔT2. At the end of the count, the data sync down counter 18B turns on the data sync detection window Wd.
The data sync detector 13A detects the data sync Da2 of the (k + 1) th sector S (k + 1) during the ON period of the data sync detection window Wd.
To detect. When the data sync Da2 is successfully detected, the data sync detection unit 13A outputs the data sync detection signal SYd. Data Da3 of the (k + 1) th sector S (k + 1) after that
Is demodulated in the same manner as before the retry.

[0024]

The bit stream Bs actually output by the reading section R of the disc reproducing apparatus.
The pulse waveform of changes from the ideal shape due to the following reasons. Causes thereof include, for example, data loss due to scratches and dirt on the surface of the disk D, magnetic deterioration, etc., and head read error due to vibration and shock during reproduction. When the pulse waveform of the bit stream Bs greatly changes from the ideal shape, the PLL in the reading unit R unlocks. As a result, the phase and frequency of the read clock RCK change greatly.

The frequency of the write clock WCK is more stable than that of the read clock RCK. Therefore, the data sync down counter 18B and the pseudo data sync down counter 19B count in synchronization with the write clock WCK as described above. As a result, each down counter
Counting is more stable and accurate than counting in synchronization with the read clock RCK. But write clock WC
Counts synchronized with K also generally include an error. Because,
The synchronization between the write clock WCK and the bit stream Bs
This is because, for example, it is indirectly performed based on the time when the ID sync Id2 is detected. Further, in the above physical format, the length of the pad P is slightly different depending on the drive in which the data is recorded on the disc D. As a result, the counts above include errors.

When the count of the pseudo data sync generation time ΔT1 by the pseudo data sync down counter 19B includes an error to some extent, the generation of the pseudo data sync Sp is difficult to synchronize with the input of the target data sync. Therefore, the decoder
101 is likely to fail in demodulating target data. Therefore, the conventional disc reproducing apparatus cannot reduce the number of retries.

Since the target data sync input prediction time ΔT2 is longer than the normal data sync input prediction time ΔT0,
The above error is largely included. Therefore, at the time of retry, the input of the target data sync is likely to deviate from the ON period of the data sync detection window Wd. At that time, the decoder 101 cannot demodulate the target data. Therefore, the conventional disc reproducing apparatus cannot reduce the number of retries. As a result, the conventional disc reproducing apparatus cannot reduce the reproducing time of the data from the disc D and the waiting time of the host Hs.

Further, the physical format of the disk D is shown in FIG.
As shown in, the length of the Nth gap GN is different for each track T. Therefore, when the data of the first sector S1 is demodulated as described above using the ID sync of the Nth sector SN, the target data sync input prediction time ΔT2
Is different for each track T. Therefore, the calculation of the target data sync input predicted time ΔT2 was complicated.

Therefore, it is an object of the present invention to provide a data reproducing circuit and a reproducing method therefor capable of quickly and easily demodulating target data when detection of a target ID sync and a data sync fails in a disk reproducing apparatus. To do.

[0030]

According to one aspect of the present invention, there is provided a data reproducing circuit of a disk reproducing apparatus, comprising: (1) a sector synchronization signal and a (b) sector in each of a plurality of sectors according to a fixed format. Identification information,
A decoder for converting a serial signal read by a head from a disk-shaped recording medium on which (c) a data synchronization signal and (d) data are sequentially recorded into a parallel signal and demodulating the signal. ) A sector synchronization signal detection unit for detecting the sector synchronization signal from the serial signal, (B) a data synchronization signal detection unit for detecting the data synchronization signal from the serial signal, (C) A serial / parallel converter for converting a serial signal into the parallel signal, (D) a demodulator for demodulating the parallel signal, and (E) a start signal when the target sector synchronization signal is successfully detected. A decoder having an activation control unit for outputting, and (F) a shifter activation unit for outputting a shifter activation signal when detection of the target data synchronization signal fails; (2) the decoder RAM for temporarily storing the demodulated parallel signal; (3) Memory control unit for controlling writing and reading of data to and from the RAM; (4) Parallel signal demodulated by the decoder,
An error detector for detecting a code error; (5) a parallel signal demodulated by the decoder,
An error correction unit for correcting a code error; (6) A parallel signal whose code error has not been detected by the error detection unit and a parallel signal whose code error has been corrected by the error correction unit from the RAM to the host Host interface for transferring to (7) (a) the activation signal is input, and (b) the serial signal read by the head is converted into a parallel signal by a predetermined amount, and the RAM is used as a sample signal.
Serial / parallel converter for temporarily storing in;
And (8) (a) start by inputting the shifter start signal,
(b) A shifter for shifting the sample signal by a predetermined number of bits and outputting the sample signal to the demodulation unit.

Here, the disc-shaped recording medium is, for example, F
Including D, HD, CD, DVD and MO. Compared to the tape-shaped recording medium, the disk-shaped recording medium can easily and quickly retry the data reproducing operation for the same sector.

In the above data reproducing circuit, when the decoder succeeds in detecting the sector synchronization signal, it can demodulate the sector identification information that is subsequently input. Further, the decoder can demodulate the subsequently input data when the data sync signal is successfully detected.

The above data reproducing circuit activates the serial / parallel converter when the target sector synchronization signal is successfully detected. The serial / parallel converter temporarily stores the sample signal in the RAM in parallel with the operation of the decoder. The sampled signal typically contains the target data. Then, when the decoder fails to detect the target data synchronization signal, the shifter starting unit starts the shifter.
The shifter reads the sample signal from the RAM, shifts it by a predetermined number of bits, and outputs it to the demodulation unit. Thereby,
When the decoder fails to detect the target data synchronization signal, it can demodulate the target data from the sample signal stored in the RAM. As a result, the above data reproducing circuit can demodulate the target data faster than re-detecting the target sector synchronization signal and the data synchronization signal from the disk-shaped recording medium by retry.

In the above data reproduction circuit, (A) the demodulation section demodulates the sample signal input from the shifter; (B) the error detection section determines a code error of the demodulated sample signal. (C) each time the control signal is input, the shifter changes the number of bits, and (b) the original stored in the RAM is detected. The sample signal may be shifted by the changed number of bits and output to the demodulation unit. In this way, the data reproducing circuit can more reliably extract the target data from the sample signal by detecting the error in the sample signal.

The data reproducing circuit may further include a sector identification section for identifying the target sector synchronization signal from the sector identification information demodulated by the demodulation section. As a result, the data reproducing circuit can determine whether the detected sector synchronization signal is the target one by demodulating the sector identification information input subsequently to the sector synchronization signal.

The start control is performed by the data reproducing circuit based on a detection signal output by a physical mark detecting section for detecting a physical mark which is a specific shape portion on the surface of the disc-shaped recording medium. It may further include a serial / parallel converter operation time adjusting unit for adjusting the timing of either or both of outputting the activation signal by the unit and stopping the serial / parallel converter.

The physical mark corresponds to, for example, an index hole in the FD, and a wobble and a prepit in the optical disc. The above-mentioned data reproducing circuit utilizes the physical mark of the disc-shaped recording medium to perform serial / serial recording.
The operation time of the parallel converter can be adjusted. Thereby,
The sample signal converted by the serial / parallel converter can surely contain the target data. As a result, the above data reproducing circuit can suppress the data amount of the sample signal to an appropriate amount.

According to another aspect of the present invention, there is provided a data reproducing circuit of a disk reproducing apparatus, comprising: (1) sector synchronization signal, (b) sector identification information for each of a plurality of sectors according to a fixed format,
A decoder for converting a serial signal read by a head from a disk-shaped recording medium in which (c) a data synchronization signal and (d) data are sequentially recorded into a parallel signal and demodulating the signal. ) A sector synchronization signal detection unit for detecting the sector synchronization signal from the serial signal, (B) data for detecting the data synchronization signal from the serial signal for a predetermined time by inputting a detection start signal A synchronization signal detection unit, (C) a serial / parallel conversion unit for converting the serial signal into the parallel signal, (D) a demodulation unit for demodulating the parallel signal, and (E) (a) a target The sector (target sector)
From the input of the error detection end signal to the input of the target data synchronization signal by the serial / parallel converter is predicted based on the format as the target data synchronization signal input prediction time, (b) A decoder having a data synchronization signal detection control unit for outputting the detection start signal to the data synchronization signal detection unit when the target data synchronization signal input prediction time has elapsed from the input of the error detection end signal for the target sector. (2) RAM for temporarily storing the parallel signal demodulated by the decoder; (3) Memory control unit for controlling writing and reading of data to and from the RAM; (4) (a) Demodulation by the decoder The code error of the parallel signal generated is detected, and (b) the error detection end signal is output to the decoder at the end of error detection. And (5) an error correction unit for correcting a code error of the parallel signal demodulated by the decoder; and (6) a parallel signal in which no code error is detected by the error detection unit, And a host interface for transferring, from the RAM to the host, a parallel signal whose code error has been corrected by the error correction unit.

In the above data reproducing circuit, when the decoder succeeds in detecting the sector synchronization signal, it can demodulate the sector identification information that is subsequently input. Further, the decoder can demodulate the subsequently input data when the data sync signal is successfully detected.

In the above data reproducing circuit, when the decoder fails to detect the target sector synchronization signal, it can detect the target data synchronization signal as follows. First, a sector which includes a detectable sector synchronization signal and data and is preferably the last sector is set as the target sector from the sectors before the sector including the target sector synchronization signal. Next, the above data reproduction circuit executes a retry,
The data of the target sector is demodulated and its code error is detected. The error detector outputs an error detection end signal for the target sector. The data synchronization signal detection control unit outputs a detection start signal when the target data synchronization signal input predicted time has elapsed from the input of the error detection end signal. The data synchronization signal detector detects the data synchronization signal for a predetermined time after the detection start signal is input.

In the above data reproducing circuit, unlike the conventional one, the measurement of the target data synchronization signal input predicted time is started from the input of the error detection end signal. That is, the start time of the measurement of the target data synchronization signal input predicted time is closer than that of the conventional time when the target data synchronization signal is input. Therefore, the error in the target data synchronization signal input prediction time can be substantially reduced as compared with the conventional case. Therefore, the target data synchronization signal can be detected more reliably than before.

The data reproduction circuit may further include a sector identification information error detection unit for detecting a code error of the sector identification information demodulated by the demodulation unit. Thereby, when the sector identification information does not include a code error, the above data reproducing circuit can demodulate the data. As a result, the above data reproducing circuit can transfer the demodulated data and the correct sector identification information corresponding to the data to the host.

The data reproduction circuit may further include a sector identification section for identifying the target sector from the sector identification information demodulated by the demodulation section.
Thereby, the above-mentioned data reproducing circuit can judge whether the detected sector synchronization signal is the target signal or not based on the sector identification information.

The data reproduction circuit described above inputs the target data based on a detection signal output by a physical mark detection unit for detecting a physical mark which is a specific shape portion on the surface of the disc-shaped recording medium. It may further include a target data synchronization signal input estimated time correction unit for correcting the estimated time. The target data synchronization signal input prediction time generally includes an error. The above-mentioned data reproducing circuit can correct the target data synchronization signal input predicted time to a more accurate one by utilizing the physical mark of the disc-shaped recording medium.

According to still another aspect of the present invention, there is provided a data reproducing circuit of a disk reproducing apparatus, comprising: (1) sector synchronization signal, (b) sector identification information, and
A decoder for converting a serial signal read by a head from a disk-shaped recording medium in which (c) a data synchronization signal and (d) data are sequentially recorded into a parallel signal and demodulating the signal. ) A sector synchronization signal detection unit for detecting the sector synchronization signal from the serial signal, (B) data for detecting the data synchronization signal from the serial signal for a predetermined time by inputting a detection start signal A synchronization signal detection unit, (C) a serial / parallel conversion unit for converting the serial signal into the parallel signal, (D) a demodulation unit for demodulating the parallel signal, and (E) (a) a target The time from the successful detection of the sector sync signal to the input of the target data sync signal by the data sync signal detector is taken as the target data sync signal input predicted time. Predicting based on (b) from the time of successful detection of the target sector synchronization signal until the lapse of the target data synchronization signal input prediction time, of another synchronization signal detected from the disk-shaped recording medium Correct the target data synchronization signal input prediction time for each input, (c) to the data synchronization signal detection unit when the target data synchronization signal input prediction time has elapsed from the time when the target sector synchronization signal was successfully detected. A decoder having a data synchronization signal detection controller for outputting the detection start signal; (2) a RAM for temporarily storing the parallel signal demodulated by the decoder; (3) writing data to the RAM and Memory control unit for controlling reading; (4) Error detection unit for detecting code error of parallel signal demodulated by the decoder; (5) Decoder An error correction unit for correcting a code error of the demodulated parallel signal; and (6) a parallel signal whose code error is not detected by the error detection unit, and a code error corrected by the error correction unit. A parallel interface, which transfers the parallel signals from the RAM to the host.

In the above data reproducing circuit, when the decoder succeeds in detecting the sector synchronization signal, it can demodulate the sector identification information that is subsequently input. Further, the decoder can demodulate the subsequently input data when the data sync signal is successfully detected.

In the above data reproducing circuit, when the decoder fails to detect the target sector sync signal, it can detect the target data sync signal as follows. First, a sector including a detectable sector synchronization signal is set as a target sector among the sectors preceding the sector including the target sector synchronization signal. Next, the data reproducing circuit described above executes a retry to detect the sector synchronization signal included in the target sector. The data synchronization signal detection controller outputs a detection start signal when the target data synchronization signal input predicted time has elapsed from the time when the sector synchronization signal was successfully detected. The data synchronization signal detector detects the data synchronization signal for a predetermined time after the detection start signal is input.

The target data synchronization signal input prediction time generally includes an error. Therefore, unlike the conventional data reproduction circuit, the target data synchronization signal input predicted time is corrected for each input of another synchronization signal detected during the counting. As a result, the target data synchronization signal input prediction time can be made more accurate than in the conventional data reproducing circuit. In particular, when the sector that is a plurality of sectors before the sector synchronization signal detection has failed is the target sector, the error in the target data synchronization signal input prediction time can be greatly reduced compared to the conventional case. As a result, the above data reproduction circuit outputs the target data synchronization signal,
It can be detected more reliably than before.

The above-mentioned other synchronization signal is, for example, a sector synchronization signal newly detected by the sector synchronization signal detecting section,
It may be either a data synchronization signal newly detected by the data synchronization signal detection unit or a detection signal output by the physical mark detection unit. That is, any sync signal can be used as long as it can correct the target data sync signal input predicted time based on the physical format of the disc-shaped recording medium.

The data reproduction circuit may further include a sector identification section for identifying the target sector from the sector identification information demodulated by the demodulation section.
Thereby, the above-mentioned data reproducing circuit can judge whether the detected sector synchronization signal is the target signal or not based on the sector identification information.

According to another aspect of the present invention, there is provided a data reproducing circuit of a disk reproducing apparatus, comprising: (1) sector synchronization signal, (b) sector identification information for each of a plurality of sectors according to a fixed format,
A decoder for converting a serial signal read by a head from a disk-shaped recording medium on which (c) a data synchronization signal and (d) data are sequentially recorded into a parallel signal and demodulating the signal. ) A sector synchronization signal detection unit for detecting the sector synchronization signal from the serial signal, (B) data for detecting the data synchronization signal from the serial signal for a predetermined time by inputting a detection start signal A synchronization signal detection unit, (C) a serial / parallel conversion unit for converting the serial signal into the parallel signal, (D) a demodulation unit for demodulating the parallel signal, and (E) (a) the disc The physical mark that is a specific shape portion of the surface of the recording medium is detected by the physical mark detection unit, and then the target data synchronization signal is input by the data synchronization signal detection unit. Of the target data synchronization signal input prediction time is predicted based on the format as the target data synchronization signal input prediction time, and (b) the target data synchronization signal input prediction time from the time when the physical mark detection unit successfully detects the physical mark. A decoder having a data synchronization signal detection control unit for outputting the detection start signal to the data synchronization signal detection unit when the time has elapsed; (2) RAM for temporarily storing the parallel signal demodulated by the decoder; (3) Memory control unit for controlling writing and reading of data to and from the RAM; (4) Error detection unit for detecting code error of the parallel signal demodulated by the decoder; (5) Demodulation by the decoder An error correction unit for correcting the code error of the parallel signal generated; and (6) no code error is detected by the error detection unit. Parallel signals, and the parallel signal, which is corrected the code error by the error correction unit host interface for transferring from the RAM to the host; comprises a.

In the above data reproducing circuit, when the decoder succeeds in detecting the sector synchronization signal, it can demodulate the sector identification information that is subsequently input. Further, the decoder can demodulate the subsequently input data when the data sync signal is successfully detected.

In the above data reproduction circuit, when the decoder fails to detect the target sector synchronization signal, it can detect the target data synchronization signal as follows. First, the data synchronization signal of the sector including the target sector synchronization signal is set to the target. Next, the data reproduction circuit described above executes a retry. The data synchronization signal detection controller outputs a detection start signal when the target data synchronization signal input predicted time has elapsed from the time when the physical mark detection unit succeeded in detecting the physical mark. The data synchronization signal detector detects the data synchronization signal for a predetermined time after the detection start signal is input.

The physical mark is a physical shape portion of the surface of the disc-shaped recording medium, such as an index hole in an FD, a wobble and a prepit in an optical disc. Therefore, the physical mark is less likely to deteriorate than other sync signals. Furthermore, the surface of the disk-shaped recording medium can be detected with high accuracy without being significantly affected by scratches and dirt, and vibration and impact. Therefore, as compared with the conventional data reproducing circuit which calculates the target data synchronizing signal input predicted time with the sector synchronizing signal as a reference, the above data reproducing circuit can detect the target data synchronizing signal more reliably.

According to one aspect of the present invention, there is provided a data reproducing method for a disk reproducing apparatus, comprising: (A) sector synchronization signal; (b) sector identification information;
(c) a step of detecting the target sector synchronization signal from among the serial signal read by the head from the disk-shaped recording medium in which the data synchronization signal and (d) data are sequentially recorded; Detecting the target data synchronization signal from the serial signal; (C) when the target data synchronization signal is successfully detected,
Converting the serial signal into a parallel signal and demodulating the parallel signal into the data; (D) temporarily storing the demodulated data in a RAM; (E) detecting a code error in the demodulated data (F) correcting a code error in the demodulated data; (G) the data in which no code error is detected; and
A step of transferring the code-corrected data from the RAM to the host; (H) when the target sector synchronization signal is successfully detected,
Converting the serial signal into a parallel signal by a predetermined amount,
Temporarily storing in the RAM as a sample signal; and (I) when the detection of the target data synchronization signal fails,
Shifting the sampled signal by a predetermined number of bits and demodulating.

Here, the disc-shaped recording medium is, for example, F
Including D, HD, CD, DVD and MO. Compared to the tape-shaped recording medium, the disk-shaped recording medium can easily and quickly retry the data reproducing operation for the same sector.

In the above data reproducing method, the serial signal is converted into the sample signal and the sample signal is transferred to the RAM in parallel with the normal data demodulation. As a result, when the detection of the target data synchronization signal fails, the RAM
Target data can be extracted and demodulated from the above sample signals. As a result, the above data reproducing method can demodulate the target data faster than the conventional method of re-detecting the target sector synchronization signal and the data synchronization signal from the disk-shaped recording medium by retry.

The above data reproducing method further includes: (A) detecting a code error in the demodulated sample signal; (B) detecting a predetermined number or more of code errors in the demodulated sample signal, Change the number of bits and change the RA
Demodulating the original sample signal stored in M by shifting it by the changed number of bits; (C) correcting a code error in the demodulated sample signal; and (D) correcting a code error. The sample signal not detected,
And a step of transferring the sample signal whose code error has been corrected from the RAM to the host. Thus, the error detection for the sample signal
The target data can be more reliably extracted from the sample signal.

The above data reproducing method further includes: (A) converting the serial signal into a parallel signal when the target sector synchronization signal is successfully detected, and demodulating the parallel signal into the sector identification information; And (B) identifying the target sector synchronization signal from the demodulated sector identification information. This makes it possible to determine whether or not the detected sector synchronization signal is the target one by demodulating the sector identification information input subsequently to the sector synchronization signal.

The above-described data reproducing method further includes the physical mark detection unit for detecting a physical mark which is a specific shape portion of the surface of the disc-shaped recording medium, based on the detection signal output from the target. Adjusting the time from the time when the sector sync signal is successfully detected to the start or end of the conversion of the serial signal into the sample signal or each of them.

The physical marks correspond to index holes in the FD and wobbles and prepits in the optical disc, respectively. In the above data reproducing method, the operation time of the serial / parallel converter can be adjusted by using the physical mark of the disc-shaped recording medium. Thereby, the sample signal converted by the serial / parallel converter can surely include the target data. As a result, the data amount of the sample signal can be suppressed to an appropriate amount.

According to another aspect of the present invention, there is provided a data reproducing method for a disk reproducing apparatus, comprising: (A) sector synchronization signal, (b) sector identification information, and
(c) a step of detecting the target sector synchronization signal from among a serial signal reproduced by a head from a disk-shaped recording medium in which a data synchronization signal and (d) data are recorded in sequence; (B) the target When the sector sync signal of is successfully detected,
Detecting the target data synchronization signal from the serial signal; (C) when the target data synchronization signal is successfully detected,
Converting the serial signal into a parallel signal and demodulating the parallel signal into the data; (D) temporarily storing the demodulated data in a RAM; (E) detecting a code error in the demodulated data (F) correcting a code error in the demodulated data; (G) the data in which no code error is detected; and
A step of transferring the code-error-corrected data from the RAM to the host; (H) the time from the end of error code detection for the target sector to the input of the target data synchronization signal, the target data Predicting based on the format as a sync signal input prediction time; and (I) from the serial signal when the target data sync signal input prediction time elapses from the end of error code detection for the target sector Detecting the target data synchronization signal for a predetermined time.

In the above data reproducing method, when the detection of the target sector synchronization signal fails, the target data synchronization signal is detected as follows. First, among the sectors preceding the sector including the target sector synchronization signal, the sector including the detectable sector synchronization signal and data and preferably the last sector is set as the target sector. Next, a retry is executed to demodulate the data of the target sector, and the code error is detected. When the target data synchronization signal input predicted time has elapsed from the end of the error detection, the target data synchronization signal is detected for a predetermined time.

In the above data reproducing method, unlike the conventional method, the target data synchronization signal input prediction time is measured from the end of error detection. That is, the start time of the measurement of the target data synchronization signal input predicted time is closer than that of the conventional time when the target data synchronization signal is input. Therefore, the error in the target data synchronization signal input prediction time can be reduced as compared with the conventional case. Therefore, the target data synchronization signal can be detected more reliably than before.

The above data reproducing method further includes: (A) converting the serial signal into a parallel signal when the target sector synchronization signal is successfully detected, and demodulating the parallel signal into the sector identification information; And (B) detecting a code error in the demodulated sector identification information. Thereby, when the sector identification information does not include a code error, the data can be demodulated by the above data reproducing method. As a result, in the above data reproducing method, the accurate sector identification information corresponding to the demodulated data can be transferred to the host together with the demodulated data.

The above data reproducing method may further include the step of identifying the target sector from the demodulated sector identification information. This makes it possible to determine whether the detected sector synchronization signal is the target signal based on the sector identification information.

In the above data reproducing method, the target data synchronization is performed based on the detection signal output by the physical mark detecting section for detecting a physical mark which is a specific shape portion on the surface of the disc-shaped recording medium. The method may further include the step of modifying the predicted signal input time. The target data synchronization signal input prediction time generally includes an error. In the above data reproducing method, the target mark for inputting the data synchronization signal can be corrected to be more accurate by using the physical mark of the disc-shaped recording medium.

According to still another aspect of the present invention, there is provided a data reproducing method of a disk reproducing apparatus, comprising: (A) sector synchronization signal, (b) sector identification information, in each of a plurality of sectors according to a fixed format,
(c) a step of detecting the target sector synchronization signal from among the serial signal read by the head from the disk-shaped recording medium in which the data synchronization signal and (d) data are sequentially recorded; When the target sector sync signal is successfully detected,
Detecting the target data synchronization signal from the serial signal; (C) when the target data synchronization signal is successfully detected,
Converting the serial signal into a parallel signal and demodulating the parallel signal into the data; (D) temporarily storing the demodulated data in a RAM; (E) detecting a code error in the demodulated data (F) correcting a code error in the demodulated data; (G) the data in which no code error is detected; and
A step of transferring the code-corrected data from the RAM to the host; (H) targeting a time from when the target sector sync signal is successfully detected to the input of the target data sync signal Predicting based on the format as the data synchronization signal input prediction time; (I) From the disc-shaped recording medium from the time when the target sector synchronization signal is successfully detected to the lapse of the target data synchronization signal input prediction time. Modifying the target data synchronization signal input prediction time for each input of another detected synchronization signal; and (J) the target data synchronization signal input prediction time from the time when the target sector synchronization signal is successfully detected. When the time elapses, the step of detecting the target data synchronization signal for a predetermined time.

In the above data reproducing method, when the detection of the target sector synchronization signal fails, the target data synchronization signal can be detected as follows. First, a sector including a detectable sector synchronization signal is set as a target sector among the sectors preceding the sector including the target sector synchronization signal. Next, retry is executed to detect the sector synchronization signal included in the target sector. The data synchronization signal detection controller outputs a detection start signal when the target data synchronization signal input predicted time has elapsed from the time when the sector synchronization signal was successfully detected. The data synchronization signal detector detects the data synchronization signal for a predetermined time after the detection start signal is input.

The target data synchronization signal input prediction time generally includes an error. In the above data reproducing method, unlike the conventional method, the target data sync signal input predicted time is corrected for each input of another sync signal detected during the counting.
As a result, the error in the target data synchronization signal input prediction time can be reduced as compared with the conventional data reproducing method. In particular, when the sector that is a plurality of sectors before the sector synchronization signal detection failure is set as the target sector, the error in the target data synchronization signal input prediction time can be greatly reduced compared to the conventional case. As a result, in the above data reproducing method, the target data synchronization signal can be detected more reliably than before.

The above-mentioned other synchronization signal may be, for example, a newly detected sector synchronization signal or data synchronization signal, or a detection signal output by the physical mark detection unit. That is, any sync signal can be used as long as it can correct the target data sync signal input predicted time based on the physical format of the disc-shaped recording medium.

The above data reproducing method further includes: (A) converting the serial signal into a parallel signal when the target sector synchronization signal is successfully detected, and demodulating the parallel signal into the sector identification information; And (B) identifying the target sector from the demodulated sector identification information. This makes it possible to determine whether the detected sector synchronization signal is the target signal based on the sector identification information.

According to another aspect of the present invention, there is provided a data reproducing method for a disk reproducing apparatus, which comprises: (A) sector synchronization signal, (b) sector identification information, and
(c) a step of detecting the target sector synchronization signal from among the serial signal read by the head from the disk-shaped recording medium in which the data synchronization signal and (d) data are sequentially recorded; When the target sector sync signal is successfully detected,
Detecting the target data synchronization signal from the serial signal; (C) when the target data synchronization signal is successfully detected,
Converting the serial signal into a parallel signal and demodulating the parallel signal into the data; (D) temporarily storing the demodulated data in a RAM; (E) detecting a code error in the demodulated data (F) correcting a code error in the demodulated data; (G) the data in which no code error is detected; and
Transferring the code-error-corrected data from the RAM to the host; (H) detecting the physical mark, which is a specific shape portion of the surface of the disk-shaped recording medium, by the physical mark detection unit, and Of predicting the time until the input of the data synchronization signal as the target data synchronization signal input prediction time based on the format; and (I) the passage of the target data synchronization signal input prediction time from the detection of the physical mark. Sometimes detecting the target data synchronization signal for a predetermined time.

In the above data reproducing method, when the detection of the target sector synchronization signal fails, the target data synchronization signal can be detected as follows. First, the data synchronization signal of the sector including the target sector synchronization signal is set to the target, and the retry is executed. Next, when the target data synchronization signal input predicted time has elapsed from the time when the physical mark detection unit succeeded in detecting the physical mark, the target data synchronization signal is detected for a predetermined time.

The physical mark is a physical shape portion of the surface of the disc-shaped recording medium, such as an index hole in an FD, a wobble and a prepit in an optical disc. Therefore, the physical mark is less likely to deteriorate than other sync signals. Furthermore, the surface of the disk-shaped recording medium can be detected with high accuracy without being significantly affected by scratches and dirt, and vibration and impact. Therefore, as compared with the conventional data reproducing method in which the target data synchronizing signal input predicted time is calculated with the sector synchronizing signal as a reference, the above data reproducing method can detect the target data synchronizing signal more reliably.

[0076]

BEST MODE FOR CARRYING OUT THE INVENTION The best mode for carrying out the present invention will be described below with reference to the accompanying drawings with reference to its preferred embodiments.

The disk reproducing apparatuses according to the embodiments of the present invention described below are all FDDs for large-capacity FDs. First, the physical format of the large-capacity FD that is the reproduction target of those FDDs will be described.

FIG. 1 is a schematic diagram showing a track T recorded on a disk D having a large capacity FD. On the disc D, a plurality of tracks T are recorded concentrically around the center C of the disc D. Each track T is a positive integer N
Sectors S1, S2, ..., S (N−1), SN and N gaps G1, G2, ..., G (N−1), GN are alternately divided. . However, the number N of sectors differs for each track T. The head of the first sector S1 on each track T is on a predetermined radius O of the disk D.

Each sector is an area for recording the same amount of data and has the same length. Therefore,
The linear recording density of data in each sector is constant. The FDD head reads data for each sector.

The gap is an area for discriminating adjacent sectors on one track T. A specific code is recorded on the gap to distinguish it from the data. The first gap G1 to the (N−1) th gap G (N−1) are set to have the same length. On the other hand, the Nth gap GN has a different length for each track T.

A small hole called an index hole IH is formed in the inner peripheral portion of the disk D. The center of the index hole IH is set on a predetermined radius 0 of the disk D, for example, and indicates the beginning of the first sector S1. Therefore, by detecting the center of the index hole IH, the first sector S
The beginning of 1 can be detected.

FIG. 2 is a diagram showing the physical format of one track T on the disc D. Figure 2 (a) shows a truck T
Shows the overall physical format. FIG. 2B shows the physical format of each sector. As shown in FIG. 2B, each sector includes an ID field Id, a pad P, and a data field Da in order from the beginning.

The ID field Id is the sector identification information (I
This is an area in which D) is recorded. The ID field Id is the ID preamble Id1 and the ID synchronization signal (sync) I in order from the beginning.
It includes d2 and IDId3. ID preamble Id1 is ID
Indicates the beginning of field Id. The ID sync Id2 is a synchronization signal for synchronizing the subsequent IDId3 and the reproduction operation of the disc reproducing apparatus. IDId3 is sector identification information and includes, for example, a track number and a sector number. In addition, IDId3 contains its own error detection code.

The data field Da is an area in which data is recorded. The data field Da is a 64-bit data preamble Da1 and a 16-bit data sync D in order from the beginning.
It includes a2, 4096-bit data Da3, and a 160-bit parity code Da4. The data preamble Da1 represents the beginning of the data field Da. The data sync Da2 is a synchronization signal for synchronizing the subsequent data Da3 and the reproduction operation of the disc reproducing apparatus. The data Da3 is the main body of the information recorded on the disc D. Furthermore, the data Da3 includes a cyclic code as its own error detection code. The parity code Da4 is an error correction code for the data Da3 according to the Reed-Solomon code system.

The pad P is an area for distinguishing the ID field Id and the data field Da. Both the data of the ID field Id and the data of the data field Da consist of a bit string modulated by a predetermined modulation method. On the other hand, the pad P consists of a 32-bit bit string that is not used in the modulation method. As described above, the physical format of the disk D is two sync signals per sector, that is,
It includes an ID sync Id2 and a data sync Da2.

<< First Embodiment >> FIG. 3 is a block diagram of an FDD according to a first embodiment of the present invention. Readout section R is head H
Including d. The head Hd reproduces data as an analog signal from a disk-shaped recording medium (hereinafter referred to as a disk) D.
The reading unit R performs analog / digital conversion on the analog signal and outputs it as a bit stream Bs which is a serial digital signal. Further, the reading unit R generates the read clock RCK with substantially the same frequency as the bit stream Bs. The phase of the read clock RCK is adjusted by, for example, a PLL so as to be synchronized with the bit stream Bs.

The index hole detection unit IHD is a disc D
The center of the index hole IH (see Fig. 1) of is detected as follows: A circle that is concentric with the disk D and passes through the center of the index hole IH is assumed to be on the surface of the disk D, and a predetermined circle on the circumference is assumed. The light from the photodiode is applied to one point.
When the index hole IH reaches its irradiation position by the rotation of the disk D, the light of the photodiode passes through the index hole IH. The passed light is detected by a photodetector. Thereby, it can be detected that the center of the index hole IH is at the light irradiation position of the photodiode. The index hole detector IHD outputs a predetermined detection signal IND when the center of the index hole IH is successfully detected.

The data reproducing circuit 10 converts the data from the bit stream Bs into parallel signals, demodulates them, and transfers them to the host Hs. The host Hs is, for example, the FDD according to the first embodiment.
Is a personal computer main body to which is connected. Communication between the data reproduction circuit 10 and the host Hs is performed by, for example, IDE.
It is performed through an expansion bus B such as a bus, a PCI bus and a USB.

<Structure of Data Reproducing Circuit 10> The data reproducing circuit 10 according to the first embodiment includes the following components. decoder
1 is a detection signal of the bit stream Bs and the read clock RCK from the reading unit R, and a detection signal from the index hole detection unit IHD
Enter IND respectively. The decoder 1 extracts data from the bit stream Bs according to the read clock RCK and the detection signal IND and converts it into a parallel signal Bp. The parallel signal Bp is obtained by parallelizing the bit stream Bs by 8 bits (= 1 byte). Further, the decoder 1 demodulates and outputs the parallel signal Bp. Details of the decoder 1 will be described later.

The memory controller 2 controls the input / output of data to / from the RAM 3. RAM3 is a memory for temporarily storing parallel signals. The memory control unit 2 temporarily stores the parallel signal Bp from the decoder 1 in the buffer area of the RAM 3 and the sample signal SMP from the serial / parallel converter 7 in the work area of the RAM 3.

FIG. 4 is a memory space diagram of the RAM3. RA
In M3, addresses 0-Aa are in work area 3w
Ab to Ab + 511 is the data area 3bd in the buffer area 3b
Addresses Ac to Ac + 19 are respectively allocated to the parity code area 3bp in the buffer area 3b. RA
One word of M3 is, for example, one byte. That is, in the first embodiment, the number of parallel data of the parallel signal Bp is RAM3.
Matches the word width of. Therefore, the work area 3w is maximum
A parallel signal of (Aa + 1) bytes can be stored. On the other hand, the data area 3bd and the parity code area 3bp in the buffer area 3b are 512 bytes (4096 bits) and 20 bytes, respectively.
Byte (160 bits) parallel signal can be stored. As a result, the data Da3 in the parallel signal Bp is sent to the data area 3bd and the parity code is sent to the parity code area 3bp.
Arrange Da4 respectively. The arrangement is determined according to the Reed-Solomon coding method.

The error detector 4 detects a code error in the parallel signal Bp output from the decoder 1 based on the error detection code included in the data Da3. Further, the error detection unit 4 outputs information about the detected code error to the memory control unit 2. In addition, when the number of detected code errors exceeds the error correctable value, a predetermined control signal CTL is output to the N bit shifter 8.

The error correction unit 5 corrects the code error of the parallel signal Bp arranged in the buffer area of the RAM 3 based on the parity code Da4. Host interface 6
Transfers the parallel signal Bp arranged in the buffer area of the RAM 3 to the host Hs by the communication method of the expansion bus B.

The serial / parallel converter 7, in addition to the decoder 1, converts the bit stream Bs into a parallel signal. Let the converted parallel signal be the sample signal SMP. The sample signal SMP is the parallel signal Bp from the decoder 1.
Similarly to, the bit stream Bs is parallelized in units of 8 bits. The serial / parallel converter 7 is started by the start signal S1 from the decoder 1 and stopped by the stop signal S2. The memory control unit 2 is a serial / parallel converter 7
The sample signal SMP output from is stored in the work area 3w of the RAM 3 in order from its head address.

The N-bit shifter 8 inputs the sample signal SMP from the work area 3w of the RAM 3 through the memory control unit 2. Further, the input sample signal SMP is shifted by a predetermined number of bits and output to the decoder 1. The decoder 1 demodulates the input sample signal SMP. The memory control unit 2 regards the demodulated sample signal as the data Da3 and the parity code Da4, and stores it in the buffer area 3b of the RAM 3 as with the parallel signal Bp.

FIG. 5 is a block diagram of the inside of the N-bit shifter 8. The selector 80 selects the first word of the sample signal (input sample signal) In input from the work area 3w of the RAM 3 and outputs it to the first flip-flop (FF) 81. After outputting the first word, the selector 80 outputs the second FF.
The word output from 82 is selected and output to the first FF 81. As a result, the second and subsequent words of the input sample signal In are input to the second FF 82.

The first FF 81 and the second FF 82 latch the input sample signal In one word (= 8 bits) at a time, thereby outputting the respective latched words to the bus selector 84 at the same time. At that time, the address of the word W1 latched in the first FF 81 is one address before the address of the word W2 latched in the second FF 82. For example, N
Assume that the sample signal input to the bit shifter 8 is sequentially read from the kth address of the work area 3w (see FIG. 4). First, the first FF81 is the kth word Wk
Latch. On the other hand, the second FF 82 latches the (k + 1) th word W (k + 1). Next, the first FF 81 and the second FF 82 simultaneously output the kth word Wk and the (k + 1) th word W (k + 1), respectively. Further, at that time, the first FF 81 outputs the (k + 1) th word W (k + 1) to the second FF8.
2 inputs the (k + 2) th word W (k + 2), respectively.
Similar input / output is repeated for the (k + 3) th and subsequent words.

The bus selector 84 selects consecutive 8 bits from the two words W1 and W2 input from the first FF 81 and the second FF 82, and outputs them to the third FF 83. At that time, consecutive 8-bit head bits are determined by shifting a predetermined number of bits from the head bit of the word W1 output from the first FF 81. Hereinafter, the predetermined number of bits will be referred to as the number of shift bits. If a given positive integer is N,
The number of shift bits depends on the control signal CTL from the error detector 4, -N,-(N-1), ..., -1, 0, +1, ..., +
It is determined to be either (N-1) or + N. Here, the predetermined positive integer N may be 8 or more. At that time, if the number of shift bits of 8 or more is expressed as 8m + r (m: positive integer of 1 or more, r: integer of 0 to 7), the word first latched by the first FF 81 is
The kth address is shifted to the (k + m) th address, and the first bit is shifted by r bits. Furthermore,
The number of negative shift bits is -8m + r (m: positive integer of 1 or more, r:
If expressed as an integer of 0 to 7, the word first latched by the first FF 81 is shifted from the kth address to the (k−m) th address, and the first bit is shifted by r bits. The third FF 83 latches the 8 bits output from the bus selector 84, thereby simultaneously outputting the 8 bits to the decoder 1 as one parallel signal.

(Structure of Decoder 1) FIG. 6 is a block diagram of the decoder 1. The preamble detection unit 11 detects the preamble of the head of the ID field Id from the bitstream Bs.
Detect Id1 (see Figure 2). When the detection is successful, the preamble detection unit 11 outputs the activation signal Wi to the ID sync detection unit 12. This activation signal Wi is called an ID sync detection window. ID
The sync detection window Wi is generally a rectangular pulse signal composed of two values of a high potential H (hereinafter referred to as ON) and a low potential L (hereinafter referred to as OFF). When the ID sync detection window Wi is on, I
The D sync detector 12 performs a detection operation. On the other hand, when the ID sync detection window Wi is off, the ID sync detection unit 12 stops. When the preamble detection unit 11 succeeds in detecting the preamble Id1 of the ID field Id, the preamble detection window Wi
Is turned on for a predetermined time. The predetermined time is measured by counting the number of clocks of the read clock RCK.

The ID sync detection unit 12 displays the ID sync detection window Wi.
The ID sync Id2 is detected only during the ON period. Thereby, the probability of false detection of the ID sync Id2 is reduced. When the ID sync detector 12 succeeds in detecting the ID sync Id2, it outputs the ID sync detection signal SYi to the serial / parallel converter 14 and the sector coincidence detector 16.

The data sync detector 13 is activated by the activation signal Wd input from the data sync down counter 18.
This activation signal Wd is called a data sync detection window. Like the ID sync detection window Wi, the data sync detection window Wd is a rectangular pulse signal composed of two values, a high potential H (on) and a low potential L (off). When the data sync detection window Wd is on, the data sync detection unit 13 performs a detection operation. On the other hand, when the data sync detection window Wd is off, the data sync detection unit 13 stops. The data sync detection unit 13 detects the data sync Da2 only during the ON period of the data sync detection window Wd. As a result, the probability of false detection of the data sync Da2 is reduced.

The data sync detector 13 uses the data sync Da2.
When the data is detected successfully, the data sync detection signal SYd is output to the serial / parallel converter 14. On the other hand, when the detection of the data sync Da2 is unsuccessful, the data sync detection unit 13 inputs the stop signal S2 and the shifter activation signal S3 at the same time as the preamble detection unit 11, the ID sync detection unit 12, and the N-bit shifter.
Output to 8. By inputting the shifter activation signal S3, the preamble detection unit 11 and the ID sync detection unit 12 are stopped, and the N-bit shifter 8 is activated.

The serial / parallel converter 14 is activated by the input of either the ID sync detection signal SYi or the data sync detection signal SYd and starts the bit stream Bs for a predetermined time.
Convert to parallel signal Bp0. The predetermined time is represented by the number of read clocks RCK. For example, when the ID sync detection code SYi is input, the above predetermined time is equal to the number of bits of IDId3. On the other hand, when the data sync detection code SYd is input, the data Da3 and the parity code D
sum of the number of bits with a4, 4096 + 160 = 4256 bits (that is,
532 bytes).

The demodulation section 15 includes a serial / parallel conversion section 14
To the parallel signal Bp0 from the N-bit shifter 8 and the sample signal SMP from the N-bit shifter 8 are demodulated. Each demodulation method depends on the modulation method of IDId3 in the ID field Id, the data Da3 in the data field Da, and the parity code Da4.

The sector coincidence detection unit 16 outputs the ID sync detection signal.
I which is started by the input of SYi and demodulated by the demodulation unit 15
A code error of Did3 is detected. Further, when the code error is not detected, the sector number in IDId3 is compared with the sector number of the target sector 17. When the match of both sector numbers is successfully detected, the sector match detection unit 16 sends the first load signal Td to the data sync down counter 18 and the third load signal Ts to the sample output start down counter 20a.
Are output respectively.

The data sync down counter 18 is a down counter and decrements the count value by 1 bit at each rising edge of each pulse of the write clock WCK. here,
The write clock WCK is generated by a synthesizer (not shown).
It is generated independently of the read clock RCK. The frequency of the write clock WCK is substantially equal to the frequency of the operation clock when writing data to the disc D, and is kept constant for each track T of the disc D. Therefore, when the read clock RCK is stable, the frequency of the write clock WCK is substantially equal to the frequency of the read clock RCK. In the first embodiment, the write clock WCK is generated in synchronization with the bit stream Bs with reference to the time when the ID sync Id2 is successfully detected. Further, when the data sync down counter 18 counts the count value to 0, the data sync detection window Wd is turned on for a predetermined number of clocks.

The data sync down counter 18 receives the first load signal Td and outputs the count value as the data sync input predicted time ΔT0 or the target data sync input predicted time Δ.
Preset to any of T2.

The data sync input prediction time ΔT0 is shorter than the prediction time from the output of the first load signal Td by the sector coincidence detection unit 16 to the input of the data sync Da2 of the target sector 17 to the decoder 1 by a predetermined length. It's time. The reason why the data sync detection window Wd is shorter than the predetermined length is that the data sync detection window Wd is turned on earlier than the predicted time so that the input data sync Da2 can be detected earlier than the predicted time.

The target data sync input predicted time ΔT2 is from the output of the first load signal Td by the sector coincidence detection unit 16 to the input of the target data sync Da2 to the decoder 1.
Is a predetermined time shorter than the predicted time of. The reason why it is shorter by the predetermined length is the same as the above reason for the data sync input prediction time ΔT0. Furthermore, the target data sync Da2
Is set to the data sync Da2 of the sector one or more after the target sector 17, as described later.

Both the data sync input predicted time ΔT0 and the target data sync input predicted time ΔT2 are write clocks.
It is represented by the number of WCK clocks and is determined by the sector coincidence detection unit 16 based on the physical format of FIG.

The sample output start down counter 20a is a down counter, and decrements the count value by one bit at each rising edge of the pulse of the write clock WCK. Further, when the count value reaches 0, the start signal S1 is output to the serial / parallel converter 7.

When the third load signal Ts is input, the sample output start down counter 20a presets the count value to either the data input prediction time ΔTa or the target data input prediction time ΔTa1. Here, the data input estimated time ΔTa is the third load signal by the sector coincidence detection unit 16.
It is the estimated time from the output of Ts to the start of input of the pad P of the target sector 17 to the serial / parallel converter 7.
On the other hand, the target data input prediction time ΔTa1 is from the output of the third load signal Ts by the sector coincidence detection unit 16 to the start of input of the target pad P to the serial / parallel converter 7.
Is the estimated time. The target pad P is set to the pad P of the sector one or more after the target sector 17, as described later. The data input prediction time ΔTa and the target data input prediction time ΔTa1 are both represented by the number of clocks of the write clock WCK, and are determined by the sector coincidence detection unit 16 based on the above physical format.

The sample output stop down counter 20b is a down counter and decrements the count value by one bit at each rising edge of the pulse of the write clock WCK. Further, when the count value reaches 0, the stop signal S2 is output to the serial / parallel converter 7.

The sample output stop down counter 20b is preset with a constant count value ΔTb by the input of the start signal S1. The constant count value ΔTb is larger than the total number of bits of the pad P and the data field Da by a predetermined number of clocks.

The count correction unit 21 receives the data sync down counter 18 and the sample output start down counter for each input of the detection signal IND from the index hole detection unit IHD.
Modify each count value of 20a. At that time, the count value of the data sync down counter 18 is shorter than the predicted time from the time of successful detection of the index hole IH to the input of the target data sync Da2 to the decoder 1 by a predetermined length (first correction). (Predicted time) ΔT21. The count value of the sample output start down counter 20a is the estimated time (second corrected estimated time) ΔTa2 from the time when the detection of the index hole IH is successful to the start of the input of the target pad P to the serial / parallel converter 7. Is replaced by.

<Reproduction of data by the data reproduction circuit 10>
With the above components, the data reproduction circuit 10 demodulates the bit stream Bs as follows and transfers it to the host Hs. Decoder 1 reads bitstream Bs with read clock R
Input in sync with CK. The decoder 1 extracts the target data Da3 together with the parity code Da4 from the bit stream Bs as described below, converts it into the parallel signal Bp, and demodulates it.

FIG. 7 is a timing chart of the bit stream Bs input to the decoder 1 and each signal in the decoder 1. The bit stream Bs in FIG. 7 has a positive integer kth sector Sk, a kth gap Gk, and a (k + 1) th sector S
It corresponds to the serial signal read from (k + 1). The bit stream Bs normally includes both the ID sync Id2 and the data sync Da2 for the kth sector Sk. On the other hand, for the (k + 1) th sector S (k + 1), the ID sync I
Includes d2 normally, but misses data sync Da2.
Causes of loss of the data sync Da2 from the bit stream Bs include, for example, data loss due to scratches and dirt on the surface of the disk D, magnetic deterioration, and head read errors due to vibration and shock during reproduction.

(A) When both the target ID sync Id2 and the target data sync Da2 can be detected: When the kth sector Sk is set as the target sector, the data Da3 and the parity code Da4 of the kth sector Sk are set. Are demodulated according to the following steps 1 to 8.

Step 1: The preamble detection unit 11 detects the preamble Id1 of the ID field Id of the kth sector Sk and turns on the ID sync detection window Wi. Step 2: ID sync detection unit 12 causes ID sync detection window W
The ID sync Id2 is detected during the ON period of i. ID sync
When the detection of Id2 is successful, the ID sync detection unit 12 outputs the ID sync detection signal SYi. As a result, serial /
The parallel conversion unit 14 and the sector coincidence detection unit 16 are activated, and I
Did3 is demodulated. Step 3: The sector coincidence detection unit 16 compares the sector number in IDId3 with the sector number of the target sector. When the match between both sector numbers is successfully detected, the sector match detection unit 16 outputs the first load signal Td and the third load signal Ts. At that time, the time Δt from the output of the ID sync detection signal SYi to the output of the two load signals Td and Ts is substantially constant.

Step 4: The data sync down counter 18 decrements the count value in synchronization with the write clock WCK from the preset completion of the data sync input prediction time ΔT0. When the count value reaches 0, the data sync down counter 18 turns on the data sync detection window Wd. The data sync detection unit 13 detects the data sync Da2 during the ON period of the data sync detection window Wd. Step 5: When the detection of the data sync Da2 is successful, the data sync detection unit 13 outputs the data sync detection signal SYd. As a result, the serial / parallel conversion unit 14 is activated to convert the data Da3 and the parity code Da4 of the target sector Sk into the parallel signal Bp0. Then, the demodulation unit 15 demodulates the parallel signal Bp0.

Step 6: The memory control unit 2 is the decoder
The parallel signal Bp demodulated by 1 is arranged in the buffer area 3b of the RAM 3. Step 7: When the error detection unit 4 detects a code error in the data Da3, the memory control unit 2 causes the buffer area 3b of the RAM 3
The array in is output to the error correction unit 5. The error correction unit 5 corrects the code error of the data Da3 based on the input array. After that, the memory controller 2 outputs the error-corrected data Da3
Are rearranged in the buffer area 3b of the RAM3. Step 8: The memory control unit 2 outputs the parallel signal Bp in the buffer area 3b of the RAM 3 to the host interface 6. The host interface 6 transfers the input parallel signal Bp to the host Hs.

The data reproducing circuit 10 according to the first embodiment executes the following steps 9 and 10 in parallel with the above steps 4 and 5. Step 9: The sample output start down counter 20a decreases the count value in synchronization with the write clock WCK from the preset completion of the data input prediction time ΔTa. Count value is 0
When it reaches, the sample output start down counter 20a outputs a start signal S1 to start the serial / parallel converter 7 and the sample output stop down counter 20b. The serial / parallel converter 7 starts converting the bit stream Bs from the portion corresponding to the pad P of the k-th sector Sk into a parallel signal. The parallel signal is the sample signal SMP
Are sequentially stored from the top address of the work area 3w of the RAM3.

Step 10: The sample output stop down counter 20b outputs the count value preset to the constant count value ΔTb from the input of the start signal S1 to the write clock WC.
Decrease by 1 bit in synchronization with K. When the count value reaches 0, the sample output stop down counter 20b displays the stop signal S
2 is output and the serial / parallel converter 7 is stopped. As a result, at least a portion corresponding to the parity code Da4 of the k-th sector Sk, and further up to a portion of the k-th gap Gk immediately after that are converted into parallel signals and stored in the work area 3w of the RAM3 as the sample signal SMP. It

However, since the data sync detector 13 has succeeded in detecting the data sync Da2 for the kth sector Sk, it does not output the shifter activation signal S3. That is, when the data sync detection unit 13 succeeds in detecting the data sync Da2,
The N-bit shifter 8 does not read the sample signal in the work area 3w of RAM3.

(B) When the target ID sync Id2 can be detected but the target data sync Da2 cannot be detected: In the example shown in FIG. 7, the kth sector Sk is followed by the next sector S
(k + 1) is set to the target sector. (k + 1) th sector
In S (k + 1), unlike the kth sector Sk, data sync
Da2 is damaged and cannot be detected.

Step 1 to Step 4: From the detection of the preamble Id1 of the ID field Id by the preamble detection unit 11 to the turning on of the data sync detection window Wd by the data sync down counter 18, the above steps 1 to 4 of (A) are performed. It is executed as before. Step 5: Unlike the step 5 of (A) above, the data sync detection unit 13 cannot detect the data sync Da2 during the ON period of the data sync detection window Wd. Therefore, the data sync detection unit 13 does not output the data sync detection signal SYd.

Step 9 and Step 10: In parallel with Step 4 and Step 5, the sample signal SMP is changed by the serial / parallel converter 7 etc. to the work of the RAM 3 as in Step 9 and Step 10 of (A) above. Stored in area 3w.

When the data reproducing circuit 10 according to the first embodiment fails in detecting the data sync Da2, it searches for the target data Da3 and the parity code Da4 from the sample signal SMP in the work area 3W of the RAM3 as follows. FIG. 8 is a flowchart of the search operation. Step 11: The data sync detector 13 outputs the shifter activation signal S3 at the same time as the input of the stop signal S2. As a result, the preamble detector 11 and the ID sync detector 12 are stopped, and the N-bit shifter 8 is activated. Step 12: The N-bit shifter 8 sets the number of shift bits to 0.

Step 13: The N-bit shifter 8 reads the sample signal SMP of the work area 3w of the RAM 3 through the memory controller 2. At that time, since the number of shift bits is 0, the N-bit shifter 8 reads the sample signal SMP of the work area 3w of the RAM 3 from the 14th address to the (14 + 531) th address in order. Here, the data amount of the sample signal stored from the first address to the 13th address of the work area 3w is 14 bytes = 112 bits,
It is equal to the sum of the data amounts of the pad P (32 bits), the preamble Da1 (64 bits) of the data field Da, and the data sync Da2 (16 bits). Furthermore, from the 14th address (14 + 5
The data amount up to the 31) th address is 532 bytes,
It is equal to the sum of the data amounts of data Da3 (4096 bits) and parity code Da4 (160 bits). The N-bit shifter 8 uses the read 532-byte sample signal as it is, and the decoder 1
It is output to the demodulation unit 15 therein. The 532-byte sample signal output from the N-bit shifter 8 will be simply referred to as a sample hereinafter. Especially, 14 to (14 + 53) of the work area 3w of RAM3
The sample signal in the 1) th address range is called the first sample. As mentioned above, the bits of the first sample are not shifted by the N-bit shifter 8.

Step 14: The demodulator 15 demodulates the sample input from the N-bit shifter 8. The memory control unit 2 stores the sample in the buffer area 3b of the RAM 3. Step 15: The error detector 4 detects a code error of the sample stored in the buffer area 3b of the RAM 3. Step 16: When the error detection unit 4 detects no code error, the sample stored in the buffer area 3b of the RAM 3 is regarded as the data Da3 and the parity code Da4 of the (k + 1) th sector S (k + 1). Step 17: The memory control unit 2 outputs the sample of the buffer area 3b of the RAM 3 to the host interface 6.
Host interface 6 inputs the input sample to host Hs
Transfer to. After that, the data reproducing circuit 10 selects the target sector.
It is set next to the (k + 1) th sector S (k + 1) and data reproduction is restarted.

Step 18: The error detecting section 4 executes the step 1
When the sample code error is detected in step 5, the control signal CTL is set to N
Output to bit shifter 8. As a result, the N-bit shifter 8 changes the shift bit number by the bus selector 84 to +1. Thereafter, each time step 18 is repeated, the number of shift bits is further −1, +2, −2, +3, −3, ... + N,
It is changed in the order of −N. Steps 13-18: N-bit shifter 8 shifts the first sample by the number of shift bits. Demodulation and buffer area 3b of RAM3
Storing to and error detection are repeated in the same manner as above. If no code error is detected for any sample, that sample is forwarded to host Hs.

Step 19: When the number of shift bits is -N, when a code error is detected in the sample, the data reproducing circuit 10 stops the reproduction of the target data. Step 20: The data reproduction circuit 10 outputs a predetermined reproduction error signal to the host Hs to notify the stop of the reproduction of the target data.

The target data Da3 and the parity code Da4 are practically always included in the sample signal of the work area 3w of the RAM3. Therefore, the data reproducing circuit 10 according to the first embodiment can search for the target data Da3 from the sample signal in the work area 3w of the RAM3 by the loop of steps 13 to 18 described above. Further, the time required to find the target data Da3 from the sampled signal is generally shorter than the time required for the retry in the conventional FDD. Therefore, when the FDD according to the first embodiment fails to detect the target data sync Da2, the target data Da3 can be transferred to the host Hs faster than the retry is executed for the sector.

The FDD according to the first embodiment does not execute the retry in the above (B). In addition, when the detection of the data sync Da2 fails, the retry may be executed in parallel with the same operation as the above (B). In that case, compared to the conventional FDD, the target data can be found in the sample signal by the start of the retry. As a result, conventional FDD
The number of retries can be further reduced.

(C) When the target ID sync Id2 cannot be detected: The bit stream Bs is the same as in (A) and (B) above.
Assume a time corresponding to the kth sector Sk to the (k + 1) th sector S (k + 1). Furthermore, the (k + 1) th sector S (k
In +1), it is assumed that the ID sync Id2 cannot be detected because it is damaged due to scratches on the disk D or magnetic deterioration.

Step 0: (k + 1) th sector S (k + 1)
As for the ID sync detection unit 12, the ID sync detection unit 12 fails to detect the ID sync Id2 during the ON period of the ID sync detection window Wi. At that time, the FDD according to the first embodiment sets the target sector 17 to the k-th sector Sk and starts retrying to the target sector.

FIG. 9 is a timing chart of the bit stream Bs input to the decoder 1 and each signal in the decoder 1 at the time of retry. Step 1: The preamble detection unit 11 makes the k-th sector Sk
The preamble Id1 of the ID field Id of
Turn on the ID sync detection window Wi. Step 2: Subsequently, the ID sync detection unit 12 detects the ID sync Id2 and outputs the ID sync detection signal SYi. This activates the serial / parallel converter 14 and the sector coincidence detector 16 to demodulate IDId3. Step 3: The sector coincidence detection unit 16 detects the coincidence between the sector number in IDId3 and the sector number of the target sector, and outputs the first load signal Td and the third load signal Ts.

At the time of retry, unlike the above (A) and (B), the target data sync input predicted time ΔT2 is preset in the data sync down counter 18 by the first load signal Td. Here, the target data sync input estimated time Δ
T2 is a predetermined length from the predicted time from the output of the first load signal Td by the sector coincidence detection unit 16 to the input to the decoder 1 of the data sync Da2 of the target (k + 1) th sector S (k + 1) It's a short time. On the other hand, the third load signal Ts presets the target data input prediction time ΔTa1 to the sample output start down counter 20a. The target data input predicted time ΔTa1 is calculated based on the output of the third load signal Ts from the sector coincidence detection unit 16 to the target (k + 1) th sector S (k
It is the estimated time until the input of the pad P of (+1) to the serial / parallel converter 7 is started.

Step 4: The data sync down counter 18 decrements the count value in synchronization with the write clock WCK from the preset completion of the target data sync input predicted time ΔT2. When the count value reaches 0, the data sync down counter 18 turns on the data sync detection window Wd. The data sync detection unit 13 detects the data sync Da2 during the ON period of the data sync detection window Wd. If data sync Da2
Is detected, the data Da3 and the parity code Da4 of the (k + 1) th sector S (k + 1) are demodulated as in steps 5 to 8 of (A) above. However, in the example shown in FIG. 9, since the data sync detection unit 13 cannot detect the data sync Da2 for the (k + 1) th sector S (k + 1), the data sync detection signal SYd is not output.

Step 9: In parallel with the above step 4, the sample output start down counter 20a decreases the count value in synchronization with the write clock WCK from the preset completion of the target data input prediction time ΔTa1. When the count value reaches 0, the sample output start down counter 20a outputs a start signal S1 to start the serial / parallel converter 7 and the sample output stop down counter 20b. The serial / parallel converter 7 converts the bit stream Bs into (k + 1)
The conversion from the portion corresponding to the pad P of the th sector S (k + 1) to a parallel signal is started. The converted parallel signal is stored as a sample signal SMP in order from the top address of the work area 3w of the RAM3.

Step 10: The sample output stop down counter 20b outputs the count value preset to the constant count value ΔTb from the input of the start signal S1 to the write clock WC.
Decrease by 1 bit in synchronization with K. When the count value reaches 0, the sample output stop down counter 20b displays the stop signal S
2 is output and the serial / parallel converter 7 is stopped. As a result, a part of the (k + 1) th gap G (k + 1) is converted into a parallel signal, and the sample signal SMP is R
It is stored in the work area 3w of AM3.

Hereinafter, the data reproducing circuit 10 according to the first embodiment.
Is the target data Da3 and the parity code Da4 from the sample signal SMP in the work area 3W of RAM3.
Search in the same way as steps 11 to 20 in (B). The description of the search operation is based on that of FIG. 8 and (B) above.

The target data Da3 and the parity code Da4 are practically always included in the sample signal of the work area 3w of the RAM3. Therefore, the data reproducing circuit 10 according to the first embodiment can search for the target data Da3 from the sample signal in the work area 3w of the RAM3 by the loop of steps 13 to 18 described above. Further, the time required to find the target data Da3 from the sampled signal is generally shorter than the time required for the retry in the conventional FDD. Therefore, when the FDD according to the first embodiment fails to detect the target ID sync Id2, the target data Da3 can be transferred to the host Hs faster than repeatedly executing the retry for the sector.

At the time of retry in (C) above, the data sync down counter 18 and the sample output start down counter
It is assumed that the count correction unit 21 inputs the detection signal IND from the index hole detection unit IHD during each counting of 20a. At that time, the count correction unit 21 replaces the count value of the data sync down counter 18 with the first correction prediction time ΔT21 and the count value of the sample output start down counter 20a with the second correction prediction time ΔTa2. Each counter newly counts the replaced count value. Thus, each predicted time is modified based on the detection of index holes.

As described above, the data reproducing circuit 10 according to the first embodiment, in parallel with the data demodulation by the decoder 1,
A part of the bit stream Bs is stored in the work area 3w of the RAM3. As a result, the ID sync Id2 of the target sector
Alternatively, when the detection of the data sync Da2 fails, the target data Da3 and the parity code Da4 can be extracted from the work area 3w of the RAM3. As a result, the FDD according to the first embodiment
Since the number of retries can be reduced as compared with the conventional FDD in which only the retries are repeated, the data reproduction time can be shortened.

In the first embodiment, when the error detecting unit 4 does not detect a code error in the sample read from the work area 3w of the RAM 3, the sample is regarded as the target data and parity code. In addition, when the error detection unit 4 detects a code error in the above sample, but the number of code errors detected by the error detection unit 4 is within the error correctable range, the sample is set as the target data and It may be regarded as a parity code.

Furthermore, at the end of error correction by the error correction unit 5, the data in the buffer area 3b of the RAM 3 is
The error detection unit 4 may perform error detection again. Thereby, the accuracy of detecting a code error in data can be improved.

<< Second Embodiment >> FIG. 10 is a block diagram of an FDD according to a second embodiment of the present invention. In FIG. 10, the same components as those of the data reproducing circuit 10 (FIG. 1) according to the first embodiment are designated by the same reference numerals as those in the first embodiment. Further, the description of the first embodiment is cited for the description of those similar components.

The data reproducing circuit 10A according to the second embodiment differs from the data reproducing circuit 10A according to the first embodiment in the decoder 1A and the error detector 4A. The error detection unit 4A detects a code error of the parallel signal Bp demodulated by the decoder 1A, and outputs information about the detected code error to the memory control unit 2 as in the first embodiment.
Output to. Further, the error detector 4A outputs an error detection end signal END to the decoder 1A each time the error detection is completed.

FIG. 11 is a block diagram of the decoder 1A. The preamble detection unit 11A, the ID sync detection unit 12A, and the data sync detection unit 13A are the same as those of the first embodiment except that they do not have a function for the shifter activation signal S3 (FIG. 6).

The sector coincidence detection unit 16A is activated by the input of the ID sync detection signal SYi, and detects the code error of the IDId3 demodulated by the demodulation unit 15. Further, when the code error is not detected, the sector number in IDId3 is compared with the sector number of the target sector 17. When the coincidence of both sector numbers is successfully detected, the sector coincidence detection unit 16A outputs the first load signal Td to the data sync down counter 18A. Further, the sector coincidence detection unit 16A uses the first load signal T
Simultaneously with the output of d, the sector coincidence detection signal Se is output to the count determination unit 22 at the first retry, and the second load signal Tp is output to the pseudo data sync down counter 19 at the second retry.

During normal reproduction, the data sync down counter 18A is preset with a count value at the data sync input prediction time ΔT0 by the input of the first load signal Td.

At the first retry, the data sync down counter 18A presets the count value to the second target data sync input predicted time ΔT3 by the input of the count decision signal Te from the count decision unit 22. Here, the second target data sync input predicted time ΔT3 is the count determination unit.
The time from the output of the count determination signal Te by 22 to the input of the target data sync Da2 to the decoder 1A is shorter than the predicted time by a predetermined length. The reason why it is shorter by the predetermined length is the same as the above reason for the data sync input prediction time ΔT0. The second target data sync input predicted time ΔT3 is represented by the number of clocks of the write clock WCK, and is determined by the count determination unit 22 based on the physical format of FIG.

At the second retry, the data sync down counter 18A presets the count value to the target data sync input predicted time ΔT2 by the input of the first load signal Td.

The data sync down counter 18A decrements the count value by 1 bit at each rising edge of the pulse of the write clock WCK. Furthermore, when the count value reaches 0,
The data sync detection window Wd is turned on for a predetermined number of clocks.

The pseudo data sync down counter 19 is a down counter and decrements the count value by 1 bit at each rising edge of the pulse of the write clock WCK. Further, when the count value reaches 0, the pseudo data sync Sp is output to the data sync detection unit 13A. The pseudo data sync down counter 19 is preset with the count value at the pseudo data sync input predicted time ΔT1 by the input of the second load signal Tp. Here, the pseudo data sync Sp is a signal for instructing the data sync detection unit 13A to output the data sync detection signal SYd regardless of the detection of the data sync Da2. The pseudo data sync generation time ΔT1 is a predicted time from the output of the second load signal Tp by the sector coincidence detection unit 16A to the input of the target data sync Da2 to the decoder 1A. That is, the pseudo data sync generation time ΔT1 is longer than the target data sync input predicted time ΔT2 and shorter than the target data sync input predicted time ΔT2 plus the ON period of the data sync detection window Wd. Pseudo data sync generation time Δ
T1 is represented by the number of clocks of the write clock WCK, and is determined by the sector coincidence detection unit 16 based on the above physical format.

At the time of retry, the count correction unit 21A corrects the count values of the data sync down counter 18A and the pseudo data sync down counter 19 for each input of the detection signal IND from the index hole detection unit IHD. The count value of the data sync down counter 18A is
Time from the successful detection of the index hole IH to the input of the target data sink Da2 to the decoder 1A by a predetermined length shorter than the predicted time (first modified predicted time) ΔT21
Is replaced by On the other hand, pseudo data sync down counter
The count value of 19 is the estimated time from the successful detection of the index hole IH to the input of the target data sync Da2 to the decoder 1A (pseudo data sync correction generation time).
Replaced by ΔT11.

At the time of retry, the count determination unit 22 is activated by the input of the sector coincidence detection signal Se from the sector coincidence detection unit 16A. Furthermore, the error detection end signal from the error detection unit 4A
By inputting END, the second target data sync input predicted time ΔT3 is calculated. Moreover, the count determination signal Te is output to the data sync down counter 18A, and the count value is preset to the second target data sync input predicted time ΔT3.

<Reproduction of Data by Data Reproducing Circuit 10A> With the above components, the data reproducing circuit 10A demodulates the bit stream Bs as follows and transfers it to the host Hs: FIG. 3 is a timing chart of the bit stream Bs input to 1A and each signal in the decoder 1A. The bit stream Bs in FIG. 12 corresponds to the serial signal read from the kth sector Sk, the kth gap Gk, and the (k + 1) th sector S (k + 1).
Here, for the kth sector Sk, both the ID sync Id2 and the data sync Da2 can be detected, while
It is assumed that the ID sync Id2 cannot be detected for the (k + 1) th sector S (k + 1).

When the target sector is set to the kth sector Sk, the decoder 1A executes from the detection of the preamble Id1 of the ID field Id by the preamble detection unit 11A to the output of the data sync detection signal SYd by the data sync detection unit 13A. It operates as in Example 1. Further, as in the first embodiment, the serial / parallel conversion unit 14 is activated to convert the data Da3 and the parity code Da4 of the target sector Sk into the parallel signal Bp0. Then, the demodulation unit 15 demodulates the parallel signal Bp0.

The memory control unit 2 arranges the parallel signal Bp demodulated by the decoder 1A in the buffer area 3b of the RAM 3. When the error detection unit 4A detects a code error in the data Da3, the memory control unit 2 displays the buffer area of the RAM3.
The array in 3b is output to the error correction unit 5. The error correction unit 5 corrects the code error of the data Da3 based on the input array. After that, the memory controller 2 outputs the error-corrected data Da3
Are rearranged in the buffer area 3b of the RAM3. After the above processing, the memory control unit 2 outputs the parallel signal Bp in the buffer area 3b of the RAM 3 to the host interface 6. Host interface 6 is parallel signal Bp input
To host Hs.

Next, the target sector is the (k + 1) th sector
It is set to S (k + 1). The preamble detection unit 11A detects the preamble Id1 of the ID field Id and turns on the ID sync detection window Wi. However, the ID sync detector 12A
Since the ID sync Id2 cannot be detected during the ON period of the D sync detection window Wi, the ID sync detection signal SYi is not output.
At that time, the FDD according to the second embodiment sets the target sector to the immediately preceding sector, that is, the k-th sector Sk, and starts the retry.

FIG. 13 is a timing chart of the bit stream Bs input to the decoder 1A and each signal in the decoder 1 at the first retry. Preamble detection unit 11A
From the detection of the preamble Id1 of the ID field Id of the kth sector Sk to the detection of the error in the data Da3 by the error detection unit 4A is the same as in normal reproduction. Further, during the first retry, the sector match detection unit 16A outputs the sector match detection signal Se at the same time as the output of the first load signal Td. This activates the count determination unit 22.

The error detector 4A performs error detection on the data Da3 of the target sector Sk, as in the normal reproduction. At the end of the error detection, the error detection unit 4A outputs the error detection end signal END
Is output to the count determination unit 22. Thereby, the count determination unit 22 outputs the count determination signal Te to the data sync down counter 18A and presets the count value to the second target data input prediction time ΔT3.

The data sync down counter 18A decrements the count value in synchronization with the write clock WCK from the completion of presetting of the second target data sync input prediction time ΔT3. When the count value reaches 0, the data sync down counter 18A turns on the data sync detection window Wd. The data sync detection unit 13A detects the data sync Da2 during the ON period of the data sync detection window Wd. Data sync detector 13A
Data sync Da2 for the (k + 1) th sector S (k + 1)
When the detection of is successful, the data Da3 and the parity code Da4 of the (k + 1) th sector S (k + 1) are the same as in the normal reproduction.
Demodulated. On the other hand, when the data sync detection unit 13A fails to detect the data sync Da2, the data sync detection signal SYd
Is not output. Therefore, the FDD according to the second embodiment sets the target sector to the immediately preceding sector, that is, the k-th sector Sk, and restarts the retry.

It is assumed that the count correction unit 21A inputs the detection signal IND from the index hole detection unit IHD during the count of the data sync down counter 18A at the first retry. At that time, the count correction unit 21A changes the count value of the data sync down counter 18A to the first correction estimated time ΔT.
Replace with 21. The data sync down counter 18A newly counts the replaced count value. In this way, the estimated time is corrected.

FIG. 14 is a timing chart of the bit stream Bs input to the decoder 1A and each signal in the decoder 1 at the second retry. Preamble detection unit 11
From the detection of the preamble Id1 of the ID field Id of the kth sector Sk by A to the output of the first load signal Td by the sector coincidence detection unit 16A, it is the same as in normal reproduction. Furthermore, at the time of the second retry, the sector match detection unit
16A outputs the second load signal Tp simultaneously with the output of the first load signal Td.

At the second retry, the first load signal Td
As a result, the target data sync input predicted time ΔT2 is preset in the data sync down counter 18A. The data sync down counter 18A counts the target data sync input predicted time ΔT2 and turns on the data sync detection window Wd. On the other hand, the pseudo data sync down counter 19 is preset with the pseudo data sync generation time ΔT1 by the second load signal Tp. Pseudo data sync down counter 19
Reduces the count value in synchronization with the write clock WCK from the preset completion of the pseudo data sync generation time ΔT1.
When the count value reaches 0, the pseudo data sync Sp is output. As a result, the data sync detection unit 13A outputs the data sync detection signal SYd. After that, the demodulation of the data Da3 and the parity code Da4 of the target sector from the bit stream Bs input to the decoder 1 is attempted in the same manner as in normal reproduction. Similar to the above, the demodulated data is determined as target data based on the detection of a code error by the error detection unit 4.

It is assumed that the count correction unit 21A inputs the detection signal IND from the index hole detection unit IHD during the respective counts of the data sync down counter 18A and the pseudo data sync down counter 19 during the second retry. . At that time, the count correction unit 21A replaces the count value of the data sync down counter 18A with the first correction predicted time ΔT21 and the count value of the pseudo data sync down counter 19 with the pseudo data sync correction generation time ΔT11. Each counter newly counts the replaced count value. In this way, each estimated time is corrected.

Further, when the error detection unit 4 continues to detect a code error each time the retry is repeated a predetermined number of times, the data reproducing circuit 10A according to the second embodiment determines that the data of the target sector cannot be reproduced, and the sector To stop playback from.

As described above, the FDD according to the second embodiment is
When the ID sync Id2 detection fails and retry is performed, I
The time from the end of the error detection for the data Da3 of the sector before the sector where the detection of the D sync Id2 has failed to the input of the target data sync Da2 is predicted. As a result, the prediction time can be generally shortened as compared with the conventional FDD that predicts the time from the time when the ID sync Id2 is detected, so that the error can be reduced as compared with the related art. Therefore, the detection accuracy of the target data sync Da2 can be improved. As a result, the number of retries can be reduced, and the target data Da3 can be reproduced faster than before.

In the second embodiment, at the time of the first retry, the sector immediately before the sector in which the ID sync detection has failed is set as the target sector. In addition, as the target sector at the time of retry, two or more sectors before the sector in which the ID sync detection has failed may be set.

In the second embodiment, the pseudo data sync is generated at the second retry. Alternatively, the pseudo data sync may be generated after the retry is repeated three times or more.

<< Third Embodiment >> FIG. 15 is a block diagram of an FDD according to a third embodiment of the present invention. In FIG. 15, the same components as those of the data reproducing circuit according to the first and second embodiments are denoted by the same reference numerals as those of the first and second embodiments. Furthermore,
The descriptions of those similar components are based on those of the first and second embodiments.

The data reproducing circuit 10B according to the third embodiment is different from the first and second embodiments in that the decoder 1B and the error detecting section 4B are different.
About different. The error detection unit 4B is the same as the first and second embodiments except that it has no output signal other than the signal to the memory control unit 2.

FIG. 16 is a block diagram of the decoder 1B. I
The D sync detector 12B has the same I as in the first and second embodiments.
D sync Id2 is detected. Furthermore, the ID sync detector 12B
Outputs the ID sync detection signal SYi to the serial / parallel conversion unit 14 and the sector coincidence detection unit 16B when the ID sync Id2 is successfully detected. In addition, at the time of retry, the second ID sync detection signal Ci is output to the count correction unit 21B.

At the time of retry, the count correction unit 21B corrects the count values of the data sync down counter 18 and the pseudo data sync down counter 19 for each input of the detection signal IND from the index hole detection unit IHD. The count value of the data sync down counter 18 is determined by the decoder after the index hole IH is detected successfully.
Time until the target data sync Da2 input by 1B is shorter than the predicted time by a predetermined length (first modified predicted time) ΔT21
Is replaced by On the other hand, pseudo data sync down counter
The count value of 19 is the target data sync Da2 by the decoder 1B from the time when the detection of the index hole IH is successful.
Until the input of, the predicted time (pseudo data sync correction generation time) ΔT11 is replaced.

Furthermore, when the count correction unit 21B retries,
Second ID sync detection signal C from the ID sync detector 12B
Each count value of the data sync down counter 18 and the pseudo data sync down counter 19 is corrected for each input of i. The count value of the data sync down counter 18 is shorter than the predicted time from the input of the second ID sync detection signal Ci from the ID sync detector 12B to the input of the target data sync Da2 by the decoder 1B by a predetermined length. (Target data sync correction input estimated time) Replaced by ΔT4. On the other hand, the count value of the pseudo data sync down counter 19 is the estimated time from the input of the second ID sync detection signal Ci from the ID sync detector 12B to the input of the target data sync Da2 by the decoder 1B (second (Pseudo data sync correction generation time) of ΔT12.

<Reproduction of Data by Data Reproducing Circuit 10B> With the above components, the data reproducing circuit 10B demodulates the bit stream Bs as follows and transfers it to the host Hs: normal reproducing operation is the same as that of the second embodiment. Since it is the same, the description is based on that of the second embodiment.

FIG. 17 is a timing chart of the bit stream Bs input to the decoder 1B and each signal in the decoder 1B at the time of retry. The bitstream Bs in FIG. 17 is
(k−1) th sector S (k−1) to (k + 1) th sector S (k
It corresponds to +1). Here, the (k−1) th sector S (k
−1) and for the kth sector Sk, both the ID sync Id2 and the data sync Da2 can be detected, and (k + 1)
It is assumed that the ID sync Id2 cannot be detected for the th sector S (k + 1).

In the third embodiment, at the time of retry, the target sector is I
The (k + 1) th sector S (k +) that failed to detect the D sync Id2
Two sectors before 1), that is, the (k−1) th sector
It is set to S (k−1). At the time of retry, from the detection of the preamble Id1 of the ID field Id by the preamble detection unit 11A to the output of the first load signal Td and the second load signal Tp by the sector coincidence detection unit 16B, the decoder 1B uses Operates as in Example 2. However, the second load signal Tp is output not at the first retry but at the second retry in the third embodiment. In FIG. 17, the second load signal Tp and the pseudo data sync Sp are shown. However, they are for the second retry and do not exist for the first retry.

The data sync down counter 18 decrements the count value in synchronization with the write clock WCK from the preset completion of the target data sync input prediction time ΔT2. When the count value reaches 0, the data sync down counter 18 turns on the data sync detection window Wd. Data sync detector 13
A is data sync D while data sync detection window Wd is on
Detect a2. When the data sync detection unit 13A succeeds in detecting the data sync Da2 for the (k + 1) th sector S (k + 1), the data Da3 and the parity code Da4 of the (k + 1) th sector S (k + 1) are different from those during normal reproduction. It is also demodulated. On the other hand, when the data sync detection unit 13A fails to detect the data sync Da2, the data sync detection signal SYd is not output. Therefore, the FDD according to the third embodiment selects the target sector as (k−
1) Set to sector S (k−1) th and start retry again.

At retry, data sync down counter
It is assumed that the count correction unit 21B inputs the detection signal IND from the index hole detection unit IHD during the counting of 18.
At that time, the count correction unit 21B replaces the count value of the data sync down counter 18 with the first corrected prediction time ΔT21. The data sync down counter 18 newly counts the replaced count value. In this way, the target data sync input predicted time ΔT2 is corrected based on the detection of the index hole.

Further, at the time of retry, it is assumed that the ID sync detector 12B succeeds in detecting the ID sync Id2 of the k-th sector Sk while the data sync down counter 18 is counting. At that time, the ID sync detection unit 12B outputs the second ID sync detection signal Ci to the count correction unit 21B. As a result, the count correction unit 21B causes the data sync down counter 1
The count value of 8 is replaced with the target data sync correction input predicted time ΔT4. The data sync down counter 18 newly counts the replaced count value. In this way, the target data sync input predicted time ΔT2 is corrected based on the detection of the ID sync Id2.

At the second retry, in addition to the above operation, the pseudo data sync down counter 19 sets the write clock from the preset completion of the pseudo data sync generation time ΔT1.
Decrements the count value in synchronization with WCK. When the count value reaches 0, the pseudo data sync down counter 19 outputs the pseudo data sync Sp. As a result, the data sync detection unit 13A outputs the data sync detection signal SYd. Bit stream Bs after output of data sync input detection signal SYd
Are regarded as the data Da3 and the parity code Da4 of the (k + 1) th sector S (k + 1) and demodulated.

It is assumed that the count correction unit 21B inputs the detection signal IND from the index hole detection unit IHD while the pseudo data sync down counter 19 is counting. At that time,
The count correction unit 21B sets the count value of the pseudo data sync down counter 19 to the pseudo data sync correction generation time ΔT1.
Replace with 1. The pseudo data sync down counter 19 newly counts the replaced count value. Thus
The pseudo data sync generation time ΔT1 is modified based on the detection of the index hole.

Further, the pseudo data sync down counter 19
ID sync detector 12B detects the kth sector
It is assumed that the Sk ID sync Id2 is successfully detected. At that time, the ID sync detection unit 12B outputs the second ID sync detection signal C
i is output to the count correction unit 21B. Thereby, the count correction unit 21B changes the count value of the pseudo data sync down counter 19 to the second pseudo data sync correction generation time ΔT1.
Replace with 2. The pseudo data sync down counter 19A newly counts the replaced count value. Thus
The pseudo data sync generation time ΔT1 is modified based on the detection of the ID sync Id2.

As described above, in the data reproducing circuit 10B according to the third embodiment, when the detection of the ID sync Id2 fails and the retry is performed, the target data sync input prediction time ΔT2 and the pseudo data sync generation time ΔT1 are It is modified based on the index hole and ID sync Id2 detected during counting. Thereby, the error generated during the above counting can be reduced. Therefore, the target data sync Da
The detection accuracy of 2 can be improved. As a result, the number of retries can be reduced, and the target data Da3 can be reproduced faster than before.

In the third embodiment, at the time of retry, the sector two before the sector in which the ID sync detection has failed is set as the target sector. In addition, as the target sector at the time of retry, three or more sectors before the sector in which the ID sync detection has failed may be set.

In the third embodiment, the pseudo data sync is generated at the second retry. Alternatively, the pseudo data sync may be generated after the retry is repeated three times or more.

Example 4 FD according to Example 4 of the present invention
D is the same as in the third embodiment except for the internal configuration of the decoder 1B. Therefore, the descriptions of those similar components are based on those of the third embodiment.

FIG. 18 is a block diagram of a decoder 1B according to the fourth embodiment. In FIG. 18, the same components as those of the data reproducing circuits according to the first, second and third embodiments are designated by the same reference numerals. Furthermore, the description of those similar components is based on those of the first, second, and third embodiments.

The data sync detector 13B detects the data sync Da2 during the ON periods of the data sync detection window Wd and the retry data detection window Wd0. Here, the data detection window Wd0 during retry is the data sync detection window Wd.
It is the same signal as d. The data sync detection unit 13B outputs the data sync detection signal SYd to the serial / parallel conversion unit 14 when the data sync Da2 is successfully detected during the ON period of the data sync detection window Wd. On the other hand, when the data sync detection window Wd0 during retry succeeds in detecting the data sync Da2 during the ON period, it outputs the second data sync detection signal Cd to the count correction unit 21C instead of outputting the data sync detection signal SYd. To do.

The sector coincidence detection unit 16C is activated by the input of the ID sync detection signal SYi, and detects the code error of the IDId3 demodulated by the demodulation unit 15. Further, when the code error is not detected, the sector number in IDId3 is compared with the sector number of the target sector 17. When the match between both sector numbers is successfully detected, the sector match detecting unit 16C outputs the first load signal Td to the data sync down counter 18. As a result, the data sync input predicted time ΔT0 is preset in the data sync down counter 18 during normal reproduction, and the target data sync input predicted time ΔT2 is preset during retry.

The sector coincidence detection unit 16C outputs the fourth load signal Td0 for each input of the ID sync detection signal SYi at the time of the first retry and the data sync down counter 23 at the time of retry.
Output to. As a result, the data sync input estimated time ΔT7 at retry is set to the data sync down counter at retry.
Preset to 23. Here, the data sync input predicted time ΔT7 at the time of retry is the ID by the ID sync detection unit 12A.
This is a time shorter than the predicted time from the output of the sync detection signal SYi to the input of the data sync Da2 by the decoder 1B by a predetermined length. The reason why it is shorter by the predetermined length is the same as the data sync input prediction time ΔT0.

At the time of the second retry, the sector coincidence detection unit 16C outputs the second load signal Tp to the pseudo data sync down counter 19 simultaneously with the output of the first load signal Td. Thereby, the pseudo data sync generation time ΔT1 is preset in the pseudo data sync down counter 19.

At the time of retry, the count correction unit 21C counts the count values of the data sync down counter 18 and the pseudo data sync down counter 19 for each input of the detection signal IND from the index hole detection unit IHD to the count of the third embodiment. Correction is performed in the same manner as the correction unit 21B.

At the time of retry, the count correction unit 21C receives the second data sync detection signal Cd from the data sync detection unit 13B.
For each input of, the count values of the data sync down counter 18A and the pseudo data sync down counter 19 are corrected. The count value of the data sync down counter 18 is a time shorter than the predicted time from the input of the second data sync detection signal Cd from the data sync detection unit 13B to the input of the target data sync Da2 by the decoder 1B by a predetermined length. (Second and third target data sync correction input prediction time) Replaced by ΔT5 and ΔT6. On the other hand, the count value of the pseudo data sync down counter 19 is the estimated time from the input of the second data sync detection signal Cd from the data sync detection unit 13B to the input of the target data sync Da2 by the decoder 1B (third And fourth pseudo data sync correction generation time) ΔT13 and ΔT14.

Data Sync Down Counter 23 at Retry
Is a down counter similar to the data sync down counter 18, and decrements the count value by 1 bit at each rising edge of the pulse of the write clock WCK. Further, when the count value reaches 0, the data sync detection window Wd0 during retry is turned on for a predetermined number of clocks.

<Reproduction of Data by Data Reproducing Circuit 10B> With the above components, the data reproducing circuit 10B demodulates the bit stream Bs as follows and transfers it to the host Hs: Normal reproducing operation is the same as that of the second embodiment. Since it is the same, the description is based on that of the second embodiment.

FIG. 19 is a timing chart of the bit stream Bs input to the decoder 1B and each signal in the decoder 1B at the time of retry. The bitstream Bs in Fig. 19 is
(k−1) th sector S (k−1) to (k + 1) th sector S (k
It corresponds to +1). Here, the (k−1) th sector S (k
−1) and for the kth sector Sk, both the ID sync Id2 and the data sync Da2 can be detected, and (k + 1)
It is assumed that the ID sync Id2 cannot be detected for the th sector S (k + 1).

In the fourth embodiment, the target sector is I
The (k + 1) th sector S (k +) that failed to detect the D sync Id2
Two sectors before 1), that is, the (k−1) th sector
Set to S (k−1). Preamble detector 1 at retry
1A detects the preamble Id1 of the ID field Id, and I
Turn on the D sync detection window Wi. The ID sync detection unit 12A detects the ID sync Id2 during the ON period of the ID sync detection window Wi. When the detection is successful, the ID sync detection unit 12A
Outputs the ID sync detection signal SYi. This activates the sector coincidence detection unit 16C. The sector coincidence detection unit 16C outputs the fourth load signal Td0 and presets the retry data sync input predicted time ΔT7 to the retry data sync down counter 23.

On the other hand, when the ID sync detection signal SYi is input, the serial / parallel converter 14 is activated and the detected I
The bit stream Bs input following the D sync Id2 is converted into a parallel signal Bp0. The demodulation unit 15 demodulates IDId3 from the parallel signal Bp0. Sector match detection unit 16C
Is the demodulated sector number in IDId3 and the target (k−1)
The sector number of the th sector S (k−1) is compared. When the coincidence of both sector numbers is detected, the sector coincidence detector 16C outputs the first load signal Td and the second load signal Tp. However, the second load signal Tp is output not at the first retry but at the second retry in the fourth embodiment.
In FIG. 19, the second load signal Tp and the pseudo data sync Sp are shown. However, they are for the second retry and do not exist for the first retry.

The data sync down counter 18 decreases the count value in synchronization with the write clock WCK from the completion of presetting of the target data sync input prediction time ΔT2. When the count value reaches 0, the data sync down counter 18 turns on the data sync detection window Wd. Data sync detector 13
B is data sync D while the data sync detection window Wd is on
Detect a2. When the data sync detection unit 13B succeeds in detecting the data sync Da2 for the (k + 1) th sector S (k + 1), the data Da3 and the parity code Da4 of the (k + 1) th sector S (k + 1) are different from those during normal reproduction. It is also demodulated. On the other hand, when the data sync detection unit 13B fails to detect the data sync Da2, the data sync detection signal SYd is not output. Therefore, the FDD according to the fourth embodiment selects the target sector as (k−
1) Set to sector S (k−1) th and start retry again.

Data sync down counter 23 at retry
Reduces the count value in synchronization with the write clock WCK from the preset completion of the data sync input prediction time ΔT7 at the time of retry. When the count value reaches 0, the retry data sync down counter 23 turns on the retry data sync detection window Wd0. The data sync detection unit 13B receives the data sync D during the ON period of the data sync detection window Wd0 during retry.
Detect a2. When the data sync Da2 is successfully detected for each of the (k−1) th sector S (k−1) and the kth sector Sk, the data sync detection unit 13B corrects the count of the second data sync detection signal Cd. Output to section 21C. Thereby, the count correction unit 21C changes the count value of the data sync down counter 18 to the second target data sync correction input predicted time when the data sync Da2 of the (k−1) th sector S (k−1) is detected. ΔT5 is replaced with the third target data sync correction input predicted time ΔT6 when the data sync Da2 of the kth sector Sk is detected. The data sync down counter 18 newly counts the replaced count value. Thus, the target data sync input predicted time ΔT2 is corrected based on the detection of the data sync Da2.

[0206] While the data sync down counter 18 is counting, the count correction unit 21C causes the index hole detection unit I
It is assumed that the detection signal IND is input from HD. At that time, the count correction unit 21C replaces the count value of the data sync down counter 18 with the first correction estimated time ΔT21. The data sync down counter 18 newly counts the replaced count value. In this way, the target data sync input predicted time ΔT2 is corrected based on the detection of the index hole.

At the time of the second retry, in addition to the above operation, the pseudo data sync down counter 19 sets the write clock after completion of presetting of the pseudo data sync generation time ΔT1.
Decrements the count value in synchronization with WCK. When the count value reaches 0, the pseudo data sync down counter 19 outputs the pseudo data sync Sp. As a result, the data sync detection unit 13B outputs the data sync detection signal SYd. Bit stream Bs after output of data sync input detection signal SYd
Are regarded as the data Da3 and the parity code Da4 of the (k + 1) th sector S (k + 1) and demodulated.

It is assumed that the count correction unit 21C inputs the detection signal IND from the index hole detection unit IHD while the pseudo data sync down counter 19 is counting. At that time,
The count correction unit 21C is a pseudo data sync down counter 1
The count value of 9 is replaced with the pseudo data sync correction generation time ΔT11. The pseudo data sync down counter 19 newly counts the replaced count value. In this way, the pseudo data sync generation time ΔT1 is corrected based on the detection of the index hole.

[0209] Further, the pseudo data sync down counter 19
While counting, the count correction unit 21C inputs the second data sync detection signal Cd. At that time, the count correction unit 21
C indicates the count value of the pseudo data sync down counter 19 to the third pseudo data sync correction generation time ΔT13 when the data sync Da2 of the (k−1) th sector S (k−1) is detected.
When the data sync Da2 of the th sector Sk is detected, it is replaced with the fourth pseudo data sync correction generation time ΔT14. The pseudo data sync down counter 19 newly counts the replaced count value. In this way, the pseudo data sync generation time ΔT1 is corrected based on the detection of the data sync Da2.

As described above, in the data reproducing circuit 10B according to the fourth embodiment, when the detection of the ID sync Id2 fails and the retry is performed, the target data sync input predicted time ΔT2 and the pseudo data sync generation time ΔT1 are Corrected based on index holes and data sink Da2 detected during counting. Thereby, the error generated during the above counting can be reduced. Therefore, the target data sync
The detection accuracy of Da2 can be improved. As a result, the number of retries can be reduced, and the target data Da3 can be reproduced faster than before.

In the fourth embodiment, at the time of retry, the sector immediately before the sector in which the ID sync detection has failed is set as the target sector. In addition, as the target sector at the time of retry, three or more sectors before the sector in which the ID sync detection has failed may be set.

In the fourth embodiment, the pseudo data sync is generated at the second retry. Alternatively, the pseudo data sync may be generated after the retry is repeated three times or more.

In the above embodiment, the target sector is identified by the sector number in IDId3 according to the format of the disk D shown in FIGS. In addition to the format, for a format in which information for identifying a sector is recorded in the data Da3, the target sector may be identified from the information. Further, in the above embodiments, each down counter has a write clock.
Counted in synchronization with WCK. Alternatively, each down counter may count in synchronization with the read clock RCK. However, the phase of the read clock RCK often deviates from the bitstream Bs. Therefore, the counting of the down counter is preferably performed in synchronization with the write clock WCK.

[0214]

As described above, the data reproducing circuit of the disk reproducing apparatus according to the present invention converts the bit stream into a sample signal and RAM in parallel with the demodulation by the decoder.
To memorize. Further, when the detection of the target ID sync or the data sync fails, the target data is extracted from the sample signal stored in the RAM. Thereby, the number of retries can be reduced as compared with the conventional case. As a result, the demodulated data can be transferred to the host faster than the conventional disc reproducing apparatus.

Further, when the disc reproducing apparatus according to the present invention fails in the detection of the target ID sync and retries, the disc reproducing apparatus detects the target from the end of the error detection for the sector before the sector in which the detection of the ID sync fails. Predict the time until data sink input. As a result, the error in the input prediction time of the target data sync can be reduced as compared with the conventional disc reproducing apparatus, and the number of retries can be reduced. As a result, the demodulated data can be transferred to the host faster than the conventional disc reproducing apparatus.

Moreover, the data reproducing circuit according to the present invention is
When failing to detect the target ID sync and retrying,
The estimated input time of the target data sync is modified based on the ID sync, the data sync and the physical mark detected during the measurement. As a result, the error in the input prediction time of the target data sync can be reduced as compared with the conventional case, and the number of retries can be reduced. As a result, the demodulated data can be transferred to the host faster than the conventional disc reproducing apparatus.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a track T recorded on a disc D having a large capacity FD.

FIG. 2 is a diagram showing a physical format of one track T on a disc D.

FIG. 3 is a block diagram of an FDD according to the first embodiment of the present invention.

FIG. 4 is a memory space diagram of the RAM 3 according to the first embodiment of the present invention.

FIG. 5 is a block diagram of the inside of the N-bit shifter 8 according to the first embodiment of the present invention.

FIG. 6 is a block diagram of a decoder 1 according to the first embodiment of the present invention.

FIG. 7 is a timing chart of the bit stream Bs input to the decoder 1 and each signal in the decoder 1 in the first embodiment of the present invention.

FIG. 8 is a flowchart of an operation of searching the target data Da3 and the parity code Da4 in the sample signal SMP of the work area 3W of the RAM3 in the data reproducing circuit 10 according to the first embodiment of the present invention.

FIG. 9 is a timing chart of the bit stream Bs input to the decoder 1 and each signal in the decoder 1 at the time of retry in the first embodiment of the present invention.

FIG. 10 is a block diagram of an FDD according to a second embodiment of the present invention.

FIG. 11 is a block diagram of a decoder 1A according to a second embodiment of the present invention.

[Fig. 12] In Embodiment 2 of the present invention, the bit stream Bs and the decoder 1A input to the decoder 1A during normal reproduction.
3 is a timing chart with each signal in FIG.

FIG. 13 is a timing chart of the bit stream Bs input to the decoder 1A and each signal in the decoder 1 at the first retry in the second embodiment of the present invention.

FIG. 14 is a timing chart of the bit stream Bs input to the decoder 1A and each signal in the decoder 1 at the time of the second retry in the second embodiment of the present invention.

FIG. 15 is a block diagram of an FDD according to a third embodiment of the present invention.

FIG. 16 is a block diagram of a decoder 1B according to a third embodiment of the present invention.

FIG. 17 is a timing chart of the bit stream Bs input to the decoder 1B and each signal in the decoder 1B at the time of retry in the third embodiment of the present invention.

FIG. 18 is a block diagram of a decoder 1B according to a fourth embodiment of the present invention.

FIG. 19 is a timing chart of the bit stream Bs input to the decoder 1B and each signal in the decoder 1B at the time of retry in the fourth embodiment of the present invention.

FIG. 20 is a block diagram of a conventional disc reproducing device.

FIG. 21 is a decoder 101 in a conventional data reproduction circuit 100.
It is a block diagram of.

[Fig. 22] Fig. 22 is a timing chart of the bit stream Bs input to the decoder 101 and each signal in the decoder 101 during normal reproduction in the conventional data reproduction circuit 100.

[Fig. 23] Fig. 23 is a timing chart of the bit stream Bs and each signal in the decoder 101 when a data sync detection fails and retry is performed in the conventional data reproduction circuit 100.

[Fig. 24] Fig. 24 is a timing chart of the bit stream Bs and each signal in the decoder 101 when the ID sync detection fails and retry is performed in the conventional data reproduction circuit 100.

[Explanation of symbols]

10 Data recovery circuit D disk Bs bitstream RCK read clock IND index hole detection signal S1 serial / parallel converter start signal S2 serial / parallel converter stop signal S3 shifter start signal Bp parallel signal SMP sample signal CTL control signal B expansion bus

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kimio Idei             1 Juden Matsushita, 1-8 Koshinmachi, Takamatsu City, Kagawa Prefecture             Child Industry Co., Ltd. F-term (reference) 5D044 AB01 BC01 BC02 CC04 DE34                       DE70 FG10 FG18 GK19 GM26                       GM27

Claims (28)

[Claims] 1. A disk shape in which (a) sector synchronization signal, (b) sector identification information, (c) data synchronization signal, and (d) data are sequentially recorded in each of a plurality of sectors according to a fixed format. A decoder for converting a serial signal read by a head from a recording medium into a parallel signal for demodulation, comprising: (A) Sector synchronization signal detection for detecting the sector synchronization signal from the serial signal. Section, (B) a data synchronization signal detection section for detecting the data synchronization signal from the serial signal, (C) a serial / parallel conversion section for converting the serial signal into the parallel signal, (D) A demodulation unit for demodulating the parallel signal, (E) when the target sector synchronization signal is successfully detected,
A start control unit for outputting a start signal, and (F) when the detection of the target data synchronization signal fails,
A decoder having a shifter activation unit for outputting a shifter activation signal; a RAM for temporarily storing the parallel signal demodulated by the decoder; a memory control unit for controlling writing and reading of data to and from the RAM; Error detecting unit for detecting code error of parallel signal demodulated by decoder; Error correcting unit for correcting code error of parallel signal demodulated by decoder; No code error detected by the error detecting unit The parallel signal and the parallel signal whose code error has been corrected by the error correction unit.
From the host interface for transferring from the host to the host; (a) activated by input of the activation signal; A serial / parallel converter for temporarily storing; and (a) activated by input of the shifter activation signal, and (b) shifting the sample signal by a predetermined number of bits and outputting it to the demodulation unit. A data reproducing circuit of a disk reproducing device, which comprises a shifter of 2. The demodulator demodulates the sample signal input from the shifter; (B) the error detector detects a predetermined number or more of code errors in the demodulated sample signal. At this time, the control signal is output to the shifter; (C) the shifter changes the number of bits for each input of the control signal, and (b) the original sample signal stored in the RAM. 2. The data reproducing circuit of the disk reproducing apparatus according to claim 1, wherein the data is shifted by the changed number of bits and output to the demodulation unit. 3. The data reproducing circuit of the disk reproducing apparatus according to claim 1, further comprising a sector identification unit for identifying the target sector synchronization signal from the sector identification information demodulated by the demodulation unit. 4. The activation signal by the activation control unit based on a detection signal output by a physical mark detection unit for detecting a physical mark that is a specific shape portion on the surface of the disk-shaped recording medium. 2. The data reproducing circuit of the disk reproducing apparatus according to claim 1, further comprising a serial / parallel converter operation time adjusting unit for adjusting the timing of either or both of the output of the output and the stop of the serial / parallel converter. . 5. A disk shape in which (a) sector synchronization signal, (b) sector identification information, (c) data synchronization signal, and (d) data are sequentially recorded in each of a plurality of sectors according to a fixed format. A decoder for converting a serial signal read by a head from a recording medium into a parallel signal for demodulation, comprising: (A) Sector synchronization signal detection for detecting the sector synchronization signal from the serial signal. Section, (B) a data synchronization signal detecting section for detecting the data synchronization signal from the serial signal for a predetermined time by inputting a detection start signal, (C) for converting the serial signal to the parallel signal Serial / parallel conversion unit, (D) demodulation unit for demodulating the parallel signal, and (E) (a) end of error detection for the target sector (hereinafter referred to as target sector) From the input of the signal to the input of the target data synchronization signal by the serial / parallel converter based on the format as a target data synchronization signal input prediction time, and (b) an error about the target sector A decoder having a data synchronization signal detection control unit for outputting the detection start signal to the data synchronization signal detection unit when the target data synchronization signal input prediction time has elapsed from the input of a detection end signal; RAM for temporarily storing the generated parallel signal; Memory control unit for controlling writing and reading of data to and from the RAM; (a) Detecting a code error of the parallel signal demodulated by the decoder, (b) An error detector for outputting the error detection end signal to the decoder at the end of error detection; the decoder An error correction unit for correcting a code error of the parallel signal demodulated by the above; a parallel signal whose code error is not detected by the error detection unit; and a parallel signal whose code error is corrected by the error correction unit , A host interface for transferring the data from the RAM to the host; 6. The data reproducing circuit of the disk reproducing apparatus according to claim 5, further comprising a sector identification information error detection unit for detecting a code error of the sector identification information demodulated by the demodulation unit. 7. The data reproducing circuit of the disk reproducing apparatus according to claim 6, further comprising a sector identification unit for identifying the target sector from the sector identification information demodulated by the demodulation unit. 8. The target data synchronization signal input predicted time is based on a detection signal output by a physical mark detection unit for detecting a physical mark that is a specific shape portion of the surface of the disk-shaped recording medium. The data reproducing circuit of the disk reproducing apparatus according to claim 5, further comprising a target data synchronization signal input predicted time correcting unit for correcting. 9. A disk shape in which (a) sector synchronization signal, (b) sector identification information, (c) data synchronization signal, and (d) data are sequentially recorded in each of a plurality of sectors according to a fixed format. A decoder for converting a serial signal read by a head from a recording medium into a parallel signal for demodulation, comprising: (A) Sector synchronization signal detection for detecting the sector synchronization signal from the serial signal. Section, (B) a data synchronization signal detecting section for detecting the data synchronization signal from the serial signal for a predetermined time by inputting a detection start signal, (C) for converting the serial signal to the parallel signal A serial / parallel conversion section, (D) a demodulation section for demodulating the parallel signal, and (E) (a) the data synchronization signal after the target sector synchronization signal is successfully detected. The time until the input of the target data synchronization signal by the detection unit is predicted based on the format as the target data synchronization signal input predicted time, (b) the target from the time when the target sector synchronization signal is successfully detected. Correct the target data synchronization signal input prediction time for each input of another synchronization signal detected from the disk-shaped recording medium until the data synchronization signal input prediction time elapses, and (c) detect the target sector synchronization signal. A data synchronization signal detection control unit for outputting the detection start signal to the data synchronization signal detection unit when the target data synchronization signal input prediction time has elapsed from the time when the data synchronization signal input prediction time has passed, RAM for temporarily storing parallel signals; memory control unit for controlling writing and reading of data to and from the RAM An error detection unit for detecting a code error of the parallel signal demodulated by the decoder; an error correction unit for correcting a code error of the parallel signal demodulated by the decoder; and a code error by the error detection unit. A data reproducing circuit of a disk reproducing apparatus, comprising: a host interface for transferring a parallel signal that has not been detected and a parallel signal in which a code error is corrected by the error correction unit from the RAM to a host. 10. The data reproducing circuit of the disk reproducing apparatus according to claim 9, further comprising a sector identification unit for identifying the target sector synchronization signal from the sector identification information demodulated by the demodulation unit. 11. A data reproducing circuit of a disk reproducing apparatus according to claim 9, wherein said another synchronization signal includes said sector synchronization signal newly detected by said sector synchronization signal detecting section. 12. A data reproducing circuit of a disk reproducing apparatus according to claim 9, wherein said another synchronizing signal includes said data synchronizing signal newly detected by said data synchronizing signal detector. 13. The another synchronization signal includes a detection signal output by a physical mark detection unit for detecting a physical mark that is a specific shape portion of the surface of the disk-shaped recording medium. 9. A data reproducing circuit of the disk reproducing device described in 9. 14. A disk shape in which (a) sector synchronization signal, (b) sector identification information, (c) data synchronization signal, and (d) data are sequentially recorded in each of a plurality of sectors according to a fixed format. A decoder for converting a serial signal read by a head from a recording medium into a parallel signal for demodulation, comprising: (A) Sector synchronization signal detection for detecting the sector synchronization signal from the serial signal. Section, (B) a data synchronization signal detecting section for detecting the data synchronization signal from the serial signal for a predetermined time by inputting a detection start signal, (C) for converting the serial signal to the parallel signal A serial / parallel conversion unit, (D) a demodulation unit for demodulating the parallel signal, and (E) (a) a physical mark that is a specific shape portion of the surface of the disk-shaped recording medium. From the time of successful detection by the physical mark detection unit until the input of the target data synchronization signal by the data synchronization signal detection unit, the time is predicted based on the format as the target data synchronization signal input prediction time, ( b) Data synchronization for outputting the detection start signal to the data synchronization signal detection unit when the target data synchronization signal input prediction time has elapsed from the time when the physical mark detection unit succeeded in detecting the physical mark. A decoder having a signal detection control unit; a RAM for temporarily storing the parallel signal demodulated by the decoder; a memory control unit for controlling writing and reading of data to and from the RAM; a parallel signal demodulated by the decoder Error detection unit for detecting the code error of the parallel signal demodulated by the decoder An error correction unit for correcting the code error of the host, a parallel signal in which the code error is not detected by the error detection unit, and a parallel signal in which the code error is corrected by the error correction unit from the RAM. Data reproduction circuit of the disk reproduction device, which is provided with a host interface for transferring to the disk. 15. A disk shape in which (a) sector synchronization signal, (b) sector identification information, (c) data synchronization signal, and (d) data are sequentially recorded in each of a plurality of sectors according to a fixed format. Detecting the target sector synchronization signal from the serial signal read by the head from the recording medium; detecting the target data synchronization signal from the serial signal; When the detection is successful, the serial signal is converted into a parallel signal, and the parallel signal is demodulated into the data;
Temporarily storing in M; detecting a code error in the demodulated data; correcting a code error in the demodulated data; the data in which no code error is detected and the code error is corrected Transferring the data from the RAM to the host; converting the serial signal into a parallel signal by a predetermined amount when the target sector synchronization signal is successfully detected, and temporarily storing the sample signal in the RAM as a sample signal. And a step of demodulating the sample signal by shifting it by a predetermined number of bits when the detection of the target data synchronization signal has failed. 16. A step of detecting a code error of the demodulated sample signal; when a predetermined number or more of code errors of the demodulated sample signal are detected, the number of bits is changed and stored in the RAM. Demodulating the original sample signal by shifting it by the changed number of bits; correcting a code error in the demodulated sample signal; and the sample signal in which no code error is detected, and a code 16. The data reproducing method of the disk reproducing apparatus according to claim 15, further comprising the step of transferring the error-corrected sample signal from the RAM to a host. 17. When the target sector synchronization signal is successfully detected, the serial signal is converted into a parallel signal,
16. The method further comprising: demodulating the parallel signal into the sector identification information; and identifying the target sector synchronization signal from the demodulated sector identification information.
A data reproducing method of the described disk reproducing device. 18. The detection of the target sector synchronization signal based on a detection signal output by a physical mark detection unit for detecting a physical mark that is a specific shape portion of the surface of the disk-shaped recording medium. 16. The data reproducing method of the disk reproducing apparatus according to claim 15, further comprising the step of adjusting the time from the time when the conversion is successful to the start or end of the conversion of the serial signal into the sample signal or each of them. . 19. A disk shape in which (a) sector synchronization signal, (b) sector identification information, (c) data synchronization signal, and (d) data are sequentially recorded in each of a plurality of sectors according to a fixed format. Detecting the target sector synchronization signal from the serial signal reproduced by the head from the recording medium; when the target sector synchronization signal is successfully detected, the target data synchronization signal from the serial signal Detecting the target data synchronization signal, converting the serial signal into a parallel signal when the target data synchronization signal is successfully detected, and demodulating the parallel signal into the data; temporarily storing the demodulated data in a RAM. Step; detecting a code error in the demodulated data; correcting a code error in the demodulated data; code error From the RAM to the host, the data which has not been detected and the data whose code error has been corrected; from the end of the error code detection for the target sector, the input of the target data synchronization signal Up to the target data synchronization signal input prediction time based on the format; and, when the target data synchronization signal input prediction time elapses from the end of error code detection for the target sector, the serial A step of detecting the target data synchronization signal from the signal for a predetermined period of time; 20. When the target sector synchronization signal is successfully detected, the serial signal is converted into a parallel signal,
20. The data reproducing method of the disk reproducing apparatus according to claim 19, further comprising: a step of demodulating the parallel signal into the sector identification information; and a step of detecting a code error of the demodulated sector identification information. 21. The data reproducing method of a disk reproducing apparatus according to claim 20, further comprising the step of identifying the target sector from the demodulated sector identification information. 22. The target data synchronization signal input prediction time is calculated based on a detection signal output by a physical mark detection unit for detecting a physical mark that is a specific shape portion of the surface of the disk-shaped recording medium. Steps to fix,
20. The data reproducing method of the disk reproducing apparatus according to claim 19, further comprising: 23. A disk shape in which (a) sector synchronization signal, (b) sector identification information, (c) data synchronization signal, and (d) data are sequentially recorded in each of a plurality of sectors according to a fixed format. Detecting the target sector synchronization signal from the serial signal read from the recording medium by the head; when the target sector synchronization signal is successfully detected, the target data synchronization from the serial signal A step of detecting a signal; a step of converting the serial signal into a parallel signal when the target data synchronization signal is successfully detected and demodulating the parallel signal into the data; temporarily storing the demodulated data in a RAM A step of detecting a code error in the demodulated data; a step of correcting a code error in the demodulated data; a code error The data which has not been detected and the data whose code error has been corrected from the RAM to the host; from the time when the target sector synchronization signal has been successfully detected, the target data synchronization signal Predicting the time until the input of as the target data sync signal input predicted time based on the format; from the time when the target sector sync signal is successfully detected to the lapse of the target data sync signal input predicted time, Modifying the target data synchronization signal input prediction time for each input of another synchronization signal detected from the disc-shaped recording medium; and the target data synchronization signal from the time when the target sector synchronization signal is successfully detected. A step of detecting the target data synchronization signal for a predetermined time when the estimated input time has elapsed; Data reproduction method of storage. 24. When the detection of the target sector synchronization signal is successful, the serial signal is converted into a parallel signal,
24. The data reproducing method of the disk reproducing apparatus according to claim 23, further comprising: demodulating the parallel signal into the sector identification information; and identifying the target sector from the demodulated sector identification information. 25. The data reproducing method of a disk reproducing apparatus according to claim 23, wherein the another synchronization signal includes the newly detected sector synchronization signal. 26. The data reproducing method of a disk reproducing apparatus according to claim 23, wherein the another synchronization signal includes the newly detected data synchronization signal. 27. The another synchronization signal includes a detection signal output by a physical mark detection unit for detecting a physical mark that is a specific shape portion of the surface of the disc-shaped recording medium. 23. A data reproducing method of a disk reproducing device according to 23. 28. A disk shape in which (a) sector synchronization signal, (b) sector identification information, (c) data synchronization signal, and (d) data are sequentially recorded in each of a plurality of sectors according to a fixed format. Detecting the target sector synchronization signal from the serial signal read from the recording medium by the head; when the target sector synchronization signal is successfully detected, the target data synchronization from the serial signal A step of detecting a signal; a step of converting the serial signal into a parallel signal when the target data synchronization signal is successfully detected and demodulating the parallel signal into the data; temporarily storing the demodulated data in a RAM A step of detecting a code error in the demodulated data; a step of correcting a code error in the demodulated data; a code error Transfer of the data that has not been detected from the RAM and the data whose code error has been corrected to the host from the RAM; a physical mark of a physical mark that is a specific shape portion of the surface of the disk-shaped recording medium. Predicting the time from the detection by the mark detection unit to the input of the target data synchronization signal based on the format as the target data synchronization signal input prediction time; and the detection of the physical mark to the target data synchronization A step of detecting the target data synchronization signal for a predetermined time when a predicted signal input time has elapsed;