JP2003018554A - Additional information decoder for television signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extract WST(word system teletext) data inserted into a vertical synchronization period of PAL. SOLUTION: A WST detecting circuit 16 is provided with a timing oscillator 31 and a sampling rate converter 32, and extracts the WST data using a WST data clock and an asynchronous system clock. Also, in the circuit 16, a sampling timing is set at a frequency two times the WST data clock (horizontal synchronization frequency fH×888) to sample a piece of WST data twice at positions with different phases. The data is alternately apportioned for each sampling at time division to generate two pieces of WST data, and one WST data with higher reliability is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an additional information decoding device for decoding coded data inserted in a vertical blanking period of a composite video signal such as a WST signal in a PAL signal.

[0002]

2. Description of the Related Art PA is a signal standard for television signals.
In the L system, for example, it is specified that a WST (Word System Telatext) signal that represents information such as traffic information and weather information in text is inserted as additional information of a video signal.

Normally, when decoding this WST signal, a data clock (a frequency that is 444 times the horizontal synchronization period fh of 6.9375 MHz) is reproduced by using a PLL or the like and extraction is performed.

[0004]

By the way, in recent years, digitization of demodulators for television signals is progressing.

When performing digital demodulation of a PAL composite video signal, a system clock that is four times the color carrier frequency (4.43 MHz) is required to perform chroma decoding. Further, when outputting a video signal chroma-decoded by a digital component signal specified in ITU-R601, a system clock of line lock output frequency (13.5 MHz) is further required.

Further, when the WST signal is digitally demodulated, a system clock of 6.9375 MHz is required.

Therefore, for PAL composite video signals, chroma decoding, line clock output, WS
When performing the three processes of T data decoding digitally,
At least three types of system clocks are required.

However, when a plurality of system clocks are mounted on one board or one semiconductor chip,
Interference occurs between the clocks, and the interference signal sneak into the analog input of the A / D converter, for example, resulting in beat noise on the screen. Therefore, it has been very difficult to form the above three modules for performing digital processing on, for example, one substrate or one semiconductor chip due to the above-mentioned restrictions on the system clock.

The present invention has been made in view of the above circumstances, and removes the constraint on the system clock required when decoding encoded data such as WST signals inserted in a composite video signal. , Additional information of television signal which can be mounted on one board or integrated on one chip together with a module requiring a system clock of other frequency such as a chroma decoder or a line clock output circuit An object is to provide a decoding device.

[0010]

An additional information decoding apparatus according to the present invention is an additional information decoding apparatus for decoding coded data inserted in a vertical blanking period of a composite video signal, and having a predetermined frequency. From the sampling point of the composite video signal sampled by the system clock of, the sampling point corresponding to the timing of the virtual clock is extracted, the timing signal generating means for generating the timing signal synchronized with the extracted sampling point, and the system clock. The signal level at each sampling point of the virtual clock is interpolated from the signal level at each sampling point of the sampled composite video signal to generate a composite video signal sampled at the virtual clock. Interpolation means for outputting the composite video signal sampled in step S1 in synchronization with the timing signal, control means for controlling the frequency of the virtual clock to double the data rate of the encoded data, and the virtual clock. The signal included in the vertical blanking period of the composite video signal sampled by is extracted, and the extracted signal is time-divided in units of 1/2 cycle of the data rate of the encoded data. Generate a second phase signal, decode each of the first phase signal and the second phase signal to generate two encoded data, compare the two encoded data and select one encoded data And output the encoded data.

In this additional information decoding device, a timing signal synchronized with any one system clock is generated, and between the original clock of the encoded data inserted in the vertical blanking period and the timing signal. The generated error is interpolated, and the value sampled at the original clock of the encoded data is calculated. Then, the calculated value is output in synchronization with the timing signal. As a result, chroma decoding processing, frequency conversion processing to output signal timing, and decoding processing of encoded data can be performed with only one system clock. Further, this additional information decoding device converts the encoded data to a data rate of 2
Two pieces of encoded data, which are sampled by double multiplication and shifted in phase, are decoded, and data having higher reliability of the two encoded data is output.

Further, the additional information decoding device according to the present invention performs an error check using the Hamming code included in the coded data and outputs the data of the higher reliability of the two coded data. To do.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A chroma decoder to which the present invention is applied will be described below as an embodiment of the present invention.

The chroma decoder of the present embodiment is a PAL
It is a device for separating a composite video signal of a system into a luminance signal and a color difference signal, and outputting the separated luminance signal and color difference signal as a video signal of a digital signal standard based on the ITU-R601 recommendation of a sampling clock of 13.5 MHz. .

FIG. 1 shows a block diagram of a chroma decoder 1 according to an embodiment of the present invention.

The chroma decoder 1 includes a system clock oscillator 11 and a digital signal processor (DSP) 1.
2, an analog / digital converter (A / D converter) 13, a clamp circuit 14, and a synchronization detection circuit (SY).
NC circuit) 15, WST detection circuit 16, first timing oscillator (DTO) 17, first sampling rate converter (SRC) 18, luminance / chroma separation circuit (Y / C separation circuit) 19, A chroma demodulation circuit 20,
A second timing oscillator (DTO) 21, a second sampling rate converter (SRC) 22, a visual correction circuit 23, a synchronization detection circuit (SYNC circuit) 24, a formatter 25, a first-in / first-out memory ( FIFO) 26.

The system clock oscillator 11 generates a system clock Cs and supplies it to each circuit in the chroma decoder 1. Each circuit in the chroma decoder 1 operates based on this system clock Cs. The frequency of the system clock Cs is the PAL color carrier frequency fsc.
It is desirable to set the frequency to twice or more of the basic frequency of 4 times (17.8 MHz). For example, the frequency of the system clock Cs is 40 MHz.

The DSP 12 controls each circuit in the chroma decoder 1.

An analog composite video signal (CVBS) supplied from the outside is input to the A / D converter 13. The A / D converter 11 samples the input composite video signal at the system clock Cs and converts it into digital data.

The clamp circuit 14 keeps the pedestal level of the input composite video signal constant.
Perform clamp processing.

The SYNC circuit 15 extracts a sync signal from the input composite video signal and detects a vertical sync timing and a horizontal sync timing. The synchronization timing is supplied to the DSP 12.

The WST detection circuit 16 extracts the WST signal inserted in the vertical blanking period from the composite video signal sampled by the A / D converter 13 and decodes it. The details of the WST detection circuit 16 will be described later.

As described above, the clamp processing is performed and the digital composite video signal sampled at the system clock Cs is supplied to the first SRC 18.

The first DTO 17 generates the first timing signal T1 and supplies the generated first timing signal T1 to the first SRC 18. First timing signal T
1 is a signal synchronized with the system clock Cs, and
It is a signal that coincides with the period of the first virtual clock Cv1 when the pulse generation period is averaged.

Here, the first virtual clock Cv1 is a sampling clock which is necessary to perform luminance / color difference separation by digital processing from the composite video signal and then perform chroma demodulation by digital processing. That is, the first virtual clock Cv1 is a clock having a frequency four times (17.8 MHz) the color carrier frequency fsc of the PAL signal.

With respect to the first virtual clock Cv1 as described above, the first timing signal T1 is a signal synchronized with the system clock Cs. First virtual clock Cv1
And the system clock Cs have no multiplication relation. Therefore, the first virtual clock Cv1 and the first timing signal T1 are also not synchronized. Therefore, the first timing signal T1 matches the cycle of the first virtual clock Cv1 when the pulse generation cycle is averaged, that is, the first timing signal T1 is the first when the sampling frequency is averaged in the long term.
Although the frequency of the virtual clock Cv1 coincides with that of the virtual clock Cv1, the signals become irregular when the sampling intervals are not constant.

If the frequency of the system clock Cs is sufficiently high, the frequency of the first virtual clock Cv1 may be a multiplication of the above frequencies. However, it is desirable that the frequency of the first virtual clock Cv1 is set in a range of 1/2 or less of the system clock Cs in order to maintain the accuracy of the rate conversion performed in the first SRC 18.

The first SRC 18 sets the signal level at each sampling point when the analog composite video signal is sampled at the first virtual clock Cv1 at the sampling point of the composite video signal sampled at the system clock Cs. It is obtained by interpolating from the signal level. That is, the first SRC 18 performs so-called sampling rate conversion, which converts the sampling rate of the composite video signal from the system clock Cs to the first virtual clock Cv1 (17.8 MHz). And the first SRC18
Is the first timing signal T1 generated by the first DTO 17 for each sampled signal after the rate conversion.
And output in synchronization with.

Therefore, from the first SRC 18, the data itself is the first virtual clock Cv1 (17.8 MH).
The signal of the value sampled at the timing of z), the output timing of which is synchronized with the system clock Cs, and the composite video signal in an irregular state where the sampling period is not constant is output.

The composite video signal having the sampling rate converted to the first virtual clock Cv1 is supplied to the Y / C separation circuit 19.

The Y / C separation circuit 19 separates the composite video signal sampled by the first virtual clock Cv1 into a luminance signal Y and a carrier color difference signal C (color difference signal in a state of being modulated to a color carrier). . Since the sampling rate of the composite video signal is the first virtual clock Cv1 (17.8 MHz), the Y / C separation circuit 19 can reasonably process digitally. The brightness signal Y is supplied to the second SRC 22. Further, the separated carrier color difference signal C is supplied to the chroma demodulation circuit 20.

The chroma demodulation circuit 20 orthogonally demodulates the color difference signal (Cr / Cb) from the carrier color difference signal C sampled by the first virtual clock Cv1. The chroma demodulation circuit 20 has the first sampling rate of the carrier color difference signal C.
By using the virtual clock Cv1 (17.8 MHz) of, it is possible to perform digitally rational processing. The demodulated color difference signal (Cr / Cb) is the second SRC
22 is supplied.

Data samples are periodically input to the Y / C separation circuit 19 and the chroma demodulation circuit 20 in an irregular state, but since they are digitally processed, they can be processed without problems.

The second DTO 21 generates the second timing signal T2 and supplies the generated second timing signal T2 to the second SRC 22. Second timing signal T
Reference numeral 2 is a signal that is synchronized with the first timing signal T1 and that coincides with the period of the second virtual clock Cv2 when the pulse generation period is averaged.

Here, the second virtual clock Cv2 is an output clock of the component video output output from the chroma decoder 1. That is, the second virtual clock is a 13.5 MHz clock that is a digital signal standard based on the ITU-R601 recommendation.

With respect to such a second virtual clock Cv2, the second timing signal T2 is a signal synchronized with the first timing signal T1, that is, the system clock C2.
It is a signal synchronized with s. The second virtual clock Cv2 and the system clock Cs have no multiplication relationship. Therefore, the second virtual clock Cv2 and the second timing signal T2 are also not synchronized. Therefore, the second timing signal T2 coincides with the period of the second virtual clock Cv2 when the pulse generation period is averaged, that is, when the sampling frequency is averaged over a long period of time, the second virtual clock Cv2 becomes equal to the second virtual clock Cv2. Although the signals match the frequencies, the sampling intervals of the signals result in irregular signals with non-uniform periods.

The second DTO 21 generates the second timing signal T2 based on the frequency of the second virtual clock Cv2.

The second SRC 22 outputs the analog luminance signal Y and the color difference signal (Cr / Cb) to the second virtual clock C.
The signal level at each sampling point in the case of sampling at v2 is the luminance signal Y and the color difference signal (Cr / C) sampled at the first virtual clock Cv1.
It is obtained by interpolating from the signal level of each sampling point in b). That is, the second SRC 22
The so-called sampling rate conversion is performed to convert the sampling rate of the composite video signal from the first virtual clock Cv1 to the second virtual clock Cv2. Then, the second SRC 22 outputs each sampled signal after performing the rate conversion to the second DTO 21 generated by the second DTO 21.
And output in synchronization with the timing signal T2.

Therefore, from the second SRC 22, the data itself is a signal of a value sampled at the timing of the second virtual clock Cv2, but its output timing is synchronized with the system clock Cs and the sampling period is constant. A composite video signal in a non-uniform state is output.

The luminance signal Y having the sampling rate converted to the second virtual clock Cv2 is supplied to the visual correction circuit 23. Further, the color difference signal (Cr / Cb) that has been subjected to the sampling rate conversion to the second virtual clock Cv2 is supplied to the formatter 25.

The visual correction circuit 23 performs gradation correction on the input luminance signal Y to perform visual correction. The visually corrected luminance signal Y is supplied to the formatter 25.

The SYNC circuit 24 detects the vertical synchronizing signal (V) and the horizontal synchronizing signal (H) from the luminance signal Y component,
The synchronization timing is notified to the DSP 12.

The formatter 25 synthesizes an input OSD (On Screen Display) signal with the input luminance signal Y and color difference signal (Cr / Cb). The luminance signal Y and the color difference signal (C
The r / Cb) is supplied to the FIFO 26.

The FIFO 26 receives the second timing signal T
The luminance signal Y and the color difference signals (Cr / Cb) that are input in a state in which the cycles are not synchronized in synchronism with 2 are temporarily stored, for example, read at the clock timing of 13.5 MHz that is input from the outside, and data is smoothed Is output.

Next, the WST detection process will be described.

First, the format of the WST signal will be described.

The WST signal is line numbers 6H to 22H and 318H to 33 in the vertical blanking period of the PAL signal.
It is inserted between 5H. The inserted signal is NR
Digital data in Z (Non Return to Zero) format. The data rate is 6.9375 MHz ± 25
Horizontal synchronization frequency f _H (15.625 kHz) in ppm
It is defined by 444 times. 4 in 1 horizontal line
Data of 5 bytes is inserted. Therefore, the amount of information is 1530 bytes (45 bytes × 34 lines) in frame units.

FIG. 2 shows WS inserted in one line.
The wave form diagram of T signal is shown.

The WST signal starts to be inserted from a position 10.3 us (+0.4 to -1.0 us) after the edge of the horizontal synchronizing signal. In the WST signal, the first 2 bytes of 45 bytes are a clock run-in signal (a signal that repeats 0 and 1) for synchronizing the PLL clock. The following third byte is a framing code. Then, a data area including information bits is formed in the fourth byte and thereafter.

The first and second bytes of the data area (that is, the fourth and fifth bytes as a whole) have a data structure including a Hamming code of 8: 4. That is, the beginning and 2 in the data area
As for the byte, as shown in FIG. 3, 4 bits out of 8 bits are parity bits.

FIG. 4 shows a circuit configuration diagram of the WST detection circuit 16. In FIG. 4, the DSP 12, the A / D converter 13, and the SYNC circuit 1 related to the WST detection processing are shown.
5 is also shown together.

The WST detection circuit 16 comprises a third timing oscillator (DTO) 21, a third sampling rate converter (SRC) 22, and a WST decoding circuit 23.

The third DTO 31 generates the third timing signal T3 and supplies the generated third timing signal T3 to the third SRC 31. Third timing signal T
3 is a signal synchronized with the system clock Cs, and
It is a signal that coincides with the cycle of the third virtual clock Cv3 when the pulse generation cycle is averaged.

Here, the third virtual clock Cv3 is W
2 of ST signal data clock (6.9375 MHz)
Double the frequency. That is, the horizontal synchronization frequency f _H (=
13.87 of the frequency of 888 times (6.9375 MHz)
It is 5 MHz.

With respect to such a third virtual clock Cv3, the third timing signal T3 is a signal synchronized with the system clock Cs. Third virtual clock Cv3
And the system clock Cs have no multiplication relation. Therefore, the third virtual clock Cv3 and the third timing signal T3 are also not synchronized. Therefore, the third timing signal T3 coincides with the period of the third virtual clock Cv3 when the pulse generation period is averaged, that is, the third timing signal T3 is the third if the sampling frequency is averaged in the long term.
Although the frequency of the virtual clock Cv3 coincides with that of the virtual clock Cv3, the sampling intervals of the virtual clocks Cv3 result in an irregular signal having a non-constant period.

A composite video signal sampled by the system clock Cs output from the A / D converter 13 is input to the third SRC 32. Third SR
C32 interpolates each signal level of each sampling point when the analog composite video signal is sampled by the third virtual clock Cv3 from the signal level of each sampling point of the composite video signal sampled by the system clock Cs. Ask by. That is, the third SRC 32 changes the sampling timing of the composite video signal from the system clock Cs to the third virtual clock Cv3 (13.87).
5 MHz), that is, so-called sampling rate conversion. Then, the third SRC 32 outputs each sample signal after the rate conversion in synchronization with the third timing signal T3 generated by the third DTO 31.

Therefore, from the third SRC 31, the data itself is the third virtual clock Cv3 (13.875M).
Although the signal is a signal sampled at a timing of (Hz), a composite video signal whose output timing is synchronized with the system clock Cs and whose sampling period is not constant is output.

The composite video signal having the sampling rate converted to the third virtual clock Cv3 is supplied to the WST decoding circuit 33.

The WST decoding circuit 33 receives the WST from the composite video signal whose sampling rate is converted.
Decode the signal.

Next, the above-mentioned third DTO 31 will be described in more detail.

FIG. 5 shows a circuit configuration diagram of the third DTO 31.

The third DTO 31 has an adder circuit 41,
And a delay element 42. This third DTO
Each circuit constituting 31 operates at the timing of the system clock Cs.

The inclination value A and the addition value Y in the previous sample stored in the delay element 42 are input to the adder circuit 41. The adder circuit 41 adds the slope value A and the previous sample addition value Y and outputs the current sample addition value (A + Y). This current sample addition value (A + Y) is stored in the delay element 42, and is fed back from the delay element 42 to the adder circuit 41 as the previous sample addition value Y at the next clock timing. That is, the adder circuit 41 and the delay element 42 cumulatively add the slope value A for each sample. The cumulative addition output will be referred to as an adder output Y hereinafter.
Call.

The output of the adder circuit 41 is
It is designed to be expressed in the range of N bits. Tsuma
, "N^TwoCan only be output up to, and values higher than that can be output.
It becomes a bar flow. The adder circuit 41, if the addition result
Is "N^TwoIn case of overflow beyond ",
^TwoIf the value exceeds "", the value is returned from 0 and output.
That is, the addition result (A + Y) is N^TwoWhen is over
Is {(A + Y) -N ^Two} Will be output.
In addition, the adder circuit 41 overflows.
If so, an overflow flag is output.

The third DTO 31, as shown in FIG.
This overflow flag is set to the first timing signal T1.
Output as.

The first DTO 17 and the second DTO 2
1 also has the same circuit configuration as the third DTO 31.

By the way, since the third timing signal T3 is an overflow flag, its cycle is shown in FIG.
The tilt can be controlled by the inclination of the adder output Y shown in FIG. The inclination of the adder output Y can be controlled by the inclination value A. That is, if the value of the slope value A is increased, the frequency of the third timing signal T3 can be controlled to be increased, and if the value of the slope value A is reduced, the frequency of the third timing signal T3 is decreased. Can be controlled in the direction.

Here, the target frequency of the third timing signal T3 is 888 times the horizontal synchronizing frequency f _H. That is, as shown in FIG. 7, the inclination value A may be adjusted so that 888 pulses are generated within the horizontal synchronization signal (Hsync) generation interval.

Therefore, the DSP 12 refers to the horizontal synchronizing signal (Hsync) and refers to the horizontal synchronizing signal (Hsync).
The inclination value A given to the DSO 31 is adjusted so that the overflow flag is generated 888 times within the generation interval of c).

Next, the third SRC 32 will be described in detail.

The third SRC 32 can be constructed by, for example, an interpolation filter using an FIR filter as shown in FIG. Here, an example using a 9-tap FIR filter is shown.

The third SRC 32, as shown in FIG.
With the first to eighth delay circuits 51 to 58, the first to ninth multipliers 61 to 69, and the adder 70, a 9-tap F
It constitutes an IR filter.

The third SRC 32 has a coefficient ROM 71 which gives tap coefficients to each of the multipliers 61 to 69, and a register 72 which takes in the filtered output from the adder 70 with the third timing signal T3. There is.

In the third SRC 32, each delay element is operated by the system clock Cs, only the interpolation result obtained by the third timing signal T3 is taken into the register 72, and is output as the interpolation result.

Here, in the third SRC 32, the composite video signal is sampled at the third virtual clock Cv3 (f _H × 888) from the signal level at each sampling point of the composite video signal sampled at the system clock Cs. However, since the system clock Cs and the third virtual clock Cv3 have different frequencies, the phase shift between the system clock Cs and the third virtual clock Cv3 is taken into consideration. Interpolation must be done. Furthermore, since the phase shift fluctuates for each sample, the tap coefficient of the FIR filter must be changed for each sample.

FIG. 9 shows a timing chart of each signal related to the third SRC 32.

The signal shown in FIG. 9A is an input composite video signal. White circles and black circles shown on this composite video signal indicate sampling points at the system clock Cs. The black circles in each point are sample points at positions synchronized with the third timing signal T3. FIG. 9B shows the system clock Cs. FIG. 9C shows the third timing signal T3. In addition, FIG. 9 (D)
Indicates the adder output Y of the first DTO 16. FIG. 9E shows the third virtual clock Cv3.

Here, a predetermined sampling point of the system clock Cs is set to D (0). This D (0)
Is a sampling point synchronized with the third timing signal T3. A signal Dr of a predetermined sampling point of the third virtual clock Cv3 having a predetermined phase difference θ from the signal D (0) of the predetermined sampling point.
It is assumed that eal (0) is obtained by interpolation with an FIR filter.

First, as shown in FIG. 9, the phase difference θ is D
It is represented by the adder output Y when (0) is output, that is, when the third timing signal T3 is asserted.
This is so that the value of the adder output Y from 0 to overflow corresponds to the cycle of the virtual clock Cv3.
This is because the slope value A is preset by the DSP 12.

The phase difference θ corresponds to the delay amount T of the impulse response of the FIR filter, as shown in FIG.

That is, Dreal which is a signal at a predetermined sampling point of the third virtual clock Cv3.
(0) is a tap coefficient (K ′ (− 4), K ′ (which is obtained by multiplying the impulse response of the FIR filter by a predetermined window function and is corrected by a delay amount of a predetermined time T). -3),
K '(-2), K' (-1), K '(0), K' (1), K '(2), K' (3), K '(4)) be able to.

Dreal (0) = K '(-4) * D (-4) + K' (-3) * D (-3) +
K '(-2) * D (-2) + K' (-1) * D (-1) + K '(0) * D (0) + K' (1) * D (1) + K '
(2) * D (2) + K '(3) * D (3) + K' (4) * D (4) Therefore, the phase delay amount θ and the tap coefficient group corresponding to the delay amount θ are set in advance. If the tap coefficient is stored in the coefficient ROM 71 and the adder output Y is used as an address and the read tap coefficient is given to each of the multipliers 61 to 69,
Interpolation processing in which the phase shift is appropriately corrected can be performed.

The first SRC 18 and the second SRC 2
2 also has the same circuit configuration as that of the third SRC 32.

Next, the WST decoder 33 will be described in detail.

As shown in FIG. 11, the WST decoder 33 includes a binarizing circuit 81, a dividing circuit 82, and a first WST.
Slice circuit 83 and second WST slice circuit 84
A parity discriminating circuit 85 and a selector 86.

The binarization circuit 81 receives the composite video signal sampled at the third virtual clock (f _H × 888). The binarization circuit 81 binarizes the input composite video signal at a predetermined slice level. This slice level is appropriately controlled by the DSP 12. The binarized composite video signal is supplied to the dividing circuit 82.

The dividing circuit 82 uses the third virtual clock (f
_HX 888) sampled composite video signal
The signal is alternately divided every sample and assigned to two signals.
Divide. As a result, f_HSampled at x888
The composite video signal is f _HSampling at × 444
Converted into two signals. Two output signals
Are two signals whose sampling points have different phases.
It becomes the issue. Note that one signal is called the first phase signal, and the other
Signal is called a second phase signal.

The first phase signal is supplied to the first WST slice circuit 83, and the second phase signal is supplied to the second WST slice circuit 84.

The first WST slice circuit 83 is a DSP.
Based on the horizontal synchronization signal (Hsync) and line number information (lineNo.) Supplied from 12, the line numbers 6H to 22H and 318H to 335H in which WST is inserted are input to the input first phase signal. Identify.
When the line in which WST is inserted, the frame code is recognized from the data inserted in that line, and 39 bytes of WST information following the frame code are extracted. The WST information extracted from the first phase signal is supplied to the parity determination circuit 85 and the selector 86 for each line.

The second WST slice circuit 83 performs the same processing as the first WST slice circuit 83 on the second phase signal. The WST information extracted from the second phase signal is
It is supplied to the parity discrimination circuit 85 and the selector 86 for each line.

The parity discrimination circuit 85 receives the two WST information extracted from the first phase signal and the second phase signal,
Perform a Hamming code check of 8: 4 respectively. As shown in FIG. 12, the parity determination circuit 85 performs a 3-bit Hamming check (P1 to P3) and a 1-bit parity check (P4) defined by the 8: 4 Hamming code, and each byte Judge the reliability of the.

Regarding the reliability level, the results of the Hamming check of P1 to P3 are "All correct" and the result of the parity check of P4 is "Correct (Correc
t) ”is the highest. Subsequently, the Hamming check result of P1-P3 is“ All correct ”and the parity check result of P4 is“ Incorrect (Not
"correct") is the next highest. Next, the Hamming check results of P1-P3 are "Not all correct (Not al
“L correct)” and the result of the parity check of P4 is “Correct”, which is the next highest.
The lowest case is that the 1-P3 Hamming check result is "Not all correct" and the P4 parity check result is "Not correct".

As a result of the above reliability judgment, the parity judgment circuit 85 specifies the WST information of one of the more reliable phases.

Then, the selector 86 selects and outputs the more reliable WST information of the first phase signal and the second phase signal based on the discrimination result of the parity discrimination circuit 86.

As described above, in the WST detection circuit 16,
A third DTO 31 and a third SRC 32 are provided, and the WST
The WST data is extracted by the system clock Cs asynchronous with the data clock. Therefore, it is possible to use the same system clock as a module that requires a system clock of another frequency such as a PAL composite video signal chroma decoder or a line clock output circuit, and therefore, these modules can be mounted on one board together. And can be integrated on one chip.

Further, when the WST data is extracted by the system clock Cs which is asynchronous with the WST data, phase synchronization cannot be achieved even if the frequencies of the sampling clock and the WST data clock match.
If the phases are not synchronized, for example, the sampling points may coincide with the data change points of the WST data, and stable data extraction cannot be performed. Therefore, in the present WST detection circuit 16, the sampling timing is twice the WST data clock (f _H × 888).
The frequency is set so that one WST data is sampled twice at different positions. Then, the sampling points sampled at the doubled frequency are alternately allocated in time division for each sample, and two pieces of data having the same number of samples as the number of WST data clocks are generated. By doing so, at least one of the data is W
Since the ST data can be extracted, it is possible to solve the problem caused by the failure of phase synchronization.

Then, the present WST detection circuit 16 judges the reliability of each of the two WST data detected in the two phases, and outputs only one of the highly reliable data.

The WST detection circuit 16 determines reliability by referring to a Hamming code defined in the WST data format. Therefore, this reliability judgment can be performed with high accuracy and easily.

[0099]

According to the additional information decoding device of the present invention,
A timing signal synchronized with any one system clock is generated, and an error generated between the original clock of the encoded data inserted in the vertical blanking period and the timing signal is interpolated to obtain the encoded data. Calculate the value sampled with the original clock. Then, the calculated value is output in synchronization with the timing signal.
As a result, chroma decoding processing, frequency conversion processing to output signal timing, and decoding processing of encoded data can be performed with only one system clock.
Further, the additional information decoding device samples the coded data at a multiplication of twice the data rate, decodes the two coded data sampled by shifting the phase, and outputs the reliability of the two coded data. The data of the higher one is output.

Therefore, in the additional information decoding device according to the present invention, the WS inserted in the composite video signal is used.
The restrictions on the system clock required when decoding encoded data such as T signals are removed, and, for example, a module that requires a system clock of another frequency such as a chroma decoder or a line clock output circuit
It can be mounted on one substrate or integrated on one chip.

Further, in this additional information decoding device, the coded data is sampled at a multiplication of twice the data rate, and the two coded data sampled with the phase shifted are decoded. Even if the sampling is performed by the system clock that is not phase-synchronized with the signal clock, the data is phase-synchronized for at least one of the data.

[Brief description of drawings]

FIG. 1 is a diagram showing a block configuration of a chroma decoder to which the present invention is applied.

FIG. 2 is a diagram showing a waveform of a WST signal.

FIG. 3 is a diagram for explaining an 8: 4 Hamming code included in a WST signal.

FIG. 4 is a diagram showing a circuit configuration of a WST detection circuit in the chroma decoder.

FIG. 5 is a diagram showing a circuit configuration of a DTO in the WST detection circuit.

FIG. 6 is a timing chart of the output signal of the DSO.

FIG. 7 is a diagram for explaining control of a frequency of a virtual clock set in the DSO.

FIG. 8 is a diagram showing a circuit configuration of an SRC in the WST detection circuit.

FIG. 9 is a timing chart of signals related to the SRC.

FIG. 10 is a waveform diagram showing the impulse response of the FIR filter.

FIG. 11 is a diagram showing a circuit configuration of a WST decoding circuit in the WST detection circuit.

FIG. 12 is a diagram for explaining a calculation result of an 8: 4 Hamming code.

[Explanation of symbols]

1 chroma decoder, 11 system clock oscillator,
12 digital signal processor, 13 analog /
Digital converter, 15, 24 Synchronization detection circuit, 16
WST detection circuit, 17 First timing oscillator, 1
8 first sampling rate converter, 19 luminance / chroma separation circuit, 20 chroma demodulation circuit, 21 second
Timing oscillator, 22 second sampling rate converter, 23 visual correction circuit, 25 formatter, 26 first-in / first-out memory,
31 Third Timing Oscillator, 32 Third Sampling Rate Converter, 33 WST Decoding Circuit

Claims (5)

[Claims] 1. An additional information decoding device for decoding coded data inserted in a vertical blanking period of a composite video signal, wherein a virtual point is extracted from a sampling point of the composite video signal sampled at a system clock of a predetermined frequency. From the signal level at each sampling point of the composite video signal sampled at the system clock, the timing signal generating means for extracting the sampling point corresponding to the clock timing and generating the timing signal synchronized with the extracted sampling point, The signal level at the sampling point of the virtual clock is interpolated to generate a composite video signal sampled by the virtual clock, and the composite video signal sampled by the virtual clock is An interpolating means for outputting in synchronization with an imming signal, a control means for controlling the frequency of the virtual clock to be a double of the data rate of the encoded data, and a vertical direction of the composite video signal sampled by the virtual clock. A signal included in the blanking period is extracted, and the extracted signal is time-divided in units of 1/2 cycle of the data rate of the encoded data to generate a first phase signal and a second phase signal. , The first phase signal and the second
Information signal decoding means for respectively decoding the phase signals of 1 to generate the above-mentioned coded data, comparing the two coded data, and selecting and outputting one coded data. apparatus. 2. The additional information decoding device according to claim 1, wherein the control means controls the frequency of the virtual clock based on a horizontal synchronizing signal of the composite video signal. 3. The additional information decoding according to claim 1, wherein the composite video signal is a PAL system video signal, and the encoded data is a WST signal defined by the PAL system. apparatus. 4. The additional information decoding device according to claim 3, wherein said control means sets the frequency of said virtual clock to a multiplication of 888 times the horizontal synchronizing frequency in the PAL system. 5. The encoded data decoding means performs an error check by referring to a Hamming code added to 2-byte data following the framing code of the WST signal, and performs either one of the two encoded data. 5. The additional information decoding device according to claim 4, wherein is selected.