JP2003015861A - Semiconductor integrated circuit and computer readable recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a shift operation module capable of performing a shift operation without using an exclusive shift operation instruction of a plurality of optional bits. SOLUTION: The shift operation module (6) is provided with a data register (31) to store data to be shifted and can be accessed by a data transfer instruction such as a load/store instruction of a CPU. The shift operation module is provided with a barrel shifter (32) as a shift operation circuit to vary shift quantity by a reading address of shift data. A plurality of reading addresses of the shift data are allocated according to variation of the shift quantity. The shift operation circuit is realized as a peripheral I/O module of a CPU core without depending on architecture of the CPU. In addition, no change is required for the architecture of the existing CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a shift calculation module and a recording medium in which design data of the shift calculation module is stored so that it can be read by a computer, and is effective when applied to, for example, a microcomputer. Regarding technology.

[0002]

2. Description of the Related Art A barrel shifter can be used to shift a plurality of bits of data for digit alignment such as normalization in floating point arithmetic. For example, if the shift amount is represented by a binary number Sn-1Sn-2 ... S0 of n bits, the barrel shifter can be realized by using transfer gates of n stages for each bit. A microcomputer incorporating a barrel shifter has an instruction set with an arbitrary multiple bit shift instruction (barrel shift instruction) for enabling a shift operation using the barrel shifter to be executed at high speed.

A barrel shifter is disclosed in Japanese Patent Laid-Open No. 8-2.
21257, Japanese Patent Laid-Open No. 5-73516, Special Table 2000-5
03146, JP-A-9-198232 and the like.

[0004]

However, having the barrel shift instruction in the instruction set means that the original architecture of the CPU must be compatible with the barrel shifter. However, in the case of a CPU that supports only shift instructions of 1-bit shift and 2-bit shift, in order to shift an arbitrary bit, it is necessary to combine 1-bit shift and 2-bit shift instructions several times. I won't. If an instruction that can execute an arbitrary multi-bit shift operation is added to such an existing CPU in the instruction set, not only the hardware of the CPU is changed but also the software of the assembler and the high-level language compiler accompanying it is changed. It has been clarified by the inventor of the present invention that it is often necessary and often not easily realized.

An object of the present invention is to make it possible to provide a shift operation module capable of performing the shift operation without using a dedicated shift operation instruction of arbitrary plural bits.

Another object of the present invention is to provide a semiconductor integrated circuit equipped with a shift operation module capable of performing a shift operation of arbitrary plural bits by diverting a data transfer instruction executed by a CPU.

Another object of the present invention is to facilitate the design of a semiconductor integrated circuit which employs the shift operation module capable of performing the shift operation of arbitrary plural bits.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Means for Solving the Problems [1] The outline of representative ones of inventions disclosed in the present application will be briefly described as follows.

That is, in a CPU having no multi-bit shift instruction, the CPU core itself is not changed at all, and a semiconductor integrated circuit is provided with a shift operation module for executing a shift operation as an external coprocessor.

The shift operation module is provided with a data register for storing data to be shifted, and loads / loads the CPU.
It is made accessible by a data transfer instruction such as a store instruction. It has a barrel shifter as a shift operation circuit that changes the shift amount according to the read address of the shift data. In this form, a plurality of shift data read addresses are assigned according to variations in shift amount.

As another form of the shift operation circuit, a mode register is used to specify the shift amount. The operation designation for the barrel shifter is performed by the read address of the shift data. In this case, one read address of the shift data may be assigned.

As described above, the shift arithmetic circuit can be realized as an external I / O device without depending on the special architecture of the CPU. Also, no changes are required to the existing CPU architecture. Conventionally, a shift operation of an arbitrary bit, which is conventionally performed by combining a plurality of 1-bit or 2-bit shift operation instructions, can be executed by an external shift operation circuit, so that the program execution speed can be improved. CP
Since there is no need to change U, an arbitrary bit shift arithmetic circuit can be added later to most CPUs that support data transfer instructions.

[2] The present invention will be described in more detail with reference to specific embodiments. A semiconductor integrated circuit according to a first aspect of the present invention includes a CPU, a shift operation module, and a bus connecting the CPU and the shift operation module in one semiconductor chip. The shift operation module includes a data register for latching data from the bus, and a barrel shifter capable of performing a shift operation on the data latched in the data register and outputting shift data. When the CPU specifies a read address of shift data and executes a data transfer instruction, the barrel shifter performs a shift operation with a shift amount according to the read address of the shift data output by the CPU to the bus. In this aspect, the read address of the shift data is determined according to the description of the address designation field in the data transfer instruction according to the addressing mode of the instruction.

A semiconductor integrated circuit according to a second aspect of the present invention includes a CPU, a shift operation module, and a bus connecting the CPU and the shift operation module in one semiconductor chip. The shift operation module includes a data register for latching data from the bus, a barrel shifter capable of performing a shift operation on the data latched in the data register and outputting shift data, and a mode register. When the CPU specifies a read address of shift data and executes a data transfer instruction, the barrel shifter performs a shift operation with a shift amount according to the set value of the mode register. In this mode, the shift amount is determined by the set value in the mode register.

A semiconductor integrated circuit according to a third aspect of the present invention includes a CPU, a shift operation module, and a bus connecting the CPU and the shift operation module in one semiconductor chip. The shift operation module includes a data register for latching data from the bus, and a barrel shifter capable of performing a shift operation on the data latched in the data register and outputting shift data. When the CPU designates the first read address of the shift data and executes the data transfer instruction, the barrel shifter outputs CP
When the CPU performs a shift operation with a shift amount according to the read address of the shift data output to the bus, and the CPU executes the data transfer instruction by designating the second read address of the shift data, the set value of the mode register is set. A shift operation is performed with a corresponding shift amount. In short, the shift amount designation in the first mode and the shift amount designation in the second mode can be selected.

[3] A semiconductor integrated circuit which grasps the above-mentioned third aspect from still another viewpoint is a semiconductor chip in which a CPU, a shift operation module, and a bus connecting the CPU and the shift operation module are included in one semiconductor chip. Including. The shift operation module includes a data register, a barrel shifter, and
It has a mode register and a control unit. The shift operation module is assigned to a predetermined address area in the CPU address space, and the predetermined address area has an address assigned to a data register, an address assigned to a mode register, a plurality of addresses assigned to a shift amount, and a specific shift operation. Contains the address assigned to. The controller barrel shifts the data in the data register to the barrel shifter in a shift amount designated by the address in response to one of a plurality of addresses assigned to the shift amount being input from the bus. Then, the data subjected to the barrel shift operation is output to the bus, and the address assigned to the specific shift operation is designated by the first set value of the mode register in response to the input from the bus. The barrel shifter causes the data in the data register to be barrel-shifted by the shift amount, and the barrel-shifted data is output to the bus.

At this time, the mode register may specify whether the barrel shift operation by the barrel shifter is a logical shift operation or an arithmetic shift operation according to the second set value. For example, the CPU can execute a data transfer instruction in which an address assigned to the shift amount is described in a source operand designation field, and output an address corresponding to the shift amount to the bus. Further, the CPU can execute, for example, a data transfer instruction in which an address assigned to a specific shift operation is described in a source operand designation field, and output an address corresponding to the specific shift operation to the bus.

[4] A computer-readable recording medium is a circuit for designing a semiconductor integrated circuit to be formed on a semiconductor chip, from the viewpoint of facilitating the design of a semiconductor integrated circuit employing the shift operation module. Module data is recorded so that it can be read by a computer. The circuit module data stored in the recording medium includes graphic pattern data or function description data for forming a shift operation module including a data register, a barrel shifter, a mode register and a control unit on the semiconductor chip. The control unit has an address decoding unit for an address area including an address assigned to a data register, an address assigned to a mode register, and a plurality of addresses assigned to a shift amount, and the address decoding unit assigns the shift amount. In response to detecting that one of the plurality of addresses is input from the bus, the barrel shifter causes the data in the data register to perform a barrel shift operation by the shift amount designated by the address, and the barrel-shifted data is transferred. The data is output to the bus.

The control unit in the shift operation module corresponding to another circuit module data recorded on the recording medium is an address area including an address assigned to the data register, an address assigned to the mode register, and an address assigned to the shift operation. To the shift designated by the first set value of the mode register in response to detecting by the address decode means that the address assigned to the shift operation is input from the bus. The barrel shifter causes the data in the data register to be barrel-shifted by an amount, and the barrel-shifted data is output to the bus.

The control unit in the shift operation module corresponding to the further circuit module data recorded on the recording medium includes an address assigned to the data register, an address assigned to the mode register, a plurality of addresses assigned to the shift amount, and a specific value. Responsive to detecting that one of a plurality of addresses assigned to the shift amount is input from the bus by the address decoding means, the address decoding means having an address area including an address assigned to a shift operation, The barrel shifter causes the data in the data register to perform a barrel shift operation by the shift amount designated by the address, and the barrel-shifted data is output to the bus.
In response to the address assigned to the specific shift operation being input from the bus, the barrel shifter causes the data in the data register to perform a barrel shift operation by a shift amount specified by the first setting value of the mode register, The barrel-shifted data is output to the bus.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a data processor 1 which is an example of a semiconductor integrated circuit according to the present invention. The data processor 1 shown in the figure is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique, for example.

The data processor 1 comprises a central processing unit (C
PU) 2, DMA controller (DMAC) 3, CPU
A read only memory (ROM) 4, which is a program memory for storing the processing program of 2, a random access memory (RAM) 5 used for temporary storage of data and a work area of the CPU 2, and a shift capable of performing an arbitrary multi-bit shift operation Arithmetic module 6, bus controller 7,
Clock generation circuit (CPG) 8, interrupt controller 1
0, timer counter (TMR) 11, serial communication interface controller (SCI) 1
2, digital-to-analog converter (D / A) 13, analog-to-digital converter (A / D) 14, pulse-wise modulator (PWM) 16, watchdog timer (WD)
T) 17 and input / output ports (PORT) 18 to 20. CPU2, DMAC3, ROM4, RAM
5, the shift operation module 6 and the bus controller 7 are connected to the CPU bus 21. The CPU bus 21 is interfaced with the peripheral bus 22 via the bus controller 7, and the peripheral bus 22 has the interrupt controller 10, TMR 11, SCI 12, D / A as peripheral circuits.
13, A / D 14, PWM 16, and WDT 17 are connected. The CPU bus 21 and the peripheral bus 22 are respectively
It includes a data bus, an address bus and a control bus (control signal bus). The peripheral bus 22 is interfaced with an external bus (not shown) via the input / output port 18, the CPU bus 21 is interfaced with the peripheral bus 22 via the bus controller 7, and further with the external bus via the input / output port 18. To be done. The input / output ports 19 and 20 function as external interface buffers for peripheral circuits.

The bus master module in the data processor 1 is the CPU 2 and the DMAC 3. The CPU 2 has, for example, an instruction control unit that fetches an instruction from the ROM 4 and decodes the fetched instruction, and an execution unit that performs arithmetic processing using a general-purpose register or an arithmetic logic unit according to the instruction decoding result by the instruction control unit. Have. DM
The data transfer condition of the AC3 is initialized by the CPU 2, and the data transfer control is performed in response to a data transfer request from a peripheral circuit or the like.

The bus controller 7 arbitrates the competition of the bus right request among the bus master module CPU 2, the DMAC 7, and the external bus master. The arbitration logic is, for example, arbitration control based on priority. As a result of the arbitration, the bus master module to which the bus right is given outputs a bus command, and the bus controller 7 controls the bus based on this bus command. When the address signal output from the bus master module means the external address space of the data processor 1, the bus controller 7 outputs the address signal and the access strobe signal to the outside through the input / output port 18.

The interrupt controller 10 uses the peripheral bus 2
An interrupt request signal (not shown) output from a circuit module such as the SCI 12 connected to 2 is input, priority control and mask control are performed on the input interrupt request signal, and the interrupt request is accepted. Upon accepting the interrupt, the interrupt controller 10 outputs an interrupt request signal (not shown) to the CPU 2. When the interrupt request signal is given to the CPU 2, the CPU 2 interrupts the process being executed and branches to a predetermined processing routine corresponding to the interrupt factor. At the end of the processing routine at the branch destination, a return instruction is executed, and by executing this instruction, the interrupted processing can be restarted.

In addition, the data processor 1 has external terminals such as a ground level (Vss) and a power supply voltage level (Vcc) as power supply terminals, and also has a reset input (RES) and a standby (input STBY) as dedicated control terminals. ), Mode control inputs (MD0, MD1), and clock inputs (EXTAL, XTAL).

The CPG 8 generates a system clock signal φ based on an external clock signal input to a crystal oscillator connected to the terminals EXTAL and XTAL or an EXTAL terminal, although not particularly limited.

Reset signal RES to data processor 1
Is given, the on-chip circuit module such as the CPU 2 is reset. When the reset state by the reset signal RES is released, the CPU 2 reads an instruction from a predetermined start address and starts executing the program, and accordingly, for example, fetches data from the RAM 5 and arithmetically processes the fetched data. And then
Based on the processing result, the SCI 12 or the like is used to perform signal input / output with the outside to control various devices.

FIG. 1 shows an example of the shift calculation module 6. Although not particularly limited, the shift operation module 6 has a control unit 30, a data register 31, a barrel shifter 32, and a mode register 33, which are commonly connected to the in-module bus 34. The control unit 30
Is connected to the CPU bus 21. The data register 3
1 latches the barrel shift target data given from the in-module bus 34. The barrel shifter 32 shifts the data supplied from the data register 31 by a plurality of bits (barrel shift), and outputs the shift data to the in-module bus 34. The number of shift bits by the barrel shifter 32 is designated by the control unit 30. The mode register 33 indicates by a signal S1 whether the shift operation by the barrel shifter 32 is an arithmetic shift or a logical shift.

In the logical shift operation, as shown in FIGS. 3 and 4, when the original data is regarded as an unsigned 32-bit integer, an N-bit left shift is performed unless bit overflow or underflow occurs. 2 times N, right shift is 2
It corresponds to the unsigned arithmetic operation of 1 / N.

In the arithmetic shift operation, as shown in FIGS. 5 and 6, when the original data is regarded as a signed 32-bit integer, an N-bit left shift is performed unless there is a bit overflow or underflow. 2 times N, right shift is 2
It corresponds to a signed arithmetic operation of 1 / N.

Further, the shift calculation module 6 will be described in detail. The CPU 2 accesses the shift operation module 6 like a memory-mapped IO, and the control unit 30 controls internal initialization operation and barrel shift operation in response to the access control.

The CPU bus 21 is a data bus IDB,
It includes a control bus ICB and an address bus IAB. When executing a data transfer instruction such as a load instruction or a store instruction, the CPU 2 outputs strobe signals such as a read signal instructing a read operation and a write signal instructing a write operation to the control bus ICB. At the same time, the CPU 2 outputs an address signal indicating the access address to the address bus IAB. C for read operation
PU2 takes in the data output to the data bus IDB from the circuit to be accessed, and if it is a write operation, the CPU 2 outputs the data to be written to the data bus IDB. For example, when the CPU 2 specifies the address of the data register 31 and executes the store instruction, the data register 3
Data for shift operation is set to 1 from the data bus IDB (PS1). By the CPU 2 specifying the address of the mode register 33 and executing the store instruction,
Control data is set in the mode register 33 from the data bus IDB (PS3). When the CPU 2 executes the load instruction by designating the read address of the shift operation result data, the shift operation result data is transferred to the data bus I.
It is output to DB.

The register space in the barrel shift module 6 has the address mapping illustrated in FIG. As is clear from FIG. 7, 32 virtual left shift data registers (LS) are arranged on the upper side around the mapping address (0x000FF00) of the data register 31.
T1 to LST32) are mapped to 32 virtual right shift data registers (RST1 to RST) on the lower side.
32) is mapped. As will be described later in detail, each virtual shift data register is a virtually defined register in order to correspond the shift amount to the register address. For example, left shift data register (LST
The address 0x000FF80 designating 32) designates the number of shift bits as 32 bits to the left in the read operation of the shift data designating the register address.

The control unit 30 has an address decoder 35 having an address decoding logic for identifying the mapping address of FIG. 7, and determines which address signal of the mapping address of FIG. 7 is input. The address decoder 35 uses the CPU bus (IAB, ICB, I
When there is access from the CPU 2 through the DB) 21,
The address signal input from the address bus IAB is decoded to determine which register in FIG. 7 is accessed.

Data register 31 and mode register 33
Actually has a memory circuit for storing data, and C
Register operation is actually performed for read and write access from PU2. In short, when the address decoder 35 detects access to the data register 31 or the mode register 33, the control unit 30 causes the data register 3
1 or a register selection signal (not shown) for the mode register 33 is set to a selection level, and a register output operation or a register input operation is instructed by a register input / output control signal (not shown) in accordance with a read or write operation instruction.

Data register 31 and mode register 33
Other shift data registers (left shift data registers LST1 to LST32 and right shift data register RS
T1 to RST32 are collectively referred to as a shift register), and do not have an actual memory circuit. When the shift register is designated as a read access target address from the CPU 2, the shift amount data N [6: 0] corresponding to the designated address is given to the barrel shifter 32, and the value stored in the data register 31 is changed. A plurality of bits are shifted by the shift amount, and the shift operation result is stored in the bus 34.
Is output to. That is, when the CPU 2 makes a read access to any one of the shift registers, the address decoder 35 decodes the value of the address bus IAB indicating the address of the shift register and detects that the read access is instructed. As a result, the control unit 30 supplies the 32-bit data stored in the data register 31 to the barrel shifter 32 as DI [31: 0]. Along with this, the address decoder 35
From the decoding result of the value on the address bus IAB indicating the address of the shift register, the shift amount N [6: 0]
Is generated and supplied to the barrel shifter 32.

The shift operation range is 1 bit to 32 bits for left shift and 64 bits for right shift of 1 bit to 32 bits.
Therefore, the shift amount N is sufficient if there is a data amount of 6 bits, but N = 0 in the case of no shift is added to 65.
Therefore, a data amount of 7 bits is assigned.

As shown in FIG. 7, from the starting data register 31, the left shift data registers LST1 to LST32 are moved toward the upper side of the address space, and the right shift data registers RST1 to R are moved toward the lower side of the address space.
When ST32 is arranged, the shift amount N [6: 0] is N
[6: 0] = (IAB- @ data register) / 4 can be obtained. “@Data register” means a mapping address of the data register 31. In short, since the address of the shift register for which the CPU 2 has issued the read request is input via the address bus IAB, the address of the data register 31 as the starting point is subtracted from the value of the address bus IAB, and the register size is 4 bytes ( Divide by 32 bits) to obtain the shift amount. The address is assumed to be a byte unit address (byte address). For example, when the CPU requests reading from the right shift register RST3, the address of the right shift register RST3 is supplied to the address bus IAB. The address of the right shift register RST3 and the address of the data register 31 differ by 12 and the address of the right shift register RST3 has a smaller value. Therefore, (IAB- @ data register) =-12, which is divided by 4 to obtain N [6: 0] =-3. When the value of N is negative, right shift operation is instructed, and when it is positive, left shift operation is instructed.

The barrel shifter 32 receives the value D of the data register 31 from the shift operation target data DI [31: 0], the shift amount N [6: 0], and the logical / arithmetic shift signal S1.
The data obtained by shifting I [31: 0] is output to the in-module bus 34. The control unit 30 outputs the data output to the in-module bus 34 to the internal data bus IDB, and returns the result of the shift operation in response to the read request from the CPU 2. The logical / arithmetic shift signal S1 is a value of a bit assigned in the mode register 33, and indicates a logical shift operation when the logical value is "0" and an arithmetic shift operation when the logical value is "1", for example. And

The shift calculation module 6 illustrated in FIG.
According to the above, the CPU 2 writes the data to be shifted into the data register 31 of the shift operation module 6, and for the shift amount N bits, (@data register +
By simply reading the data from the address indicated by (N × 4), it is possible to obtain the data that has been subjected to an arbitrary multi-bit shift operation. At this time, depending on whether the value of N is positive or negative, N>
It is possible to obtain data that is left-shifted when 0 and right-shifted when N <0. The CPU 2 only needs to be able to read and write an arbitrary address, and can implement the shift operation module 6 as a peripheral circuit that does not depend on the special architecture of the CPU 2.

FIG. 8 shows an example of another shift operation module 6A. In the configuration of FIG. 1, the shift amount is changed depending on the address for reading the data, but here, a virtual register (result register RLT) for storing the shift operation result is newly provided, and the mode register 33 has the shift value. Information that indicates the amount can be set. The result register R
In the read operation in which LT is designated, the mode register 33
The result of the multi-bit shift operation using the shift amount set to is output from the barrel shifter 32 to the in-module bus 34. At this time also, as in FIG. 1, the mode register 3
By the logical / arithmetic shift signal S1 given from 3,
Logical shift and arithmetic shift are made selectable. FIG. 9 illustrates the address mapping of the register in the shift operation module 6A of FIG. In this example, the address decoder 35A may detect the input of the mapping address shown in FIG. Virtual shift data register L
Mapping of ST1 to LST32 and RST1 to RST32 is not necessary.

In the shift operation module 6A of FIG. 8, when executing the shift operation, the CPU 2 first writes the original data to be shifted into the data register 31 (P
S1). Next, the CPU 2 writes the type of logical / arithmetic shift together with the shift amount in the mode register 33 (PS
2). After that, when the CPU 2 executes a load instruction using the address of the result register RLT as a read address, in the shift operation module 6A, the barrel shifter 32 shifts a plurality of bits based on the value of the data register 31 and the shift amount of the mode register 33. It is possible to execute the operation and read the shift operation result to the in-module bus 34 (PS2).

FIG. 10 shows another example of the shift operation module 6B. The configuration of FIG. 10 has both configurations of FIG. 1 and FIG. 8, and the shift amount N [6: 0] generated according to the decoding result of the data read address and the shift specified by the set value of the mode register 33. It has a selector 36 which selects the quantity N [6: 0] and supplies it to the barrel shifter 32. The register mapping in this shift calculation module 6B has an address mapping in which a virtual register (result register RLT) for storing the shift calculation result is arranged at address 0x0000FE08 based on FIG. Data register 31 and mode register 33
Is the same regardless of which shift amount is used. The address decoder 35B outputs the selection signal S2 of the selector 36. In the read cycle by the CPU 2, when the address decoder 35B detects the designation of the result register RLT by the address from the address bus IAB, the address decoder 35B selects the shift amount from the mode register 33 by the signal S2 and supplies it to the barrel shifter 32. The configuration of FIG. 10 depends on the configuration of FIG. 1 depending on whether the data read address is selected from the virtual shift data registers LST1 to LST32, RST1 to RST32, or the virtual result register RLT. The barrel shift operation performed or the barrel shift operation depending on the configuration of FIG. 8 can be arbitrarily selected.

FIG. 11 shows C having no barrel shift instruction.
PU2 does not use shift operation module
A program for executing a constant shift operation (for example, 9-bit right shift) using a bit or 2-bit shift operation instruction is illustrated.

It is assumed that the CPU 2 has a right shift instruction (SHR) capable of shifting 1 bit or 2 bits. In this example, the 9-bit right shift operation can be completed in 4 steps.

FIG. 12 shows the shift calculation module 6 of FIG.
A program for performing a constant shift operation (for example, a 9-bit right shift operation) is illustrated. The address of the data register 31 is indicated by the label DATAREG. According to the address map of FIG. 7, it is necessary to assign the corresponding address 0x0000FF00 to the label DATAREG at any place on the program. In the first operation mode using the shift operation module 6 of FIG. 1, since the shift amount changes depending on the read address, it is only necessary to read the data from the address that shifts to the right by 9 bits by the offset from DATAREG. By using the shift operation module 6 of FIG. 1, the 9-bit right shift operation, which requires 4 steps in FIG. 11, can be completed in 2 steps.

FIG. 13 shows the shift operation module 6A of FIG.
A program for performing a constant shift operation (for example, a 9-bit right shift operation) is illustrated. Set the address of the data register 31 of the shift operation module 6A to D
MOD of ATAREG and mode register 33 address
The address of the result register RLT for storing the EREG and the operation result is shown by the label RSLTREG. According to the address map of FIG. 9, the address 0x0000FF00 for the label DATAREG, the address 0x0000FF04 for the label MODEREG, and RSLT
Address 0x0000FF for the label REG
It is necessary to allocate 08.

The original data is written to DATAREG, and then the immediate value -9 indicating a 9-bit shift to the right (minus) direction is written to the mode register 33. When the result register RLT is read in this state, a value obtained by shifting the value of the data register 31 by 9 bits to the right is read.

The second operation mode using the shift operation module 6A of FIG. 8 requires four steps as in the case of FIG. 11 in which the present invention is not implemented. In the form of FIG.
Although it appears ineffective, the advantages of the second mode of operation of FIG. 8 are maximized when any N-bit shift is performed, as illustrated below.

FIG. 14 shows a program in which the CPU 2 having no barrel shift instruction executes an arbitrary N-bit shift operation using the 1-bit or 2-bit shift operation instruction of the CPU without using the shift operation module. Is exemplified. In this example, the shift amount N is set to the register R of the CPU.
The original data to be shifted is stored in R1, and the calculation result is obtained in R1. In addition, the shift amount N is N> 0
If so, a left shift is calculated, and if N <0, a right shift is calculated. The program repeatedly executes the 1-bit right shift instruction SHR or the 1-bit left shift instruction SHL a specified number of times N. In this example, which does not implement the invention, the N-bit shift operation requires 3 + 4 * N steps, including branch instructions. The symbol * means product.

FIG. 15 shows the shift operation module 6 of FIG.
An example of a program for executing an arbitrary N-bit shift operation by using is shown. The number N of bit shifts is arbitrary, and a virtual shift data register LST1 corresponding thereto is used.
~ LST32 or RST1 to RSL32 cannot directly describe the address in the operand specification field of the instruction. This point is different from the case of the constant bit shift in the case of FIG. Therefore, after writing the data to be shifted in the data register 31,
From the shift amount N, the address calculation for obtaining the address of the corresponding register follows. Since one register has a storage area of 4 bytes, it is necessary to multiply N by 4 to obtain the corresponding register address from the shift amount N. now,
Since the value of N is stored in R0 and the operation of multiplying by 4 is the same as the 2-bit left shift, the SHL instruction for shifting the R0 register left by 2 bits is executed first. DATA is added to the value R0 that is four times N using the addition instruction ADD.
The address can be calculated by adding the addresses of the data registers indicated by G. If a value is read from the calculated address, it becomes a value shifted by N bits. in this case,
Regardless of the shift amount N, arbitrary N-bit shift is completed in 4 steps.

FIG. 16 shows the shift operation module 6 of FIG.
A program example for executing an arbitrary N-bit shift operation by using A is shown. Since the data to be shifted is stored in R1, it is written in the data register 31. Similarly, the shift amount N is written in the mode register 33. Finally, when the result register RLT is read, it has a value shifted by N bits. In the example of FIG. 16, FIG.
The shift operation is completed in 3 steps, which is less than the example of 5.

As is apparent from the description of FIGS. 11 to 16, the arithmetic form of the multiple bit shift described in FIG. 1 is advantageous for the constant shift, and the arbitrary bit shift shown in FIG.
The multi-bit shift operation form described in 1 above is advantageous.
In this sense, the configuration capable of selecting the operation form of the multiple bit shift described in FIG. 10 can dynamically or optimally select the optimum shift operation according to the operation content. As a result, it is possible to further improve the operation processing efficiency that involves a multi-bit shift operation. It should be noted that, in any of FIG. 1, FIG. 8 and FIG. 10, compared to the shift operation performed by the CPU not having the barrel shift instruction using the 1-bit or 2-bit shift operation instruction of the CPU without using the shift operation module. It goes without saying that performance improvement can be expected regardless of whether it is a constant shift or an arbitrary multiple bit shift.

Next, from the viewpoint of facilitating the design of the data processor or the shift operation module integrated into the semiconductor circuit, the design data of the shift operation modules 6, 6A and 6B described above is provided as a so-called IP module. What to do is explained.

Circuit module data provided as an IP module is at least graphic pattern data for forming the shift operation module on the semiconductor chip or RTL (register transfer level) by HDL (hardware description language). Including function description data such as. The figure pattern data is mask pattern data or electron beam drawing data. The function description data is so-called program data, and a circuit or the like can be specified by symbol display by reading it into a predetermined design tool.

The data of such an IP module is data for designing an integrated circuit to be formed on a semiconductor chip by using a computer 40 such as a design tool, as shown in FIG. A recording medium 41, such as a magnetic tape, a flexible disk, a hard disk, a CD-ROM, an MO (magnet optical disk), which can be read by the computer 40,
It is recorded so that it can be read by the computer 40. The recording medium 41 is attached to a disk drive device 40A that is a peripheral device of the computer 40, and in that state, the recording information is read into the memory or the like of the computer 40.
The data of the IP module corresponding to the shift calculation module recorded in the recording medium 41 is roughly classified into a hard IP module that can specify a mask pattern and a soft IP module that specifies a circuit at a function level. Hard I
As the data of the P module, the mask pattern data D1 for forming the shift operation module, the function description data D2 of the shift operation module, and the data of the IP module of the shift operation module are applied and the LS is applied.
When I is designed, it has verification data D3 for enabling simulation in consideration of the relationship with other modules. The data of the soft IP module includes at least the function description data D2 of the shift calculation module.

FIG. 18 illustrates another relationship between a computer and a recording medium recording design data and the like. The recording medium 41 is held by a server (IP providing server) 42 used for providing IP module data. Server 4
2 is a computer 4 such as an engineering workstation through a network 43 such as the Internet
Connected to 0. The design data stored in the recording medium 41 is downloaded to the computer 40 via the network 43. The downloaded design data is stored in a local hard disk or memory of the computer 40 and used for designing a semiconductor integrated circuit.

By using the data of the shift operation module stored and provided in the recording medium 41, C
It is possible to facilitate the design of a semiconductor integrated circuit that can efficiently perform a shift operation of arbitrary plural bits by diverting a data transfer instruction executed by PU.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, the circuit module on-chip in the data processor is not limited to that shown in FIG. 1 and can be changed as appropriate. The data transfer instruction is not limited to the MOV instruction. The instruction may have a mnemonic such as STORE or LOAD, or may be another instruction.

[0063]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the operation is designated by the read address of the shift data and the shift amount is changed,
In addition, since the shift calculation module adopts means for using the set value of the mode register to specify the shift amount by specifying the calculation according to the read address of the shift data,
The shift arithmetic circuit can be realized as an external I / O device without depending on the special architecture of the CPU. Also, no changes are required to the existing CPU architecture. Conventionally, a shift operation of an arbitrary bit, which is performed by combining a plurality of 1-bit or 2-bit shift operation instructions,
Since it can be executed by an external shift arithmetic circuit, the program execution speed can be improved. Since it is not necessary to change the CPU, an arbitrary bit shift arithmetic circuit can be added later to most of the CPUs that support the data transfer instruction. In short, it becomes possible to provide a shift operation module that can perform the shift operation without using a dedicated shift operation instruction of arbitrary plural bits.

Further, by designing the mask pattern or the functional description of the shift operation module described above in a computer-readable recording medium and providing it,
It is possible to facilitate the design of the shift operation module capable of performing the shift operation of arbitrary plural bits and further the semiconductor integrated circuit adopting such a shift operation module.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an example of a shift calculation module.

FIG. 2 is a block diagram showing an example of a data processor.

FIG. 3 is an explanatory diagram of a logical shift left operation.

FIG. 4 is an explanatory diagram of a logical right shift arithmetic operation.

FIG. 5 is an explanatory diagram of an arithmetic left shift calculation operation.

FIG. 6 is an explanatory diagram of arithmetic right shift operation.

FIG. 7 is an address mapping diagram illustrating a register space in the shift operation module.

FIG. 8 is a block diagram showing an example of another shift calculation module.

9 is an address mapping diagram illustrating a register space in the shift operation module of FIG.

FIG. 10 is a block diagram showing an example of still another shift calculation module.

FIG. 11 is an explanatory diagram showing a program example when a CPU having no barrel shift instruction executes a constant shift operation using a 1-bit or 2-bit shift operation instruction of the CPU without using a shift operation module. is there.

12 is an explanatory diagram showing an example of a program for performing a constant shift operation using the shift operation module of FIG.

13 is an explanatory diagram exemplifying a program for performing a constant shift operation using the shift operation module of FIG.

FIG. 14 is an explanatory diagram showing a program example in the case where a CPU having no barrel shift instruction executes an arbitrary N-bit shift operation using a 1-bit or 2-bit shift operation instruction of the CPU without using a shift operation module. It is a figure.

FIG. 15 is an explanatory diagram showing a program example when an arbitrary N-bit shift operation is executed using the shift operation module of FIG.

16 is an explanatory diagram showing a program example in the case of performing an arbitrary N-bit shift operation using the shift operation module of FIG.

FIG. 17 is an explanatory diagram illustrating the relationship between a computer and a recording medium that records IP module data of a shift calculation module.

FIG. 18 is an explanatory diagram illustrating another relationship between a computer and a recording medium that records IP module data of a shift calculation module.

[Explanation of symbols]

1 Data Processor 2 CPU 6, 6A, 6B Shift Operation Module 21 CPU Bus IAB Address Bus IDB Data Bus ICB Control 30, 30A, 30B Control Unit 31 Data Register 32 Barrel Shifter 33 Mode Register 34 Module Bus 35, 35A, 35B Address Decoder 36 selectors LST1 to LST32, RST1 to RST32 shift data register RLT result register 40 computer 41 recording medium

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tatsuro Nishino             Hitachi, 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido             Inside North Sea Semiconductor Co., Ltd. (72) Inventor Kenichi Ishibashi             Hitachi, 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido             Inside North Sea Semiconductor Co., Ltd. F-term (reference) 5B022 AA05 BA00 CA01 DA01 DA09                       DA10 EA03 FA12

Claims (10)

[Claims] 1. A semiconductor chip including a CPU, a shift operation module, and a bus connecting the CPU and the shift operation module, wherein the shift operation module includes a data register for latching data from the bus. , A barrel shifter capable of performing a shift operation on the data latched in the data register and outputting the shift data. The barrel shifter has a C when a CPU specifies a read address of the shift data and executes a data transfer instruction.
A semiconductor integrated circuit, wherein a PU performs a shift operation with a shift amount according to a read address of shift data output to a bus. 2. A CPU, a shift operation module, and a bus connecting the CPU and the shift operation module are included in one semiconductor chip, and the shift operation module includes a data register for latching data from the bus. , A barrel shifter capable of performing a shift operation on the data latched in the data register and outputting the shift data, and a mode register, wherein the CPU executes a data transfer instruction by designating a read address of the shift data by the CPU. At this time, the semiconductor integrated circuit is characterized in that a shift operation is performed with a shift amount according to the set value of the mode register. 3. A semiconductor chip including a CPU, a shift operation module, and a bus connecting the CPU and the shift operation module, wherein the shift operation module includes a data register for latching data from the bus. A barrel shifter capable of performing a shift operation on the data latched in the data register and outputting the shift data, wherein the barrel shifter executes a data transfer instruction by the CPU designating a first read address of the shift data. , The CPU performs the shift operation with the shift amount according to the read address of the shift data output to the bus.
When the data transfer instruction is executed by designating the second read address of the shift data, the semiconductor integrated circuit performs a shift operation with a shift amount according to the set value of the mode register. 4. A semiconductor chip including a CPU, a shift operation module, and a bus connecting the CPU and the shift operation module, wherein the shift operation module includes a data register, a barrel shifter, and a mode register. And a control unit, wherein the shift operation module is assigned to a predetermined address area in the address space of the CPU, and the predetermined address area has an address assigned to a data register,
The control unit includes an address assigned to a mode register, a plurality of addresses assigned to a shift amount, and an address assigned to a specific shift operation. One of the plurality of addresses assigned to the shift amount is input from the bus to the control unit. In response to
Barrel shift the data of the data register to the barrel shifter by the shift amount specified by the address,
Output the barrel-shifted data to the bus,
Further, in response to the address assigned to the specific shift operation being input from the bus, the data of the data register is barrel-shifted to the barrel shifter by a shift amount designated by the first set value of the mode register. The semiconductor integrated circuit is characterized in that the data subjected to the barrel shift operation is output to the bus. 5. The mode register specifies whether the barrel shift operation by the barrel shifter is a logical shift operation or an arithmetic shift operation, according to a second set value of the mode register. Semiconductor integrated circuit. 6. The CPU can execute a data transfer instruction in which an address assigned to the shift amount is described in a source operand designation field, and output an address corresponding to the shift amount to the bus. The semiconductor integrated circuit according to claim 4. 7. The CPU can execute a data transfer instruction in which an address assigned to a specific shift operation is described in a source operand designation field, and output an address corresponding to the specific shift operation to the bus. The semiconductor integrated circuit according to claim 4, which is characterized in that: 8. A recording medium in which circuit module data for designing a semiconductor integrated circuit to be formed on a semiconductor chip is recorded so that it can be read by a computer, and the circuit module data stored in the recording medium is: Includes graphic pattern data or function description data for forming a shift operation module consisting of a data register, a barrel shifter, a mode register and a control unit on the semiconductor chip, the control unit assigning an address assigned to the data register and a mode register A plurality of addresses assigned to the shift amount and an address decoding unit for an address area including a plurality of addresses assigned to the shift amount, and detecting one of the plurality of addresses assigned to the shift amount from the bus by the address decoding unit. In response to The address barrel shifting operation of the data of the data register to said barrel shifter by the shift amount specified, in which to output the barrel shift operation data to the bus, a computer readable recording medium characterized in that. 9. A recording medium in which circuit module data for designing a semiconductor integrated circuit to be formed on a semiconductor chip is stored so that it can be read by a computer, and the circuit module data stored in the recording medium is: Includes graphic pattern data or function description data for forming a shift operation module consisting of a data register, a barrel shifter, a mode register and a control unit on the semiconductor chip, the control unit assigning an address assigned to the data register and a mode register The address assigned to the shift operation is detected by the address decoding means for the address area including the address assigned to the shift operation and the address area assigned to the shift operation. , Said Mo Computer reading, wherein the barrel shifter causes the barrel shifter to perform a barrel shift operation on the data in the data register, and outputs the barrel shifted data to the bus. Possible recording medium. 10. A recording medium in which circuit module data for designing a semiconductor integrated circuit to be formed on a semiconductor chip is stored so that it can be read by a computer, and the circuit module data stored in the recording medium is: Includes graphic pattern data or function description data for forming a shift operation module consisting of a data register, a barrel shifter, a mode register and a control unit on the semiconductor chip, the control unit assigning an address assigned to the data register and a mode register Address address, a plurality of addresses assigned to a shift amount, and an address decoding unit for an address area including an address assigned to a specific shift operation, and one of the plurality of addresses assigned to the shift amount by the address decoding unit is the bus. In response to detecting from being et input,
Barrel shift the data of the data register to the barrel shifter by the shift amount specified by the address,
Output the barrel-shifted data to the bus,
Further, in response to the address assigned to the specific shift operation being input from the bus, the data of the data register is barrel-shifted to the barrel shifter by a shift amount designated by the first set value of the mode register. A computer-readable recording medium, characterized in that the data subjected to barrel shift operation is output to the bus.