JP2003014807A - Measuring method for capacitance as well as method and apparatus for inspection of circuit board - Google Patents

Measuring method for capacitance as well as method and apparatus for inspection of circuit board

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Publication number
JP2003014807A
JP2003014807A JP2001195945A JP2001195945A JP2003014807A JP 2003014807 A JP2003014807 A JP 2003014807A JP 2001195945 A JP2001195945 A JP 2001195945A JP 2001195945 A JP2001195945 A JP 2001195945A JP 2003014807 A JP2003014807 A JP 2003014807A
Authority
JP
Japan
Prior art keywords
capacitance
electrode
conductor pattern
inter
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001195945A
Other languages
Japanese (ja)
Other versions
JP4663918B2 (en
Inventor
Yuji Tanaka
裕士 田中
Hideaki Minami
秀明 南
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hioki EE Corp
Original Assignee
Hioki EE Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hioki EE Corp filed Critical Hioki EE Corp
Priority to JP2001195945A priority Critical patent/JP4663918B2/en
Publication of JP2003014807A publication Critical patent/JP2003014807A/en
Application granted granted Critical
Publication of JP4663918B2 publication Critical patent/JP4663918B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a measuring method in which the capacitance of a pattern is measured in a short time and with satisfactory efficiency. SOLUTION: In the method in which a probe is brought into contact with each pattern so as to measure an interelectrode capacitance across each pattern and an electrode, a process (Step 30) in which the disconnection of the pattern is inspected is executed, a process (Step 32) in which a first interelectrode capacitance is measured regarding each pattern whose disconnection is not detected in a state that the probe is separated, a process (Step 33) in which the probe is brought into contact with the pattern so as to measure a second interelectrode capacitance and a process (Step 34) in which the difference capacitance between both interelectrode capacitances is stored as interelectrode capacitances with reference to the pattern are executed, a process (Step 36) wherein a group of patterns to which the stored interelectrode capacitances are brought close is detected, and a process (Step 37) in which a short circuit across the patterns belonging to the group is inspected are executed. The interelectrode capacitance stored by excluding the interelectrode capacitance of the patterns whose short circuit is detected is regarded as a normal interelectrode capacitance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、測定対象の回路基
板における複数の導体パターンと基準電極との間の対電
極間静電容量を測定する静電容量測定方法、測定した対
電極間静電容量に基づいて回路基板を検査する回路基板
検査方法および回路基板検査装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance measuring method for measuring the capacitance between counter electrodes between a plurality of conductor patterns and a reference electrode on a circuit board to be measured, and the measured capacitance between counter electrodes. The present invention relates to a circuit board inspection method and a circuit board inspection device for inspecting a circuit board based on a capacity.

【0002】[0002]

【従来の技術】この種の静電容量測定方法として、図4
に示す手順で静電容量を測定する静電容量測定方法が従
来から知られている。この静電容量測定方法は、例えば
図2に示す回路基板検査装置41による回路基板検査処
理で実施されている。この場合、回路基板検査装置41
は、絶縁フィルム2aが貼付された電極2bを有する電
極部2、検査用プローブ3,4、移動機構5a,5b、
制御部46、RAM7およびROM8を備えて構成され
ている。一方、検査対象の回路基板Pは、図3に示すよ
うに、ガラスエポキシ系基材の表面に複数の導体パター
ンCP1 ,CP2,・・・(以下、特に区別しないとき
には「導体パターンCP」ともいう)が形成されて構成
されている。また、各導体パターンCPにおける各端点
には、同図に示すように、ランドが形成され、このラン
ドは、測定ポイントTP1 ,TP2,・・・(以下、特
に区別しないときには「測定ポイントTP」ともいう)
として機能する。
2. Description of the Related Art FIG.
A capacitance measuring method for measuring the capacitance according to the procedure shown in FIG. This capacitance measuring method is carried out, for example, in a circuit board inspection process by the circuit board inspection device 41 shown in FIG. In this case, the circuit board inspection device 41
Is an electrode portion 2 having an electrode 2b to which an insulating film 2a is attached, inspection probes 3 and 4, moving mechanisms 5a and 5b,
The control unit 46, the RAM 7 and the ROM 8 are provided. On the other hand, as shown in FIG. 3, the circuit board P to be inspected has a plurality of conductor patterns CP1, CP2, ... On the surface of the glass epoxy base material (hereinafter, also referred to as “conductor pattern CP” unless otherwise distinguished). ) Is formed and configured. Further, as shown in the figure, lands are formed at each end point of each conductor pattern CP, and these lands are referred to as measurement points TP1, TP2 ,. Say)
Function as.

【0003】次に、回路基板検査装置41の動作につい
て図2〜図4を参照して説明する。まず、導体パターン
CPの形成面を上向きにして回路基板Pを電極部2にお
ける電極2bの上に載置する。次に、制御部46が、移
動機構5a,5bを制御してプローブ固定具3a,4a
に取り付けられた検査用プローブ3,4を回路基板Pの
導体パターンCP1 における測定ポイントTP1 ,TP
2 にそれぞれ接触させる(ステップ50)。次いで、制
御部46が、検査信号としての交流電圧を順次出力する
ことにより、測定ポイントTP1 における導体パターン
CP1 と電極2bとの間の対電極間静電容量CTC1 、お
よび測定ポイントTP2 における導体パターンCP1 と
電極2bとの間の対電極間静電容量CTC2 をオートレン
ジ測定でそれぞれ仮測定する。この場合、対電極間静電
容量を正確に測定するためには、測定される対電極間静
電容量に適した測定レンジを選択する必要がある。つま
り、例えば測定レンジの上限値や下限値の近傍まで達す
る対電極間静電容量をその測定レンジで正確に測定する
のは困難となる。このため、仮測定した各対電極間静電
容量CTC1 ,CTC2 (以下、区別しないときには、「対
電極間静電容量CTC」ともいう)に適した測定レンジを
選択して設定する(ステップ51)。より具体的には、
例えば、対電極間静電容量CTC1 をフルスケール20p
Fの測定レンジで仮測定して3pFを得た際には、3p
Fを正確に測定するのに最も適したフルスケール10p
Fの測定レンジを選択して設定する。
Next, the operation of the circuit board inspection device 41 will be described with reference to FIGS. First, the circuit board P is placed on the electrode 2b in the electrode portion 2 with the surface on which the conductor pattern CP is formed facing upward. Next, the controller 46 controls the moving mechanisms 5a and 5b to control the probe fixtures 3a and 4a.
The test probes 3 and 4 attached to the measurement points TP1 and TP on the conductor pattern CP1 of the circuit board P.
2 are contacted with each other (step 50). Then, the control unit 46 sequentially outputs the AC voltage as the inspection signal, so that the inter-electrode capacitance CTC1 between the conductor pattern CP1 and the electrode 2b at the measurement point TP1 and the conductor pattern CP1 at the measurement point TP2. Electrostatic capacitance CTC2 between the counter electrode and the electrode 2b is provisionally measured by autoranging. In this case, in order to accurately measure the capacitance between the counter electrodes, it is necessary to select a measurement range suitable for the measured capacitance between the counter electrodes. That is, for example, it is difficult to accurately measure the capacitance between the counter electrodes which reaches near the upper limit value or the lower limit value of the measurement range in the measurement range. Therefore, a measurement range suitable for each tentatively measured capacitance between counter electrodes CTC1 and CTC2 (hereinafter, also referred to as "counterelectrode capacitance CTC" when no distinction is made) is selected and set (step 51). . More specifically,
For example, set the capacitance between counter electrodes CTC1 to full scale 20p.
When 3pF is obtained by tentative measurement in the F measurement range, 3p
Full scale 10p most suitable for measuring F accurately
Select and set the F measurement range.

【0004】次に、制御部46は、移動機構5a,5b
を制御して検査用プローブ3,4を上動させて各測定ポ
イントTP1 ,TP2 から若干離間させ、この状態で検
査信号としての交流電圧を順次出力することにより、測
定ポイントTP1 での浮遊容量CS1、および測定ポイン
トTP2 での浮遊容量CS2を設定した測定レンジでそれ
ぞれ測定してRAM7に記憶させる(ステップ52)。
このステップ52による測定処理により、検査用プロー
ブ3,4やプローブ固定具3a,4aに起因する浮遊容
量が測定される。次に、制御部46は、移動機構5a,
5bを制御して検査用プローブ3,4を各測定ポイント
TP1 ,TP2 に再度接触させ、検査信号としての交流
電圧を順次出力することにより、測定ポイントTP1 に
おける導体パターンCP1 と電極2bとの間の対電極間
静電容量CPR1 、および測定ポイントTP2 における導
体パターンCP1 と電極2bとの間の対電極間静電容量
CPR2 (以下、区別しないときには「対電極間静電容量
CPR」ともいう)をそれぞれステップ51において設定
した測定レンジで測定する(ステップ53)。次いで、
制御部46は、測定した各測定ポイントTP1 ,TP2
における各対電極間静電容量CPR1 ,CPR2 から各測定
ポイントTP1 ,TP2 における各浮遊容量CS1,CS2
(以下、区別しないときには、「浮遊容量CS 」ともい
う)を差し引き、この差分容量を浮遊容量の影響を排除
した各測定ポイントTP1 ,TP2 における正規の対電
極間静電容量CTP1 ,CTP2 としてRAM7に記憶させ
る(ステップ54)。制御部46は、導体パターンCP
1 における残りの測定ポイントTP3 に対しても上記各
ステップ50〜54を実施し、対電極間静電容量CTP3
を算出してRAM7に記憶させる。
Next, the control unit 46 controls the moving mechanisms 5a and 5b.
Control unit to move the inspection probes 3 and 4 upward to separate them slightly from the measurement points TP1 and TP2, and sequentially output an AC voltage as a test signal in this state, thereby stray capacitance CS1 at the measurement point TP1. , And the stray capacitance CS2 at the measurement point TP2 are measured in the set measurement ranges and stored in the RAM 7 (step 52).
By the measurement process in step 52, the stray capacitance caused by the inspection probes 3 and 4 and the probe fixtures 3a and 4a is measured. Next, the control unit 46 causes the moving mechanism 5a,
5b is controlled to bring the inspection probes 3 and 4 into contact with the measurement points TP1 and TP2 again, and the alternating voltage as the inspection signal is sequentially output, so that between the conductor pattern CP1 and the electrode 2b at the measurement point TP1. The inter-electrode capacitance CPR1 and the inter-electrode capacitance CPR2 between the conductor pattern CP1 and the electrode 2b at the measurement point TP2 (hereinafter, also referred to as “inter-electrode capacitance CPR” when not distinguished) are respectively set. The measurement is performed in the measurement range set in step 51 (step 53). Then
The control unit 46 controls the measured measurement points TP1 and TP2.
From the electrostatic capacitances CPR1 and CPR2 between the counter electrodes to the stray capacitances CS1 and CS2 at the measurement points TP1 and TP2, respectively.
(Hereinafter, when no distinction is made, it is also referred to as "stray capacitance CS"), and this differential capacitance is stored in the RAM7 as the regular interelectrode capacitances CTP1 and CTP2 at the respective measurement points TP1 and TP2 that eliminate the influence of the stray capacitance. It is stored (step 54). The control unit 46 uses the conductor pattern CP.
The above steps 50 to 54 are carried out for the remaining measurement point TP3 in 1 as well, and the capacitance between counter electrodes CTP3
Is calculated and stored in the RAM 7.

【0005】制御部46は、すべての測定ポイントTP
における対電極間静電容量CTPを測定したか否かを判断
し(ステップ55)、未測定の測定ポイントが存在する
ときには上記各ステップ50〜54を繰り返し実施し
て、他の導体パターンCPに規定された各測定ポイント
TPにおける対電極間静電容量CTPを順次測定しRAM
7に記憶させる。次に、制御部46は、ステップ55に
おいてすべての測定ポイントTPの対電極間静電容量C
TPを測定したと判断したときには、RAM7に記憶させ
た各対電極間静電容量CTPに基づき、各導体パターンC
P毎に、その導体パターンCP内の各測定ポイントTP
における対電極間静電容量CTP,CTP同士を比較し、対
電極間静電容量CTPが異なる導体パターンCPが存在す
るか否かを判別する(ステップ56)。この場合、図3
に示す導体パターンCP2 のように断線箇所が存在しな
いときには、各測定ポイントTP4 〜TP6 における各
対電極間静電容量CTP4 〜CTP6 は互いに同一または近
似する容量値となる。一方、導体パターンCP1 のよう
に断線箇所Bが存在するときには、測定ポイントTP2
における対電極間静電容量CTP2 が、本来的には同一の
容量となるべき他の測定ポイントTP1 ,TP3 におけ
る対電極間静電容量CTP1 ,CTP3 とは異なる値とな
る。このため、制御部46は、ステップ56において、
同一の導体パターンCPにおける各測定ポイントTPの
各対電極間静電容量CTPが互いに異なるときには、この
導体パターンCPに対して断線検査を実施して、断線箇
所を特定する(ステップ57)。具体的には、移動機構
5a,5bを制御して一方の検査用プローブ3をその対
電極間静電容量CTPが他の対電極間静電容量CTPと異な
る測定ポイントTPに接触させると共に、他方の検査用
プローブ4を残りの測定ポイントTPに順次接触させつ
つ両検査用プローブ3,4間の抵抗値を測定することに
より、断線箇所を特定して断線箇所情報をRAM7に記
憶させる。
The control unit 46 controls all the measurement points TP.
It is determined whether or not the capacitance CTP between the counter electrodes has been measured (step 55), and when there is an unmeasured measurement point, the above steps 50 to 54 are repeated to define another conductor pattern CP. The measured capacitance CTP between the counter electrodes at each measured point TP is sequentially measured and RAM
Store in 7. Next, the control unit 46, in step 55, the capacitance C between the counter electrodes of all the measurement points TP.
When it is determined that TP has been measured, each conductor pattern C is calculated based on the capacitance CTP between the counter electrodes stored in the RAM 7.
For each P, each measurement point TP in the conductor pattern CP
The electrostatic capacitances CTP and CTP between the counter electrodes are compared with each other, and it is determined whether or not there are conductor patterns CP having different electrostatic capacitances CTP between the counter electrodes (step 56). In this case,
When there is no disconnection point like the conductor pattern CP2 shown in FIG. 3, the capacitances CTP4 to CTP6 between the counter electrodes at the measurement points TP4 to TP6 have the same or similar capacitance values. On the other hand, when the disconnection point B exists like the conductor pattern CP1, the measurement point TP2
The electrostatic capacitance CTP2 between the counter electrodes at is different from the electrostatic capacitances CTP1 and CTP3 between the counter electrodes at the other measurement points TP1 and TP3, which should have essentially the same capacitance. Therefore, the control unit 46, in step 56,
When the capacitance CTP between the counter electrodes at each measurement point TP in the same conductor pattern CP is different from each other, a disconnection inspection is performed on this conductor pattern CP to identify the disconnection point (step 57). Specifically, the moving mechanisms 5a and 5b are controlled to bring one of the inspection probes 3 into contact with a measurement point TP whose electrostatic capacitance CTP between its counter electrodes is different from that of the other electrostatic capacitance CTP between its counter electrodes, and By measuring the resistance value between the inspection probes 3 and 4 while sequentially contacting the inspection probe 4 with the remaining measurement points TP, the disconnection point is specified and the disconnection point information is stored in the RAM 7.

【0006】次いで、ステップ56において、対電極間
静電容量CTPが異なる導体パターンCPがなかったと
き、およびステップ57の断線検査を終了したときに
は、制御部46は、RAM7に記憶させた各対電極間静
電容量CTPに基づき、対電極間静電容量CTPが互いに近
似する導体パターンCPの群の有無を検出する(ステッ
プ58)。この際に、対電極間静電容量CTPが互いに近
似する導体パターンCPの群を検出したときには、その
導体パターンCP,CP間に、図3に示すような短絡箇
所Aが存在する可能性がある。このため、制御部46
は、対電極間静電容量CTPが互いに近似する導体パター
ンCP,CP間の短絡検査を実施する(ステップ5
9)。具体的には、移動機構5a,5bを制御して対電
極間静電容量CTPが互いに近似する一対の導体パターン
CP,CPに検査用プローブ3,4をそれぞれ接触さ
せ、両導体パターンCP,CP間の抵抗値を測定するこ
とにより、短絡箇所の有無を特定する。次いで、短絡箇
所が存在するときには、短絡箇所情報(短絡の有無の情
報)をRAM7に記憶させる。一方、ステップ58にお
いて、対電極間静電容量CTPが互いに近似する導体パタ
ーンCPの群が検出されないときには、この静電容量測
定処理を終了する。
Next, in step 56, when there is no conductor pattern CP having a different inter-electrode capacitance CTP, and when the disconnection inspection in step 57 is completed, the control unit 46 causes each counter electrode stored in the RAM 7 to be stored. Based on the inter-electrode capacitance CTP, the presence / absence of a group of conductor patterns CP whose inter-electrode capacitances CTP are similar to each other is detected (step 58). At this time, when a group of conductor patterns CP whose counter electrode electrostatic capacitances CTP are close to each other is detected, there is a possibility that a short circuit portion A as shown in FIG. 3 exists between the conductor patterns CP and CP. . Therefore, the control unit 46
Performs a short-circuit inspection between the conductor patterns CP and CP in which the electrostatic capacitances CTP between the counter electrodes are close to each other (step 5).
9). Specifically, by controlling the moving mechanisms 5a and 5b, the inspection probes 3 and 4 are respectively brought into contact with the pair of conductor patterns CP and CP whose electrostatic capacitances CTP between the counter electrodes are close to each other, and both conductor patterns CP and CP are The presence or absence of a short-circuit point is specified by measuring the resistance value between them. Next, when there is a short-circuited portion, the short-circuited portion information (information regarding the presence or absence of a short-circuit) is stored in the RAM 7. On the other hand, in step 58, when the group of the conductor patterns CP having the electrostatic capacitances CTP between the counter electrodes that are close to each other is not detected, the electrostatic capacitance measuring process is ended.

【0007】この回路基板検査装置41による静電容量
測定方法によれば、断線した導体パターンCP、および
この断線した導体パターンCPの断線箇所を検出し、か
つ他の導体パターンCPに短絡している導体パターンC
Pを検出しつつ、正常な導体パターンCPについての対
電極間静電容量CTPの測定および記憶が可能となってい
る。
According to the capacitance measuring method by the circuit board inspecting device 41, the broken conductor pattern CP and the broken portion of the broken conductor pattern CP are detected and short-circuited to another conductor pattern CP. Conductor pattern C
While detecting P, it is possible to measure and store the capacitance CTP between the counter electrodes for the normal conductor pattern CP.

【0008】[0008]

【発明が解決しようとする課題】ところが、従来の静電
容量測定方法には、以下の問題点がある。すなわち、従
来の静電容量測定方法では、すべての測定ポイントTP
において、適正な測定レンジを選択するために対電極間
静電容量CTCを測定した後に浮遊容量CS を測定し、そ
の上で、さらに対電極間静電容量CPRを測定して正規な
対電極間静電容量CTPを算出する必要がある。したがっ
て、各測定ポイントTPにおいて、少なくとも2回は検
査用プローブ3(または4)を測定ポイントTPに対し
て接離動(上下動)させる必要がある。この場合、検査
用プローブ3(または4)の上下動は、検査用プローブ
3に対する加速やブレーキの制御を行う関係上、ある程
度長いタクトタイムを必要とする。したがって、すべて
の導体パターンCPにおけるすべての測定ポイントTP
についての対電極間静電容量CTPを測定するために膨大
な時間を要するという問題点がある。また、導体パター
ンCPに断線が存在していた場合には、その導体パター
ンCP上の各測定ポイントTPに対する対電極間静電容
量CTPの測定が無駄となる。このため、測定効率が低下
しているという問題点もある。
However, the conventional capacitance measuring method has the following problems. That is, in the conventional capacitance measuring method, all measurement points TP
In order to select an appropriate measurement range, the inter-electrode capacitance CTC is measured, then the stray capacitance CS is measured, and then the inter-electrode capacitance CPR is further measured to determine the normal inter-electrode capacitance. It is necessary to calculate the electrostatic capacitance CTP. Therefore, at each measurement point TP, it is necessary to move the inspection probe 3 (or 4) toward and away from the measurement point TP (up and down movement) at least twice. In this case, the vertical movement of the inspection probe 3 (or 4) requires a somewhat long tact time in order to control the acceleration and the brake of the inspection probe 3. Therefore, all measurement points TP on all conductor patterns CP
There is a problem that it takes an enormous amount of time to measure the capacitance C TP between the counter electrodes of the above. Further, when the conductor pattern CP has a disconnection, the measurement of the capacitance CTP between the counter electrodes for each measurement point TP on the conductor pattern CP becomes useless. Therefore, there is a problem that the measurement efficiency is lowered.

【0009】本発明は、かかる問題点に鑑みてなされた
ものであり、短時間で効率よく導体パターンの静電容量
を測定し得る静電容量測定方法を提供することを主目的
とする。また、短時間で効率よく回路基板を検査し得る
回路基板検査方法および回路基板検査装置を提供するこ
とを他の目的とする。
The present invention has been made in view of the above problems, and its main object is to provide a capacitance measuring method capable of efficiently measuring the capacitance of a conductor pattern in a short time. Another object is to provide a circuit board inspecting method and a circuit board inspecting apparatus capable of efficiently inspecting a circuit board in a short time.

【0010】[0010]

【課題を解決するための手段】上記目的を達成すべく請
求項1記載の静電容量測定方法は、測定対象の回路基板
における複数の導体パターンに接触型のプローブを順次
接触させて当該各導体パターンと基準電極との間の対電
極間静電容量を測定する静電容量測定方法であって、前
記各導体パターンの断線を検査する断線検査処理を実行
した後に、前記断線検査処理において断線が検出されな
かった前記各導体パターン毎に、当該導体パターンに対
して前記プローブを離間した状態で配置させて当該プロ
ーブと前記基準電極との間の第1の対電極間静電容量を
測定する第1の容量測定処理と、前記プローブを離間し
た状態から前記導体パターン上の1つの測定ポイントに
接触させて当該導体パターンと前記基準電極との間の第
2の対電極間静電容量を測定する第2の容量測定処理
と、前記測定した第2の対電極間静電容量と前記第1の
対電極間静電容量との差分容量を当該導体パターンに対
応する前記対電極間静電容量として保存する測定結果保
存処理とを実行し、前記保存した対電極間静電容量同士
が近接する前記導体パターンの群を検出する検出処理
と、当該検出された群に属する前記導体パターン同士間
の短絡を検査する短絡検査処理とを実行し、前記短絡検
査処理によって短絡が検出された前記導体パターンにつ
いての前記対電極間静電容量を除いて前記保存した対電
極間静電容量を正規な前記対電極間静電容量とすること
を特徴とする。
In order to achieve the above object, the capacitance measuring method according to claim 1 is such that a contact type probe is brought into contact with a plurality of conductor patterns on a circuit board to be measured one after another. A capacitance measuring method for measuring a capacitance between counter electrodes between a pattern and a reference electrode, wherein after performing a disconnection inspection process for inspecting a disconnection of each of the conductor patterns, a disconnection occurs in the disconnection inspection process. A first inter-electrode capacitance between the probe and the reference electrode is measured by arranging the probe in a state of being separated from the conductor pattern for each of the conductor patterns not detected. And a second inter-electrode electrostatic capacitance between the conductor pattern and the reference electrode by contacting one measurement point on the conductor pattern from a state where the probe is separated. A second capacitance measuring process for measuring an amount, and a difference capacitance between the measured second capacitance between the counter electrodes and the first capacitance between the counter electrodes is measured between the counter electrodes corresponding to the conductor pattern. A detection process of executing a measurement result saving process of saving as electrostatic capacitance, and detecting a group of the conductor patterns in which the stored inter-electrode capacitances are close to each other, and the conductor pattern belonging to the detected group A short-circuit inspection process for inspecting a short circuit between the electrodes is performed, and the stored inter-electrode capacitance is excluded except the inter-electrode capacitance for the conductor pattern in which a short circuit is detected by the short-circuit inspection process. It is characterized in that it is a normal capacitance between the counter electrodes.

【0011】請求項2記載の回路基板検査方法は、検査
対象の回路基板における各導体パターン毎に、当該導体
パターンに対して接触型のプローブを離間した状態で配
置させて当該プローブと前記基準電極との間の第1の対
電極間静電容量を測定する第1の容量測定処理と、前記
プローブを離間した状態から前記導体パターン上の1つ
の測定ポイントに接触させて当該導体パターンと前記基
準電極との間の第2の対電極間静電容量を測定する第2
の容量測定処理と、前記測定した第2の対電極間静電容
量と前記第1の対電極間静電容量との差分容量を当該導
体パターンに対応する前記対電極間静電容量として保存
する測定結果保存処理とを実行し、請求項1記載の静電
容量測定方法によって測定された前記各正規な対電極間
静電容量を基準データとして、前記検査対象の回路基板
についての前記保存した対電極間静電容量が、対応する
前記基準データに対して所定範囲内のときに当該導体パ
ターンに断線および短絡が生じていないと判別すること
を特徴とする。
According to a second aspect of the present invention, there is provided a circuit board inspecting method, in which a contact-type probe is arranged for each conductor pattern on a circuit board to be inspected so as to be spaced from the conductor pattern, and the probe and the reference electrode. A first capacitance measuring process for measuring a first inter-electrode capacitance between the conductor pattern and the reference by bringing the probe into contact with one measurement point on the conductor pattern from a separated state. A second measuring capacitance between a second counter electrode and the electrode;
And the difference capacitance between the measured second capacitance between the counter electrodes and the first capacitance between the counter electrodes is stored as the capacitance between the counter electrodes corresponding to the conductor pattern. A measurement result storage process is executed, and the stored pairs of the circuit board to be inspected are used with the respective regular inter-electrode capacitances measured by the capacitance measurement method according to claim 1 as reference data. When the inter-electrode capacitance is within a predetermined range with respect to the corresponding reference data, it is determined that the conductor pattern is not broken or short-circuited.

【0012】請求項3記載の回路基板検査装置は、接触
型のプローブと、測定対象の回路基板における複数の導
体パターンの各々に前記プローブを接触させた状態で当
該各導体パターンと基準電極との間の対電極間静電容量
を測定すると共に当該測定した対電極間静電容量に基づ
いて検査対象の回路基板を検査する制御部とを備えた回
路基板検査装置であって、前記制御部は、前記各導体パ
ターンの断線を検査する断線検査処理を実行した後に、
前記断線検査処理において断線が検出されなかった前記
各導体パターン毎に、当該導体パターンに対して前記プ
ローブを離間した状態で配置させて当該プローブと前記
基準電極との間の第1の対電極間静電容量を測定する第
1の容量測定処理と、前記プローブを離間した状態から
前記導体パターン上の1つの測定ポイントに接触させて
当該導体パターンと前記基準電極との間の第2の対電極
間静電容量を測定する第2の容量測定処理と、前記測定
した第2の対電極間静電容量と前記第1の対電極間静電
容量との差分容量を当該導体パターンに対応する前記対
電極間静電容量として保存する測定結果保存処理とを実
行し、かつ、前記保存した対電極間静電容量同士が近接
する前記導体パターンの群を検出する検出処理と、当該
検出された群に属する前記導体パターン同士間の短絡を
検査する短絡検査処理とを実行し、当該短絡検査処理に
よって短絡が検出された前記導体パターンについての前
記対電極間静電容量を除いて前記保存した対電極間静電
容量を正規な前記対電極間静電容量とすることを特徴と
する。
According to a third aspect of the present invention, there is provided a circuit board inspecting apparatus which comprises a contact-type probe and each conductor pattern and a reference electrode in a state where the probe is in contact with each of a plurality of conductor patterns on a circuit board to be measured. A circuit board inspection apparatus comprising: a control unit that measures an inter-counter electrode electrostatic capacitance between and a control unit that inspects a circuit board to be inspected based on the measured inter-electrode electrostatic capacitance, wherein the control unit is After performing the disconnection inspection process for inspecting the disconnection of each of the conductor patterns,
For each of the conductor patterns for which no disconnection was detected in the disconnection inspection process, the probe is arranged in a state of being separated from the conductor pattern, and the first counter electrode between the probe and the reference electrode is arranged. A first capacitance measurement process for measuring capacitance, and a second counter electrode between the conductor pattern and the reference electrode by bringing the probe into contact with one measurement point on the conductor pattern from a separated state. A second capacitance measuring process for measuring an inter-electrode capacitance, and a difference capacitance between the measured second inter-electrode capacitance and the first inter-electrode capacitance, which corresponds to the conductor pattern. A detection process of performing a measurement result storage process of storing the capacitance between the counter electrodes and detecting a group of the conductor patterns in which the stored capacitances between the counter electrodes are close to each other, and the detected group. Belongs to Performing a short-circuit inspection process for inspecting a short circuit between the conductor patterns, and between the stored counter electrodes except for the inter-electrode capacitance of the conductor pattern in which a short circuit is detected by the short-circuit inspection process. It is characterized in that the electrostatic capacitance is a normal electrostatic capacitance between the counter electrodes.

【0013】[0013]

【発明の実施の形態】以下、添付図面を参照して、本発
明に係る静電容量測定方法、回路基板検査方法および回
路基板検査装置の好適な発明の実施の形態について説明
する。なお、従来の回路基板検査装置41と同一の構成
要素、および検査対象の回路基板Pについては、同一の
符号を付して重複した説明を省略する。
BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of a capacitance measuring method, a circuit board inspecting method and a circuit board inspecting apparatus according to the present invention will be described below with reference to the accompanying drawings. The same components as those of the conventional circuit board inspecting device 41 and the circuit board P to be inspected are designated by the same reference numerals, and a duplicate description will be omitted.

【0014】最初に、本発明を適用した回路基板検査装
置1の構成について、図2を参照して説明する。
First, the structure of the circuit board inspection apparatus 1 to which the present invention is applied will be described with reference to FIG.

【0015】同図に示すように、回路基板検査装置1
は、電極部2、検査用プローブ3,4、移動機構5a,
5b、制御部6、RAM7およびROM8を備えて構成
されている。電極部2は、その表面に絶縁フィルム2a
が貼付された平板状の電極2bを有し検査対象の回路基
板Pを載置可能に構成されている。検査用プローブ3,
4は、接触型プローブであって、プローブ固定具3a,
4aを介して移動機構5a,5bに取り付けられた状態
で電極部2の上方に配設されている。制御部6は、電極
部2および検査用プローブ3,4を用いての回路基板P
に対する検査処理や、移動機構5a,5bの駆動制御な
どを実行する。RAM7は、導体パターンCP毎の測定
ポイントTPの位置データ、測定した浮遊容量CS 、測
定した対電極間静電容量CTP、検出した断線箇所や短絡
箇所の情報、および制御部6の演算結果などを一時的に
記憶する。ROM8は、制御部6の動作プログラムを記
憶する。
As shown in FIG. 1, the circuit board inspection apparatus 1
Is an electrode unit 2, inspection probes 3 and 4, a moving mechanism 5a,
5b, a control unit 6, a RAM 7 and a ROM 8 are provided. The electrode part 2 has an insulating film 2a on its surface.
It has a flat plate-shaped electrode 2b to which is attached so that a circuit board P to be inspected can be placed. Inspection probe 3,
4 is a contact type probe, which is a probe fixture 3a,
It is arranged above the electrode unit 2 in a state of being attached to the moving mechanisms 5a and 5b via the 4a. The control unit 6 includes a circuit board P using the electrode unit 2 and the inspection probes 3 and 4.
And the drive control of the moving mechanisms 5a and 5b. The RAM 7 stores the position data of the measurement point TP for each conductor pattern CP, the measured stray capacitance CS, the measured capacitance between counter electrodes CTP, the information on the detected disconnection point and short-circuited point, the calculation result of the control unit 6, and the like. Store temporarily. The ROM 8 stores the operation program of the control unit 6.

【0016】次に、回路基板検査装置1の動作につい
て、図1を参照して説明する。なお、回路基板検査装置
41と同一の動作については、その旨を記載して重複す
る説明は省略する。
Next, the operation of the circuit board inspection apparatus 1 will be described with reference to FIG. In addition, about the same operation | movement as the circuit board inspection apparatus 41, that effect is described and the overlapping description is abbreviate | omitted.

【0017】まず、導体パターンCP1 ,CP2 の形成
面を上向きにして回路基板Pを電極部2の上に載置す
る。
First, the circuit board P is placed on the electrode portion 2 with the surface on which the conductor patterns CP1 and CP2 are formed facing upward.

【0018】次に、制御部6が、図1に示す静電容量測
定処理を開始する。この処理では、制御部6は、移動機
構5a,5bを制御してプローブ固定具3a,4aに取
り付けられた検査用プローブ3,4を回路基板Pの導体
パターンCP1 の上方に移動させ、この導体パターンC
P1 に対する断線検査を実施する(ステップ30:断線
検査処理)。具体的には、制御部6は、検査用プローブ
3を図3に示す測定ポイントTP1 に接触させると共
に、検査用プローブ4を測定ポイントTP2 および測定
ポイントTP3 に順次接触させ、測定ポイントTP1 ,
TP2 間、測定ポイントTP1 ,TP3 間に検査信号と
しての交流電圧(または直流電圧)を出力することによ
り、各測定ポイントTP,TP間の抵抗値を測定して導
体パターンCP1 に対する断線を検査する。
Next, the control section 6 starts the capacitance measuring process shown in FIG. In this process, the control unit 6 controls the moving mechanisms 5a and 5b to move the inspection probes 3 and 4 attached to the probe fixtures 3a and 4a to above the conductor pattern CP1 of the circuit board P, and Pattern C
A disconnection inspection is performed on P1 (step 30: disconnection inspection processing). Specifically, the control unit 6 brings the inspection probe 3 into contact with the measurement point TP1 shown in FIG. 3, and simultaneously brings the inspection probe 4 into contact with the measurement point TP2 and the measurement point TP3 in order to make the measurement point TP1,
By outputting an AC voltage (or DC voltage) as a test signal between TP2 and between measurement points TP1 and TP3, the resistance value between each measurement point TP and TP is measured to inspect the conductor pattern CP1 for disconnection.

【0019】ステップ30において、図3に示すような
断線箇所Bが導体パターンCP1 に存在しないと判別し
たときには、制御部6は、移動機構5a,5bを制御し
て検査用プローブ3,4のいずれか一方(一例として検
査用プローブ4)を上動させると共に1つの測定ポイン
トTP(一例として測定ポイントTP1 )にいずれか他
方の検査用プローブ(一例として検査用プローブ3)の
接触を維持する。次いで、検査用プローブ3を介して検
査信号としての交流電圧を出力することにより、導体パ
ターンCP1 と電極2bとの間の仮の対電極間静電容量
CTC1 を仮測定する。続いて、制御部6は、測定した対
電極間静電容量CTC1 に基づいて、この導体パターンC
P1 の測定ポイントTPでの容量測定に適した測定レン
ジを選択して設定する(ステップ31)。次に、制御部
6は、移動機構5aを制御して検査用プローブ3を測定
ポイントTP1 から若干離間(上動)させ、この状態で
検査信号としての交流電圧を出力することにより、測定
ポイントTP1 での浮遊容量(本発明における第1の対
電極間静電容量に相当する)CS1を測定してRAM7に
記憶させる(ステップ32:第1の容量測定処理)。こ
れにより、その位置での検査用プローブ3やプローブ固
定具3aに起因する浮遊容量が測定される。
When it is determined in step 30 that the disconnection point B as shown in FIG. 3 does not exist in the conductor pattern CP1, the control section 6 controls the moving mechanisms 5a and 5b to determine which of the inspection probes 3 and 4 is to be used. One of the inspection probes (as an example, the inspection probe 4) is moved upward, and one measurement point TP (as an example, the measurement point TP1) is maintained in contact with the other inspection probe (as an example, the inspection probe 3). Then, by outputting an AC voltage as an inspection signal through the inspection probe 3, the provisional inter-electrode capacitance CTC1 between the conductor pattern CP1 and the electrode 2b is provisionally measured. Subsequently, the control unit 6 determines the conductor pattern C based on the measured capacitance CTC1 between the counter electrodes.
A measurement range suitable for the capacitance measurement at the measurement point TP of P1 is selected and set (step 31). Next, the control unit 6 controls the moving mechanism 5a to move the inspection probe 3 slightly away (upward) from the measurement point TP1, and in this state, outputs an AC voltage as the inspection signal, so that the measurement point TP1. The stray capacitance (corresponding to the first capacitance between the counter electrodes in the present invention) CS1 is measured and stored in the RAM 7 (step 32: first capacitance measurement process). Thereby, the stray capacitance due to the inspection probe 3 and the probe fixture 3a at that position is measured.

【0020】次に、制御部46は、移動機構5aを制御
して検査用プローブ3を測定ポイントTP1 に再度接触
させ、検査信号としての交流電圧を出力することによ
り、測定ポイントTP1 での導体パターンCP1 と電極
2bとの間の対電極間静電容量(本発明における第2の
対電極間静電容量に相当する)CPR1 をステップ31で
設定した測定レンジを使用して測定する(ステップ3
3:第2の容量測定処理)。次いで、制御部46は、対
電極間静電容量CPR1 から浮遊容量CS1を差し引き、こ
の差分(CPR1 −CS1)を浮遊容量の影響を排除した導
体パターンCP1 についての正規な対電極間静電容量C
CP1 としてRAM7に記憶(保存)させる(ステップ3
4:測定結果保存処理)。この後、制御部46は、すべ
ての導体パターンCPについての対電極間静電容量CCP
1 ,CCP2 ・・(以下、区別しないときには、「対電極
間静電容量CCP」ともいう)を測定したか否かを判別し
(ステップ35)、他の導体パターンCPに対しても上
記各ステップ30〜34を実施して、各対電極間静電容
量CCPを順次測定してRAM7に記憶させる。この場
合、ステップ30の断線検査において、断線箇所が導体
パターンCPに存在すると判別したときには、制御部6
は、断線箇所情報をRAM7に記憶し、この導体パター
ンCPに対するステップ31〜34の処理を行わずに、
ステップ35に移行する。なお、ステップ30の断線検
査において断線箇所が存在すると判別した導体パターン
CPが1つでも存在するときには、その回路基板Pに対
するすべての測定処理を終了して他の回路基板Pに対し
てこの静電容量測定処理を実行してもよい。
Next, the control section 46 controls the moving mechanism 5a to bring the inspection probe 3 into contact with the measurement point TP1 again, and outputs an AC voltage as an inspection signal, thereby the conductor pattern at the measurement point TP1. The capacitance between counter electrodes between CP1 and the electrode 2b (corresponding to the second capacitance between counter electrodes in the present invention) CPR1 is measured using the measurement range set in step 31 (step 3).
3: Second capacity measurement process). Next, the control unit 46 subtracts the stray capacitance CS1 from the inter-electrode electrostatic capacitance CPR1 and subtracts the difference (CPR1-CS1) from the regular inter-electrode electrostatic capacitance C for the conductor pattern CP1 in which the influence of the stray capacitance is eliminated.
It is stored (saved) in RAM 7 as CP1 (step 3)
4: measurement result storage process). After that, the control unit 46 controls the inter-counterelectrode capacitance CCP for all the conductor patterns CP.
1, CCP2 ··· (hereinafter, when no distinction is made, also referred to as “counter electrode capacitance CCP”) is determined (step 35), and the above steps are performed for other conductor patterns CP as well. 30 to 34 are carried out to sequentially measure the electrostatic capacitance CCp between the counter electrodes and store it in the RAM 7. In this case, in the disconnection inspection in step 30, when it is determined that the disconnection point exists in the conductor pattern CP, the control unit 6
Stores the disconnection location information in the RAM 7 and does not perform steps 31 to 34 for this conductor pattern CP,
Go to step 35. When there is at least one conductor pattern CP that is determined to have a disconnection point in the disconnection inspection of step 30, all the measurement processing for that circuit board P is completed and this electrostatic discharge is performed on another circuit board P. The capacity measurement process may be executed.

【0021】次に、制御部6は、ステップ35において
すべての導体パターンCPの対電極間静電容量CCPを測
定したと判別したときには、RAM7に記憶させた各対
電極間静電容量CCPに基づき、対電極間静電容量CCP同
士が互いに近似する導体パターンCP,CP・・の群の
有無を検出する(ステップ36:検出処理)。この処理
において、対電極間静電容量CCP同士が互いに近似する
導体パターンCPの群が検出されたときには、その導体
パターンCP,CP間(または3以上の導体パターンC
P,CP,CP間)に、例えば、図3に示すような短絡
箇所Aが存在する可能性がある。このため、制御部6
は、検出された群に属する導体パターンCP,CP同士
の短絡を検査する(ステップ37:短絡検査処理)。具
体的には、移動機構5a,5bを制御して検査用プロー
ブ3,4を対電極間静電容量CCPが互いに近似する導体
パターンCP,CPに接触させ、両導体パターン間の抵
抗値を測定することにより、短絡箇所の有無を判別する
と共に、短絡箇所が存在するときにはその箇所を特定
し、その短絡箇所情報をRAM7に記憶させる。一方、
ステップ36において、対電極間静電容量CCPが互いに
近似する導体パターンCPの群が検出されないときに
は、この静電容量測定処理を終了する。以上の処理を実
行することにより、回路基板Pについての正常な導体パ
ターンCPについての対電極間静電容量CCPの測定が完
了すると共に、この回路基板に対する断線箇所や短絡箇
所の有無に関する回路基板検査が完了する。
Next, when the control section 6 determines in step 35 that the inter-electrode capacitances CCP of all the conductor patterns CP have been measured, the control section 6 is based on the inter-electrode capacitances CCP stored in the RAM 7. , The presence / absence of a group of conductor patterns CP, CP, ... whose electrostatic capacitances CCP between counter electrodes are similar to each other is detected (step 36: detection processing). In this process, when a group of conductor patterns CP in which the capacitances CCp between the counter electrodes are close to each other is detected, between the conductor patterns CP, CP (or three or more conductor patterns C).
For example, there is a possibility that a short circuit portion A as shown in FIG. 3 exists between (P, CP, CP). Therefore, the control unit 6
Inspects a short circuit between the conductor patterns CP belonging to the detected group, CP (step 37: short circuit inspection process). Specifically, by controlling the moving mechanisms 5a and 5b, the inspection probes 3 and 4 are brought into contact with the conductor patterns CP and CP having electrostatic capacitances CCP close to each other, and the resistance value between the conductor patterns is measured. By doing so, the presence or absence of the short-circuited portion is determined, and when the short-circuited portion exists, the portion is specified and the short-circuited portion information is stored in the RAM 7. on the other hand,
In step 36, when the group of the conductor patterns CP whose capacitances CCP between the counter electrodes are similar to each other is not detected, this capacitance measurement process is ended. By performing the above processing, the measurement of the inter-electrode capacitance CCP of the normal conductor pattern CP of the circuit board P is completed, and the circuit board inspection regarding the presence or absence of the disconnection point or the short circuit point on the circuit board is completed. Is completed.

【0022】次に、同種の回路基板Pを検査する際に
は、まず、検査対象の回路基板Pを導体パターンCP1
,CP2 の形成面を上向きにして電極部2の上に載置
する。次いで、制御部6が、図1に示す静電容量測定処
理のうちの対電極間静電容量CPRの測定処理(ステップ
33)と、このステップ33によって測定された対電極
間静電容量CPRおよび上記した静電容量測定処理によっ
て予め測定されている導体パターンCP毎の浮遊容量C
S に基づく対電極間静電容量CCPの算出処理(ステップ
34)とを各導体パターンCP毎に繰り返し実行する。
この場合、対電極間静電容量CPRの測定処理(ステップ
33)では、静電容量測定処理において使用した測定レ
ンジと同じ測定レンジで対電極間静電容量CPRを測定す
る。また、回路基板P上のすべての導体パターンCPの
各々に対して、上記した静電容量測定処理のステップ3
3で測定した測定ポイントTPと同じ測定ポイントTP
についての対電極間静電容量CCPを測定してRAM7に
保存する。次に、制御部6は、既にRAM7に記憶され
ている対電極間静電容量CCPを基準データとして、検査
対象の回路基板Pについて保存した対電極間静電容量C
CPが、対応する基準データに対して所定範囲内(例え
ば、±10%以内)のときに、その導体パターンCPに
断線および短絡が存在しないと判別する(判別処理)。
この判別処理をすべての導体パターンCPに対して行う
ことにより、検査対象の回路基板Pについての回路基板
検査処理が完了する。
Next, when inspecting the same type of circuit board P, the circuit board P to be inspected is first subjected to the conductor pattern CP1.
, CP2 is placed on the electrode portion 2 with the formation surface facing upward. Next, the control unit 6 measures the inter-electrode capacitance CPR in the capacitance measurement process shown in FIG. 1 (step 33), and measures the inter-electrode capacitance CPR measured in this step 33. Stray capacitance C for each conductor pattern CP that has been measured in advance by the above-described capacitance measurement process.
The calculation process of the inter-electrode capacitance CCP based on S (step 34) is repeatedly executed for each conductor pattern CP.
In this case, in the measurement process of the capacitance CPR between the counter electrodes (step 33), the capacitance CPR between the counter electrodes is measured in the same measurement range as that used in the capacitance measurement process. Further, for each of all the conductor patterns CP on the circuit board P, step 3 of the above-described capacitance measurement process.
The same measurement point TP as the measurement point TP measured in 3
The inter-electrode electrostatic capacitance CCP of is measured and stored in the RAM 7. Next, the control section 6 uses the inter-electrode capacitance CCCP already stored in the RAM 7 as reference data and stores the inter-electrode capacitance C stored for the circuit board P to be inspected.
When CP is within a predetermined range (for example, within ± 10%) with respect to the corresponding reference data, it is determined that the conductor pattern CP has no disconnection or short circuit (determination process).
By performing this determination process for all the conductor patterns CP, the circuit board inspection process for the circuit board P to be inspected is completed.

【0023】このように、この静電容量測定方法によれ
ば、1つの導体パターンCPに対して、対電極間静電容
量CCPを測定するために適した測定レンジを選択するた
めの対電極間静電容量CTCの測定、浮遊容量CS の測
定、対電極間静電容量CTPの再測定、および対電極間静
電容量CCPの算出処理をそれぞれ1回ずつ行うだけで対
電極間静電容量CCPを測定することができる。したがっ
て、各測定ポイントTPのすべてに対して、上記の各処
理をそれぞれ1回ずつ行う必要がある従来の静電容量測
定方法と比較して、極めて短時間ですべての対電極間静
電容量CCPを測定することができる。具体的には、比較
的短時間で終了する断線検査処理(ステップ30)に要
する時間を無視し、1つの導体パターンCPに平均4つ
の測定ポイントTPが存在するとした場合、対電極間静
電容量CCPについての測定時間を1/4に短縮すること
ができる。また、各導体パターンCPに対して、対電極
間静電容量CCPの測定に先立って断線検査処理(ステッ
プ30)を行うことにより、断線箇所が存在する導体パ
ターンCPについての対電極間静電容量CCPの無駄な測
定を回避することができる。このため、その分、測定効
率を向上させることができる。さらに、対電極間静電容
量CCPを短時間で測定できる結果、回路基板Pに対する
基板検査を短時間で行うことができ、これにより、回路
基板Pについての検査コストを低減することができる。
As described above, according to this capacitance measuring method, between the counter electrodes for selecting a measurement range suitable for measuring the capacitance between counter electrodes CCP for one conductor pattern CP. Capacitance between counter electrodes CCP can be measured only once by measuring capacitance CTC, measurement of stray capacitance CS, remeasurement of capacitance between counter electrodes CTP, and calculation of capacitance between counter electrodes CCP. Can be measured. Therefore, as compared with the conventional capacitance measuring method that requires performing each of the above processes once for each of the measurement points TP, all the capacitances between the counter electrodes CCP are extremely short. Can be measured. Specifically, ignoring the time required for the disconnection inspection process (step 30) that is completed in a relatively short time, and assuming that there are an average of four measurement points TP in one conductor pattern CP, the capacitance between the counter electrodes is The measurement time for CCP can be shortened to 1/4. Further, by performing a disconnection inspection process (step 30) on each conductor pattern CP prior to the measurement of the inter-electrode electrostatic capacitance CCP, the inter-electrode electrostatic capacitance for the conductor pattern CP in which the disconnection point exists. Useless measurement of CCP can be avoided. Therefore, the measurement efficiency can be improved accordingly. Furthermore, as a result of being able to measure the capacitance CCP between the counter electrodes in a short time, the circuit board P can be inspected in a short time, and thus the inspection cost for the circuit board P can be reduced.

【0024】なお、本発明は、上記した本発明の実施の
形態に示した構成に限定されない。例えば、本発明の実
施の形態では、本発明における静電容量測定方法を回路
基板検査装置の検査処理に適用した例について説明した
が、単に静電容量の測定を行う静電容量測定装置に適用
することもできる。また、本発明の実施の形態では、基
準電極として電極部2の電極2bを用いた静電容量測定
の例について説明したが、例えば、検査対象の回路基板
Pにおいて広い面積を有するグランドパターンや電源パ
ターンなどを基準電極として用いることもできる。さら
に、すべての導体パターンCPに対する断線検査処理
(ステップ30)を対電極間静電容量CCPの測定(ステ
ップ31〜34)に先立って一括的に行うこともでき
る。また、本発明の実施の形態では、対電極間静電容量
CCPの測定精度を上げるべく測定に適した測定レンジを
選択設定する例について説明したが、これに限定されな
い。つまり、測定に適した測定レンジを選定設定するた
めの対電極間静電容量CTCの仮測定処理を省いて、上記
した測定ポイントTP上での測定処理(ステップ32:
第1の容量測定処理)によって測定した浮遊容量(本発
明における第1の対電極間静電容量)CS と、その導体
パターンCPおよび電極2bの間の対電極間静電容量測
定処理(ステップ33:第2の容量測定処理)によって
測定された対電極間静電容量(本発明における第2の対
電極間静電容量)CPRとに基づいて対電極間静電容量C
CPを測定することができるのは勿論である。
The present invention is not limited to the configuration shown in the above-mentioned embodiment of the present invention. For example, in the embodiment of the present invention, the example in which the capacitance measuring method according to the present invention is applied to the inspection process of the circuit board inspecting device has been described, but it is applied to the capacitance measuring device that simply measures the capacitance. You can also do it. Further, in the embodiment of the present invention, an example of capacitance measurement using the electrode 2b of the electrode portion 2 as the reference electrode has been described. However, for example, a ground pattern or a power source having a large area in the circuit board P to be inspected. A pattern or the like can also be used as the reference electrode. Furthermore, the disconnection inspection process (step 30) for all the conductor patterns CP can be collectively performed prior to the measurement of the capacitance CCP between the counter electrodes (steps 31 to 34). Further, in the embodiment of the present invention, an example in which a measurement range suitable for measurement is selectively set in order to improve the measurement accuracy of the capacitance between counter electrodes CCP has been described, but the present invention is not limited to this. That is, the provisional measurement process of the capacitance CTC between the counter electrodes for selecting and setting the measurement range suitable for the measurement is omitted, and the measurement process on the measurement point TP described above (step 32:
The stray capacitance (first inter-electrode capacitance in the present invention) CS measured by the first capacitance measurement process and the inter-electrode capacitance measurement process between the conductor pattern CP and the electrode 2b thereof (step 33) : The counter electrode capacitance C based on the counter electrode capacitance (second counter electrode capacitance in the present invention) CPR measured by the second capacitance measurement process).
Of course, CP can be measured.

【0025】[0025]

【発明の効果】以上のように、請求項1記載の静電容量
測定方法によれば、各導体パターン上の測定ポイントで
の静電容量測定に先立って、導体パターンに対する断線
検査を行うことにより、1つの導体パターンに対して、
例えば、対電極間静電容量を測定するために適した測定
レンジを選択するための対電極間静電容量の測定処理、
第1の測定処理、第2の測定処理および測定結果保存処
理をそれぞれ1回ずつ行うだけで対電極間静電容量を測
定することができる。したがって、各測定ポイントのす
べてに対して、上記の各処理をそれぞれ1回ずつ行う必
要がある従来の静電容量測定方法と比較して、極めて短
時間ですべての対電極間静電容量を測定することができ
る。また、各導体パターンに対して、対電極間静電容量
の測定に先立って断線検査処理を行うことにより、断線
箇所が存在する導体パターンについての対電極間静電容
量の無駄な測定を回避することができるため、その分、
測定効率を向上させることができる。
As described above, according to the capacitance measuring method of the first aspect, the disconnection inspection of the conductor pattern is performed prior to the capacitance measurement at the measurement point on each conductor pattern. For one conductor pattern,
For example, the measurement process of the capacitance between the counter electrodes for selecting a measurement range suitable for measuring the capacitance between the counter electrodes,
The capacitance between the counter electrodes can be measured by performing the first measurement process, the second measurement process, and the measurement result storage process only once each. Therefore, compared to the conventional capacitance measurement method, which requires performing each of the above processes once for each measurement point, all capacitances between counter electrodes can be measured in an extremely short time. can do. Further, by performing a disconnection inspection process on each conductor pattern prior to measuring the capacitance between the counter electrodes, it is possible to avoid wasteful measurement of the capacitance between the counter electrodes for the conductor pattern having the disconnection point. Because you can,
The measurement efficiency can be improved.

【0026】また、請求項2記載の回路基板検査方法お
よび請求項3記載の回路基板検査装置によれば、対電極
間静電容量を短時間で測定できる結果、回路基板に対す
る基板検査を短時間で行うことができ、これにより、回
路基板についての検査コストを十分に低減することがで
きる。
According to the circuit board inspection method of the second aspect and the circuit board inspection apparatus of the third aspect, the capacitance between the counter electrodes can be measured in a short time, and as a result, the circuit board inspection for the circuit board can be performed in a short time. Therefore, the inspection cost for the circuit board can be sufficiently reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態に係る回路基板検査装置1
による静電容量測定処理を示すフローチャートである。
FIG. 1 is a circuit board inspection apparatus 1 according to an embodiment of the present invention.
5 is a flowchart showing a capacitance measurement process by the.

【図2】回路基板検査装置1および従来の回路基板検査
装置41の構成を示す構成図である。
FIG. 2 is a configuration diagram showing configurations of a circuit board inspection device 1 and a conventional circuit board inspection device 41.

【図3】検査対象の一例である回路基板Pの上面図であ
る。
FIG. 3 is a top view of a circuit board P which is an example of an inspection target.

【図4】従来の回路基板検査装置41による静電容量測
定処理を示すフローチャートである。
FIG. 4 is a flowchart showing a capacitance measurement process by a conventional circuit board inspection device 41.

【符号の説明】[Explanation of symbols]

1 回路基板検査装置 2 電極部 3,4 検査用プローブ 5a,5b 移動機構 6 制御部 7 RAM CP1 ,CP2 導体パターン P 回路基板 TP1 〜TP6 測定ポイント 1 Circuit board inspection device 2 electrodes 3,4 Inspection probe 5a, 5b moving mechanism 6 control unit 7 RAM CP1, CP2 conductor pattern P circuit board TP1 to TP6 measurement points

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 測定対象の回路基板における複数の導体
パターンに接触型のプローブを順次接触させて当該各導
体パターンと基準電極との間の対電極間静電容量を測定
する静電容量測定方法であって、 前記各導体パターンの断線を検査する断線検査処理を実
行した後に、 前記断線検査処理において断線が検出されなかった前記
各導体パターン毎に、当該導体パターンに対して前記プ
ローブを離間した状態で配置させて当該プローブと前記
基準電極との間の第1の対電極間静電容量を測定する第
1の容量測定処理と、前記プローブを離間した状態から
前記導体パターン上の1つの測定ポイントに接触させて
当該導体パターンと前記基準電極との間の第2の対電極
間静電容量を測定する第2の容量測定処理と、前記測定
した第2の対電極間静電容量と前記第1の対電極間静電
容量との差分容量を当該導体パターンに対応する前記対
電極間静電容量として保存する測定結果保存処理とを実
行し、 前記保存した対電極間静電容量同士が近接する前記導体
パターンの群を検出する検出処理と、当該検出された群
に属する前記導体パターン同士間の短絡を検査する短絡
検査処理とを実行し、 前記短絡検査処理によって短絡が検出された前記導体パ
ターンについての前記対電極間静電容量を除いて前記保
存した対電極間静電容量を正規な前記対電極間静電容量
とすることを特徴とする静電容量測定方法。
1. A capacitance measuring method in which a contact-type probe is sequentially brought into contact with a plurality of conductor patterns on a circuit board to be measured to measure an inter-electrode capacitance between each conductor pattern and a reference electrode. That is, after performing the disconnection inspection process for inspecting the disconnection of each of the conductor patterns, for each of the conductor patterns in which no disconnection was detected in the disconnection inspection process, the probe was separated from the conductor pattern. A first capacitance measuring process for arranging the probe in a state and measuring a first inter-electrode capacitance between the probe and the reference electrode; and one measurement on the conductor pattern from a state where the probe is separated. A second capacitance measurement process of contacting a point to measure a second inter-electrode capacitance between the conductor pattern and the reference electrode; and the measured second inter-electrode capacitance. And a measurement result storage process of storing a difference capacitance between the first and second counter-electrode capacitances as the counter-electrode capacitance corresponding to the conductor pattern, and storing the stored counter-electrode capacitances. A detection process of detecting a group of the conductor patterns that are close to each other and a short circuit inspection process of inspecting a short circuit between the conductor patterns belonging to the detected group are executed, and a short circuit is detected by the short circuit inspection process. The electrostatic capacitance measuring method, wherein the stored inter-electrode capacitance excluding the inter-electrode capacitance of the conductor pattern is set as the normal inter-electrode capacitance.
【請求項2】 検査対象の回路基板における各導体パタ
ーン毎に、当該導体パターンに対して接触型のプローブ
を離間した状態で配置させて当該プローブと前記基準電
極との間の第1の対電極間静電容量を測定する第1の容
量測定処理と、前記プローブを離間した状態から前記導
体パターン上の1つの測定ポイントに接触させて当該導
体パターンと前記基準電極との間の第2の対電極間静電
容量を測定する第2の容量測定処理と、前記測定した第
2の対電極間静電容量と前記第1の対電極間静電容量と
の差分容量を当該導体パターンに対応する前記対電極間
静電容量として保存する測定結果保存処理とを実行し、 請求項1記載の静電容量測定方法によって測定された前
記各正規な対電極間静電容量を基準データとして、前記
検査対象の回路基板についての前記保存した対電極間静
電容量が、対応する前記基準データに対して所定範囲内
のときに当該導体パターンに断線および短絡が生じてい
ないと判別することを特徴とする回路基板検査方法。
2. A first counter electrode between the probe and the reference electrode, wherein a contact-type probe is arranged in a state of being separated from the conductor pattern for each conductor pattern on a circuit board to be inspected. A first capacitance measuring process for measuring the electrostatic capacitance between the conductor pattern and the second pair between the conductor pattern and the reference electrode by bringing the probe into contact with one measurement point on the conductor pattern from a separated state. A second capacitance measuring process for measuring an inter-electrode capacitance and a differential capacitance between the measured second inter-electrode capacitance and the first inter-electrode capacitance correspond to the conductor pattern. The measurement result storage process of storing the capacitance between the counter electrodes is executed, and the inspection is performed by using the respective regular capacitance between the counter electrodes measured by the capacitance measuring method according to claim 1 as reference data. Target circuit board The circuit board inspection method is characterized in that when the stored capacitance between the counter electrodes is within a predetermined range with respect to the corresponding reference data, the conductor pattern is not broken or short-circuited. .
【請求項3】 接触型のプローブと、測定対象の回路基
板における複数の導体パターンの各々に前記プローブを
接触させた状態で当該各導体パターンと基準電極との間
の対電極間静電容量を測定すると共に当該測定した対電
極間静電容量に基づいて検査対象の回路基板を検査する
制御部とを備えた回路基板検査装置であって、 前記制御部は、前記各導体パターンの断線を検査する断
線検査処理を実行した後に、 前記断線検査処理において断線が検出されなかった前記
各導体パターン毎に、当該導体パターンに対して前記プ
ローブを離間した状態で配置させて当該プローブと前記
基準電極との間の第1の対電極間静電容量を測定する第
1の容量測定処理と、前記プローブを離間した状態から
前記導体パターン上の1つの測定ポイントに接触させて
当該導体パターンと前記基準電極との間の第2の対電極
間静電容量を測定する第2の容量測定処理と、前記測定
した第2の対電極間静電容量と前記第1の対電極間静電
容量との差分容量を当該導体パターンに対応する前記対
電極間静電容量として保存する測定結果保存処理とを実
行し、 かつ、前記保存した対電極間静電容量同士が近接する前
記導体パターンの群を検出する検出処理と、当該検出さ
れた群に属する前記導体パターン同士間の短絡を検査す
る短絡検査処理とを実行し、当該短絡検査処理によって
短絡が検出された前記導体パターンについての前記対電
極間静電容量を除いて前記保存した対電極間静電容量を
正規な前記対電極間静電容量とすることを特徴とする回
路基板検査装置。
3. A contact-type probe and a counter electrode capacitance between each conductor pattern and a reference electrode in a state where the probe is in contact with each of a plurality of conductor patterns on a circuit board to be measured. A circuit board inspecting device comprising: a control unit that inspects a circuit board to be inspected based on the measured capacitance between the counter electrodes, and the control unit inspects a break in each of the conductor patterns. After performing the disconnection inspection process, for each of the conductor patterns for which no disconnection was detected in the disconnection inspection process, the probe and the reference electrode are arranged in a state of being separated from the conductor pattern. And a first capacitance measuring process for measuring the capacitance between the first counter electrodes between the two electrodes, and bringing the probe into contact with one measurement point on the conductor pattern from a separated state. Second capacitance measurement processing for measuring a second inter-electrode capacitance between the conductor pattern and the reference electrode, the measured second inter-electrode capacitance and the first counter electrode A measurement result storing process of storing a difference capacitance between the inter-electrode capacitance as the inter-electrode capacitance corresponding to the conductor pattern, and the stored inter-electrode capacitance is close to each other. A detection process for detecting a group of conductor patterns and a short circuit inspection process for inspecting a short circuit between the conductor patterns belonging to the detected group are executed, and the short circuit is detected by the short circuit inspection process. The circuit board inspecting device, wherein the stored inter-electrode capacitance excluding the inter-electrode capacitance is set as the normal inter-electrode capacitance.
JP2001195945A 2001-06-28 2001-06-28 Capacitance measurement method, circuit board inspection method, and circuit board inspection apparatus Expired - Fee Related JP4663918B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005037170A (en) * 2003-07-17 2005-02-10 Hioki Ee Corp Circuit board inspection apparatus
US7605553B2 (en) 2005-11-11 2009-10-20 Kia Motor Corporation System for safely opening/closing power window of vehicle
KR101256235B1 (en) 2004-07-05 2013-04-17 오를리콘 트레이딩 아크티엔게젤샤프트, 트뤼프바흐 Night vision system for vehicle
KR20230002489A (en) 2020-04-28 2023-01-05 니혼덴산리드가부시키가이샤 Inspection device and inspection method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168375A (en) * 1983-03-07 1984-09-22 インテグリ―テスト コーポレイション Method and device for testing electric connection network
JPS59187274A (en) * 1983-04-07 1984-10-24 Toshiba Corp Master data setter for conduction tester in insulation of circuit board
JPH01143974A (en) * 1987-11-30 1989-06-06 Toshiba Corp In-circuit tester
JPH04503105A (en) * 1988-10-17 1992-06-04 バス、サイエンティフィック、リミテッド Electrical circuit testing
JPH04323572A (en) * 1991-04-23 1992-11-12 Nec Corp Method for inspecting circuit pattern
JPH0974122A (en) * 1995-09-04 1997-03-18 Sumitomo Metal Ind Ltd Capacitance measuring pattern and its measuring method for semiconductor device
JP2000214206A (en) * 1999-01-21 2000-08-04 Hioki Ee Corp Circuit substrate inspecting method and circuit substrate inspecting apparatus

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168375A (en) * 1983-03-07 1984-09-22 インテグリ―テスト コーポレイション Method and device for testing electric connection network
JPS59187274A (en) * 1983-04-07 1984-10-24 Toshiba Corp Master data setter for conduction tester in insulation of circuit board
JPH01143974A (en) * 1987-11-30 1989-06-06 Toshiba Corp In-circuit tester
JPH04503105A (en) * 1988-10-17 1992-06-04 バス、サイエンティフィック、リミテッド Electrical circuit testing
JPH04323572A (en) * 1991-04-23 1992-11-12 Nec Corp Method for inspecting circuit pattern
JPH0974122A (en) * 1995-09-04 1997-03-18 Sumitomo Metal Ind Ltd Capacitance measuring pattern and its measuring method for semiconductor device
JP2000214206A (en) * 1999-01-21 2000-08-04 Hioki Ee Corp Circuit substrate inspecting method and circuit substrate inspecting apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005037170A (en) * 2003-07-17 2005-02-10 Hioki Ee Corp Circuit board inspection apparatus
KR101256235B1 (en) 2004-07-05 2013-04-17 오를리콘 트레이딩 아크티엔게젤샤프트, 트뤼프바흐 Night vision system for vehicle
US7605553B2 (en) 2005-11-11 2009-10-20 Kia Motor Corporation System for safely opening/closing power window of vehicle
KR20230002489A (en) 2020-04-28 2023-01-05 니혼덴산리드가부시키가이샤 Inspection device and inspection method

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