JP2003009585A - Detector for revolution of direct-current motor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a detector for the revolution of a direct-current motor, which is simply constituted and is capable of appropriately detecting the state of revolution without influence of change in the revolution of the direct-current motor. SOLUTION: A ripple current outputted from the direct-current motor M is outputted through a variable cut-off frequency filter means (switched capacitor filter), and further the cut-off frequency of the filter means is adjusted according to the ripple pulse outputted through the filter means and the state of driving of the direct-current motor. (A) The maximum ripple frequency of the ripple current outputted from the direct-current motor is computed based on the state of driving of the direct-current motor. Further, (B) the ripple pulse outputted through the filter means is subjected to frequency conversion to compute the actual ripple frequency, and (C) the cut-off frequency is adjusted according to the difference between the maximum ripple frequency and the actual ripple frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotating state detecting device for a DC motor having a brush, and more particularly to a rotating state detecting device for a DC motor suitable for detecting the number of rotations of a DC motor for driving on-vehicle functional parts.

[0002]

2. Description of the Related Art A direct current motor is used in vehicle-mounted functional parts such as a seat having a memory function and a power window regulator mounted on a vehicle, and the position and operating speed of each device driven by this are properly controlled. In order to control it, it is necessary to accurately detect the rotation state of the DC motor. Therefore, for example, in Japanese Unexamined Patent Publication No. 2000-333485, even if the rotation state of the motor changes, the cutoff frequency changes and pulse generation can be performed.
A motor rotation pulse generation circuit for a DC motor with the following configuration has been proposed, with the objective of enabling stable ripple pulse generation without pulse errors even when the motor is started. ing.

That is, noise is removed based on an input signal from the DC motor and a cutoff frequency is variable by an external signal, and a ripple corresponding to the motor rotation of the DC motor based on the output of the filter means. Motor rotation provided with a pulse shaping means for generating a pulse and a clock generating means for generating a clock signal based on a ripple pulse and a rotation state signal of the DC motor, and applying the clock signal to the filter means to vary the cutoff frequency of the filter means A pulse generation circuit has been proposed.

[0004]

In the circuit described in the above publication, in order to improve the followability at high frequency due to the characteristics of the circuit, the stability at low frequency becomes poor and, conversely, at low frequency. In order to improve the stability at the frequency, the contradictory operation of deteriorating the followability at the high frequency is inevitable (this will be described later in detail with reference to FIG. 12 and the like). For example, when the rotation of the motor changes abruptly at high rotation, the cutoff frequency may be delayed, or at low rotation, the cutoff frequency may become unstable. Therefore, it is necessary to adjust the cutoff frequency at high frequency and low frequency according to the required motor characteristics to find a compromise.

Therefore, the present invention is to provide a DC motor rotation state detecting device having a simple structure and capable of appropriately detecting the rotation state of the DC motor without being affected by changes in the rotation of the DC motor. It is an issue.

[0006]

In order to solve the above-mentioned problems, according to the present invention, as described in claim 1, the ripple current output from the DC motor is output through the cut-off frequency variable filter means. Together with a ripple pulse output through the filter means and a DC motor rotation state detecting device for adjusting the cut-off frequency of the filter means according to the drive state of the DC motor, the DC based on the drive state of the DC motor A maximum ripple frequency calculating means for calculating the maximum ripple frequency of the ripple current output from the motor; an actual ripple frequency calculating means for calculating the actual ripple frequency by frequency converting the ripple pulse output via the filter means; The maximum ripple frequency calculated by the ripple frequency calculation means and the actual ripple frequency calculation means are Depending on the difference between the actual ripple frequency were calculated in which was decided and a cutoff frequency adjusting means for adjusting the cut-off frequency.

As described in claim 2, the cutoff frequency adjusting means sets a predetermined value to a difference between the maximum ripple frequency calculated by the maximum ripple frequency calculating means and the actual ripple frequency calculated by the actual ripple frequency calculating means. The cutoff frequency may be set by multiplication.

Further, the cutoff frequency adjusting means is provided with a feedback amount setting means for setting a feedback amount based on the actual ripple frequency calculated by the actual ripple frequency calculating means, as described in claim 3. The cutoff frequency may be adjusted according to the feedback amount set by the setting unit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a rotation state detection device for a DC motor according to an embodiment. One end (upstream side) of a DC motor M is connected to a power supply (+ B),
The other end (downstream side) is grounded via a shunt resistor and is also connected to the electronic control unit ECU and the switched capacitor filter SCF. The electronic control unit ECU is the arithmetic circuit CL shown in the frame of the dashed line in FIG.
Etc., and the input signal described later has an A / D converter AD
1, AD2 and AD3 are input to the arithmetic circuit CL, the count value of the counter CT is input to the arithmetic circuit CL, and a signal corresponding to the cutoff frequency of the arithmetic result is input to the switched capacitor via the clock output circuit CK.・ Filter S
It is configured to be output to CF.

At the input side of the arithmetic circuit CL, the voltage Vb of the power source (+ B) is divided by a voltage dividing resistor to a predetermined value (v1) and A
The voltage (v2) on the downstream side of the motor M is input to the A / D converter AD2, and the constant voltage Vcc is divided into predetermined values (v4, v5) by two sets of voltage dividing resistors. It is configured to be compressed and input to the A / D converter AD3. The counter CT counts the pulse frequency of a feedback signal of a ripple pulse output described later and supplies it to the arithmetic circuit CL.

In the DC motor M (hereinafter, simply referred to as the motor M), when the commutator (not shown) passes through the brush, the current flowing through the coil (not shown) changes and a ripple current is output. However, this ripple current is used as a signal indicating the rotation state. Therefore, the current flowing through the motor M includes a ripple component, noise is removed through the switched capacitor filter SCF, and the ripple pulse is output after being shaped by the ripple pulse shaping circuit WF. The ripple pulse is output as it is as a signal representing the rotation state of the motor M, particularly the rotation speed, and is fed back to the counter CT.

Switched capacitor filter SCF
Is configured as described in the above-mentioned Japanese Patent Laid-Open No. 2000-333485, and its cutoff frequency fc
Is adjusted according to the frequency (clock input frequency CLK) that intermittently switches two switches (not shown) that form the switched capacitor filter SCF. That is, the cutoff frequency fc is variable, and is expressed as fc = CLK / N (where N is a constant and is 100 in this embodiment).
Therefore, for example, for cutoff frequency fc, CLK = 100fc
If the clock input frequency CLK becomes
00 is the cutoff frequency fc. The ripple pulse shaping circuit WF is also configured as described in the above-mentioned Japanese Patent Application Laid-Open No. 2000-333485, and since it is the same as the circuit shown in FIG.

The switched capacitor filter SCF constitutes the filter means of the present invention, and the maximum ripple frequency calculation means, the actual ripple frequency calculation means and the cutoff frequency adjustment means of the present invention are provided in the electronic control unit ECU. Is configured and is processed according to the flowcharts shown in FIGS. 7 to 11 as will be described later. First, description will be made with reference to the functional block diagram of FIG.

In FIG. 2, the maximum ripple frequency calculation block (A) corresponds to the maximum ripple frequency calculation means, and the rotation state of the motor M (current and voltage information of the motor M here) is indicated in blocks A1 and A2. Based on
The maximum value of the ripple pulse frequency is obtained. As shown in FIG. 3 as an example of the current-frequency characteristic of the motor M, the frequency (ripple frequency) f of the ripple pulse with respect to the current i flowing in the motor M is expressed as -56i + 594, and fluctuates within the range surrounded by the broken line. Therefore, the ripple frequency f
The maximum value y4 of y is calculated as follows.

First, y1 = based on the voltage (v1) corresponding to the power supply voltage input through the A / D converter AD1.
v1 / (5/255) is obtained, and y2 = v2 / (5/255) is obtained based on the voltage (v2) corresponding to the current of the motor M input through the A / D converter AD2.
Further, y12 = v4 / (5/255) and y based on the reference voltage (v4, v5) input through the A / D converter AD3.
13 = v5 / (5/255) is required. Then, based on these, in the block A1, y3 = (y1 / y12)-
(Y2 * y13), y12 = 2.525, y13 = 7.472 are obtained, and further, y3 * (5/255) is converted into the maximum ripple frequency y4 which is the maximum ripple frequency in block A2 based on FIG. It That is, y4 = 500 * y3 * (5/25
Five) . Incidentally, the value of 500 or the like is a value for finally matching the characteristic of the motor M, and a different value is set depending on the specifications of the motor M or the like. Further, 5/255 is a value indicating the resolution of each A / D converter AD1 to AD3 (5V / 8bit).

On the other hand, the actual ripple frequency calculation block (B) corresponds to the actual ripple frequency calculation means, and the block B
1, the counter CT detects the clock frequency fck (for example, 1 MHz) between the edges of each pulse of the ripple pulse.
Is counted by y6 = (1 / f) / (1 / fc
k) is required. Then, in block B2, the count value is frequency-converted based on FIG. 5, and is converted into the actual ripple frequency y7 = 1 / (y6 * (1 / fck)).

The cutoff frequency optimizing block (C) corresponds to cutoff frequency adjusting means, and the feedback amount is calculated in block C1 based on the actual ripple frequency. Block C corresponding to feedback amount setting means
In No. 1, first, the feedback adjustment amount y8 is calculated based on the actual ripple frequency y7 obtained by the actual ripple frequency calculation block and the reference value (y10 / 1.2) for the previous cutoff frequency y10. That is, y8 = (y10 / 1.
2-y7) * x. Here, x is a constant and is set to 0.125, for example. That is, 12.5% of the difference obtained by subtracting the actual ripple frequency y7 from the reference value (y10 / 1.2) of the cutoff frequency is used as the feedback adjustment amount y8 in order to prevent a hypersensitive reaction to the frequency change and perform smooth control. . Then, this feedback adjustment amount y8 is added to the previous feedback amount y9 to obtain a new feedback amount y9.
Is updated as (y9 = y9 + y8).

This feedback amount y9 is calculated in block C.
In 2, the cutoff frequency y10 at this time is calculated according to the difference between the maximum ripple frequency y4 and the feedback amount y9 calculated based on the actual ripple frequency y7. Specifically, the cutoff frequency y10 is set to y10 = 1.2 (y4-y9), and the maximum ripple frequency y4 and the feedback amount y9 are set.
It is set to a value 1.2 times the difference (calculated based on the actual ripple frequency y7). In other words, without directly using the difference between the maximum ripple frequency y4 and the feedback amount y9,
The value is set to 1.2 times, and it is set to properly remove the fluctuating noise. The relationship between the values of these frequencies is shown in FIG.

Then, in the block D1 of the SCF drive clock output block shown in FIG. 2D, the cutoff frequency y10 is multiplied by a constant (N in this embodiment 100) to obtain S.
The CF drive clock is y11 (y11 = y10 * 100), and the SCF drive clock y11 (Hz) of the signal corresponding to the cutoff frequency is used.
Is output as an SCF drive pulse, which adjusts the cutoff frequency of the switched capacitor filter SCF.

Next, in the present embodiment configured as shown in FIGS. 1 and 2, the electronic control unit ECU performs the processing as shown in FIG. 7 to detect the rotation state of the motor M. First, the operating state of the motor M is determined in step 101, and if the motor M is operating, step 102
The processes of to 105 are repeated in a predetermined cycle. That is,
The maximum ripple frequency is calculated in step 102, the ripple pulse is counted in step 103, the cutoff frequency is optimized in step 104, and S is calculated in step 105.
Output processing of the CF drive clock is performed. When it is determined in step 101 that the motor M is stopped, the count value Nc of the counter CT is determined in step 106.
Is cleared and the calculated value y3 is calculated in step 107.
Etc. are cleared.

FIG. 8 shows the calculation process of the maximum ripple frequency performed in the above step 102. First, in step 201, the values y1, y2, y12 and y13 converted by the A / D converters AD1 to AD3 are read.
Then, based on these values, y3 = (y1 / y12)-
The maximum ripple frequency y which is the maximum value of the ripple frequency according to (y2 * y13) and y4 = 500 * y3 * (5/255)
4 is calculated.

FIG. 9 shows the ripple pulse counting process performed in the above-mentioned step 103. First, in step 301, it is judged whether or not the rising edge of the ripple pulse is present. And step 30
After proceeding to step 2 and the count value Nc is stored as y6, the count value Nc is cleared (0) in step 303,
In step 304, the actual ripple frequency y7 is y7 =
It is calculated according to 1 / (y6 * (1 / fck)). On the other hand, when it is determined in step 301 that the rising edge of the ripple pulse is not present, the process proceeds to step 305, where the count value Nc is incremented (Nc + 1), and the routine shown in FIG.
Return to the main routine of.

FIG. 10 shows the optimization processing of the cutoff frequency performed in step 104 of FIG. 7. First, in step 401, the feedback adjustment amount y8 is y8 = (y
It is calculated as 10 / 1.2-y7) * 0.125. Next, in step 402, the feedback amount y of the previous time
It is added to 9 and updated as a new feedback amount y9 (y9 = y9 + y8). Then, step 40
3, the cutoff frequency y10 is y10 = 1.2 (y4-y
9) is calculated. That is, the maximum ripple frequency y
It is set to 1.2 times the difference between 4 and the feedback amount y9.

FIG. 11 shows the output process of the SCF drive clock performed in step 105 of FIG. 7. In step 501, the cutoff frequency y10 is multiplied by a constant 100 to obtain the SCF drive clock y11 (y11 = y10 *). Ten
0), at step 502, this SCF drive clock y11
(Hz) is output.

FIG. 12 shows a PLL circuit used in a conventional apparatus in comparison with the present embodiment having the above-described configuration, which is an analog circuit using an IC of a phase locked loop (Phase Locked Loop). It is composed. This PLL is composed of a phase comparator (not shown), an LPF (low-pass filter, not shown), and a VCO (voltage-controlled oscillator, not shown), as described in Japanese Patent Laid-Open No. 2000-333485. This is a feedback loop, which compares the phase of the ripple pulse output of the motor M with the phase of the VCO signal, converts the difference signal generated when there is a difference between them into a DC voltage via the LPF, adds it to the VCO, and adds the VCO signal. Is to be phase-synchronized with the ripple pulse output, and the PLL circuit in FIG. 12 includes an IC having this PLL function.

In FIG. 12, the ripple frequency maximum value calculation circuit (AC) is divided by a one-dot chain line so as to be compared with the functional block diagram of the present embodiment shown in FIG.
It consists of a phase comparison circuit (BC), a cutoff frequency optimization circuit (CC) and an SCF drive clock oscillation circuit (DC), and the signals at points a to d in FIG. 12 are shown in the time chart of FIG. The signal at the point a in the PLL circuit of FIG. 12 is the output of the above-mentioned phase comparator, and becomes the output of H level and L level centering on the high impedance Himp as shown in FIG. The signal at point b in FIG. 12 is the output of the LPF and is shown in FIG. 13 at (b), and the signal at point c is the maximum of the ripple pulse frequency set according to the change in the current of the motor M and the terminal voltage of the motor M. The signal corresponding to the value is shown in FIG. 13C, and the signal obtained by subtracting the signal at point b from the signal at point c is output as the signal at point d, which has the characteristic shown in FIG.

The ripple pulse output of the motor M is formed as shown in the second stage from the bottom of FIG. 13, and the value of 1 / 1.2 of the cutoff frequency value (value divided by 100) is shown in FIG. It will be as shown at the bottom. These two pulse signals are phase-compared at the rising edge to output the LPF (b).
Is output as a feedback signal. In FIG. 13, the motor M is started at t0 and the phase is reversed at t8.

Next, FIG. 14 shows the states of signals corresponding to the respective signals of FIG. 13 when the frequency of the ripple pulse output of the motor M is high, for example, 500 Hz in the PLL circuit of FIG. If the cutoff frequency / 1.2 value is 510 Hz (the frequency difference is 10 Hz),
Since the phase difference is small (for example, between ta time and tb time in FIG. 13), the feedback amount (LPF signal) once is extremely small as shown in FIG. 14 (b). On the other hand,
As shown in FIG. 5, when the frequency of the ripple pulse output of the motor M is low, for example, 100 Hz, and the cutoff frequency / 1.2 value is 110 Hz (the frequency difference is 10 Hz), the phase difference is Since it is large (for example, between time tc and time td in FIG. 15), the amount of feedback (LPF signal) once is large as shown in FIG.

That is, as is clear by comparing the characteristic of FIG. 14 in which the frequency of the ripple pulse output is high with the characteristic of FIG. 15 in which the frequency of the ripple pulse is low, the frequency difference is the same (10 Hz). Therefore, the cutoff frequency of the switched-capacitor filter SCF greatly fluctuates as compared with the former case. In order to prevent this, for example, if the value of the H level is reduced, the feedback at high frequency cannot follow. As described above, it is extremely difficult to deal with the trade-off in response to the change in the frequency of the ripple pulse output, and it is necessary to individually deal with the required motor characteristics.

On the other hand, according to the present embodiment shown in FIGS. 1 to 11, the maximum ripple frequency y of the motor M is increased.
According to the frequency difference between 4 and the feedback amount y9 calculated based on the actual ripple frequency y7, y10 = 1.2 (y
4-y9) as a switched capacitor filter S
Since the cutoff frequency of CF is calculated, it is possible to drive the switched capacitor filter SCF by appropriately following the change of the frequency of the ripple pulse output, and secure an appropriate ripple pulse output. can do. That is, the cutoff frequency can be adjusted according to the difference between the maximum ripple frequency and the actual ripple frequency, and the rotation state of the DC motor can be appropriately detected without being affected by the change in the rotation of the DC motor.

In the present embodiment shown in FIGS. 1 to 11, the cutoff frequency is calculated according to the frequency difference between the maximum ripple frequency of the motor M and the feedback amount. Alternatively, the cutoff frequency may be calculated in accordance with the difference in the cycle. Compared to the case where the frequency difference is used, the accuracy is slightly reduced when the reciprocal cycle is used, Included in one aspect of the invention.

[0032]

Since the present invention is constructed as described above, it has the following effects. That is, in the DC motor rotation state detecting device according to the first aspect, the cutoff frequency is adjusted by the cutoff frequency adjusting means according to the difference between the maximum ripple frequency and the actual ripple frequency. The rotation state can be appropriately detected without being affected by the change in the rotation of the motor.

If the cutoff frequency adjusting means is configured to set the cutoff frequency by multiplying the difference between the maximum ripple frequency and the actual ripple frequency by a predetermined value as described in claim 2, the fluctuating noise is appropriately adjusted. Therefore, the rotation state of the DC motor can be properly detected.

If the cut-off frequency adjusting means is configured to adjust the cut-off frequency according to the feedback amount set based on the actual ripple frequency, the rotation speed of the DC motor can be improved. The rotation state of the DC motor can be detected smoothly and appropriately without sensitively reacting to changes.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a rotation state detection device for a DC motor according to an embodiment of the present invention.

FIG. 2 is a functional block diagram according to an embodiment of the present invention.

FIG. 3 is a graph showing an example of current-frequency characteristics of the DC motor according to the embodiment of the present invention.

FIG. 4 is a graph showing an example of characteristics when converting an output of a DC motor into a frequency in an embodiment of the present invention.

FIG. 5 is a graph showing an example of characteristics when a count value by a counter is converted into a frequency according to the embodiment of the present invention.

FIG. 6 is a graph showing the relationship between the maximum ripple frequency, the actual ripple frequency, and the feedback amount in the embodiment of the present invention.

FIG. 7 is a flowchart showing a process of detecting a rotation state of a DC motor according to the embodiment of the present invention.

8 is a flowchart showing a calculation process of a maximum ripple frequency in FIG.

9 is a flowchart showing a ripple pulse counting process in FIG. 7. FIG.

10 is a flowchart showing a cutoff frequency optimization process in FIG. 7. FIG.

11 is a flowchart showing an output process of the SCF drive clock in FIG.

FIG. 12 is a circuit diagram showing a PLL circuit used in a conventional device.

13 is a timing chart showing the state of each signal at points a to d in FIG.

14 is a timing chart showing the states of signals corresponding to the respective signals of FIG. 13 when the frequency of the ripple pulse output in FIG. 12 is high.

15 is a timing chart showing states of signals corresponding to the respective signals of FIG. 13 when the frequency of the ripple pulse output in FIG. 12 is low.

[Explanation of symbols]

M DC motor, ECU electronic control unit, CL
Arithmetic circuit, AD1 to AD3 A / D converter, C
K clock output circuit, CT counter, SCF switched capacitor filter, WF ripple pulse shaping circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideyuki Kanie             Aichi, 2-chome, Asahi-cho, Kariya city, Aichi prefecture             Within Seiki Co., Ltd. (72) Inventor Hidetoshi Kadani             Aichi, 2-chome, Asahi-cho, Kariya city, Aichi prefecture             Within Seiki Co., Ltd. (72) Inventor Hitoshi Ishikawa             Aichi, 2-chome, Asahi-cho, Kariya city, Aichi prefecture             Within Seiki Co., Ltd. (72) Inventor Kazumu Higashi             1 Toyota Town, Toyota City, Aichi Prefecture Toyota Auto             Car Co., Ltd. F-term (reference) 5H571 GG06 GG07 GG08 HA08 JJ03                       JJ12 JJ13 JJ16 JJ26 KK06                       LL22 LL30 LL50

Claims (3)

[Claims] 1. A ripple current output from a DC motor is
In a rotation state detecting device for a DC motor, which outputs through a cutoff frequency variable filter means and adjusts the cutoff frequency of the filter means according to the ripple pulse output through the filter means and the driving state of the DC motor. A maximum ripple frequency calculating means for calculating the maximum ripple frequency of the ripple current output from the DC motor based on the driving state of the DC motor, and the actual ripple frequency by converting the ripple pulse output through the filter means. Real ripple frequency calculating means for calculating, and cutoff frequency adjusting means for adjusting the cutoff frequency according to a difference between the maximum ripple frequency calculated by the maximum ripple frequency calculating means and the actual ripple frequency calculated by the actual ripple frequency calculating means. DC motor rotation state characterized by having Detection device. 2. The cutoff frequency adjusting means sets the cutoff frequency by multiplying a difference between the maximum ripple frequency calculated by the maximum ripple frequency calculating means and the actual ripple frequency calculated by the actual ripple frequency calculating means by a predetermined value. The rotation state detection device for a DC motor according to claim 1, wherein the rotation state detection device is configured as follows. 3. The cut-off frequency adjusting means includes a feedback amount setting means for setting a feedback amount based on the actual ripple frequency calculated by the actual ripple frequency calculating means, and the feedback amount setting means sets a feedback amount according to the feedback amount set by the feedback amount setting means. The rotation state detecting device for a DC motor according to claim 1, wherein the cutoff frequency is adjusted by adjusting the cutoff frequency.